gcc6809-4.6.4.patchset revision 309ccdde
1From 0c5f25aaf0fedee6f09bc07507aec23eb6776bdd Mon Sep 17 00:00:00 2001
2From: Adrien Destugues <pulkomandy@pulkomandy.tk>
3Date: Sun, 15 Jan 2017 21:13:16 +0100
4Subject: applying patch gcc6809-4.6.4.patch
5
6
7diff --git a/README.LW b/README.LW
8new file mode 100644
9index 0000000..bf40e54
10--- /dev/null
11+++ b/README.LW
12@@ -0,0 +1,14 @@
13+This is a port of gcc6809 which is designed to work with the lwtools
14+cross-assembler and linker package.  You will need several scripts from that
15+package, available at http://lost.l-w.ca/coco/lwtools/, in order to use
16+this.  Instructions for building are present in the lwtools package.
17+
18+This work is based extensively on the gcc6809 4.3.4-3 release by Brian
19+Dominy (brian@oddchange.com) with some significant renovations to make it
20+work with gcc 4.6.1.
21+
22+There is no guarantee that it will work for any particular purpose you
23+choose to put it to.
24+
25+If you run into any problems, contact William Astle (lost@l-w.ca). DO NOT
26+contact the main GCC developers!
27diff --git a/config.sub b/config.sub
28index 204218c..75da021 100755
29--- a/config.sub
30+++ b/config.sub
31@@ -313,7 +313,7 @@ case $basic_machine in
32 	c6x)
33 		basic_machine=tic6x-unknown
34 		;;
35-	m6811 | m68hc11 | m6812 | m68hc12 | picochip)
36+	m6809 | m6811 | m68hc11 | m6812 | m68hc12 | picochip)
37 		# Motorola 68HC11/12.
38 		basic_machine=$basic_machine-unknown
39 		os=-none
40@@ -354,7 +354,7 @@ case $basic_machine in
41 	| i*86-* | i860-* | i960-* | ia64-* \
42 	| ip2k-* | iq2000-* \
43 	| lm32-* \
44-	| m32c-* | m32r-* | m32rle-* \
45+	| m32c-* | m32r-* | m32rle-* | m6809-* \
46 	| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
47 	| m88110-* | m88k-* | maxq-* | mcore-* | metag-* | microblaze-* \
48 	| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
49@@ -509,6 +509,10 @@ case $basic_machine in
50 		basic_machine=arm-unknown
51 		os=-cegcc
52 		;;
53+	coco)
54+		basic_machine=coco
55+		os=-none
56+		;;
57 	convex-c1)
58 		basic_machine=c1-convex
59 		os=-bsd
60diff --git a/configure b/configure
61index 6be5e9d..33ed6f6 100755
62--- a/configure
63+++ b/configure
64@@ -3439,6 +3439,9 @@ case "${target}" in
65   m32r-*-*)
66     noconfigdirs="$noconfigdirs ${libgcj}"
67     ;;
68+  m6809*)
69+    noconfigdirs="$noconfigdirs target-libiberty target-libstdc++-v3 target-libgloss ${libgcj}"
70+    ;;
71   m68hc11-*-*|m6811-*-*|m68hc12-*-*|m6812-*-*)
72     noconfigdirs="$noconfigdirs target-libstdc++-v3 ${libgcj}"
73     libgloss_dir=m68hc11
74diff --git a/configure.ac b/configure.ac
75index ba6d84d..ae8e733 100644
76--- a/configure.ac
77+++ b/configure.ac
78@@ -885,6 +885,9 @@ case "${target}" in
79   m32r-*-*)
80     noconfigdirs="$noconfigdirs ${libgcj}"
81     ;;
82+  m6809*)
83+    noconfigdirs="$noconfigdirs target-libiberty target-libstdc++-v3 target-libgloss ${libgcj}"
84+    ;;
85   m68hc11-*-*|m6811-*-*|m68hc12-*-*|m6812-*-*)
86     noconfigdirs="$noconfigdirs target-libstdc++-v3 ${libgcj}"
87     libgloss_dir=m68hc11
88diff --git a/gcc/Makefile.in b/gcc/Makefile.in
89index e0b952f..c2f5318 100644
90--- a/gcc/Makefile.in
91+++ b/gcc/Makefile.in
92@@ -2003,14 +2003,14 @@ $(T)crtbeginT.o: crtstuff.c $(GCC_PASSES) $(TCONFIG_H) auto-host.h \
93 
94 # Compile the start modules crt0.o and mcrt0.o that are linked with
95 # every program
96-$(T)crt0.o: s-crt0 ; @true
97-$(T)mcrt0.o: s-crt0; @true
98+crt0.o: s-crt0 ; @true
99+mcrt0.o: s-crt0; @true
100 
101 s-crt0:	$(CRT0_S) $(MCRT0_S) $(GCC_PASSES) $(CONFIG_H)
102 	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(CRT0STUFF_T_CFLAGS) \
103-	  -o $(T)crt0.o -c $(CRT0_S)
104+	  -o crt0.o -c $(CRT0_S)
105 	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(CRT0STUFF_T_CFLAGS) \
106-	  -o $(T)mcrt0.o -c $(MCRT0_S)
107+	  -o mcrt0.o -c $(MCRT0_S)
108 	$(STAMP) s-crt0
109 #
110 # Compiling object files from source files.
111diff --git a/gcc/calls.c b/gcc/calls.c
112index 4ad6c3f..f3af562 100644
113--- a/gcc/calls.c
114+++ b/gcc/calls.c
115@@ -2561,7 +2561,7 @@ expand_call (tree exp, rtx target, int ignore)
116 	 call sequence.
117 	 Also do the adjustments before a throwing call, otherwise
118 	 exception handling can fail; PR 19225. */
119-      if (pending_stack_adjust >= 32
120+      if (pending_stack_adjust >= 8
121 	  || (pending_stack_adjust > 0
122 	      && (flags & ECF_MAY_BE_ALLOCA))
123 	  || (pending_stack_adjust > 0
124diff --git a/gcc/config.gcc b/gcc/config.gcc
125index 6dc2427..da0f667 100644
126--- a/gcc/config.gcc
127+++ b/gcc/config.gcc
128@@ -375,6 +375,9 @@ m32r*-*-*)
129         cpu_type=m32r
130 	extra_options="${extra_options} g.opt"
131         ;;
132+m6809-*-*)
133+        cpu_type=m6809
134+        ;;
135 m68k-*-*)
136 	extra_headers=math-68881.h
137 	;;
138@@ -1706,6 +1709,12 @@ m32rle-*-linux*)
139 		thread_file='posix'
140 	fi
141 	;;
142+m6809-coco-*)
143+	tmake_file="${tmake_file} m6809/t-m6809 m6809/t-coco"
144+	;;
145+m6809-*-*)
146+	tmake_file="${tmake_file} m6809/t-m6809 m6809/t-sim"
147+	;;
148 # m68hc11 and m68hc12 share the same machine description.
149 m68hc11-*-*|m6811-*-*)
150 	tm_file="dbxelf.h elfos.h usegas.h newlib-stdint.h m68hc11/m68hc11.h"
151diff --git a/gcc/config/m6809/crt0.S b/gcc/config/m6809/crt0.S
152new file mode 100644
153index 0000000..5f78c82
154--- /dev/null
155+++ b/gcc/config/m6809/crt0.S
156@@ -0,0 +1,173 @@
157+;;;
158+;;; Copyright 2006, 2007, 2008, 2009 by Brian Dominy <brian@oddchange.com>
159+;;;
160+;;; This file is part of GCC.
161+;;;
162+;;; GCC is free software; you can redistribute it and/or modify
163+;;; it under the terms of the GNU General Public License as published by
164+;;; the Free Software Foundation; either version 3, or (at your option)
165+;;; any later version.
166+;;;
167+;;; GCC is distributed in the hope that it will be useful,
168+;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
169+;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
170+;;; GNU General Public License for more details.
171+
172+;;; You should have received a copy of the GNU General Public License
173+;;; along with GCC; see the file COPYING3.  If not see
174+;;; <http://www.gnu.org/licenses/>.
175+
176+	/* Declare external for main() */
177+	.globl _main
178+
179+
180+/* The startup is heavily dependent on the type of machine and
181+OS environment that is available at the start point.
182+For the most part, the general idea is the same across machines,
183+but the implementation is vastly different.  This is managed via
184+conditional compiles throughout the startup code for each of the
185+supported machines. */
186+
187+#ifdef TARGET_COCO /* CoCo memory map */
188+
189+#define COCO_RAMROM_MODE 0xFFDE
190+#define COCO_ALLRAM_MODE 0xFFDF
191+#define COCO_PAGE1 0xFFD5
192+
193+/* SAM M1 and M0 adjusts the memory size */
194+
195+#define BASIC_WARMSTART_FLAG 0x0071
196+#define BASIC_START 0xA027
197+
198+#define __STACK_TOP 0x6800
199+
200+#else /* Simulator (default) memory map */
201+
202+#define SIM_EXIT_REG 0xFF01
203+
204+#define __STACK_TOP 0xFE00
205+
206+#endif
207+
208+
209+	.area .data
210+	.area .ctors
211+	.area .dtors
212+	.area .bss
213+
214+   ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
215+	;;;
216+	;;; __exit : Exit point from the program
217+	;;; For simulation, this writes to a special I/O register that
218+	;;; the simulator interprets as end-of-program.
219+	;;;
220+   ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
221+	.area	.text
222+ 	.globl __exit
223+__exit:
224+#ifdef TARGET_COCO
225+	;; Go back to ROM/RAM mode
226+	sta	COCO_RAMROM_MODE
227+	clr	BASIC_WARMSTART_FLAG
228+	jmp   BASIC_START
229+#else
230+	tfr	x,d
231+	stb	SIM_EXIT_REG
232+	bra	__exit
233+#endif
234+
235+
236+   ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
237+	;;;
238+	;;; __start : Entry point to the program
239+	;;;
240+   ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
241+	.area	.text
242+	.globl __start
243+__start:
244+
245+#ifdef HAVE_DIRECT
246+	;; Initialize the direct page pointer
247+	lda	#<s_.direct
248+	tfr	a,dp
249+#endif
250+
251+#ifdef TARGET_COCO
252+	;; Turn off interrupts
253+	orcc #(0x10|0x40)
254+	
255+	;; Setup All RAM Mode
256+	sta COCO_ALLRAM_MODE
257+#endif /* TARGET_COCO */
258+
259+	;; Initialize the stack
260+	lds	#__STACK_TOP - 2
261+	
262+	;; Call any "initializer" functions
263+	ldu	#s_.ctors
264+__ctors_loop:
265+	ldy	,u++
266+	cmpy	#0
267+	beq	__ctors_done
268+	jsr	,y
269+	bra	__ctors_loop
270+__ctors_done:
271+
272+	;; Enable interrupts on the simulator
273+#ifndef TARGET_COCO
274+	andcc	#~(0x10|0x40)
275+#endif
276+
277+	;; Set up the environment
278+
279+	;; Set up argc/argv arrays
280+
281+	;; Call the main function.  The exit code will
282+	;; be returned in the X register, unless compiled
283+	;; with -mdret, in which case it comes back in D.
284+	jsr	_main
285+
286+	;; Call any finalizer functions
287+	ldu	#s_.dtors
288+__dtors_loop:
289+	ldy	,u++
290+	cmpy	#0
291+	beq	__dtors_done
292+	jsr	,y
293+	bra	__dtors_loop
294+__dtors_done:
295+
296+	;; If main returns, then invoke _exit() to stop the program
297+	;; The C library doesn't support -mdret yet, so move the
298+	;; argument first.
299+#ifdef __DRET__
300+	tfr	d,x
301+#endif
302+	jmp	_exit
303+
304+
305+
306+	;;;
307+	;;; __crt0_vector : Default handler for interrupts
308+	;;;
309+	.area	.text
310+___crt0_vector:
311+	;; The default behavior is to simply ignore all
312+	;; non-reset interrupts.
313+	rti
314+
315+
316+	;;;
317+	;;; vector : The interrupt vector table
318+	;;; The linker will ensure that this gets loaded at address 0xFFF0.
319+	;;;
320+	.area vector
321+vectors:
322+	.word ___crt0_vector
323+	.word ___crt0_vector
324+	.word ___crt0_vector
325+	.word ___crt0_vector
326+	.word ___crt0_vector
327+	.word ___crt0_vector
328+	.word ___crt0_vector
329+	.word __start
330diff --git a/gcc/config/m6809/libgcc1.s b/gcc/config/m6809/libgcc1.s
331new file mode 100644
332index 0000000..4a1e1c7
333--- /dev/null
334+++ b/gcc/config/m6809/libgcc1.s
335@@ -0,0 +1,511 @@
336+/* libgcc routines for m6809
337+   Copyright (C) 2006 Free Software Foundation, Inc.
338+
339+This file is part of GCC.
340+
341+GCC is free software; you can redistribute it and/or modify
342+it under the terms of the GNU General Public License as published by
343+the Free Software Foundation; either version 3, or (at your option)
344+any later version.
345+
346+GCC is distributed in the hope that it will be useful,
347+but WITHOUT ANY WARRANTY; without even the implied warranty of
348+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
349+GNU General Public License for more details.
350+
351+You should have received a copy of the GNU General Public License
352+along with GCC; see the file COPYING3.  If not see
353+<http://www.gnu.org/licenses/>.  */
354+
355+/* As a special exception, if you link this library with other files,
356+   some of which are compiled with GCC, to produce an executable,
357+   this library does not by itself cause the resulting executable
358+   to be covered by the GNU General Public License.
359+   This exception does not however invalidate any other reasons why
360+   the executable file might be covered by the GNU General Public License.  */
361+
362+
363+#define SIGFPE jmp _abort
364+
365+
366+	; Shift functions
367+	; On input, D is value to be shifted, and X has shift count.
368+	; Result is also in D.
369+
370+#ifdef L_ashlhi3
371+	.area .text
372+	.globl _ashlhi3
373+_ashlhi3:
374+	pshs	x
375+1$:
376+	leax	-1,x
377+	cmpx	#-1
378+	beq	2$
379+	aslb
380+	rola
381+	bra	1$
382+2$:
383+	puls	x,pc
384+#endif
385+
386+#ifdef L_ashrhi3
387+	.area .text
388+	.globl _ashrhi3
389+_ashrhi3:
390+	pshs	x
391+1$:
392+	leax	-1,x
393+	cmpx	#-1
394+	beq	2$
395+	asra
396+	rorb
397+	bra	1$
398+2$:
399+	puls	x,pc
400+#endif
401+
402+
403+#ifdef L_lshrhi3
404+	.area .text
405+	.globl _lshrhi3
406+_lshrhi3:
407+	pshs	x
408+1$:
409+	leax	-1,x
410+	cmpx	#-1
411+	beq	2$
412+	lsra
413+	rorb
414+	bra	1$
415+2$:
416+	puls	x,pc
417+#endif
418+
419+
420+
421+#ifdef L_softregs
422+	.area		direct
423+	.globl	m0, m1, m2, m3, m4, m5, m6, m7
424+	.globl	m8, m9, m10, m11, m12, m13, m14, m15
425+m0: .blkb 1
426+m1: .blkb 1
427+m2: .blkb 1
428+m3: .blkb 1
429+m4: .blkb 1
430+m5: .blkb 1
431+m6: .blkb 1
432+m7: .blkb 1
433+m8: .blkb 1
434+m9: .blkb 1
435+m10: .blkb 1
436+m11: .blkb 1
437+m12: .blkb 1
438+m13: .blkb 1
439+m14: .blkb 1
440+m15: .blkb 1
441+#endif
442+
443+
444+#ifdef L_ashlsi3_one
445+	.area		.text
446+	.globl	_ashlsi3_one
447+_ashlsi3_one:
448+	asl	3,x
449+	rol	2,x
450+	rol	1,x
451+	rol	,x
452+	rts
453+#endif
454+
455+#ifdef L_ashlsi3
456+	/* X points to the SImode (source/dest)
457+		B is the count */
458+_ashlsi3:
459+	pshs	u
460+	cmpb	#16
461+	blt	try8
462+	subb	#16
463+	; Shift by 16
464+	ldu	2,x
465+	stu	,x
466+try8:
467+	cmpb	#8
468+	blt	try_rest
469+	subb	#8
470+	; Shift by 8
471+
472+try_rest:
473+	tstb
474+	beq	done
475+do_rest:
476+	; Shift by 1
477+	asl	3,x
478+	rol	2,x
479+	rol	1,x
480+	rol	,x
481+	decb
482+	bne	do_rest
483+done:
484+	puls	u,pc
485+#endif
486+
487+#ifdef L_ashrsi3_one
488+	.area		.text
489+	.globl	_ashlsi3_one
490+_ashrsi3_one:
491+	asr	,x
492+	ror	1,x
493+	ror	2,x
494+	ror	3,x
495+	rts
496+#endif
497+
498+
499+#ifdef L_lshrsi3_one
500+	.area		.text
501+	.globl	_lshrsi3_one
502+_lshrsi3_one:
503+	lsr	,x
504+	ror	1,x
505+	ror	2,x
506+	ror	3,x
507+	rts
508+#endif
509+
510+
511+#ifdef L_clzsi2
512+	.area .text
513+	.globl ___clzhi2
514+	; Input: X = 16-bit unsigned integer
515+	; Output: X = number of leading zeros
516+	; This function destroys the value in D.
517+___clzhi2:
518+	pshs	x
519+	; Find the offset of the leftmost '1' bit in
520+	; the left half of the word.
521+	;
522+	; Bits are numbered in the table with 1 meaning the
523+	; LSB and 8 meaning the MSB.
524+	;
525+	; If nonzero, then clz is 8-a.
526+	tfr	x,d
527+	ldx	#___clz_tab
528+	tfr	a,b
529+	clra
530+	ldb	d,x
531+	bne	upper_bit_set
532+
533+lower_bit_set:
534+	; If the upper byte is zero, then check the lower
535+	; half of the word.  Return 16-a.
536+	puls	d
537+	clra
538+	ldb	d,x
539+	negb
540+	addb	#16
541+	bra	done
542+
543+upper_bit_set:
544+	negb
545+	addb	#8
546+	puls	x
547+
548+done:
549+	tfr	d,x
550+	puls	pc
551+#endif
552+
553+#ifdef L_clzdi2
554+	.area .text
555+	.globl ___clzsi2
556+	; Input: 32-bit unsigned integer is on the stack, just
557+	; above the return address
558+	; Output: X = number of leading zeros
559+___clzsi2:
560+	; Check the upper 16-bit word
561+	; If it is not zero, then return clzhi2(X).
562+	; A branch can be used instead of a call since no
563+	; postprocessing is needed.  Use long branch form
564+	; though since functions may not be near each other.
565+	ldx	2,s
566+	lbne	___clzhi2
567+	ldx	4,s
568+	jsr	___clzhi2
569+	leax	16,x
570+	rts
571+#endif
572+
573+#ifdef L_ctzsi2
574+	.area .text
575+	.globl ___ctzhi2
576+	; Input: X = 16-bit unsigned integer
577+	; Output: X = number of trailing zeros
578+	; F(x) = 15 - clzhi2(X & -x)
579+	; This function destroys the value in D.
580+___ctzhi2:
581+	tfr	x,d
582+	coma
583+	comb
584+	addd	#1
585+	pshs	a
586+	pshs	b
587+	tfr	x,d
588+	andb	,s+
589+	anda	,s+
590+	tfr	d,x
591+	jsr	___clzhi2
592+	tfr	x,d
593+	subd	#16
594+	coma
595+	comb
596+	tfr	d,x
597+	rts
598+#endif
599+
600+
601+#ifdef L_ctzdi2
602+	.area .text
603+	.globl ___ctzsi2
604+	; Input: 32-bit unsigned integer is on the stack, just
605+	; above the return address
606+	; Output: X = number of leading zeros
607+___ctzsi2:
608+	; Check the lower 16-bit word
609+	; If it is not zero, then return ctzhi2(X).
610+	; A branch can be used instead of a call since no
611+	; postprocessing is needed.  Use long branch form
612+	; though since functions may not be near each other.
613+	ldx	4,s
614+	lbne	___ctzhi2
615+	ldx	2,s
616+	jsr	___ctzhi2
617+	leax	16,x
618+	rts
619+#endif
620+
621+
622+#ifdef L_mulhi3
623+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
624+;;; ___mulhi3 - signed/unsigned multiply
625+;;; Called by GCC to implement 16x16 multiplication
626+;;; Arguments: Two 16-bit values, one in stack, one in X.
627+;;; Result: 16-bit result in X
628+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
629+	.area .text
630+	.globl _mulhi3
631+_mulhi3:
632+	pshs	x
633+	lda   5,s   ; left msb * right lsb * 256
634+	ldb   ,s
635+	mul
636+	tfr   b,a
637+	clrb
638+	tfr   d,x
639+	ldb   1,s   ; left lsb * right msb * 256
640+	lda   4,s
641+	mul
642+	tfr   b,a
643+	clrb
644+	leax  d,x
645+	ldb   1,s   ; left lsb * right lsb
646+	lda   5,s
647+	mul
648+	leax  d,x
649+	puls	d,pc  ; kill D to remove initial push
650+#endif
651+
652+
653+#ifdef L_divhi3
654+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
655+;;; ___divhi3 - signed division
656+;;; Arguments: Dividend in X, divisor on the stack
657+;;; Returns result in X.
658+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
659+	.area .text
660+	.globl _divhi3
661+_divhi3:
662+	ldd	2,s
663+	bne	do_div		; check dividend
664+	SIGFPE
665+do_div:
666+	pshs	x
667+	jsr	_seuclid
668+	puls	x,pc
669+#endif
670+
671+
672+#ifdef L_modhi3
673+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
674+;;; ___modhi3 - signed modulo
675+;;; Arguments: Dividend in X, divisor on the stack
676+;;; Returns result in X.
677+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
678+	.area .text
679+	.globl _modhi3
680+_modhi3:
681+	ldd	2,s
682+	bne	do_mod		; check dividend
683+	SIGFPE
684+do_mod:
685+	pshs	x
686+	jsr	_seuclid
687+	leas	2,s
688+	tfr	d,x
689+	rts
690+#endif
691+
692+
693+
694+#ifdef L_udivhi3
695+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
696+;;; ___udivhi3 - unsigned division
697+;;; Arguments: Dividend in X, divisor on the stack
698+;;; Returns result in X.
699+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
700+	.area .text
701+	.globl _udivhi3
702+_udivhi3:
703+	ldd	2,s
704+	bne	do_udiv		; check dividend
705+	SIGFPE
706+do_udiv:
707+	pshs	x
708+	jsr	_euclid
709+	puls	x,pc
710+#endif
711+
712+
713+#ifdef L_umodhi3
714+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
715+;;; ___umodhi3 - unsigned modulo
716+;;; Arguments: Dividend in X, divisor on the stack
717+;;; Returns result in X.
718+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
719+	.area .text
720+	.globl _umodhi3
721+_umodhi3:
722+	ldd	2,s
723+	bne	do_umod		; check dividend
724+	SIGFPE
725+do_umod:
726+	pshs	x
727+	jsr	_euclid
728+	leas	2,s
729+	tfr	d,x
730+	rts
731+#endif
732+
733+
734+#ifdef L_euclid
735+;	unsigned euclidean division
736+;	calling: (left / right)
737+;		push left
738+;		ldd right
739+;		jsr _euclid
740+;	quotient on the stack (left)
741+;	modulus in d
742+
743+	.area	.text
744+	.globl	_euclid
745+	left=5
746+	right=1			; word
747+	count=0			; byte
748+	CARRY=1			; alias
749+_euclid:
750+	leas	-3,s		; 2 local variables
751+	clr	count,s		; prescale divisor
752+	inc	count,s
753+	tsta
754+presc:
755+	bmi	presc_done
756+	inc	count,s
757+	aslb
758+	rola
759+	bra	presc
760+presc_done:
761+	std	right,s
762+	ldd	left,s
763+	clr	left,s		; quotient = 0
764+	clr	left+1,s
765+mod1:
766+	subd	right,s		; check subtract
767+	bcc	mod2
768+	addd	right,s
769+	andcc	#~CARRY
770+	bra	mod3
771+mod2:
772+	orcc	#CARRY
773+mod3:
774+	rol	left+1,s	; roll in carry
775+	rol	left,s
776+	lsr	right,s
777+	ror	right+1,s
778+	dec	count,s
779+	bne	mod1
780+	leas	3,s
781+	rts
782+#endif
783+
784+#ifdef L_seuclid
785+;	signed euclidean division
786+;	calling: (left / right)
787+;		push left
788+;		ldd right
789+;		jsr _seuclid
790+;	quotient on the stack (left)
791+;	modulus in d
792+	.area	.text
793+	.globl	_seuclid
794+	left=6
795+	right=2
796+	quot_sign=1
797+	mod_sign=0
798+_seuclid:
799+	leas	-4,s		; 3 local variables
800+	std	right,s
801+	clr	mod_sign,s
802+	clr	quot_sign,s
803+	ldd	left,s
804+	bge	mod_abs
805+	inc	mod_sign,s	; sign(mod) = sign(left)
806+	inc	quot_sign,s
807+	bsr	negd		; abs(left) -> D
808+mod_abs:
809+	pshs	b,a		; push abs(left)
810+	ldd	right+2,s	; all references shifted by 2
811+	bge	quot_abs
812+	dec	quot_sign+2,s	; sign(quot) = sign(left) XOR sign(right)
813+	bsr	negd		; abs(right) -> D
814+quot_abs:
815+	jsr	_euclid		; call (unsigned) euclidean division
816+	std	right+2,s
817+	puls	a,b		; quot -> D
818+	tst	quot_sign,s	; all references no longer shifted
819+	beq	quot_done
820+	bsr	negd
821+quot_done:
822+	std	left,s		; quot -> left
823+	ldd	right,s
824+	tst	mod_sign,s
825+	beq	mod_done
826+	bsr	negd
827+mod_done:
828+	leas	4,s		; destroy stack frame
829+	rts
830+
831+negd:				; self-explanatory !
832+	nega
833+	negb
834+	sbca	#0
835+	rts
836+#endif
837+
838+
839+
840+#ifdef L_pending_addsi3
841+_addsi3:
842+	rts
843+#endif /* L_pending_addsi3 */
844+
845+
846+
847diff --git a/gcc/config/m6809/m6809-protos.h b/gcc/config/m6809/m6809-protos.h
848new file mode 100644
849index 0000000..ba00de5
850--- /dev/null
851+++ b/gcc/config/m6809/m6809-protos.h
852@@ -0,0 +1,94 @@
853+/* GCC for 6809 : machine-specific function prototypes
854+
855+This file is part of GCC.
856+
857+GCC is free software; you can redistribute it and/or modify
858+it under the terms of the GNU General Public License as published by
859+the Free Software Foundation; either version 3, or (at your option)
860+any later version.
861+
862+GCC is distributed in the hope that it will be useful,
863+but WITHOUT ANY WARRANTY; without even the implied warranty of
864+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
865+GNU General Public License for more details.
866+
867+You should have received a copy of the GNU General Public License
868+along with GCC; see the file COPYING3.  If not see
869+<http://www.gnu.org/licenses/>.  */
870+
871+#ifndef __M6809_PROTOS_H__
872+#define __M6809_PROTOS_H__
873+
874+void 					print_options (FILE *file);
875+void 					m6809_cpu_cpp_builtins (void);
876+void 					m6809_override_options (void);
877+void 					m6809_init_builtins (void);
878+unsigned int 		m6809_get_live_regs (void);
879+const char * 		m6809_get_regs_printable (unsigned int regs);
880+unsigned int 		m6809_get_regs_size (unsigned int regs);
881+int 					m6809_function_has_type_attr_p (tree decl, const char *);
882+int 					m6809_current_function_has_type_attr_p (const char *);
883+int 					prologue_epilogue_required (void);
884+int 					noreturn_functionp (rtx x);
885+void 					output_function_prologue (FILE *file, int size);
886+void 					output_function_epilogue (FILE *file, int size);
887+int 					check_float_value (enum machine_mode mode, double *d, int overflow);
888+void 					m6809_asm_named_section (const char *name, unsigned int flags, tree decl);
889+void 					m6809_asm_file_start (void);
890+void              m6809_output_ascii (FILE *fp, const char *str, unsigned long size);
891+void              m6809_declare_function_name (FILE *asm_out_file, const char *name, tree decl);
892+void              m6809_reorg (void);
893+int               m6809_current_function_is_void (void);
894+int               m6809_can_merge_pushpop_p (int op, int regs1, int regs2);
895+int               m6809_function_value_regno_p (unsigned int regno);
896+void              emit_prologue_insns (void);
897+void              emit_epilogue_insns (bool);
898+void              m6809_conditional_register_usage (void);
899+void              m6809_output_quoted_string (FILE *asm_file, const char *string);
900+int               m6809_match_peephole2 (unsigned int peephole_id, unsigned int stage);
901+int               m6809_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode);
902+int               power_of_two_p (unsigned int n);
903+void              m6809_do_casesi (rtx index, rtx lower_bound, rtx range, rtx table_label, rtx default_label);
904+void              m6809_output_addsi3 (int rtx_code, rtx *operands);
905+rtx               m6809_function_arg_on_stack (CUMULATIVE_ARGS *cump);
906+void              expand_constant_shift (int code, rtx dst, rtx src, rtx count);
907+int               m6809_single_operand_operator (rtx exp);
908+
909+#ifdef TREE_CODE
910+int m6809_init_cumulative_args (CUMULATIVE_ARGS cum, tree fntype, rtx libname);
911+#endif /* TREE_CODE */
912+
913+#ifdef RTX_CODE
914+void 					print_direct_prefix (FILE *file, rtx addr);
915+void 					print_operand (FILE *file, rtx x, int code);
916+void 					print_operand_address (FILE *file, rtx addr);
917+void 					notice_update_cc (rtx exp, rtx insn);
918+enum 					reg_class m6809_preferred_reload_class (rtx x, enum reg_class regclass);
919+rtx 					gen_rtx_const_high (rtx r);
920+rtx 					gen_rtx_const_low (rtx r);
921+rtx 					gen_rtx_register_pushpop (int pop_flag, int regs);
922+void 					emit_libcall_insns (enum machine_mode mode, const char *name, rtx *operands, int count);
923+const char *		output_branch_insn (enum rtx_code code, rtx *operands, int length);
924+void 					output_far_call_insn (rtx *operands, int has_return);
925+void 					m6809_initialize_trampoline (rtx tramp, tree fndecl, rtx cxt);
926+rtx 					m6809_expand_builtin (tree exp, rtx target, rtx subtarget, enum machine_mode mode, int ignore);
927+const char *      far_functionp (rtx x);
928+rtx               m6809_function_value (const tree valtype, const tree func);
929+void              m6809_output_shift_insn (int rtx_code, rtx *operands);
930+
931+const char * m6809_get_decl_bank (tree decl);
932+void output_branch_insn1 (const char *opcode, rtx *operands, int long_p);
933+rtx m6809_builtin_operand (tree arglist, enum machine_mode mode, int opnum);
934+const char * far_function_type_p (tree type);
935+void m6809_asm_trampoline_template(FILE *f);
936+bool m6809_frame_pointer_required (void);
937+int m6809_can_eliminate (int from, int to);
938+int m6809_initial_elimination_offset (int from, int to);
939+void m6809_emit_move_insn (rtx dst, rtx src);
940+void m6809_split_shift (enum rtx_code code, rtx *operands);
941+bool m6809_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED);
942+
943+
944+#endif /* RTX_CODE */
945+
946+#endif /* __M6809_PROTOS_H__ */
947diff --git a/gcc/config/m6809/m6809.c b/gcc/config/m6809/m6809.c
948new file mode 100644
949index 0000000..721583e
950--- /dev/null
951+++ b/gcc/config/m6809/m6809.c
952@@ -0,0 +1,3023 @@
953+/*-------------------------------------------------------------------
954+	FILE: m6809.c
955+-------------------------------------------------------------------*/
956+/* Subroutines for insn-output.c for MC6809.
957+   Copyright (C) 1989-2007 Free Software Foundation, Inc.
958+
959+ MC6809 Version by Tom Jones (jones@sal.wisc.edu)
960+ Space Astronomy Laboratory
961+ University of Wisconsin at Madison
962+
963+ minor changes to adapt it to gcc-2.5.8 by Matthias Doerfel
964+ ( msdoerfe@informatik.uni-erlangen.de )
965+ also added #pragma interrupt (inspired by gcc-6811)
966+
967+ minor changes to adapt it to gcc-2.8.0 by Eric Botcazou
968+ (ebotcazou@multimania.com)
969+
970+ minor changes to adapt it to gcc-2.95.3 by Eric Botcazou
971+ (ebotcazou@multimania.com)
972+
973+ major cleanup, improvements, and upgrade to gcc 3.4 by Brian Dominy
974+ (brian@oddchange.com)
975+
976+ additional adjustments, etc., for gcc 4.6.1 by William Astle (lost@l-w.ca)
977+
978+This file is part of GCC.
979+
980+GCC is free software; you can redistribute it and/or modify
981+it under the terms of the GNU General Public License as published by
982+the Free Software Foundation; either version 3, or (at your option)
983+any later version.
984+
985+GCC is distributed in the hope that it will be useful,
986+but WITHOUT ANY WARRANTY; without even the implied warranty of
987+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
988+GNU General Public License for more details.
989+
990+You should have received a copy of the GNU General Public License
991+along with GCC; see the file COPYING3.  If not see
992+<http://www.gnu.org/licenses/>.  */
993+
994+#include <string.h>
995+#include <time.h>
996+#include <sys/types.h>
997+#include <sys/timeb.h>
998+#include <stdio.h>
999+#include "config.h"
1000+#include "system.h"
1001+#include "coretypes.h"
1002+#include "tm.h"
1003+#include "tree.h"
1004+#include "rtl.h"
1005+#include "tm_p.h"
1006+#include "regs.h"
1007+#include "flags.h"
1008+#include "hard-reg-set.h"
1009+#include "real.h"
1010+#include "tree.h"
1011+#include "insn-config.h"
1012+#include "conditions.h"
1013+#include "insn-flags.h"
1014+#include "output.h"
1015+#include "insn-attr.h"
1016+#include "function.h"
1017+#include "target.h"
1018+#include "target-def.h"
1019+#include "expr.h"
1020+#include "recog.h"
1021+#include "cpplib.h"
1022+#include "c-family/c-pragma.h"
1023+#include "c-family/c-common.h"
1024+#include "toplev.h"
1025+#include "optabs.h"
1026+#include "version.h"
1027+#include "df.h"
1028+#include "rtlhooks-def.h"
1029+
1030+/* macro to return TRUE if length of operand mode is one byte */
1031+#define BYTE_MODE(X) ((GET_MODE_SIZE (GET_MODE (X))) == 1)
1032+
1033+
1034+/* REAL_REG_P(x) is a true if the rtx 'x' represents a real CPU
1035+register and not a fake one that is emulated in software. */
1036+#define REAL_REG_P(x) (REG_P(x) && !M_REG_P(x))
1037+
1038+/*-------------------------------------------------------------------
1039+    Target hooks, moved from target.h
1040+-------------------------------------------------------------------*/
1041+static void m6809_encode_section_info (tree decl, rtx rtl, int new_decl_p ATTRIBUTE_UNUSED);
1042+
1043+#undef TARGET_ENCODE_SECTION_INFO
1044+#define TARGET_ENCODE_SECTION_INFO m6809_encode_section_info
1045+
1046+#undef TARGET_ASM_FILE_START
1047+#define TARGET_ASM_FILE_START m6809_asm_file_start
1048+
1049+#undef TARGET_ASM_ALIGNED_HI_OP
1050+#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
1051+
1052+#undef TARGET_ASM_ALIGNED_SI_OP
1053+#define TARGET_ASM_ALIGNED_SI_OP NULL
1054+
1055+#undef TARGET_ASM_UNALIGNED_HI_OP
1056+#define TARGET_ASM_UNALIGNED_HI_OP "\t.word\t"
1057+
1058+#undef TARGET_ASM_UNALIGNED_SI_OP
1059+#define TARGET_ASM_UNALIGNED_SI_OP NULL
1060+
1061+#undef TARGET_RTX_COSTS
1062+#define TARGET_RTX_COSTS m6809_rtx_costs
1063+
1064+#undef TARGET_ATTRIBUTE_TABLE
1065+#define TARGET_ATTRIBUTE_TABLE m6809_attribute_table
1066+
1067+#undef TARGET_INIT_BUILTINS
1068+#define TARGET_INIT_BUILTINS m6809_init_builtins
1069+
1070+#undef TARGET_EXPAND_BUILTIN
1071+#define TARGET_EXPAND_BUILTIN m6809_expand_builtin
1072+
1073+#undef TARGET_DEFAULT_TARGET_FLAGS
1074+#define TARGET_DEFAULT_TARGET_FLAGS (MASK_REG_ARGS | MASK_DIRECT)
1075+
1076+#undef TARGET_FUNCTION_OK_FOR_SIBCALL
1077+#define TARGET_FUNCTION_OK_FOR_SIBCALL m6809_function_ok_for_sibcall
1078+
1079+#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
1080+#define TARGET_ASM_TRAMPOLINE_TEMPLATE m6809_asm_trampoline_template
1081+
1082+#undef TARGET_TRAMPOLINE_INIT
1083+#define TARGET_TRAMPOLINE_INIT m6809_initialize_trampoline
1084+
1085+#undef TARGET_FRAME_POINTER_REQUIRED
1086+#define TARGET_FRAME_POINTER_REQUIRED m6809_frame_pointer_required
1087+
1088+#undef TARGET_OPTION_OVERRIDE
1089+#define TARGET_OPTION_OVERRIDE m6809_override_options
1090+
1091+/* External variables used */
1092+extern int reload_completed;   /* set in toplev.c */
1093+extern FILE *asm_out_file;
1094+
1095+static int last_mem_size;   /* operand size (bytes) */
1096+
1097+/* True if the section was recently changed and another .area
1098+ * directive needs to be output before emitting the next label. */
1099+int section_changed = 0;
1100+
1101+/* Section names.  The defaults here are used until an
1102+ * __attribute__((section)) is seen that changes it. */
1103+char code_section_op[128] = "\t.area .text";
1104+char data_section_op[128] = "\t.area .data";
1105+char bss_section_op[128] = "\t.area .bss";
1106+const char *code_bank_option = 0;
1107+
1108+/* TRUE if the direct mode prefix might be valid in this context.
1109+ * This is set by 'print_address' prior to calling output_addr_const,
1110+ * which performs into 'print_direct_prefix' to do the final checks. */
1111+static int check_direct_prefix_flag;
1112+
1113+/* Nonzero if an address is being printed in a context which does not
1114+ * permit any PIC modifications to the address */
1115+static int pic_ok_for_addr_p = 1;
1116+
1117+/* Current code page.  This supports machines which can do bank
1118+ * switching to allow for more than 64KB of code/data. */
1119+char far_code_page[64];
1120+
1121+/* Current bank name */
1122+static char current_bank_name[8] = "-1";
1123+
1124+/* Default bank name */
1125+static char default_code_bank_name[8] = "-1";
1126+
1127+/* Direct memory reserved as soft registers */
1128+unsigned int m6809_soft_regs = 0;
1129+
1130+/* ABI version */
1131+unsigned int m6809_abi_version = M6809_ABI_VERSION_REGS;
1132+
1133+
1134+/**
1135+ * Called after options have been parsed.
1136+ * If overrides have been specified on the command-line, then
1137+ * these values are copied into the main storage variables.
1138+ */
1139+void
1140+m6809_override_options (void)
1141+{
1142+	/* Handle -mfar-code-page */
1143+	if (far_code_page_option == 0)
1144+		far_code_page_option = "__default_code_page";
1145+	strcpy (far_code_page, far_code_page_option);
1146+
1147+	/* Handle -mcode-section, -mdata-section, and -mbss-section */
1148+	if (code_section_ptr != 0)
1149+		sprintf (code_section_op, "\t.area %s", code_section_ptr);
1150+	if (data_section_ptr != 0)
1151+		sprintf (data_section_op, "\t.area %s", data_section_ptr);
1152+	if (bss_section_ptr != 0)
1153+		sprintf (bss_section_op, "\t.area %s", bss_section_ptr);
1154+
1155+	/* Handle -mcode-bank */
1156+	if (code_bank_option != 0)
1157+		sprintf (default_code_bank_name, "%s", code_bank_option);
1158+
1159+	/* Handle -mabi-version or -mno-reg-args */
1160+	if (m6809_abi_version_ptr != 0)
1161+	{
1162+		if (!strcmp (m6809_abi_version_ptr, "stack"))
1163+			m6809_abi_version = M6809_ABI_VERSION_STACK;
1164+		else if (!strcmp (m6809_abi_version_ptr, "regs"))
1165+			m6809_abi_version = M6809_ABI_VERSION_REGS;
1166+		else if (!strcmp (m6809_abi_version_ptr, "bx"))
1167+			m6809_abi_version = M6809_ABI_VERSION_BX;
1168+		else if (!strcmp (m6809_abi_version_ptr, "latest"))
1169+			m6809_abi_version = M6809_ABI_VERSION_LATEST;
1170+		else
1171+			m6809_abi_version = atoi (m6809_abi_version_ptr);
1172+	}
1173+
1174+	/* The older -mno-reg-args option is deprecated, and treated
1175+	as -mabi=stack. */
1176+	if (!TARGET_REG_ARGS)
1177+   {
1178+      warning (WARNING_OPT "-mno-reg-args deprecated; use -mabi=stack instead.");
1179+      m6809_abi_version = M6809_ABI_VERSION_STACK;
1180+   }
1181+
1182+	/* -fexceptions is unsupported */
1183+	flag_exceptions = 0;
1184+	flag_non_call_exceptions = 0;
1185+	flag_unwind_tables = 0;
1186+}
1187+
1188+
1189+/**
1190+ * Output prefix that directs the assembler to use a direct-mode
1191+ * instruction if globally enabled, address is a symbol, and symbol
1192+ * has been marked as in direct page.  Also, never do this if
1193+ * using the indirect mode. */
1194+void
1195+print_direct_prefix (FILE * file, rtx addr)
1196+{
1197+	if (TARGET_DIRECT &&
1198+       (GET_CODE (addr) == SYMBOL_REF) && 
1199+       SYMBOL_REF_FLAG (addr) &&
1200+       check_direct_prefix_flag)
1201+   {
1202+      putc ('*', file);
1203+   }
1204+}
1205+
1206+
1207+/** Prints an operand (that is not an address) in assembly from RTL. */
1208+void
1209+print_operand (FILE * file, rtx x, int code)
1210+{
1211+	if (REG_P (x)) {
1212+		/* gcc currently allocates the entire 16-bit 'd' register
1213+		 * even when it only needs an 8-bit value.  So here it
1214+		 * is tricked into printing only the lower 8-bit 'b'
1215+		 * register into the assembly output.
1216+		 *
1217+		 * Eventually gcc should be modified to allocate a/b
1218+		 * independently and this hack can be removed.
1219+		 *
1220+		 * Occasionally, we may want to do an operation using
1221+		 * the 'a' register instead of 'b'; use the 'A' code
1222+		 * to specify that.
1223+		 */
1224+		if (code == 'A')
1225+			fputs ("a", file);
1226+		else if ((BYTE_MODE (x)) && (REGNO (x) == HARD_D_REGNUM))
1227+			fputs ("b", file);
1228+		else if (M_REG_P (x) && code == 'L')
1229+			/* Soft registers can be treated like memory and accessed
1230+			 * at a particular offset. TODO : handle 'W' */
1231+			fputs (reg_names[REGNO (x)+1], file);
1232+		else
1233+			fputs (reg_names[REGNO (x)], file);
1234+	}
1235+
1236+	else if (MEM_P (x)) {
1237+		last_mem_size = GET_MODE_SIZE (GET_MODE (x));
1238+		if (code == 'L') {	/* LSH of word address */
1239+			if (GET_CODE (XEXP (x, 0)) == MEM)
1240+			{
1241+				/* Offseting an indirect addressing mode is not supported */
1242+				error ("expression too complex for 6809 (offset indirect mode)");
1243+				debug_rtx (x);
1244+			}
1245+			else
1246+				x = adjust_address (x, QImode, 1);
1247+		}
1248+		else if (code == 'M') { /* MSH of word address */
1249+			if (GET_CODE (XEXP (x, 0)) == MEM)
1250+			{
1251+				/* Offseting an indirect addressing mode is not supported */
1252+				error ("expression too complex for 6809 (offset indirect mode)");
1253+				debug_rtx (x);
1254+			}
1255+			else
1256+				x = adjust_address (x, QImode, 0);
1257+		}
1258+		else if (code == 'W') { /* least significant half of 32-bit */
1259+			x = adjust_address (x, HImode, 2);
1260+		}
1261+
1262+		pic_ok_for_addr_p = (code != 'C');
1263+		output_address (XEXP (x, 0));
1264+	}
1265+
1266+	else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != DImode) {
1267+		union { double d; int i[2]; } u;
1268+		u.i[0] = CONST_DOUBLE_LOW (x);
1269+		u.i[1] = CONST_DOUBLE_HIGH (x);
1270+		fprintf (file, "#%#9.9g", u.d);
1271+	}
1272+
1273+	else if (code == 'R') {
1274+		fprintf (file, "%s", 
1275+			m6809_get_regs_printable (INTVAL (x)));
1276+	}
1277+
1278+	else {
1279+		if (code == 'L') {	/* LSH of word address */
1280+			x = gen_rtx_CONST_INT (VOIDmode, (INTVAL(x) & 0xff));
1281+		}
1282+		else if (code == 'M') {	/* MSH of word address */
1283+			x = gen_rtx_CONST_INT (VOIDmode, ((INTVAL(x) >> 8) & 0xff));
1284+		}
1285+
1286+		putc ('#', file);
1287+		output_addr_const (file, x);
1288+	}
1289+}
1290+
1291+
1292+/** Prints an address operand to assembler from its RTL representation. */
1293+void
1294+print_operand_address (FILE *file, rtx addr)
1295+{
1296+	register rtx base = 0;
1297+	register rtx offset = 0;
1298+	int regno;
1299+	int indirect_flag = 0;
1300+
1301+	check_direct_prefix_flag = 0;
1302+
1303+	/*** check for indirect addressing ***/
1304+	if (MEM_P (addr)) {
1305+		last_mem_size = GET_MODE_SIZE (GET_MODE (addr));
1306+		addr = XEXP (addr, 0);
1307+		if (pic_ok_for_addr_p)
1308+		{
1309+			indirect_flag = 1;
1310+			fprintf (file, "[");
1311+		}
1312+	}
1313+
1314+
1315+	switch (GET_CODE (addr)) {
1316+		case REG:
1317+			regno = REGNO (addr);
1318+			fprintf (file, ",%s", reg_names[regno]);
1319+			break;
1320+
1321+		case PRE_DEC:
1322+			regno = REGNO (XEXP (addr, 0));
1323+			fputs (((last_mem_size == 1) ? ",-" : ",--"), file);
1324+			fprintf (file, "%s", reg_names[regno]);
1325+			break;
1326+
1327+		case POST_INC:
1328+			regno = REGNO (XEXP (addr, 0));
1329+			fprintf (file, ",%s", reg_names[regno]);
1330+			fputs (((last_mem_size == 1) ? "+" : "++"), file);
1331+			break;
1332+
1333+		case PLUS:
1334+			base = XEXP (addr, 0);
1335+			if (MEM_P (base))
1336+				base = XEXP (base, 0);
1337+
1338+			offset = XEXP (addr, 1);
1339+			if (MEM_P (offset))
1340+				offset = XEXP (offset, 0);
1341+
1342+			if ((CONSTANT_ADDRESS_P (base)) && (CONSTANT_ADDRESS_P (offset))) {
1343+				if (!indirect_flag)
1344+					check_direct_prefix_flag = 1;
1345+				output_addr_const (file, base);
1346+				check_direct_prefix_flag = 0;
1347+				fputs ("+", file);
1348+				output_addr_const (file, offset);
1349+			}
1350+
1351+			else if ((CONSTANT_ADDRESS_P (base)) && (A_REG_P (offset))) {
1352+				output_addr_const (file, base);
1353+				fprintf (file, ",%s", reg_names[REGNO (offset)]);
1354+			}
1355+
1356+			else if ((CONSTANT_ADDRESS_P (offset)) && (A_REG_P (base))) {
1357+				output_addr_const (file, offset);
1358+				fprintf (file, ",%s", reg_names[REGNO (base)]);
1359+			}
1360+
1361+			/*** accumulator offset ***/
1362+			else if (((D_REG_P (offset)) || (Q_REG_P (offset)))
1363+			&& (A_REG_P (base))) {
1364+				fprintf (file, "%s,%s",
1365+				reg_names[REGNO (offset)], reg_names[REGNO (base)]);
1366+			}
1367+
1368+			else if (((D_REG_P (base)) || (Q_REG_P (base)))
1369+			&& (A_REG_P (offset))) {
1370+				fprintf (file, "%s,%s",
1371+				reg_names[REGNO (base)], reg_names[REGNO (offset)]);
1372+			}
1373+
1374+			else if (GET_CODE (base) == PRE_DEC) {
1375+				regno = REGNO (XEXP (base, 0));
1376+				fputs (((last_mem_size == 1) ? ",-" : ",--"), file);
1377+				fprintf (file, "%s", reg_names[regno]);
1378+			}
1379+
1380+			else
1381+				abort ();
1382+
1383+			break;
1384+
1385+   default:
1386+		/* Set this global before calling output_addr_const() */
1387+		if (!indirect_flag)
1388+			check_direct_prefix_flag = 1;
1389+
1390+		/* When printing a SYMBOL_REF in PIC mode, do not print the leading
1391+		 * '#' and follow it by ',pcr' to enable relative addressing. */
1392+		if (flag_pic && pic_ok_for_addr_p && GET_CODE (addr) == SYMBOL_REF)
1393+		{
1394+			ASM_OUTPUT_SYMBOL_REF (file, addr);
1395+			fputs (",pcr", file);
1396+			pic_ok_for_addr_p = 1;
1397+		}
1398+		else
1399+		{
1400+      	output_addr_const (file, addr);
1401+		}
1402+
1403+		check_direct_prefix_flag = 0;
1404+      break;
1405+	}
1406+
1407+	if (indirect_flag)
1408+		fprintf (file, "]");
1409+}
1410+
1411+/*-------------------------------------------------------------------
1412+    Update the CC Status
1413+---------------------------------------------------------------------
1414+   Set the cc_status for the results of an insn whose pattern is EXP.
1415+   We assume that jumps don't affect the condition codes.
1416+   All else, clobbers the condition codes, by assumption.
1417+
1418+   We assume that ALL add, minus, etc. instructions effect the condition
1419+   codes.
1420+-------------------------------------------------------------------*/
1421+void
1422+notice_update_cc (rtx exp, rtx insn ATTRIBUTE_UNUSED)
1423+{
1424+	int src_code;
1425+	int dst_code;
1426+
1427+	/*** recognize SET insn's ***/
1428+	if (GET_CODE (exp) == SET)
1429+	{
1430+		src_code = GET_CODE (SET_SRC (exp));
1431+		dst_code = GET_CODE (SET_DEST (exp));
1432+
1433+		/* Jumps do not alter the cc's.  */
1434+		if (SET_DEST (exp) == pc_rtx)
1435+			return;
1436+
1437+		/* Moving one register into another register (tfr):
1438+		Doesn't alter the cc's.  */
1439+		if (REG_P (SET_DEST (exp)) && (REG_P (SET_SRC (exp))))
1440+			return;
1441+
1442+		/* Moving memory into a register (load): Sets cc's. */
1443+		if (REG_P (SET_DEST (exp)) && src_code == MEM) {
1444+			cc_status.value1 = SET_SRC (exp);
1445+			cc_status.value2 = SET_DEST (exp);
1446+			return;
1447+		}
1448+
1449+		/* Moving register into memory (store): Sets cc's. */
1450+		if (dst_code == MEM && REG_P (SET_SRC (exp))) {
1451+			cc_status.value1 = SET_SRC (exp);
1452+			cc_status.value2 = SET_DEST (exp);
1453+			return;
1454+		}
1455+
1456+		/* Function calls clobber the cc's.  */
1457+		else if (GET_CODE (SET_SRC (exp)) == CALL) {
1458+			CC_STATUS_INIT;
1459+			return;
1460+		}
1461+
1462+		/* Tests and compares set the cc's in predictable ways.  */
1463+		else if (SET_DEST (exp) == cc0_rtx)
1464+		{
1465+			cc_status.flags = 0;
1466+			cc_status.value1 = SET_SRC (exp);
1467+			cc_status.value2 = SET_DEST (exp);
1468+			return;
1469+		}
1470+
1471+		else if (A_REG_P (SET_DEST (exp)))
1472+		{
1473+			CC_STATUS_INIT;
1474+			return;
1475+		}
1476+
1477+		else
1478+		{
1479+			/* Certain instructions affect the condition codes. */
1480+			switch (src_code)
1481+			{
1482+				case PLUS:
1483+				case MINUS:
1484+				case NEG:
1485+				case ASHIFT:
1486+					/* These instructions set the condition codes,
1487+					 * and may modify the V bit. */
1488+					cc_status.flags |= CC_NO_OVERFLOW;
1489+					/* FALLTHRU */
1490+
1491+				case AND:
1492+				case IOR:
1493+				case XOR:
1494+				case ASHIFTRT:
1495+				case LSHIFTRT:
1496+					/* These instructions set the condition codes,
1497+					 * but cannot overflow (V=0). */
1498+					cc_status.value1 = SET_SRC (exp);
1499+					cc_status.value2 = SET_DEST (exp);
1500+					break;
1501+
1502+				default:
1503+					/* Everything else is clobbered */
1504+					CC_STATUS_INIT;
1505+			}
1506+			return;
1507+		}
1508+	} /* SET */
1509+
1510+	else if (GET_CODE (exp) == PARALLEL
1511+		&& GET_CODE (XVECEXP (exp, 0, 0)) == SET)
1512+	{
1513+		if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
1514+			return;
1515+		if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
1516+		{
1517+			CC_STATUS_INIT;
1518+			cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
1519+			return;
1520+		}
1521+	}
1522+
1523+	/*** default action if we haven't recognized something
1524+	and returned earlier ***/
1525+	CC_STATUS_INIT;
1526+}
1527+
1528+
1529+/** Returns nonzero if the expression EXP can be implemented using one
1530+ * of the 6809's single operand instructions. */
1531+int
1532+m6809_single_operand_operator (rtx exp)
1533+{
1534+	rtx op1;
1535+	HOST_WIDE_INT val;
1536+	enum rtx_code code;
1537+
1538+	debug_rtx(exp);
1539+
1540+	code = GET_CODE (exp);
1541+
1542+	/* Unary operators always qualify */
1543+	switch (code)
1544+	{
1545+		case NEG:
1546+		case NOT:
1547+			return 1;
1548+
1549+		default:
1550+			break;
1551+	}
1552+
1553+	/* Binary operators can only qualify if the second
1554+	 * argument is a CONST_INT of certain value. */
1555+	op1 = XEXP (exp, 1);
1556+	if (GET_CODE (op1) != CONST_INT)
1557+		return 0;
1558+	val = INTVAL (op1);
1559+	switch (code)
1560+	{
1561+		case PLUS:
1562+		case MINUS:
1563+			if (val == -1 || val == 1)
1564+				return 1;
1565+			break;
1566+
1567+		case ASHIFT:
1568+		case ASHIFTRT:
1569+		case LSHIFTRT:
1570+		case ROTATE:
1571+		case ROTATERT:
1572+			if (val == 1)
1573+				return 1;
1574+			break;
1575+
1576+		default:
1577+			break;
1578+	}
1579+
1580+	return 0;
1581+}
1582+
1583+
1584+/** Return a bitarray of the hard registers which are used by a function. */
1585+unsigned int
1586+m6809_get_live_regs (void)
1587+{
1588+	unsigned int regs = 0;
1589+	int regno;
1590+
1591+	if (frame_pointer_needed)
1592+		regs |= (1 << HARD_FRAME_POINTER_REGNUM);
1593+
1594+	for (regno = HARD_X_REGNUM; regno <= HARD_U_REGNUM; regno++)
1595+		if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
1596+			regs |= (1 << regno);
1597+
1598+	return regs;
1599+}
1600+
1601+
1602+/** Return a printable version of a list of hard registers, suitable
1603+ * for use in a PSHx or PULx insn. */
1604+const char *
1605+m6809_get_regs_printable (unsigned int regs)
1606+{
1607+	static char list[64];
1608+	char *listp = list;
1609+	unsigned int regno;
1610+
1611+	for (regno=0; regno < FIRST_PSEUDO_REGISTER; regno++)
1612+		if ((regs & (1 << regno)) && !S_REGNO_P (regno))
1613+			listp += sprintf (listp,
1614+				(listp == list) ? "%s" : ",%s", reg_names[regno]);
1615+
1616+	return list;
1617+}
1618+
1619+
1620+/** Return the total number of bytes covered by a set of hard registers. */
1621+unsigned int
1622+m6809_get_regs_size (unsigned int regs)
1623+{
1624+	unsigned int regno;
1625+	unsigned int size = 0;
1626+
1627+	for (regno=0; regno < FIRST_PSEUDO_REGISTER; regno++)
1628+	{
1629+		/* Only count register in the given register set */
1630+		if (REGSET_CONTAINS_P (regno, regs))
1631+		{
1632+			/* Add 1 or 2 byte, depending on the size of the register.
1633+			 * Since 'D' may be in both sets, check for WORD_REGSET first. */
1634+			if (REGSET_CONTAINS_P(regno, WORD_REGSET))
1635+				size += 2;
1636+			else if (REGSET_CONTAINS_P(regno, BYTE_REGSET))
1637+				size++;
1638+		}
1639+	}
1640+	return size;
1641+}
1642+
1643+
1644+/* Given the target of call instruction in X,
1645+ * return the tree node that contains the function declaration for
1646+ * that target.
1647+ *
1648+ * If the rtx or the tree do not appear valid for any reason,
1649+ * then return NULL_TREE.
1650+ */
1651+static tree call_target_decl (rtx x)
1652+{
1653+   tree decl;
1654+
1655+	/* Make sure the target is really a MEM. */
1656+	if (!x || !MEM_P (x))
1657+		return NULL_TREE;
1658+
1659+	/* Make sure the address is a SYMBOL_REF. */
1660+	x = XEXP (x, 0);
1661+	if (!x || (GET_CODE (x) != SYMBOL_REF))
1662+		return NULL_TREE;
1663+
1664+	/* Get the declaration of this symbol */
1665+	decl = SYMBOL_REF_DECL (x);
1666+
1667+	/* Make sure the declaration is really a function. */
1668+	if (!decl || (TREE_CODE(decl) != FUNCTION_DECL))
1669+		return NULL_TREE;
1670+
1671+   return decl;
1672+}
1673+
1674+
1675+/** Returns nonzero if a function, whose declaration is in DECL,
1676+ * was declared to have the attribute given by ATTR_NAME. */
1677+int
1678+m6809_function_has_type_attr_p (tree decl, const char *attr_name)
1679+{
1680+	tree type;
1681+
1682+	type = TREE_TYPE (decl);
1683+	return lookup_attribute (attr_name, TYPE_ATTRIBUTES (type)) != NULL;
1684+}
1685+
1686+
1687+
1688+/** Returns nonzero if the current function was declared to have the
1689+ * attribute given by ATTR_NAME. */
1690+int
1691+m6809_current_function_has_type_attr_p (const char *attr_name)
1692+{
1693+	return m6809_function_has_type_attr_p (current_function_decl, attr_name);
1694+}
1695+
1696+
1697+/** Return nonzero if the current function has no return value. */
1698+int
1699+m6809_current_function_is_void (void)
1700+{
1701+   return (VOID_TYPE_P (TREE_TYPE (TREE_TYPE (current_function_decl))));
1702+}
1703+
1704+
1705+/** Get the value of a declaration's 'bank', as set by the 'bank'
1706+ * attribute.  If no bank was declared, it returns NULL by default. */
1707+const char *
1708+m6809_get_decl_bank (tree decl)
1709+{
1710+	tree attr;
1711+
1712+	/* Lookup the 'bank' attribute.  If it does not exist, then
1713+	 * return NULL */
1714+	attr = lookup_attribute ("bank", DECL_ATTRIBUTES (decl));
1715+	if (attr == NULL_TREE)
1716+		return NULL;
1717+
1718+	/* Make sure it has a value assigned to it */
1719+	attr = TREE_VALUE (attr);
1720+	if (attr == NULL_TREE)
1721+	{
1722+		warning (WARNING_OPT "banked function did not declare a bank number");
1723+		return NULL;
1724+	}
1725+
1726+	/* Return the bank name */
1727+	attr = TREE_VALUE (attr);
1728+	return TREE_STRING_POINTER (attr);
1729+}
1730+
1731+
1732+void
1733+m6809_declare_function_name (FILE *asm_out_file, const char *name, tree decl)
1734+{
1735+	/* Check the function declaration for special properties.
1736+	 *
1737+	 * If the function was declare with __attribute__((bank)), output
1738+	 * assembler definitions to force the function to go into the named
1739+	 * bank.
1740+	 */
1741+	const char *bank_name = m6809_get_decl_bank (decl);
1742+	if (bank_name != NULL)
1743+	{
1744+		/* Declare __self_bank as a local assembler value that denotes
1745+		 * which bank the current function is in.  This is required only
1746+		 * when the bank actually changes. */
1747+		if (strcmp (bank_name, current_bank_name))
1748+		{
1749+			fprintf (asm_out_file, "__self_bank\t.equ %s\n", bank_name);
1750+			strcpy (current_bank_name, bank_name);
1751+		}
1752+
1753+		/* Declare a global assembler value that denotes which bank the
1754+		 * named function is in. */
1755+		fprintf (asm_out_file, "__%s_bank\t.gblequ %s\n", name, bank_name);
1756+
1757+		/* Force the current function into a new area */
1758+		fprintf (asm_out_file, "\t.bank bank_%s (FSFX=_%s)\n",
1759+			bank_name, bank_name);
1760+		fprintf (asm_out_file, "\t.area bank_%s (BANK=bank_%s)\n",
1761+			bank_name, bank_name);
1762+	}
1763+
1764+	/* Emit the label for the function's name */
1765+	ASM_OUTPUT_LABEL (asm_out_file, name);
1766+}
1767+
1768+#if 0
1769+/**
1770+ * Handle pragmas.  Note that only the last branch pragma seen in the 
1771+ * source has any affect on code generation.  
1772+ */
1773+
1774+#define BAD_PRAGMA(msgid, arg) \
1775+	do { warning (WARNING_OPT msgid, arg); return -1; } while (0)
1776+
1777+static int
1778+pragma_parse (const char *name, tree *sect)
1779+{
1780+  tree s, x;
1781+
1782+  if (pragma_lex (&x) != CPP_OPEN_PAREN)
1783+    BAD_PRAGMA ("missing '(' after '#pragma %s' - ignored", name);
1784+
1785+  if (pragma_lex (&s) != CPP_STRING)
1786+    BAD_PRAGMA ("missing section name in '#pragma %s' - ignored", name);
1787+
1788+  if (pragma_lex (&x) != CPP_CLOSE_PAREN)
1789+    BAD_PRAGMA ("missing ')' for '#pragma %s' - ignored", name);
1790+
1791+  if (pragma_lex (&x) != CPP_EOF)
1792+    warning (WARNING_OPT "junk at end of '#pragma %s'", name);
1793+
1794+  *sect = s;
1795+  return 0;
1796+}
1797+
1798+
1799+/*
1800+ * Handle #pragma section.
1801+ * This is deprecated; code should use __attribute__(section("name"))
1802+ * instead.
1803+ */
1804+void pragma_section (cpp_reader *pfile ATTRIBUTE_UNUSED)
1805+{
1806+	tree sect;
1807+
1808+	if (pragma_parse ("section", &sect))
1809+		return;
1810+
1811+	snprintf (code_section_op, 6+TREE_STRING_LENGTH (sect),
1812+		".area\t%s", TREE_STRING_POINTER (sect));
1813+	snprintf (data_section_op, 6+TREE_STRING_LENGTH (sect),
1814+		".area\t%s", TREE_STRING_POINTER (sect));
1815+
1816+	/* Mark a flag that sections have changed.  Upon emitting another
1817+	 * declaration, the new .area directive will be written. */
1818+	section_changed++;
1819+}
1820+#endif
1821+
1822+/**
1823+ * Check a `double' value for validity for a particular machine mode.
1824+ * Called by the CHECK_FLOAT_VALUE() machine-dependent macro.
1825+ */
1826+int
1827+check_float_value (enum machine_mode mode, double *d, int overflow)
1828+{
1829+	if (mode == SFmode) {
1830+		if (*d > 1.7014117331926443e+38) {
1831+			error("magnitude of constant too large for `float'");
1832+			*d = 1.7014117331926443e+38;
1833+		}
1834+		else if (*d < -1.7014117331926443e+38) {
1835+			error("magnitude of constant too large for `float'");
1836+			*d = -1.7014117331926443e+38;
1837+		}
1838+		else if ((*d > 0) && (*d < 2.9387358770557188e-39)) {
1839+			warning(WARNING_OPT "`float' constant truncated to zero");
1840+			*d = 0.0;
1841+		}
1842+		else if ((*d < 0) && (*d > -2.9387358770557188e-39)) {
1843+			warning(WARNING_OPT "`float' constant truncated to zero");
1844+			*d = 0.0;
1845+		}
1846+	}
1847+	return overflow;
1848+}
1849+
1850+
1851+
1852+/** Declare that the target supports named output sections. */
1853+bool m6809_have_named_section = (bool)1;
1854+
1855+
1856+/** Write to the assembler file a directive to place
1857+ * subsequent objects to a different section in the
1858+ * object file.  ASxxxx uses the "area" directive for
1859+ * this purpose.  It does not however support generalized
1860+ * alignment, and can only place items on an odd/even
1861+ * boundary. */
1862+void
1863+m6809_asm_named_section (
1864+	const char *name, 
1865+	unsigned int flags ATTRIBUTE_UNUSED,
1866+	tree decl)
1867+{
1868+	fprintf (asm_out_file, "\t.area\t%s\n", name);
1869+}
1870+
1871+
1872+enum reg_class
1873+m6809_preferred_reload_class (rtx x, enum reg_class regclass)
1874+{
1875+	/* Check cases based on type code of rtx */
1876+	switch (GET_CODE(x))
1877+	{
1878+		/*
1879+		 * Observation, 2015-07-19, William Astle
1880+		 *
1881+		 * The original comparison for range for 16 bits was wrong, adding 0x80
1882+		 * instead of 0x8000. Replaced both 8 bit and 16 bit comparisions with
1883+		 * a more straight forward range comparison - excessive cleverness isn't
1884+		 * really required here.
1885+		 */    
1886+		case CONST_INT:
1887+		   /* Constants that can fit into 1 byte should be
1888+			 * loaded into a Q_REGS reg */
1889+			if ((INTVAL(x) >= -128 && INTVAL(x) <= 127) &&
1890+//			if (((unsigned) (INTVAL(x) + 0x80) < 0x100) && 
1891+  				 (regclass > A_REGS))
1892+      		return Q_REGS;
1893+
1894+			/* 16-bit constants should be loaded into A_REGS
1895+			 * when possible.  gcc may already require A_REGS
1896+			 * or D_REGS for certain types of instructions.
1897+			 * This case applies mostly to simple copy operations
1898+			 * to/from memory when any register will do, but
1899+			 * it's best to avoid using D register since it is
1900+			 * needed for other things.
1901+			 */
1902+			else if ((INTVAL(x) >= -32768 && INTVAL(x) <= 32767) &&
1903+//			else if (((unsigned) (INTVAL(x) + 0x80) < 0x10000) &&
1904+  				 (regclass > A_REGS))
1905+      		return A_REGS;
1906+			break;
1907+
1908+		case SYMBOL_REF:
1909+		case LABEL_REF:
1910+			/* Addresses should always be loaded into A_REGS */
1911+			if (regclass >= A_REGS)
1912+				return (A_REGS);
1913+
1914+		default:
1915+			break;
1916+	}
1917+
1918+	/* Check cases based on mode of rtx */
1919+   if ((GET_MODE(x) == QImode) && (regclass != A_REGS))
1920+      return Q_REGS;
1921+
1922+	/* Default: return whatever class reload suggested */
1923+   return regclass;
1924+}
1925+
1926+
1927+/**
1928+ * Check a new declaration for the "section" attribute.
1929+ * If it exists, and the target section is "direct", then mark
1930+ * the declaration (in RTL) to indicate special treatment.
1931+ * When the variable is referenced later, we test for this flag
1932+ * and can emit special asm text to force the assembler to use
1933+ * short instructions.
1934+ */
1935+static void
1936+m6809_encode_section_info (tree decl, rtx rtl, int new_decl_p ATTRIBUTE_UNUSED)
1937+{
1938+   tree attr, id;
1939+   const char *name;
1940+   const char *decl_name;
1941+
1942+   /* We only care about variable declarations, not functions */
1943+   if (TREE_CODE (decl) != VAR_DECL)
1944+      return;
1945+
1946+	/* For debugging purposes only; grab the decl's name */
1947+   decl_name = IDENTIFIER_POINTER (DECL_NAME (decl));
1948+
1949+	/* Give up if the decl doesn't have any RTL */
1950+   if (!DECL_RTL (decl))
1951+      return;
1952+
1953+	/* See if it has a section attribute */
1954+   attr = lookup_attribute ("section", DECL_ATTRIBUTES (decl));
1955+   if (!attr)
1956+      return;
1957+
1958+	/* See if the section attribute has a value */
1959+   id = TREE_VALUE (TREE_VALUE (attr));
1960+   if (!id)
1961+      return;
1962+   name = TREE_STRING_POINTER (id);
1963+   if (!name)
1964+      return;
1965+
1966+	/* See if the value is 'direct'.  If so, mark it. */
1967+   if (!strcmp (name, "direct"))
1968+      SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
1969+}
1970+
1971+
1972+/**
1973+ * Output code to perform a complex shift, for which there is no
1974+ * direct support in the instruction set.
1975+ *
1976+ * shift1 is an instruction pattern for performing a 1-bit modification.
1977+ * This code wraps that pattern in a loop to perform the shift N times,
1978+ * where N is given by the address register in operands[2].
1979+ *
1980+ * To support 16-bit shifts, shift2 can also be provided: it is
1981+ * a second instruction to be included in the loop.  8-bit shift
1982+ * insns will pass NULL here.
1983+ *
1984+ * The insn length of shift1/shift2 is assumed to be 1 byte,
1985+ * which works in all of the cases it is needed so far.
1986+ */
1987+static void
1988+m6809_gen_register_shift (
1989+		rtx *operands,
1990+		const char *shift1,
1991+		const char *shift2 )
1992+{
1993+	char beq_pattern[32];
1994+   char bra_pattern[32];
1995+
1996+	int shiftlen = (shift1 && shift2) ? 2 : 1;
1997+	int cmplen = (REGNO (operands[2]) == HARD_X_REGNUM) ? 3 : 4;
1998+
1999+	int beq_offset = 2 + shiftlen + 2;
2000+	int bra_offset = shiftlen + 2 + cmplen + 2;
2001+
2002+	sprintf (beq_pattern, "beq\t.+%d", beq_offset);
2003+	sprintf (bra_pattern, "bra\t.-%d", bra_offset);
2004+
2005+	output_asm_insn ("pshs\t%2", operands);
2006+	output_asm_insn ("lea%2\t-1,%2", operands);
2007+   output_asm_insn ("cmp%2\t#-1", operands);
2008+   output_asm_insn (beq_pattern, operands);
2009+	if (shift1)
2010+		output_asm_insn (shift1, operands);
2011+	if (shift2)
2012+		output_asm_insn (shift2, operands);
2013+	output_asm_insn (bra_pattern, operands);
2014+	output_asm_insn ("puls\t%2", operands);
2015+}
2016+
2017+
2018+/** Generate RTL for the upper 8-bits of a 16-bit constant. */
2019+rtx
2020+gen_rtx_const_high (rtx r)
2021+{
2022+   unsigned char v = (INTVAL (r) >> 8) & 0xFF;
2023+	signed char s = (signed char)v;
2024+   return gen_int_mode (s, QImode);
2025+}
2026+
2027+
2028+/** Generate RTL for the lower 8-bits of a 16-bit constant. */
2029+rtx
2030+gen_rtx_const_low (rtx r)
2031+{
2032+   unsigned char v = INTVAL (r) & 0xFF;
2033+	signed char s = (signed char)v;
2034+   return gen_int_mode (s, QImode);
2035+}
2036+
2037+
2038+/** Generate RTL to allocate/free bytes on the stack.
2039+ * CODE is given as MINUS when allocating and PLUS when freeing,
2040+ * to match the semantics of a downward-growing stack.  SIZE
2041+ * is always given as a positive integer.
2042+ */
2043+static rtx
2044+gen_rtx_stack_adjust (enum rtx_code code, int size)
2045+{
2046+	if (size <= 0)
2047+		return NULL_RTX;
2048+
2049+	if (code == MINUS)
2050+		size = -size;
2051+
2052+	return gen_rtx_SET (Pmode, stack_pointer_rtx, 
2053+		gen_rtx_PLUS (Pmode, stack_pointer_rtx,
2054+			gen_int_mode (size, HImode)));
2055+}
2056+
2057+
2058+/** Generate RTL to push/pop a set of registers. */
2059+rtx
2060+gen_rtx_register_pushpop (int op, int regs)
2061+{
2062+	rtx nregs = gen_int_mode (regs, QImode);
2063+	
2064+	if (op == UNSPEC_PUSH_RS)
2065+		return gen_register_push (nregs);
2066+	else
2067+		return gen_register_pop (nregs);
2068+}
2069+
2070+
2071+/* Given a register set REGS, where the bit positions correspond to
2072+ * hard register numbers, return another bitmask that represents the
2073+ * order in which those registers would be pushed/popped.
2074+ * Registers that are pushed first have higher bit positions.
2075+ * The pop order is just the reverse bitmask.
2076+ * These values are the same as the bitmasks actually used in the
2077+ * machine instructions. */
2078+static unsigned int
2079+register_push_order (int regs)
2080+{
2081+	unsigned int order = 0;
2082+
2083+	if (REGSET_CONTAINS_P (HARD_PC_REGNUM, regs))
2084+		order |= 0x80;
2085+	if (REGSET_CONTAINS_P (HARD_U_REGNUM, regs))
2086+		order |= 0x40;
2087+	if (REGSET_CONTAINS_P (HARD_Y_REGNUM, regs))
2088+		order |= 0x20;
2089+	if (REGSET_CONTAINS_P (HARD_X_REGNUM, regs))
2090+		order |= 0x10;
2091+	if (REGSET_CONTAINS_P (HARD_DP_REGNUM, regs))
2092+		order |= 0x8;
2093+	if (REGSET_CONTAINS_P (HARD_B_REGNUM, regs))
2094+		order |= 0x4;
2095+	if (REGSET_CONTAINS_P (HARD_A_REGNUM, regs))
2096+		order |= 0x2;
2097+	if (REGSET_CONTAINS_P (HARD_CC_REGNUM, regs))
2098+		order |= 0x1;
2099+
2100+	if (REGSET_CONTAINS_P (HARD_D_REGNUM, regs))
2101+		order |= (0x4 | 0x2);
2102+	return order;
2103+}
2104+
2105+
2106+/* Returns nonzero if two consecutive push or pop instructions,
2107+ * as determined by the OP, can be merged into a single instruction.
2108+ * The first instruction in the sequence pushes/pops REGS1; the
2109+ * second applies to REGS2.
2110+ *
2111+ * If true, the resulting instruction can use (regs1 | regs2)
2112+ * safely.
2113+ */
2114+int
2115+m6809_can_merge_pushpop_p (int op, int regs1, int regs2)
2116+{
2117+	/* Register sets must not overlap */
2118+	if (regs1 & regs2)
2119+		return 0;
2120+
2121+	if (op == UNSPEC_PUSH_RS)
2122+		return (register_push_order (regs1) > register_push_order (regs2));
2123+	else if (op == UNSPEC_POP_RS)
2124+		return (register_push_order (regs1) < register_push_order (regs2));
2125+	else
2126+		return 0;
2127+}
2128+
2129+
2130+/** Emit instructions for making a library call.
2131+ * MODE is the mode of the operation.
2132+ * NAME is the library function name.
2133+ * OPERANDS is the rtx array provided by the recognizer.
2134+ * COUNT is the number of input operands to the call, and
2135+ * should be 1 for a unary op or 2 for a binary op.
2136+ */
2137+void
2138+emit_libcall_insns (enum machine_mode mode, 
2139+	const char *name, 
2140+	rtx *operands,
2141+	int count)
2142+{
2143+	/* Generate an rtx for the call target. */
2144+	rtx symbol = gen_rtx_SYMBOL_REF (Pmode, name);
2145+
2146+	/* Emit the library call.  Slightly different based
2147+	on the number of operands */
2148+	if (count == 2)
2149+		emit_library_call (symbol, LCT_NORMAL, mode,
2150+			2, operands[1], mode, operands[2], mode);
2151+	else
2152+		emit_library_call (symbol, LCT_NORMAL, mode,
2153+			1, operands[1], mode);
2154+
2155+	/* The library call is expected to put its result
2156+	in LIBCALL_VALUE, so need to copy it into the destination. */
2157+	emit_move_insn (operands[0], LIBCALL_VALUE(mode));
2158+}
2159+
2160+
2161+/**
2162+ * A small helper function that writes out a single branch instruction.
2163+ * OPCODE is the short name, e.g. "ble".
2164+ * OPERANDS has the rtx for the target label.
2165+ * LONG_P is nonzero if we are emitting a long branch, and need to
2166+ * prepend an 'l' to the opcode name.
2167+ */
2168+void output_branch_insn1 (const char *opcode, rtx *operands, int long_p)
2169+{
2170+	char pattern[64];
2171+	sprintf (pattern, "%s%s\t%%l0", long_p ? "l" : "", opcode);
2172+	output_asm_insn (pattern, operands);
2173+}
2174+
2175+/**
2176+ * Output a branch/conditional branch insn of the proper
2177+ * length.  code identifies the particular branch insn.
2178+ * operands holds the branch target in operands[0].
2179+ * length says what the size of this insn should be.
2180+ * Based on the length, we know whether it should be a
2181+ * short (8-bit) or long (16-bit) branch.
2182+ */
2183+const char *
2184+output_branch_insn (enum rtx_code code, rtx *operands, int length)
2185+{
2186+	int shortform; 
2187+
2188+	/* Decide whether or not to use the long or short form.
2189+	 * Calculate automatically based on insn lengths. */
2190+   shortform = ((length > 2) ? 0 : 1);
2191+
2192+	/* Determine the proper opcode.
2193+	 * Use the short (2-byte) opcode if the target is within
2194+	 * reach.  Otherwise, use jmp (3-byte opcode), unless
2195+	 * compiling with -fpic, in which case we'll need to use
2196+	 * lbra (4-byte opcode).
2197+	 */
2198+	switch (code)
2199+	{
2200+		case LABEL_REF: 
2201+			if (shortform)
2202+				output_branch_insn1 ("bra", operands, 0);
2203+			else if (flag_pic)
2204+				output_branch_insn1 ("bra", operands, 1);
2205+			else
2206+				output_branch_insn1 ("jmp", operands, 0);
2207+			break;
2208+		case EQ:
2209+			output_branch_insn1 ("beq", operands, !shortform);
2210+			break;
2211+		case NE:
2212+			output_branch_insn1 ("bne", operands, !shortform);
2213+			break;
2214+		case GT:
2215+			output_branch_insn1 ("bgt", operands, !shortform);
2216+			break;
2217+		case GTU:
2218+			output_branch_insn1 ("bhi", operands, !shortform);
2219+			break;
2220+		case LT:
2221+			if (cc_prev_status.flags & CC_NO_OVERFLOW)
2222+			{
2223+				output_branch_insn1 ("bmi", operands, !shortform);
2224+			}
2225+			else
2226+			{
2227+				output_branch_insn1 ("blt", operands, !shortform);
2228+			}
2229+			break;
2230+		case LTU:
2231+			output_branch_insn1 ("blo", operands, !shortform);
2232+			break;
2233+		case GE:
2234+			if (cc_prev_status.flags & CC_NO_OVERFLOW)
2235+			{
2236+				output_branch_insn1 ("bpl", operands, !shortform);
2237+			}
2238+			else
2239+			{
2240+				output_branch_insn1 ("bge", operands, !shortform);
2241+			}
2242+			break;
2243+		case GEU:
2244+			output_branch_insn1 ("bhs", operands, !shortform);
2245+			break;
2246+		case LE:
2247+			if (cc_prev_status.flags & CC_NO_OVERFLOW)
2248+			{
2249+				output_branch_insn1 ("bmi", operands, !shortform);
2250+				output_branch_insn1 ("beq", operands, !shortform);
2251+			}
2252+			else
2253+			{
2254+				output_branch_insn1 ("ble", operands, !shortform);
2255+			}
2256+			break;
2257+		case LEU:
2258+			output_branch_insn1 ("bls", operands, !shortform);
2259+			break;
2260+		default:
2261+			abort();
2262+			break;
2263+	}
2264+	return "";
2265+}
2266+
2267+
2268+/** Returns the "cost" of an RTL expression.
2269+ * In general, the expression "COSTS_N_INSNS(1)" is used to represent
2270+ * the cost of a fast 8-bit arithmetic instruction that operates on
2271+ * a reg/mem or a reg/immed.  Other costs are relative to this.
2272+ *
2273+ * Notes:
2274+ * - The cost of a REG is always zero; this cannot be changed.
2275+ *
2276+ * - On the 6809, instructions on two registers will nearly always take
2277+ *   longer than those that operate on a register and a constant/memory,
2278+ *   because of the way the instruction set is structured.
2279+ *
2280+ * TODO: multiply HImode by 2 should be done via shifts, instead of add.
2281+ */
2282+static bool
2283+m6809_rtx_costs (rtx X, int code, int outer_code ATTRIBUTE_UNUSED,
2284+	int *total, bool speed)
2285+{
2286+	int has_const_arg = 0;
2287+	HOST_WIDE_INT const_arg;
2288+	enum machine_mode mode;
2289+	int nargs = 1;
2290+	rtx op0, op1;
2291+
2292+	/* Data RTXs return a value between 0-3, depending on complexity.
2293+	All of these are less than COSTS_N_INSNS(1). */
2294+	switch (code)
2295+	{
2296+		case CC0:
2297+		case PC:
2298+			*total = 0;
2299+			return true;
2300+
2301+ 		case CONST_INT:
2302+    		if (X == const0_rtx)
2303+			{
2304+				*total = 0;
2305+				return true;
2306+			}
2307+			else if ((unsigned) INTVAL (X) < 077) 
2308+			{
2309+				*total = 1;
2310+				return true;
2311+			}
2312+			else
2313+			{
2314+				*total = 2;
2315+				return true;
2316+			}
2317+
2318+ 		case LABEL_REF: case CONST:
2319+   		*total = 2;
2320+			return true;
2321+
2322+ 		case SYMBOL_REF:
2323+			/* References to memory are made cheaper if they have
2324+			 * the 'direct' mode attribute set */
2325+			*total = (SYMBOL_REF_FLAG (X)) ? 1 : 2;
2326+			return true;
2327+
2328+		case MEM:
2329+			/* See what form of address was given */
2330+			X = XEXP (X, 0);
2331+			switch (GET_CODE (X))
2332+			{
2333+ 				case SYMBOL_REF:
2334+					*total = (SYMBOL_REF_FLAG (X)) ? 1 : 2;
2335+					break;
2336+
2337+				case CONST_INT:
2338+					*total = 2;
2339+					break;
2340+
2341+				case MEM:
2342+					*total = COSTS_N_INSNS (1) + 2;
2343+					break;
2344+
2345+				default:
2346+					break;
2347+			}
2348+			return true;
2349+
2350+ 		case CONST_DOUBLE:
2351+			/* TODO : not sure about this value. */
2352+   		*total = 3;
2353+			return true;
2354+
2355+		default:
2356+			break;
2357+	}
2358+
2359+	/* Decode the rtx */
2360+	mode = GET_MODE (X);
2361+	op0 = XEXP (X, 0);
2362+	op1 = XEXP (X, 1);
2363+
2364+	/* We don't implement anything in SImode or greater. */
2365+	if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (SImode))
2366+	{
2367+		*total = COSTS_N_INSNS (100);
2368+		return true;
2369+	}
2370+
2371+	/* Figure out if there is a constant argument, and its value. */
2372+	if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
2373+		|| GET_RTX_CLASS (code) == RTX_COMM_ARITH)
2374+	{
2375+		nargs = 2;
2376+		if (GET_CODE (op1) == CONST_INT)
2377+		{
2378+			has_const_arg = 1;
2379+			const_arg = INTVAL (op1);
2380+		}
2381+	}
2382+
2383+	/* Penalize a reg/reg operation by adding MEMORY_MOVE_COST,
2384+	 * Ignore soft registers, since these are really in memory.
2385+	 *
2386+	 * TODO: penalize HImode reg/reg for most operations, except maybe
2387+	 * additions since index registers allow for that.
2388+	 *
2389+	 * TODO: shifts by constant N do not always require N instructions;
2390+	 * some of this can be done cheaper.  The number of actual insns can be
2391+	 * predicted well.
2392+	 */
2393+	if (nargs == 2 && REAL_REG_P (op0) && REAL_REG_P (op1))
2394+	{
2395+		*total = MEMORY_MOVE_COST (mode, Q_REGS, 0);
2396+	}
2397+	else
2398+	{
2399+		*total = 0;
2400+	}
2401+
2402+	/* Operator RTXs are counted as COSTS_N_INSNS(N), where N is
2403+	the estimated number of actual machine instructions needed to
2404+	perform the computation.  Some small adjustments are made since
2405+	some "instructions" are more complex than others. */
2406+	switch (code)
2407+	{
2408+		case PLUS: case MINUS: case COMPARE:
2409+			/* 6809 handles these natively in QImode, and in HImode as long
2410+			 * as operand 1 is constant. */
2411+			if (mode == QImode || (mode == HImode && has_const_arg))
2412+				*total += COSTS_N_INSNS (1);
2413+			else 
2414+				*total += COSTS_N_INSNS (GET_MODE_SIZE (mode));
2415+
2416+			/* -1, 0, and 1 can be done using inherent instructions
2417+			 * for PLUS and MINUS in QImode, so don't add extra cost. */
2418+  			if (has_const_arg
2419+				&& (mode == QImode || mode == HImode)
2420+				&& (const_arg == -1 || const_arg == 0 || const_arg == 1)
2421+				&& (code == PLUS || code == MINUS))
2422+			{
2423+				return true;
2424+			}
2425+			break;
2426+
2427+		case AND: case IOR: case XOR:
2428+		case NEG: case NOT:
2429+			/* 6809 handles these natively in QImode, but requires
2430+			 * splitting in HImode.   Treat these as 2 insns. */
2431+			*total += COSTS_N_INSNS (1) * GET_MODE_SIZE (mode);
2432+			break;
2433+
2434+  		case ASHIFT: case ASHIFTRT: case LSHIFTRT:
2435+  		case ROTATE: case ROTATERT:
2436+			/* 6809 can do shift/rotates of a QImode by a constant in
2437+			 * 1 insn times the shift count, or in HImode by a constant 
2438+			 * by splitting to 2 insns.
2439+			 *
2440+			 * Shift by a nonconstant will take significantly longer
2441+			 * than any of these. */
2442+  			if (has_const_arg)
2443+			{
2444+				const_arg %= (GET_MODE_SIZE (mode) * 8);
2445+				if (const_arg == 0)
2446+				{
2447+					*total += COSTS_N_INSNS(1);
2448+					return true;
2449+				}
2450+
2451+				/* HImode shifts greater than 8 get optimized due
2452+				 * to register transfer from b to a; this cuts down the
2453+				 * cost. */
2454+				if (const_arg >= 8)
2455+				{
2456+					*total += COSTS_N_INSNS (1);
2457+					const_arg -= 8;
2458+				}
2459+
2460+				/* The computed cost is 'const_arg' 1-bit shifts, doubled
2461+				if in HImode, minus the cost of the constant itself which
2462+				will be added in later but really shouldn't be. */
2463+				*total += COSTS_N_INSNS (const_arg) * GET_MODE_SIZE (mode) - 1;
2464+				return true;
2465+			}
2466+			else
2467+			{
2468+				/* It may take up to 7 iterations of about 6-7 real
2469+				 * instructions, so make this expensive. */
2470+				*total += COSTS_N_INSNS (50);
2471+			}
2472+  			break;
2473+
2474+		case MULT:
2475+ 		{
2476+ 			/* Multiply is cheap when both arguments are 8-bits.  They
2477+ 			could be QImode, or QImode widened to HImode, or a constant
2478+ 			that fits into 8-bits.  As long as both operands qualify,
2479+ 			we can use a single mul instruction.
2480+  
2481+ 			Assume that fast multiply can be used, and change this if we find
2482+ 			differently... */
2483+ 			int ok_for_qihi3 = 1;
2484+  
2485+ 			/* Check the first operand */	
2486+ 			switch (GET_MODE (op0))
2487+ 			{
2488+ 				case QImode:
2489+ 					break;
2490+ 				case HImode:
2491+ 					if (GET_CODE (op0) != SIGN_EXTEND && GET_CODE (op0) != ZERO_EXTEND)
2492+  						ok_for_qihi3 = 0;
2493+ 					break;
2494+ 				default:
2495+ 					ok_for_qihi3 = 0;
2496+ 					break;
2497+  			}
2498+ 
2499+			/* Likewise, check the second operand.  This is where constants may appear. */
2500+ 			switch (GET_MODE (op1))
2501+ 			{
2502+ 				case QImode:
2503+ 					break;
2504+ 				case HImode:
2505+					if (GET_CODE (op1) != SIGN_EXTEND && GET_CODE (op1) != ZERO_EXTEND)
2506+ 						ok_for_qihi3 = 0;
2507+ 					break;
2508+ 				case VOIDmode:
2509+					if (!CONST_OK_FOR_LETTER_P (const_arg, 'K'))
2510+ 						ok_for_qihi3 = 0;
2511+					break;
2512+ 				default:
2513+ 					ok_for_qihi3 = 0;
2514+ 					break;
2515+ 			}
2516+ 
2517+ 			/* Fast multiply takes about 4 times as many cycles as a normal
2518+ 			arithmetic operation.  Otherwise, it will take an expensive libcall. */
2519+ 			if (ok_for_qihi3)
2520+ 				*total += COSTS_N_INSNS (4);
2521+ 			else
2522+ 				*total = COSTS_N_INSNS (50);
2523+  	  		break;
2524+ 		}
2525+
2526+		case DIV: case UDIV: case MOD: case UMOD:
2527+			/* These all require more expensive libcalls. */
2528+			*total += COSTS_N_INSNS (100);
2529+  			break;
2530+
2531+		/* TODO : TRUNCATE, SIGN_EXTEND, and ZERO_EXTEND */
2532+
2533+		/* These can normally be done with autoincrement, etc., so
2534+		 * don't charge for them. */
2535+		case PRE_DEC:
2536+		case PRE_INC:
2537+		case POST_DEC:
2538+		case POST_INC:
2539+			break;
2540+
2541+		default:
2542+			break;
2543+	}
2544+
2545+	/* Always return false, and let the caller gather the costs
2546+	 * of the operands */
2547+	return false;
2548+}
2549+
2550+
2551+static tree
2552+m6809_handle_fntype_attribute (tree *node, tree name,
2553+	tree args ATTRIBUTE_UNUSED,
2554+	int flags ATTRIBUTE_UNUSED,
2555+	bool *no_add_attrs)
2556+{
2557+	if (TREE_CODE (*node) != FUNCTION_TYPE)
2558+	{
2559+		warning (WARNING_OPT "'%s' only valid for functions", 
2560+			IDENTIFIER_POINTER (name));
2561+		*no_add_attrs = TRUE;
2562+	}
2563+
2564+	return NULL_TREE;
2565+}
2566+
2567+
2568+static tree
2569+m6809_handle_data_type_attribute (tree *node ATTRIBUTE_UNUSED,
2570+	tree name ATTRIBUTE_UNUSED,
2571+	tree args ATTRIBUTE_UNUSED,
2572+	int flags ATTRIBUTE_UNUSED,
2573+	bool *no_add_attrs ATTRIBUTE_UNUSED)
2574+{
2575+	return NULL_TREE;
2576+}
2577+
2578+
2579+
2580+static tree
2581+m6809_handle_default_attribute (tree *node ATTRIBUTE_UNUSED, 
2582+	tree name ATTRIBUTE_UNUSED,
2583+	tree args ATTRIBUTE_UNUSED,
2584+	int flags ATTRIBUTE_UNUSED,
2585+	bool *no_add_attrs ATTRIBUTE_UNUSED )
2586+{
2587+	return NULL_TREE;
2588+}
2589+
2590+
2591+/* Table of valid machine attributes */
2592+const struct attribute_spec m6809_attribute_table[] = { /*
2593+{ name,        min, max, decl,  type, fntype, handler } */
2594+{ "interrupt", 0,   0,   false, true,  true,  m6809_handle_fntype_attribute },
2595+{ "naked",     0,   0,   false, true,  true,  m6809_handle_fntype_attribute },
2596+{ "far",       0,   1,   false, true,  true,  m6809_handle_fntype_attribute },
2597+{ "bank",      0,   1,   true,  false, false, m6809_handle_default_attribute },
2598+{ "boolean",   0,   0,   false, true,  false, m6809_handle_data_type_attribute },
2599+{ NULL,        0,   0,   false, true,  false, NULL },
2600+};
2601+
2602+
2603+/** Initialize builtin routines for the 6809. */
2604+void
2605+m6809_init_builtins (void)
2606+{
2607+	/* Create type trees for each function signature required.
2608+	 *
2609+	 * void_ftype_void = void f(void)
2610+	 * void_ftype_uchar = void f(unsigned char)
2611+	 * uchar_ftype_uchar2 = unsigned char f (unsigned char, unsigned char)
2612+	 */
2613+	tree void_ftype_void = 
2614+		build_function_type (void_type_node, void_list_node);
2615+
2616+	tree void_ftype_uchar =
2617+		build_function_type (void_type_node,
2618+			tree_cons (NULL_TREE, unsigned_char_type_node, void_list_node));
2619+
2620+	tree uchar_ftype_uchar2 =
2621+		build_function_type (unsigned_char_type_node,
2622+			tree_cons (NULL_TREE, unsigned_char_type_node, 
2623+				tree_cons (NULL_TREE, unsigned_char_type_node, void_list_node)));
2624+
2625+	/* Register each builtin function. */
2626+	add_builtin_function ("__builtin_swi", void_ftype_void,
2627+		M6809_SWI, BUILT_IN_MD, NULL, NULL_TREE);
2628+
2629+	add_builtin_function ("__builtin_swi2", void_ftype_void,
2630+		M6809_SWI2, BUILT_IN_MD, NULL, NULL_TREE);
2631+
2632+	add_builtin_function ("__builtin_swi3", void_ftype_void,
2633+		M6809_SWI3, BUILT_IN_MD, NULL, NULL_TREE);
2634+
2635+	add_builtin_function ("__builtin_cwai", void_ftype_uchar,
2636+		M6809_CWAI, BUILT_IN_MD, NULL, NULL_TREE);
2637+
2638+	add_builtin_function ("__builtin_sync", void_ftype_void,
2639+		M6809_SYNC, BUILT_IN_MD, NULL, NULL_TREE);
2640+
2641+	add_builtin_function ("__builtin_nop", void_ftype_void,
2642+		M6809_NOP, BUILT_IN_MD, NULL, NULL_TREE);
2643+
2644+	add_builtin_function ("__builtin_blockage", void_ftype_void,
2645+		M6809_BLOCKAGE, BUILT_IN_MD, NULL, NULL_TREE);
2646+
2647+	add_builtin_function ("__builtin_add_decimal", uchar_ftype_uchar2,
2648+		M6809_ADD_DECIMAL, BUILT_IN_MD, NULL, NULL_TREE);
2649+
2650+	add_builtin_function ("__builtin_add_carry", uchar_ftype_uchar2,
2651+		M6809_ADD_CARRY, BUILT_IN_MD, NULL, NULL_TREE);
2652+
2653+	add_builtin_function ("__builtin_sub_carry", uchar_ftype_uchar2,
2654+		M6809_SUB_CARRY, BUILT_IN_MD, NULL, NULL_TREE);
2655+}
2656+
2657+
2658+/** Used by m6809_expand_builtin, given a tree ARGLIST which
2659+ * refers to the operands of a builtin call, return an rtx
2660+ * that represents the nth operand, as denoted by OPNUM, which
2661+ * is a zero-based integer.  MODE gives the expected mode
2662+ * of the operand.
2663+ *
2664+ * This rtx is suitable for use in the emitted RTL for the
2665+ * builtin instruction. */
2666+rtx
2667+m6809_builtin_operand (tree arglist, enum machine_mode mode, int opnum)
2668+{
2669+	tree arg;
2670+	rtx r;
2671+
2672+	arg = CALL_EXPR_ARG (arglist, opnum);
2673+
2674+	/* Convert the tree to RTL */
2675+	r = expand_expr (arg, NULL_RTX, mode, EXPAND_NORMAL);
2676+	if (r == NULL_RTX)
2677+		return NULL_RTX;
2678+	return r;
2679+}
2680+
2681+
2682+/** Expand a builtin that was registered in init_builtins into
2683+ * RTL.  */
2684+rtx
2685+m6809_expand_builtin (tree exp, 
2686+	rtx target, 
2687+	rtx subtarget ATTRIBUTE_UNUSED,
2688+	enum machine_mode mode ATTRIBUTE_UNUSED,
2689+	int ignore ATTRIBUTE_UNUSED )
2690+{
2691+   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
2692+	tree arglist = exp;
2693+	unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2694+	rtx r0, r1;
2695+
2696+	switch (fcode)
2697+	{
2698+		case M6809_SWI:
2699+			r0 = gen_rtx_CONST_INT (VOIDmode, 1);
2700+			emit_insn (target = gen_m6809_swi (r0));
2701+			return target;
2702+
2703+		case M6809_SWI2:
2704+			r0 = gen_rtx_CONST_INT (VOIDmode, 2);
2705+			emit_insn (target = gen_m6809_swi (r0));
2706+			return target;
2707+
2708+		case M6809_SWI3:
2709+			r0 = gen_rtx_CONST_INT (VOIDmode, 3);
2710+			emit_insn (target = gen_m6809_swi (r0));
2711+			return target;
2712+
2713+		case M6809_CWAI:
2714+			r0 = m6809_builtin_operand (arglist, QImode, 0);
2715+			emit_insn (target = gen_m6809_cwai (r0));
2716+			return target;
2717+
2718+		case M6809_SYNC:
2719+			emit_insn (target = gen_m6809_sync ());
2720+			return target;
2721+
2722+		case M6809_ADD_CARRY:
2723+			r0 = m6809_builtin_operand (arglist, QImode, 0);
2724+			r1 = m6809_builtin_operand (arglist, QImode, 1);
2725+			if (!target)
2726+				target = gen_reg_rtx (QImode);
2727+			emit_insn (gen_addqi3_carry (target, r0, r1));
2728+			return target;
2729+
2730+		case M6809_SUB_CARRY:
2731+			r0 = m6809_builtin_operand (arglist, QImode, 0);
2732+			r1 = m6809_builtin_operand (arglist, QImode, 1);
2733+			if (!target)
2734+				target = gen_reg_rtx (QImode);
2735+			emit_insn (gen_subqi3_carry (target, r0, r1));
2736+			return target;
2737+
2738+		case M6809_NOP:
2739+			emit_insn (target = gen_nop ());
2740+			return target;
2741+
2742+		case M6809_BLOCKAGE:
2743+			emit_insn (target = gen_blockage ());
2744+			return target;
2745+
2746+		case M6809_ADD_DECIMAL:
2747+			r0 = m6809_builtin_operand (arglist, QImode, 0);
2748+			r1 = m6809_builtin_operand (arglist, QImode, 1);
2749+			if (!target)
2750+				target = gen_reg_rtx (QImode);
2751+			emit_insn (gen_addqi3_decimal (target, r0, r1));
2752+			return target;
2753+
2754+		default:
2755+			warning (WARNING_OPT "unknown builtin expansion ignored");
2756+			return NULL_RTX;
2757+	}
2758+}
2759+
2760+
2761+
2762+/* Returns nonzero if 'x' represents a function that was declared
2763+ * as __noreturn__. */
2764+int
2765+noreturn_functionp (rtx x)
2766+{
2767+	tree decl = call_target_decl (x);
2768+
2769+	if (decl == NULL_TREE)
2770+		return 0;
2771+	else
2772+		return TREE_THIS_VOLATILE (decl);
2773+}
2774+
2775+
2776+const char *
2777+far_function_type_p (tree type)
2778+{
2779+	tree attr;
2780+	const char *page;
2781+
2782+	/* Return whether or not this decl has the far attribute */
2783+	attr = lookup_attribute ("far", TYPE_ATTRIBUTES (type));
2784+	if (attr == NULL_TREE)
2785+		return NULL;
2786+
2787+	/* If it is far, check for a value */
2788+	attr = TREE_VALUE (attr);
2789+	if (attr == NULL_TREE)
2790+	{
2791+		warning (WARNING_OPT "far code page not specified, using local value");
2792+		return far_code_page;
2793+	}
2794+
2795+	/* We have a TREE_LIST of attribute values, get the first one.
2796+	 * It should be an INTEGER_CST. */
2797+	attr = TREE_VALUE (attr);
2798+	page = TREE_STRING_POINTER (attr);
2799+	return page;
2800+}
2801+
2802+
2803+/* For a far function, returns the identifier that states which page
2804+ * it resides in.  Otherwise, returns NULL for ordinary functions. */
2805+const char *
2806+far_functionp (rtx x)
2807+{
2808+	tree decl, decl_type;
2809+	const char *page;
2810+
2811+	/* Find the FUNCTION_DECL corresponding to the rtx being called. */
2812+	decl = call_target_decl (x);
2813+	if (decl == NULL_TREE)
2814+		return NULL;
2815+
2816+	/* See if the function has the new 'banked' attribute.  These
2817+	 * are numeric instead of text */
2818+	page = m6809_get_decl_bank (decl);
2819+	if (page)
2820+		return page;
2821+
2822+	/* No, lookup the type of the function and see if the type
2823+	 * specifies far or not. */
2824+	decl_type = TREE_TYPE (decl);
2825+	if (decl_type == NULL_TREE)
2826+		return NULL;
2827+	return far_function_type_p (decl_type);
2828+}
2829+
2830+
2831+
2832+/** Outputs the assembly language for a far call. */
2833+void
2834+output_far_call_insn (rtx *operands, int has_return)
2835+{
2836+	static char page_data[64];
2837+	const char *called_page;
2838+
2839+  /* The logic is the same for functions whether or not there
2840+	* is a return value.  Skip over the return value in this
2841+	* case, so that the call location is always operands[0].  */
2842+  if (has_return)
2843+	  operands++;
2844+
2845+  /* Get the name of the page being called */
2846+  called_page = far_functionp (operands[0]);
2847+
2848+#if 0 /* TODO : broken logic */
2849+  /* See if the called page name is a 'bank' */
2850+  if (isdigit (*called_page))
2851+  {
2852+    /* New style banking */
2853+	 if (!strcmp (called_page, current_bank_name))
2854+	 {
2855+	 	/* Same page */
2856+  	  	output_asm_insn ("jsr\t%0", operands);
2857+	 }
2858+	 else
2859+	 {
2860+	 	/* Different page */
2861+		output_asm_insn ("jsr\t__far_call_handler\t;new style", operands);
2862+  	  	output_asm_insn ("\t.dw\t%0", operands);
2863+		sprintf (page_data, "\t.db\t%s", called_page);
2864+	 	output_asm_insn (page_data, operands);
2865+	 }
2866+	 return;
2867+  }
2868+#endif
2869+
2870+  /* Are we calling a different page than we are running in? */
2871+  if (!strcmp (called_page, far_code_page))
2872+  {
2873+    /* Same page : no need to execute a far call */
2874+		if (flag_pic)
2875+			output_asm_insn ("lbsr\t%C0", operands);
2876+		else
2877+			output_asm_insn ("jsr\t%0", operands);
2878+  }
2879+  else
2880+  {
2881+    /* Different page : need to emit far call thunk */
2882+
2883+    /* First output a call to the thunk for making far calls. */
2884+		if (flag_pic)
2885+			output_asm_insn ("lbsr\t__far_call_handler", operands);
2886+		else
2887+			output_asm_insn ("jsr\t__far_call_handler\t;old style", operands);
2888+  
2889+    /* Now output the name of the call site */
2890+    output_asm_insn ("\t.dw\t%C0", operands);
2891+  
2892+    /* Finally output the page number */
2893+    sprintf (page_data, "\t.db\t%s", far_functionp (operands[0]));
2894+    output_asm_insn (page_data, operands);
2895+  }
2896+}
2897+
2898+
2899+int
2900+m6809_init_cumulative_args (CUMULATIVE_ARGS cum ATTRIBUTE_UNUSED,
2901+     tree fntype,
2902+     rtx libname ATTRIBUTE_UNUSED)
2903+{
2904+	cum = 0;
2905+
2906+	/* For far functions, the current implementation does not allow for
2907+	 * stack parameters.  So note whenever the called function is far
2908+	 * and in a different page than the current one; such a function
2909+	 * should give an error if a stack parameter is generated. */
2910+	if (fntype)
2911+	{
2912+		const char *called_page = far_function_type_p (fntype);
2913+		if (called_page && strcmp (called_page, far_code_page) && !TARGET_FAR_STACK_PARAM)
2914+			cum |= CUM_STACK_INVALID;
2915+	}
2916+
2917+	if (fntype && TYPE_ARG_TYPES (fntype) != 0 &&
2918+		(TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
2919+	{
2920+		/* has variable arguments, cannot use registers */
2921+		cum |= (CUM_X_MASK | CUM_B_MASK | CUM_STACK_ONLY);
2922+	}
2923+
2924+	if (m6809_abi_version == M6809_ABI_VERSION_STACK)
2925+	{
2926+		/* cannot use registers ; only use the stack */
2927+		cum |= (CUM_STACK_ONLY | CUM_X_MASK | CUM_B_MASK);
2928+	}
2929+
2930+	return cum;
2931+}
2932+
2933+
2934+rtx
2935+m6809_function_arg_on_stack (CUMULATIVE_ARGS *cump)
2936+{
2937+	if (*cump & CUM_STACK_INVALID)
2938+	{
2939+		*cump &= ~CUM_STACK_INVALID;
2940+		error ("far function needs stack, will not work");
2941+	}
2942+	return NULL_RTX;
2943+}
2944+
2945+void m6809_asm_trampoline_template(FILE *f)
2946+{
2947+	fprintf(f, "ldy #0000\n");
2948+	fprintf(f, "jmp 0x0000\n");
2949+}
2950+
2951+/*
2952+ * Trampoline output:
2953+ *
2954+ * ldu #&cxt      4 bytes   --LDY- ?? ??
2955+ * jmp fnaddr     3 bytes   JMP ?? ??
2956+ */
2957+void
2958+m6809_initialize_trampoline (rtx tramp, tree fndecl, rtx cxt)
2959+{
2960+	rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
2961+	/* TODO - optimize by generating the entire trampoline code here,
2962+	 * and removing the template altogether, since there are only two
2963+	 * bytes there that matter. */
2964+	emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, 2)), cxt);
2965+	emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, 5)), fnaddr);
2966+}
2967+
2968+
2969+/** Echo the version of the compiler and the name of the source file
2970+ * at the beginning of each assembler output file.  asm_out_file
2971+ * is a global FILE * pointing to the output stream. */
2972+void
2973+m6809_asm_file_start (void)
2974+{
2975+	const char *module_name;
2976+
2977+	fprintf (asm_out_file, "\n;;; gcc for m6809 : %s %s\n",
2978+		__DATE__, __TIME__);
2979+	fprintf (asm_out_file, ";;; %s\n", version_string);
2980+
2981+	fprintf (asm_out_file, ";;; ABI version %d\n", m6809_abi_version);
2982+	fprintf (asm_out_file, ";;; %s\n",
2983+		(TARGET_BYTE_INT ? "-mint8" : "-mint16"));
2984+	if (TARGET_EXPERIMENT)
2985+		fprintf (asm_out_file, ";;; -mexperiment\n");
2986+	if (TARGET_WPC)
2987+		fprintf (asm_out_file, ";;; -mwpc\n");
2988+	if (TARGET_6309)
2989+		fprintf (asm_out_file, ";;; -m6309\n");
2990+
2991+	/* Print the name of the module, which is taken as the base name
2992+	 * of the input file.
2993+	 * See the 'User-Defined Symbols' section of the assembler
2994+	 * documentation for the rules on valid symbols.
2995+	 */
2996+	module_name = lbasename (main_input_filename);
2997+
2998+	fprintf (asm_out_file, "\t.module\t");
2999+
3000+	if (*module_name >= '0' && *module_name <= '9')
3001+		fprintf (asm_out_file, "_");
3002+
3003+	while (*module_name)
3004+	{
3005+		if ((*module_name >= '0' && *module_name <= '9')
3006+			|| (*module_name >= 'A' && *module_name <= 'Z')
3007+			|| (*module_name >= 'a' && *module_name <= 'z')
3008+			|| *module_name == '$'
3009+			|| *module_name == '.'
3010+			|| *module_name == '_')
3011+		{
3012+			fprintf (asm_out_file, "%c", *module_name);
3013+		}
3014+		else
3015+		{
3016+			fprintf (asm_out_file, "_");
3017+		}
3018+		module_name++;
3019+	}
3020+
3021+	fprintf (asm_out_file, "\n");
3022+}
3023+
3024+
3025+/** Returns true if prologue/epilogue code is required for the
3026+ * current function being compiled.
3027+ *
3028+ * This is just the inverse of whether the function is declared as
3029+ * 'naked'.
3030+ */
3031+int
3032+prologue_epilogue_required (void)
3033+{
3034+	return !m6809_current_function_has_type_attr_p ("naked")
3035+		&& !m6809_current_function_has_type_attr_p ("noreturn");
3036+}
3037+
3038+
3039+/** Expand RTL for function entry */
3040+void
3041+emit_prologue_insns (void)
3042+{
3043+  rtx insn;
3044+  unsigned int live_regs = m6809_get_live_regs ();
3045+  unsigned int frame_size = get_frame_size ();
3046+
3047+  /* Save all registers used, including the frame pointer */
3048+  if (live_regs && !m6809_current_function_has_type_attr_p ("interrupt"))
3049+  {
3050+    insn = emit_insn (
3051+      gen_rtx_register_pushpop (UNSPEC_PUSH_RS, live_regs));
3052+    RTX_FRAME_RELATED_P (insn) = 1;
3053+  }
3054+
3055+  /* Allocate space for local variables */
3056+  if (frame_size != 0)
3057+  {
3058+    insn = emit_insn (gen_rtx_stack_adjust (MINUS, frame_size));
3059+    RTX_FRAME_RELATED_P (insn) = 1;
3060+  }
3061+
3062+  /* Set the frame pointer if it is needed */
3063+  if (frame_pointer_needed)
3064+  {
3065+    insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3066+    RTX_FRAME_RELATED_P (insn) = 1;
3067+  }
3068+}
3069+
3070+
3071+/** Expand RTL for function exit */
3072+void
3073+emit_epilogue_insns (bool sibcall_p)
3074+{
3075+  unsigned int live_regs = m6809_get_live_regs ();
3076+  unsigned int frame_size = get_frame_size ();
3077+
3078+  if (frame_size != 0)
3079+    emit_insn (gen_rtx_stack_adjust (PLUS, frame_size));
3080+
3081+  if (sibcall_p)
3082+  {
3083+    if (live_regs)
3084+      emit_insn (gen_rtx_register_pushpop (UNSPEC_POP_RS, live_regs));
3085+  }
3086+  else
3087+  {
3088+    if (live_regs && !m6809_current_function_has_type_attr_p ("interrupt"))
3089+        emit_insn (
3090+          gen_rtx_register_pushpop (UNSPEC_POP_RS, PC_REGBIT | live_regs));
3091+  
3092+    if (m6809_current_function_has_type_attr_p ("interrupt"))
3093+      emit_jump_insn (gen_return_rti ());
3094+    else
3095+      emit_jump_insn (gen_return_rts ());
3096+  }
3097+}
3098+
3099+#if 0
3100+/** Predefine some preprocessor names according to the currently
3101+ * selected compiler options */
3102+void
3103+m6809_cpu_cpp_builtins (void)
3104+{
3105+	if (TARGET_6309)
3106+	{
3107+		builtin_define_std ("__M6309__");
3108+		builtin_define_std ("__m6309__");
3109+	}
3110+	else
3111+	{
3112+		builtin_define_std ("__M6809__");
3113+		builtin_define_std ("__m6809__");
3114+	}
3115+
3116+	if (TARGET_BYTE_INT)
3117+		builtin_define_std ("__int8__");
3118+	else
3119+		builtin_define_std ("__int16__");
3120+
3121+	switch (m6809_abi_version)
3122+	{
3123+		case M6809_ABI_VERSION_STACK:
3124+			builtin_define_std ("__regargs__");
3125+			builtin_define_std ("__ABI_STACK__");
3126+			break;
3127+		case M6809_ABI_VERSION_REGS:
3128+			builtin_define_std ("__ABI_REGS__");
3129+			break;
3130+		case M6809_ABI_VERSION_BX:
3131+			builtin_define_std ("__ABI_BX__");
3132+			break;
3133+		default:
3134+			break;
3135+	}
3136+
3137+	if (TARGET_WPC)
3138+		builtin_define_std ("__WPC__");
3139+
3140+	if (TARGET_DRET)
3141+		builtin_define_std ("__DRET__");
3142+}
3143+#endif
3144+
3145+#define MAX_ASM_ASCII_STRING 48
3146+
3147+void
3148+m6809_output_ascii (FILE *fp, const char *str, unsigned long size)
3149+{
3150+	unsigned long i;
3151+	bool use_ascii = true;
3152+
3153+	/* If the size is too large, then break this up into multiple
3154+	outputs.  The assembler can only output roughly 48 bytes at a
3155+	time.  Note that if there are lots of escape sequences in
3156+	the string, this may fail. */
3157+	if (size > MAX_ASM_ASCII_STRING)
3158+	{
3159+		m6809_output_ascii (fp, str, MAX_ASM_ASCII_STRING);
3160+		m6809_output_ascii (fp, str + MAX_ASM_ASCII_STRING, 
3161+			size - MAX_ASM_ASCII_STRING);
3162+		return;
3163+	}
3164+
3165+	/* Check for 8-bit codes, which cannot be embedded in an .ascii */
3166+	for (i = 0; i < size; i++)
3167+	{
3168+		int c = str[i] & 0377;
3169+		if (c >= 0x80)
3170+		{
3171+			use_ascii = false;
3172+			break;
3173+		}
3174+	}
3175+
3176+	if (use_ascii)
3177+		fprintf (fp, "\t.ascii \"");
3178+
3179+	for (i = 0; i < size; i++)
3180+	{
3181+		int c = str[i] & 0377;
3182+
3183+		if (use_ascii)
3184+		{
3185+		/* Just output the plain character if it is printable,
3186+		otherwise output the escape code for the character.
3187+		The assembler recognizes the same C-style octal escape sequences,
3188+		except that it only supports 7-bit codes. */
3189+		if (c >= ' ' && c < 0177 && c != '\\' && c != '"')
3190+  			putc (c, fp);
3191+		else switch (c) 
3192+		{
3193+			case '\n':
3194+#ifndef TARGET_COCO
3195+				fputs ("\\n", fp);
3196+				break;
3197+#endif
3198+				/* On the CoCo, we fallthrough and treat '\n' like '\r'. */
3199+			case '\r':
3200+				fputs ("\\r", fp);
3201+				break;
3202+			case '\t':
3203+				fputs ("\\t", fp);
3204+				break;
3205+			case '\f':
3206+				fputs ("\\f", fp);
3207+				break;
3208+			case 0:
3209+				fputs ("\\0", fp);
3210+				break;
3211+			default:
3212+				fprintf (fp, "\\%03o", c);
3213+				break;
3214+		}
3215+		}
3216+		else
3217+		{
3218+			fprintf (fp, "\t.byte\t0x%02X\n", c);
3219+		}
3220+	}
3221+
3222+	if (use_ascii)
3223+		fprintf (fp, "\"\n");
3224+}
3225+
3226+
3227+void
3228+m6809_output_quoted_string (FILE *asm_file, const char *string)
3229+{
3230+	char c;
3231+
3232+	if (strlen (string) > MAX_ASM_ASCII_STRING)
3233+	{
3234+		/* The string length is too large.  We'll have to truncate it.
3235+		This is only called from debugging functions, so it's usually
3236+		not critical. */
3237+
3238+		char truncated_string[MAX_ASM_ASCII_STRING+1];
3239+
3240+		/* Copy as many characters as we can. */
3241+		strncpy (truncated_string, string, MAX_ASM_ASCII_STRING);
3242+		truncated_string[MAX_ASM_ASCII_STRING] = '\0';
3243+		string = truncated_string;
3244+	}
3245+
3246+	/* Copied from toplev.c */
3247+
3248+	putc ('\"', asm_file);
3249+	while ((c = *string++) != 0) {
3250+		if (ISPRINT (c)) {
3251+			if (c == '\"' || c == '\\')
3252+				putc ('\\', asm_file);
3253+			putc (c, asm_file);
3254+		}
3255+      else
3256+			fprintf (asm_file, "\\%03o", (unsigned char) c);
3257+	}
3258+	putc ('\"', asm_file);
3259+}
3260+
3261+
3262+/** Output the assembly code for a shift instruction where the
3263+ * shift count is not constant. */
3264+void
3265+m6809_output_shift_insn (int rtx_code, rtx *operands)
3266+{
3267+	struct shift_opcode *op;
3268+
3269+	if (GET_CODE (operands[2]) == CONST_INT)
3270+		abort ();
3271+
3272+	if (optimize_size && GET_MODE (operands[0]) == HImode)
3273+	{
3274+		switch (rtx_code)
3275+		{
3276+			case ASHIFT:
3277+				output_asm_insn ("jsr\t_ashlhi3", operands);
3278+				break;
3279+			case ASHIFTRT:
3280+				output_asm_insn ("jsr\t_ashrhi3", operands);
3281+				break;
3282+			case LSHIFTRT:
3283+				output_asm_insn ("jsr\t_lshrhi3", operands);
3284+				break;
3285+		}
3286+	}
3287+	else if (GET_MODE (operands[0]) == HImode)
3288+	{
3289+		switch (rtx_code)
3290+		{
3291+			case ASHIFT:
3292+				m6809_gen_register_shift (operands, "aslb", "rola");
3293+				break;
3294+			case ASHIFTRT:
3295+				m6809_gen_register_shift (operands, "asra", "rorb");
3296+				break;
3297+			case LSHIFTRT:
3298+				m6809_gen_register_shift (operands, "lsra", "rorb");
3299+				break;
3300+		}
3301+	}
3302+	else
3303+	{
3304+		switch (rtx_code)
3305+		{
3306+			case ASHIFT:
3307+				m6809_gen_register_shift (operands, "aslb", NULL);
3308+				break;
3309+			case ASHIFTRT:
3310+				m6809_gen_register_shift (operands, "asrb", NULL);
3311+				break;
3312+			case LSHIFTRT:
3313+				m6809_gen_register_shift (operands, "lsrb", NULL);
3314+				break;
3315+		}
3316+	}
3317+}
3318+
3319+
3320+void
3321+m6809_emit_move_insn (rtx dst, rtx src)
3322+{
3323+	emit_insn (gen_rtx_SET (VOIDmode, dst, src));
3324+	if (ACC_A_REG_P (dst))
3325+		emit_insn (gen_rtx_USE (VOIDmode, dst));
3326+}
3327+
3328+
3329+/** Split a complex shift instruction into multiple CPU
3330+ * shift instructions. */
3331+void
3332+m6809_split_shift (enum rtx_code code, rtx *operands)
3333+{
3334+	enum machine_mode mode;
3335+	int count;
3336+
3337+	mode = GET_MODE (operands[0]);
3338+	count = INTVAL (operands[2]);
3339+	
3340+	/* Handle a shift count outside the range of 0 .. N-1, where
3341+	 * N is the mode size in bits.  We normalize the count, and
3342+	 * for negative counts we also invert the direction of the
3343+	 * shift. */
3344+	if ((count < 0) || (count >= 8 * GET_MODE_SIZE (mode)))
3345+	{
3346+		if (count < 0)
3347+		{
3348+			count = -count;
3349+			code = (code == ASHIFT) ? ASHIFTRT : ASHIFT;
3350+		}
3351+		count %= (8 * GET_MODE_SIZE (mode));
3352+		m6809_emit_move_insn (operands[0],
3353+			gen_rtx_fmt_ee (code, mode, operands[1],
3354+				gen_rtx_CONST_INT (VOIDmode, count)));
3355+	}
3356+
3357+	/* Handle shift by zero explicitly as a no-op. */
3358+	if (count == 0)
3359+	{
3360+		emit_insn (gen_nop ());
3361+		return;
3362+	}
3363+
3364+	/* Decompose the shift by a constant N > 8 into two
3365+	 * shifts, first by 8 and then by N-8.
3366+	 * This "speeds up" the process for large shifts that would be
3367+	 * handled below, but allows for some optimization.
3368+	 * In some cases shift by 8 can be implemented fast.  If an
3369+	 * instruction to shift by 8 is defined, it will be used here;
3370+	 * otherwise it will be further decomposed as below. */
3371+	if (mode == HImode && count > 8)
3372+	{
3373+		rtx output = operands[0];
3374+
3375+		m6809_emit_move_insn (operands[0],
3376+			gen_rtx_fmt_ee (code, mode, operands[1],
3377+				gen_rtx_CONST_INT (VOIDmode, 8)));
3378+
3379+		/* Unsigned shifts always produce a zero in either the
3380+		 * upper or lower half of the output; then, that part
3381+		 * does not need to be shifted anymore.  We modify the
3382+		 * output and the subsequent instructions to operate in
3383+		 * QImode only on the relevant part. */
3384+		if (REG_P (output))
3385+		{
3386+			if (code == ASHIFT)
3387+			{
3388+				output = gen_rtx_REG (QImode, HARD_A_REGNUM);
3389+				mode = QImode;
3390+			}
3391+			else
3392+			{
3393+				output = gen_rtx_REG (QImode, HARD_D_REGNUM);
3394+				mode = QImode;
3395+			}
3396+		}
3397+
3398+		m6809_emit_move_insn (output,
3399+			gen_rtx_fmt_ee (code, mode, copy_rtx (output), 
3400+				gen_rtx_CONST_INT (VOIDmode, count-8)));
3401+		return;
3402+	}
3403+
3404+	/* Rewrite the unsigned shift of an 8-bit register by a large constant N
3405+	 * (near to the maximum of 8) as a rotate and mask. */
3406+	if (mode == QImode && REG_P (operands[0]) && count >= ((code == ASHIFTRT) ? 7 : 6))
3407+	{
3408+		unsigned int mask;
3409+		unsigned int was_signed = (code == ASHIFTRT);
3410+
3411+		code = (code == ASHIFT) ? ROTATERT : ROTATE;
3412+		if (code == ROTATE)
3413+			mask = (count == 6) ? 0x03 : 0x01;
3414+		else
3415+			mask = (count == 6) ? 0xC0 - 0x100 : 0x80 - 0x100;
3416+		count = 9 - count;
3417+
3418+		do {
3419+			m6809_emit_move_insn (operands[0],
3420+				gen_rtx_fmt_ee (code, QImode, operands[1], const1_rtx));
3421+		} while (--count != 0);
3422+
3423+		m6809_emit_move_insn (operands[0],
3424+			gen_rtx_fmt_ee (AND, QImode, operands[1],
3425+				gen_rtx_CONST_INT (VOIDmode, mask)));
3426+
3427+		if (was_signed)
3428+		{
3429+			emit_insn (gen_negqi2 (operands[0], copy_rtx (operands[0])));
3430+			if (ACC_A_REG_P (operands[0]))
3431+				emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
3432+		}
3433+		return;
3434+	}
3435+
3436+	/* Decompose the shift by any constant N > 1 into a sequence
3437+	 * of N shifts.
3438+	 * This is done recursively, by creating a shift by 1 and a
3439+	 * shift by N-1, as long as N>1. */
3440+	if (count > 1)
3441+	{
3442+		m6809_emit_move_insn (operands[0],
3443+			gen_rtx_fmt_ee (code, mode, operands[1], const1_rtx));
3444+	
3445+		m6809_emit_move_insn (operands[0],
3446+			gen_rtx_fmt_ee (code, mode, operands[1], 
3447+				gen_rtx_CONST_INT (VOIDmode, count-1)));
3448+		return;
3449+	}
3450+	
3451+	/* Decompose the single shift of a 16-bit quantity into two
3452+	 * CPU instructions, one for each 8-bit half.
3453+	 */
3454+	if (mode == HImode && count == 1)
3455+	{
3456+		rtx first, second;
3457+		enum rtx_code rotate_code;
3458+
3459+		rotate_code = (code == ASHIFT) ? ROTATE : ROTATERT;
3460+
3461+		/* Split the operand into two 8-bit entities.
3462+		 * FIRST is the one that will get shifted via a regular CPU
3463+		 * instruction.
3464+		 * SECOND is the one that will have the result of the first shift
3465+		 * rotated in.
3466+		 *
3467+		 * We initialize first and second as if we are doing a left shift,
3468+		 * then swap the operands if it's a right shift.
3469+		 */
3470+		if (REG_P (operands[0]))
3471+		{
3472+			first = gen_rtx_REG (QImode, HARD_D_REGNUM); /* HARD_B_REGNUM? */
3473+			second = gen_rtx_REG (QImode, HARD_A_REGNUM);
3474+		}
3475+		else
3476+		{
3477+			first = adjust_address (operands[0], QImode, 1);
3478+			second = adjust_address (operands[0], QImode, 0);
3479+		}
3480+
3481+		if (rotate_code == ROTATERT)
3482+		{
3483+			rtx tmp; tmp = first; first = second; second = tmp;
3484+		}
3485+
3486+		/* Decompose into a shift and a rotate instruction. */
3487+		m6809_emit_move_insn (first,
3488+			gen_rtx_fmt_ee (code, QImode, copy_rtx (first), const1_rtx));
3489+		m6809_emit_move_insn (second,
3490+			gen_rtx_fmt_ee (rotate_code, QImode, copy_rtx (second), const1_rtx));
3491+		return;
3492+	}
3493+}
3494+
3495+
3496+/** Adjust register usage based on compile-time flags. */
3497+void
3498+m6809_conditional_register_usage (void)
3499+{
3500+	unsigned int soft_regno;
3501+
3502+#ifdef CONFIG_SOFT_REGS_ALWAYS
3503+	m6809_soft_regs = CONFIG_SOFT_REGS_ALWAYS;
3504+#else
3505+	if (!m6809_soft_reg_count)
3506+		return;
3507+	m6809_soft_regs = atoi (m6809_soft_reg_count);
3508+#endif
3509+
3510+	if (m6809_soft_regs == 0)
3511+		return;
3512+
3513+	if (m6809_soft_regs > NUM_M_REGS)
3514+		m6809_soft_regs = NUM_M_REGS;
3515+
3516+	/* Registers are marked FIXED by default.  Free up if
3517+	the user wishes. */
3518+	for (soft_regno = 1; soft_regno < m6809_soft_regs; soft_regno++)
3519+	{
3520+		fixed_regs[SOFT_M0_REGNUM + soft_regno] = 0;
3521+
3522+		/* Mark the softregs as call-clobbered, so that they need
3523+		 * not be saved/restored on function entry/exit. */
3524+		call_used_regs[SOFT_M0_REGNUM + soft_regno] = 1;
3525+	}
3526+}
3527+
3528+
3529+/** Return a RTX representing how to return a value from a function.
3530+  VALTYPE gives the type of the value, FUNC identifies the function
3531+  itself.
3532+
3533+  In general, we only care about the width of the result. */
3534+rtx
3535+m6809_function_value (const tree valtype, const tree func ATTRIBUTE_UNUSED)
3536+{
3537+   unsigned int regno;
3538+	enum machine_mode mode;
3539+
3540+	/* Get the mode (i.e. width) of the result. */
3541+	mode = TYPE_MODE (valtype);
3542+
3543+	if (lookup_attribute ("boolean", TYPE_ATTRIBUTES (valtype)))
3544+      regno = HARD_Z_REGNUM;
3545+   else if (mode == QImode || (TARGET_DRET && mode == HImode))
3546+      regno = HARD_D_REGNUM;
3547+   else
3548+      regno = HARD_X_REGNUM;
3549+   return gen_rtx_REG (mode, regno);
3550+}
3551+
3552+
3553+/** Return 1 if REGNO is possibly needed to return the result
3554+of a function, 0 otherwise. */
3555+int
3556+m6809_function_value_regno_p (unsigned int regno)
3557+{
3558+	if (regno == HARD_Z_REGNUM)
3559+		return 1;
3560+	else if ((TARGET_BYTE_INT || TARGET_DRET) && regno == HARD_D_REGNUM)
3561+		return 1;
3562+	else if (!TARGET_DRET && regno == HARD_X_REGNUM)
3563+		return 1;
3564+	else
3565+		return 0;
3566+}
3567+
3568+
3569+#ifdef TRACE_PEEPHOLE
3570+int
3571+m6809_match_peephole2 (unsigned int peephole_id, unsigned int stage)
3572+{
3573+	if (stage == PEEP_END)
3574+	{
3575+		printf ("%s: peephole %d pattern and predicate matched\n",
3576+			main_input_filename, peephole_id);
3577+		fflush (stdout);
3578+	}
3579+	else if (stage == PEEP_COND)
3580+	{
3581+		printf ("%s: peephole %d? at least pattern matched\n",
3582+			main_input_filename, peephole_id);
3583+		fflush (stdout);
3584+	}
3585+	return 1;
3586+}
3587+#else
3588+int
3589+m6809_match_peephole2 (unsigned int peephole_id ATTRIBUTE_UNUSED,
3590+	unsigned int stage ATTRIBUTE_UNUSED)
3591+{
3592+	return 1;
3593+}
3594+#endif /* TRACE_PEEPHOLE */
3595+
3596+
3597+/** Return 1 if it is OK to store a value of MODE in REGNO. */
3598+int
3599+m6809_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
3600+{
3601+   /* Soft registers, as they are just memory, can really hold
3602+   values of any type.  However we restrict them to values of
3603+   size HImode or QImode to prevent exhausting them for larger
3604+   values.
3605+      Word values cannot be placed into the first soft register,
3606+   as it is the low byte that is being placed there, which
3607+   corrupts the (non-soft) register before it. */
3608+   if (M_REGNO_P (regno))
3609+   {
3610+      switch (GET_MODE_SIZE (mode))
3611+      {
3612+         case 1:
3613+            return 1;
3614+         case 2:
3615+            return regno != SOFT_M0_REGNUM;
3616+         default:
3617+            return 0;
3618+      }
3619+   }
3620+
3621+   /* VOIDmode can be stored anywhere */
3622+   else if (mode == VOIDmode)
3623+      return 1;
3624+
3625+   /* Zero is a reserved register, but problems occur if we don't
3626+   say yes here??? */
3627+   else if (regno == 0)
3628+      return 1;
3629+
3630+   /* For other registers, return true only if the requested size
3631+   exactly matches the hardware size. */
3632+   else if ((G_REGNO_P (regno)) && (GET_MODE_SIZE (mode) == 2))
3633+      return 1;
3634+   else if ((BYTE_REGNO_P (regno)) && (GET_MODE_SIZE (mode) == 1))
3635+      return 1;
3636+   else
3637+      return 0;
3638+}
3639+
3640+
3641+/* exp is the call expression.  DECL is the called function,
3642+ * or NULL for an indirect call */
3643+bool
3644+m6809_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3645+{
3646+	tree type, arg;
3647+   const char *name;
3648+	bool result = 0;
3649+	int argcount = 0;
3650+	int step = 1;
3651+
3652+	/* If there is no DECL, it is an indirect call.
3653+	 * Never optimize this??? */
3654+	if (decl == NULL)
3655+		goto done;
3656+
3657+	/* Never allow an interrupt handler to be optimized this way. */
3658+	if (m6809_function_has_type_attr_p (decl, "interrupt"))
3659+		goto done;
3660+
3661+	/* Skip sibcall if the type can't be found for
3662+	 * some reason */
3663+	step++;
3664+	name = IDENTIFIER_POINTER (DECL_NAME (decl));
3665+	type = TREE_TYPE (decl);
3666+	if (type == NULL)
3667+		goto done;
3668+
3669+	/* Skip sibcall if the target is a far function */
3670+	step++;
3671+	if (far_function_type_p (type) != NULL)
3672+		goto done;
3673+
3674+	/* Skip sibcall if the called function's arguments are
3675+	 * variable */
3676+	step++;
3677+	if (TYPE_ARG_TYPES (type) == NULL)
3678+		goto done;
3679+
3680+	/* Allow sibcalls in other cases. */
3681+	result = 1;
3682+done:
3683+	/* printf ("%s ok for sibcall? %s, step %d, args %d\n", name, result ? "yes" : "no", step, argcount); */
3684+	return result;
3685+}
3686+
3687+
3688+/** Emit code for the 'casesi' pattern.
3689+ * This pattern is only used in 8-bit mode, and can be disabled
3690+ * with -mold-case there as well.  The rationale for this is to
3691+ * do a better job than the simpler but well-tested 'tablejump'
3692+ * method.
3693+ *
3694+ * For small jumptables, where the switch expression is an
3695+ * 8-bit value, the lookup can be done more efficiently
3696+ * using the "B,X" style index mode. */
3697+void
3698+m6809_do_casesi (rtx index, rtx lower_bound, rtx range,
3699+	rtx table_label, rtx default_label)
3700+{
3701+	enum machine_mode mode;
3702+	rtx scaled;
3703+	rtx table_in_reg;
3704+
3705+	/* expr.c has to be patched so that it does not promote
3706+	 * the expression to SImode, but rather to HImode.
3707+	 * Fail now if that isn't the case. */
3708+	if (GET_MODE_SIZE (GET_MODE (index)) > GET_MODE_SIZE (HImode))
3709+		error ("try_casesi promotion bug");
3710+
3711+	/* Determine whether or not we are going to work primarily in
3712+	 * QImode or HImode.  This depends on the size of the index
3713+	 * into the lookup table.  QImode can only be used when the
3714+	 * index is less than 0x40, since it will be doubled but
3715+	 * must remain unsigned. */
3716+	if ((GET_CODE (range) == CONST_INT) && (INTVAL (range) < 0x40))
3717+		mode = QImode;
3718+	else
3719+		mode = HImode;
3720+
3721+	/* Convert to QImode if necessary */
3722+	if (mode == QImode)
3723+	{
3724+		index = gen_lowpart_general (mode, index);
3725+		lower_bound = gen_lowpart_general (mode, lower_bound);
3726+	}
3727+
3728+	/* Translate from case value to table index by subtraction */
3729+	if (lower_bound != const0_rtx)
3730+		index = expand_binop (mode, sub_optab, index, lower_bound,
3731+			NULL_RTX, 0, OPTAB_LIB_WIDEN);
3732+
3733+	/* Emit compare-and-jump to test for index out-of-range */
3734+	emit_cmp_and_jump_insns (index, range, GTU, NULL_RTX, mode, 1,
3735+		default_label);
3736+
3737+	/* Put the table address is in a register */
3738+	table_in_reg = gen_reg_rtx (Pmode);
3739+	emit_move_insn (table_in_reg, gen_rtx_LABEL_REF (Pmode, table_label));
3740+
3741+	/* Emit table lookup and jump */
3742+	if (mode == QImode)
3743+	{
3744+		/* Scale the index */
3745+		scaled = gen_reg_rtx (QImode);
3746+		emit_insn (gen_ashlqi3 (scaled, index, const1_rtx));
3747+
3748+		/* Emit the jump */
3749+		emit_jump_insn (gen_tablejump_short_offset (scaled, table_in_reg));
3750+	}
3751+	else
3752+	{
3753+		/* Scale the index */
3754+		emit_insn (gen_ashlhi3 (index, index, const1_rtx));
3755+
3756+		/* Emit the jump */
3757+		emit_jump_insn (gen_tablejump_long_offset (index, table_in_reg));
3758+	}
3759+
3760+	/* Copied from expr.c */
3761+	if (!CASE_VECTOR_PC_RELATIVE && !flag_pic)
3762+		emit_barrier ();
3763+}
3764+
3765+
3766+/** Output the assembly code for a 32-bit add/subtract. */
3767+void
3768+m6809_output_addsi3 (int rtx_code, rtx *operands)
3769+{
3770+	rtx xoperands[8];
3771+	rtx dst = operands[0];
3772+
3773+	/* Prepare the operands by splitting each SImode into two HImodes
3774+	that can be operated independently.  The high word of operand 1
3775+	is further divided into two QImode components for use with 'adc'
3776+	style instructions. */
3777+	xoperands[7] = operands[3];
3778+
3779+	xoperands[0] = adjust_address (dst, HImode, 2);
3780+	xoperands[3] = adjust_address (dst, HImode, 0);
3781+
3782+#if 1
3783+	xoperands[2] = adjust_address (operands[1], HImode, 2);
3784+	xoperands[6] = adjust_address (operands[1], HImode, 0);
3785+
3786+	/* Operand 2 may be a MEM or a CONST_INT */
3787+	if (GET_CODE (operands[2]) == CONST_INT)
3788+	{
3789+		xoperands[1] = gen_int_mode (INTVAL (operands[2]) & 0xFFFF, HImode);
3790+		xoperands[4] = gen_int_mode ((INTVAL (operands[2]) >> 24) & 0xFF, QImode);
3791+		xoperands[5] = gen_int_mode ((INTVAL (operands[2]) >> 16) & 0xFF, QImode);
3792+	}
3793+	else
3794+	{
3795+		xoperands[1] = adjust_address (operands[2], HImode, 2);
3796+		xoperands[4] = adjust_address (operands[2], QImode, 0);
3797+		xoperands[5] = adjust_address (operands[2], QImode, 1);
3798+	}
3799+
3800+#endif
3801+
3802+#if 0
3803+	xoperands[1] = adjust_address (operands[1], HImode, 2);
3804+	xoperands[4] = adjust_address (operands[1], QImode, 0);
3805+	xoperands[5] = adjust_address (operands[1], QImode, 1);
3806+
3807+	/* Operand 2 may be a MEM or a CONST_INT */
3808+	if (GET_CODE (operands[2]) == CONST_INT)
3809+	{
3810+		xoperands[2] = gen_int_mode ((INTVAL (operands[2])) & 0xFFFF, HImode);
3811+		xoperands[6] = gen_int_mode ((INTVAL (operands[2]) >> 16) & 0xFFFF, HImode);
3812+	}
3813+	else
3814+	{
3815+		xoperands[2] = adjust_address (operands[2], HImode, 2);
3816+		xoperands[6] = adjust_address (operands[2], HImode, 0);
3817+	}
3818+#endif
3819+
3820+	/* Output the assembly code. */
3821+	if (rtx_code == PLUS)
3822+	{
3823+		output_asm_insn ("ld%7\t%2", xoperands);
3824+		output_asm_insn ("add%7\t%1", xoperands);
3825+		output_asm_insn ("st%7\t%0", xoperands);
3826+		output_asm_insn ("ld%7\t%6", xoperands);
3827+		output_asm_insn ("adcb\t%5", xoperands);
3828+		output_asm_insn ("adca\t%4", xoperands);
3829+		output_asm_insn ("st%7\t%3", xoperands);
3830+	}
3831+	else
3832+	{
3833+		output_asm_insn ("ld%7\t%2", xoperands);
3834+		output_asm_insn ("sub%7\t%1", xoperands);
3835+		output_asm_insn ("st%7\t%0", xoperands);
3836+		output_asm_insn ("ld%7\t%6", xoperands);
3837+		output_asm_insn ("sbcb\t%5", xoperands);
3838+		output_asm_insn ("sbca\t%4", xoperands);
3839+		output_asm_insn ("st%7\t%3", xoperands);
3840+	}
3841+}
3842+
3843+
3844+#if 0
3845+/** Output the assembly code for a 32-bit shift.
3846+Operands 0 and 1 must be the same rtx, forced by a matching
3847+constraint.  Operand 2 must be a CONST_INT.  Operand 3 is
3848+"d" in case a temporary reg is needed. */
3849+void
3850+m6809_output_shiftsi3 (int rtx_code, rtx *operands)
3851+{
3852+	unsigned int count = INTVAL (operands[2]) % 32;
3853+	unsigned int size = 4; /* sizeof (SImode) */
3854+	int s;
3855+	rtx xoperands[4];
3856+	int op;
3857+	int start, end, step;
3858+
3859+	/* Initialize */
3860+	if (rtx_code == ASHIFT)
3861+	{
3862+		start = size-1;
3863+		end = -1;
3864+		step = -1;
3865+	}
3866+	else
3867+	{
3868+		start = 0;
3869+		end = size;
3870+		step = 1;
3871+	}
3872+
3873+	xoperands[2] = operands[2];
3874+	xoperands[3] = operands[3];
3875+
3876+	if (count <= 0)
3877+		abort ();
3878+	if (rtx_code == ROTATE || rtx_code == ROTATERT)
3879+		abort ();
3880+
3881+	/* Extract bit shifts over 16 bits by HImode moves. */
3882+	if (count >= 16)
3883+	{
3884+	}
3885+
3886+	/* Extract bit shifts over 8 bits by QImode moves. */
3887+	if (count >= 8)
3888+	{
3889+	}
3890+
3891+	/* Iterate over the number of bits to be shifted. */
3892+	while (count > 0)
3893+	{
3894+		/* Each bit to be shifted requires 1 proper bit shift
3895+		and 3 rotates. */
3896+
3897+		/* First, do the arithmetic/logical shift.  Left shifts
3898+		start from the LSB; right shifts start from the MSB. */
3899+		xoperands[0] = adjust_address (operands[0], QImode, start);
3900+		switch (rtx_code)
3901+		{
3902+			case ASHIFT:
3903+				output_asm_insn ("asl\t%0", xoperands);
3904+				start--;
3905+				break;
3906+			case ASHIFTRT:
3907+				output_asm_insn ("asr\t%0", xoperands);
3908+				start++;
3909+				break;
3910+			case LSHIFTRT:
3911+				output_asm_insn ("lsr\t%0", xoperands);
3912+				start++;
3913+				break;
3914+		}
3915+
3916+		/* Next, rotate the other bytes */
3917+		for (s = start; s != end; s += step)
3918+		{
3919+			xoperands[0] = adjust_address (operands[0], QImode, s);
3920+			switch (rtx_code)
3921+			{
3922+				case ASHIFT:
3923+					output_asm_insn ("rol\t%0", xoperands);
3924+					break;
3925+				case ASHIFTRT:
3926+				case LSHIFTRT:
3927+					output_asm_insn ("ror\t%0", xoperands);
3928+					break;
3929+			}
3930+		}
3931+		count--;
3932+	}
3933+}
3934+#endif
3935+
3936+int
3937+power_of_two_p (unsigned int n)
3938+{
3939+	return (n & (n-1)) == 0;
3940+}
3941+
3942+
3943+int
3944+m6809_can_eliminate (int from, int to)
3945+{
3946+	if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
3947+		return !frame_pointer_needed;
3948+	return 1;
3949+}
3950+
3951+
3952+int
3953+m6809_initial_elimination_offset (int from, int to)
3954+{
3955+	switch (from)
3956+	{
3957+		case ARG_POINTER_REGNUM:
3958+			return get_frame_size () + m6809_get_regs_size (m6809_get_live_regs ());
3959+		case FRAME_POINTER_REGNUM:
3960+			return get_frame_size ();
3961+		default:
3962+			gcc_unreachable ();
3963+	}
3964+}
3965+
3966+
3967+bool
3968+m6809_frame_pointer_required (void)
3969+{
3970+	return false;
3971+}
3972+
3973+
3974+/* Defines the target-specific hooks structure. */
3975+struct gcc_target targetm = TARGET_INITIALIZER;
3976diff --git a/gcc/config/m6809/m6809.h b/gcc/config/m6809/m6809.h
3977new file mode 100644
3978index 0000000..386bcc9
3979--- /dev/null
3980+++ b/gcc/config/m6809/m6809.h
3981@@ -0,0 +1,1352 @@
3982+/* Definitions of target machine for GNU compiler.  MC6809 version.
3983+
3984+ MC6809 Version by Tom Jones (jones@sal.wisc.edu)
3985+ Space Astronomy Laboratory
3986+ University of Wisconsin at Madison
3987+
3988+ minor changes to adapt it to gcc-2.5.8 by Matthias Doerfel
3989+ ( msdoerfe@informatik.uni-erlangen.de )
3990+ also added #pragma interrupt (inspired by gcc-6811)
3991+
3992+ minor changes to adapt it to gcc-2.8.0 by Eric Botcazou
3993+ (ebotcazou@multimania.com)
3994+
3995+ minor changes to adapt it to egcs-1.1.2 by Eric Botcazou
3996+ (ebotcazou@multimania.com)
3997+
3998+ minor changes to adapt it to gcc-2.95.3 by Eric Botcazou
3999+ (ebotcazou@multimania.com)
4000+
4001+ changes for gcc-3.1.1 by ???
4002+
4003+ further changes for gcc-3.1.1 and beyond by Brian Dominy
4004+ (brian@oddchange.com)
4005+
4006+ even more changes for gcc-4.6.1 by William Astle (lost@l-w.ca)
4007+
4008+This file is part of GCC.
4009+
4010+GCC is free software; you can redistribute it and/or modify
4011+it under the terms of the GNU General Public License as published by
4012+the Free Software Foundation; either version 3, or (at your option)
4013+any later version.
4014+
4015+GCC is distributed in the hope that it will be useful,
4016+but WITHOUT ANY WARRANTY; without even the implied warranty of
4017+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4018+GNU General Public License for more details.
4019+
4020+You should have received a copy of the GNU General Public License
4021+along with GCC; see the file COPYING3.  If not see
4022+<http://www.gnu.org/licenses/>.  */
4023+
4024+
4025+/* Helper macros for creating strings with macros */
4026+#define C_STRING(x) C_STR(x)
4027+#define C_STR(x) #x
4028+
4029+/* Certain parts of GCC include host-side includes, which is bad.
4030+ * Some things that get pulled in need to be undone.
4031+ */
4032+#undef HAVE_GAS_HIDDEN
4033+
4034+/* Names to predefine in the preprocessor for this target machine.  */
4035+/*#define TARGET_CPU_CPP_BUILTINS() m6809_cpu_cpp_builtins () */
4036+#define TARGET_CPU_CPP_BUILTINS() do \
4037+	{ \
4038+		if (TARGET_6309) \
4039+		{ \
4040+			builtin_define_std ("__M6309__"); \
4041+			builtin_define_std ("__m6309__"); \
4042+		} \
4043+		else \
4044+		{ \
4045+			builtin_define_std ("__M6809__"); \
4046+			builtin_define_std ("__m6809__"); \
4047+		} \
4048+ \
4049+		if (TARGET_BYTE_INT) \
4050+			builtin_define_std ("__int8__"); \
4051+		else \
4052+			builtin_define_std ("__int16__"); \
4053+ \
4054+		switch (m6809_abi_version) \
4055+		{ \
4056+			case M6809_ABI_VERSION_STACK: \
4057+				builtin_define_std ("__regargs__"); \
4058+				builtin_define_std ("__ABI_STACK__"); \
4059+				break; \
4060+			case M6809_ABI_VERSION_REGS: \
4061+				builtin_define_std ("__ABI_REGS__"); \
4062+				break; \
4063+			case M6809_ABI_VERSION_BX: \
4064+				builtin_define_std ("__ABI_BX__"); \
4065+				break; \
4066+			default: \
4067+				break; \
4068+		} \
4069+ \
4070+		if (TARGET_WPC) \
4071+			builtin_define_std ("__WPC__"); \
4072+ \
4073+		if (TARGET_DRET) \
4074+			builtin_define_std ("__DRET__"); \
4075+	} while (0)
4076+
4077+/* As an embedded target, we have no libc.  */
4078+#ifndef inhibit_libc
4079+#define inhibit_libc
4080+#endif
4081+
4082+/* Print subsidiary information on the compiler version in use.  */
4083+#define TARGET_VERSION fprintf (stderr, " (MC6809)");
4084+
4085+/* Run-time compilation parameters selecting different hardware subsets.  */
4086+/*extern int target_flags; */
4087+extern short *reg_renumber;	/* def in local_alloc.c */
4088+
4089+/* Runtime current values of section names */
4090+extern int section_changed;
4091+extern char code_section_op[], data_section_op[], bss_section_op[];
4092+
4093+#define WARNING_OPT 0,
4094+/*extern const char *m6809_abi_version_ptr; */
4095+extern unsigned int m6809_soft_regs;
4096+extern unsigned int m6809_abi_version;
4097+
4098+/* ABI versions */
4099+
4100+#define M6809_ABI_VERSION_STACK 0
4101+#define M6809_ABI_VERSION_REGS 1
4102+#define M6809_ABI_VERSION_BX 2
4103+#define M6809_ABI_VERSION_LATEST  (M6809_ABI_VERSION_BX)
4104+
4105+/* Allow $ in identifiers */
4106+#define DOLLARS_IN_IDENTIFIERS 1
4107+
4108+/*--------------------------------------------------------------
4109+	Target machine storage layout
4110+--------------------------------------------------------------*/
4111+
4112+/* Define this if most significant bit is lowest numbered
4113+   in instructions that operate on numbered bit-fields.  */
4114+#define BITS_BIG_ENDIAN 0
4115+
4116+/* Define to 1 if most significant byte of a word is the lowest numbered. */
4117+#define BYTES_BIG_ENDIAN 1
4118+
4119+/* Define to 1 if most significant word of a multiword value is the lowest numbered. */
4120+#define WORDS_BIG_ENDIAN 1
4121+
4122+/* Number of bits in an addressible storage unit */
4123+#define BITS_PER_UNIT 8
4124+
4125+/* Width in bits of a "word", or the contents of a machine register.
4126+ * Although the 6809 has a few byte registers, define this to 16-bits
4127+ * since this is the natural size of most registers. */
4128+#define BITS_PER_WORD 16
4129+
4130+/* Width of a word, in units (bytes).  */
4131+#define UNITS_PER_WORD (BITS_PER_WORD/8)
4132+
4133+/* Width in bits of a pointer.  See also the macro `Pmode' defined below.  */
4134+#define POINTER_SIZE 16
4135+
4136+/* Allocation boundary (bits) for storing pointers in memory.  */
4137+#define POINTER_BOUNDARY 8
4138+
4139+/* Allocation boundary (bits) for storing arguments in argument list.  */
4140+/* PARM_BOUNDARY is divided by BITS_PER_WORD in expr.c -- tej */
4141+#define PARM_BOUNDARY 8
4142+
4143+/* Boundary (bits) on which stack pointer should be aligned.  */
4144+#define STACK_BOUNDARY 8
4145+
4146+/* Allocation boundary (bits) for the code of a function.  */
4147+#define FUNCTION_BOUNDARY 8
4148+
4149+/* Alignment of field after `int : 0' in a structure.  */
4150+#define EMPTY_FIELD_BOUNDARY 8
4151+
4152+/* Every structure's size must be a multiple of this.  */
4153+#define STRUCTURE_SIZE_BOUNDARY 8
4154+
4155+/* Largest mode size to use when putting an object, including
4156+ * a structure, into a register.  By limiting this to 16, no
4157+ * 32-bit objects will ever be allocated to a pair of hard
4158+ * registers.  This is a good thing, since there aren't that
4159+ * many of them.  32-bit objects are only needed for floats
4160+ * and "long long"s.  Larger values have been tried and did not
4161+ * work. */
4162+#define MAX_FIXED_MODE_SIZE 16
4163+
4164+/* No data type wants to be aligned rounder than this.  */
4165+#define BIGGEST_ALIGNMENT 8
4166+
4167+/* Define this if move instructions will actually fail to work
4168+   when given unaligned data.  */
4169+#define STRICT_ALIGNMENT 0
4170+
4171+/*--------------------------------------------------------------
4172+	 Standard register usage.
4173+--------------------------------------------------------------*/
4174+
4175+/* Register values as bitmasks.
4176+ * TODO : merge D_REGBIT and B_REGBIT, and treat this as the same
4177+ * register. */
4178+#define RSVD1_REGBIT    (1 << HARD_RSVD1_REGNUM)
4179+#define D_REGBIT			(1 << HARD_D_REGNUM)
4180+#define X_REGBIT			(1 << HARD_X_REGNUM)
4181+#define Y_REGBIT			(1 << HARD_Y_REGNUM)
4182+#define U_REGBIT			(1 << HARD_U_REGNUM)
4183+#define S_REGBIT			(1 << HARD_S_REGNUM)
4184+#define PC_REGBIT			(1 << HARD_PC_REGNUM)
4185+#define Z_REGBIT        (1 << HARD_Z_REGNUM)
4186+#define A_REGBIT			(1 << HARD_A_REGNUM)
4187+#define B_REGBIT			(1 << HARD_B_REGNUM)
4188+#define CC_REGBIT			(1 << HARD_CC_REGNUM)
4189+#define DP_REGBIT			(1 << HARD_DP_REGNUM)
4190+#define SOFT_FP_REGBIT  (1 << SOFT_FP_REGNUM)
4191+#define SOFT_AP_REGBIT  (1 << SOFT_AP_REGNUM)
4192+#define M_REGBIT(n)		(1 << (SOFT_M0_REGNUM + n))
4193+
4194+/* Macros for dealing with set of registers.
4195+ * A register set is just a bitwise-OR of all the register
4196+ * bitmask values. */
4197+
4198+/* Which registers can hold 8-bits */
4199+#define BYTE_REGSET \
4200+	(Z_REGBIT | A_REGBIT | D_REGBIT | CC_REGBIT | DP_REGBIT)
4201+
4202+/* Which registers can hold 16-bits.
4203+ * Note: D_REGBIT is defined as both an 8-bit and 16-bit register */
4204+#define WORD_REGSET \
4205+	(D_REGBIT | X_REGBIT | Y_REGBIT | U_REGBIT | S_REGBIT | PC_REGBIT | SOFT_FP_REGBIT | SOFT_AP_REGBIT | RSVD1_REGBIT)
4206+
4207+/* Returns nonzero if a given REGNO is in the REGSET. */
4208+#define REGSET_CONTAINS_P(regno, regset)  (((1 << (regno)) & (regset)) != 0)
4209+
4210+/* Defines related to the number of soft registers supported.
4211+ * The actual number used may be less depending on -msoft-reg-count.
4212+ * If you change one of these, you should change them all. */
4213+#define NUM_M_REGS 8
4214+#define M_REGS_FIXED 1, 1, 1, 1, 1, 1, 1, 1
4215+#define M_REGS_CALL_USED 1, 1, 1, 1, 1, 1, 1, 1
4216+#define HARD_M_REGNUMS \
4217+   SOFT_M0_REGNUM+0, SOFT_M0_REGNUM+1, SOFT_M0_REGNUM+2, SOFT_M0_REGNUM+3, \
4218+   SOFT_M0_REGNUM+4, SOFT_M0_REGNUM+5, SOFT_M0_REGNUM+6, SOFT_M0_REGNUM+7
4219+
4220+#define SOFT_M_REGBITS  (((1UL << NUM_M_REGS) - 1) << (SOFT_M0_REGNUM))
4221+
4222+/* Number of actual hardware registers.
4223+   The hardware registers are assigned numbers for the compiler
4224+   from 0 to just below FIRST_PSEUDO_REGISTER.
4225+   All registers that the compiler knows about must be given numbers,
4226+   even those that are not normally considered general registers.
4227+   Make sure the constant below matches the value of SOFT_M0_REGNUM;
4228+   for some reason, GCC won't compile if that name is used here directly. */
4229+#ifdef SOFT_M0_REGNUM
4230+#if (SOFT_M0_REGNUM != 14)
4231+#error "bad register numbering"
4232+#endif
4233+#endif
4234+#define FIRST_PSEUDO_REGISTER (14 + NUM_M_REGS)
4235+
4236+/* 1 for registers that have pervasive standard uses
4237+   and are not available for the register allocator.
4238+   The psuedoregisters (M_REGS) are declared fixed here, but
4239+   will be unfixed if -msoft-reg-count is seen later.  */
4240+#define FIXED_REGISTERS \
4241+    {1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, M_REGS_FIXED, }
4242+  /* -, X, Y, U, S, PC,D, Z, A, B, C, DP,FP,AP,M... */
4243+
4244+/* 1 for registers not available across function calls.
4245+   These must include the FIXED_REGISTERS and also any
4246+   registers that can be used without being saved.
4247+   The latter must include the registers where values are returned
4248+   and the register where structure-value addresses are passed.
4249+   Aside from that, you can include as many other registers as you like.  */
4250+#define CALL_USED_REGISTERS \
4251+    {1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, M_REGS_CALL_USED, }
4252+  /* -, X, Y, U, S, PC,D, Z, A, B, C, DP,FP,AP,M... */
4253+
4254+/* Return number of consecutive hard regs needed starting at reg REGNO
4255+   to hold something of mode MODE.
4256+	For the 6809, we distinguish between word-length and byte-length
4257+	registers. */
4258+#define HARD_REGNO_NREGS(REGNO, MODE) \
4259+   (REGSET_CONTAINS_P (REGNO, WORD_REGSET) ? \
4260+		((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) : \
4261+      (GET_MODE_SIZE (MODE)))
4262+
4263+
4264+/* Value is 1 if hard register REGNO can hold a value
4265+of machine-mode MODE. */
4266+#define HARD_REGNO_MODE_OK(REGNO, MODE) m6809_hard_regno_mode_ok (REGNO, MODE)
4267+
4268+/* Value is 1 if it is a good idea to tie two pseudo registers
4269+   when one has mode MODE1 and one has mode MODE2.
4270+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
4271+   for any hard reg, then this must be 0 for correct output.  */
4272+#define MODES_TIEABLE_P(MODE1, MODE2) 0
4273+
4274+/* Specify the registers used for certain standard purposes.
4275+   The values of these macros are register numbers.  */
4276+
4277+/* program counter if referenced as a register */
4278+#define PC_REGNUM HARD_PC_REGNUM
4279+
4280+/* Register to use for pushing function arguments.  */
4281+#define STACK_POINTER_REGNUM HARD_S_REGNUM
4282+
4283+/* Base register for access to local variables of the function.
4284+ * Before reload, FRAME_POINTER_REGNUM will be used.  Later,
4285+ * the elimination pass will convert these to STACK_POINTER_REGNUM
4286+ * if possible, or else HARD_FRAME_POINTER_REGNUM.  The idea is to
4287+ * avoid tying up a hard register (U) for the frame pointer if
4288+ * it can be eliminated entirely, making it available for use as
4289+ * a general register. */
4290+#define FRAME_POINTER_REGNUM       SOFT_FP_REGNUM
4291+#define HARD_FRAME_POINTER_REGNUM  HARD_U_REGNUM
4292+
4293+/* Define a table of possible eliminations.
4294+ * The idea is to try to avoid using hard registers for the argument
4295+ * and frame pointers if they can be derived from the stack pointer
4296+ * instead, which already has a hard register reserved for it.
4297+ *
4298+ * The order of entries in this table will try to convert
4299+ * ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM into stack pointer
4300+ * references first, but if that fails, they will be converted to use
4301+ * HARD_FRAME_POINTER_REGNUM.
4302+ */
4303+#define ELIMINABLE_REGS \
4304+{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
4305+ { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
4306+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
4307+ { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
4308+
4309+/* #define CAN_ELIMINATE(FROM, TO) m6809_can_eliminate (FROM, TO) */
4310+
4311+/* Define how to offset the frame or argument pointer to turn it
4312+ * into a stack pointer reference.  This is based on the way that
4313+ * the frame is constructed in the function prologue. */
4314+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
4315+	(OFFSET) = m6809_initial_elimination_offset (FROM, TO)
4316+
4317+/* Base register for access to arguments of the function.
4318+ * This is only used prior to reload; no instructions will ever
4319+ * be output referring to this register. */
4320+#define ARG_POINTER_REGNUM SOFT_AP_REGNUM
4321+
4322+/* Register in which static-chain is passed to a function.  */
4323+#define STATIC_CHAIN_REGNUM HARD_Y_REGNUM
4324+
4325+/* #define CONDITIONAL_REGISTER_USAGE (m6809_conditional_register_usage ()) */
4326+
4327+/* Order in which hard registers are allocated to pseudos.
4328+ *
4329+ * Since the D register is the only valid reg for 8-bit values
4330+ * now, avoid using it for 16-bit values by putting it after all
4331+ * other 16-bits.
4332+ *
4333+ * Prefer X first since the first 16-bit function argument goes
4334+ * there.  We may be able to pass in to a subroutine without
4335+ * a copy.
4336+ *
4337+ * Prefer U over Y since instructions using Y take one extra
4338+ * byte, and thus one extra cycle to execute.
4339+ */
4340+#define REG_ALLOC_ORDER \
4341+   {  HARD_X_REGNUM, HARD_U_REGNUM, HARD_Y_REGNUM, HARD_D_REGNUM, \
4342+	   HARD_M_REGNUMS, HARD_S_REGNUM, HARD_PC_REGNUM, \
4343+		HARD_B_REGNUM, HARD_A_REGNUM, HARD_CC_REGNUM, \
4344+		HARD_DP_REGNUM, SOFT_FP_REGNUM, SOFT_AP_REGNUM, \
4345+		6, HARD_Z_REGNUM }
4346+
4347+/*--------------------------------------------------------------
4348+	classes of registers
4349+--------------------------------------------------------------*/
4350+
4351+/* Define the classes of registers for register constraints in the
4352+   machine description.  Also define ranges of constants.
4353+
4354+   One of the classes must always be named ALL_REGS and include all hard regs.
4355+   If there is more than one class, another class must be named NO_REGS
4356+   and contain no registers.
4357+
4358+   The name GENERAL_REGS must be the name of a class (or an alias for
4359+   another name such as ALL_REGS).  This is the class of registers
4360+   that is allowed by "g" or "r" in a register constraint.
4361+   Also, registers outside this class are allocated only when
4362+   instructions express preferences for them.
4363+
4364+   The classes must be numbered in nondecreasing order; that is,
4365+   a larger-numbered class must never be contained completely
4366+   in a smaller-numbered class.
4367+
4368+   For any two classes, it is very desirable that there be another
4369+   class that represents their union.  */
4370+   
4371+enum reg_class {
4372+    NO_REGS,    /* The trivial class with no registers in it */
4373+    D_REGS,     /* 16-bit (word (HI)) data (D) */
4374+    ACC_A_REGS, /* The A register */
4375+    ACC_B_REGS, /* The B register */
4376+	 X_REGS,     /* The X register */
4377+	 Z_REGS,     /* The Z (zero-bit) register */
4378+    Q_REGS,     /* 8-bit (byte (QI)) data (A,B) */
4379+    M_REGS,     /* 8-bit (byte (QI)) soft registers */
4380+	 CC_REGS,    /* 8-bit condition code register */
4381+    I_REGS,     /* An index register (A,B,D) */
4382+    T_REGS,     /* 16-bit addresses, not including stack or PC (X,Y,U) */
4383+    A_REGS,     /* 16-bit addresses (X,Y,U,S,PC) */
4384+	 S_REGS,     /* 16-bit soft registers (FP, AP) */
4385+	 P_REGS,     /* 16-bit pushable registers (D,X,Y,U); omit PC and S */
4386+    G_REGS,     /* 16-bit data and address (D,X,Y,U,S,PC) */
4387+    ALL_REGS,   /* All registers */
4388+    LIM_REG_CLASSES
4389+};
4390+
4391+#define N_REG_CLASSES (int) LIM_REG_CLASSES
4392+
4393+/* Since GENERAL_REGS is a smaller class than ALL_REGS,
4394+   it is not an alias to ALL_REGS, but to G_REGS. */
4395+#define GENERAL_REGS G_REGS
4396+
4397+/* Give names of register classes as strings for dump file.   */
4398+#define REG_CLASS_NAMES \
4399+ {  "NO_REGS", "D_REGS", "ACC_A_REGS", "ACC_B_REGS", "X_REGS", "Z_REGS", "Q_REGS", "M_REGS", \
4400+	 "CC_REGS", "I_REGS", "T_REGS", "A_REGS", "S_REGS", "P_REGS", "G_REGS", \
4401+	 "ALL_REGS" }
4402+
4403+/* Define which registers fit in which classes.
4404+   This is an initializer for a vector of HARD_REG_SET
4405+   of length N_REG_CLASSES.  */
4406+
4407+#define D_REGSET	(D_REGBIT)
4408+#define ACC_A_REGSET (A_REGBIT)
4409+#define ACC_B_REGSET (D_REGBIT)
4410+#define X_REGSET (X_REGBIT)
4411+#define Z_REGSET (Z_REGBIT)
4412+#define Q_REGSET (D_REGBIT | A_REGBIT)
4413+#define M_REGSET (SOFT_M_REGBITS)
4414+#define CC_REGSET (CC_REGBIT)
4415+#define I_REGSET (A_REGBIT | B_REGBIT | D_REGBIT)
4416+#define T_REGSET (X_REGBIT | Y_REGBIT | U_REGBIT)
4417+#define A_REGSET (X_REGBIT | Y_REGBIT | U_REGBIT | S_REGBIT | PC_REGBIT)
4418+#define S_REGSET (SOFT_FP_REGBIT | SOFT_AP_REGBIT)
4419+#define P_REGSET (D_REGBIT | X_REGBIT | Y_REGBIT | U_REGBIT)
4420+#define G_REGSET \
4421+   (D_REGSET | Q_REGSET | I_REGSET | A_REGSET | M_REGSET | S_REGSET)
4422+#define ALL_REGSET (G_REGSET)
4423+
4424+#define REG_CLASS_CONTENTS { \
4425+	{0}, \
4426+	{D_REGSET}, \
4427+   {ACC_A_REGSET}, \
4428+   {ACC_B_REGSET}, \
4429+   {X_REGSET}, \
4430+   {Z_REGSET}, \
4431+	{Q_REGSET}, \
4432+	{M_REGSET}, \
4433+   {CC_REGSET}, \
4434+	{I_REGSET}, \
4435+	{T_REGSET}, \
4436+	{A_REGSET}, \
4437+	{S_REGSET}, \
4438+	{P_REGSET}, \
4439+	{G_REGSET}, \
4440+	{ALL_REGSET}, \
4441+}
4442+
4443+/* The same information, inverted.
4444+ * This is defined to use the REG_CLASS_CONTENTS defines above, so that
4445+ * these two sets of definitions are always consistent. */
4446+
4447+#define REGNO_REG_CLASS(REGNO) \
4448+  (D_REGNO_P (REGNO) ? D_REGS : \
4449+  (Z_REGNO_P (REGNO) ? Z_REGS : \
4450+  (ACC_A_REGNO_P (REGNO) ? ACC_A_REGS : \
4451+  (ACC_B_REGNO_P (REGNO) ? ACC_B_REGS : \
4452+  (X_REGNO_P (REGNO) ? X_REGS : \
4453+  (Q_REGNO_P (REGNO) ? Q_REGS : \
4454+  (M_REGNO_P (REGNO) ? M_REGS : \
4455+  (CC_REGNO_P (REGNO) ? CC_REGS : \
4456+  (I_REGNO_P (REGNO) ? I_REGS : \
4457+  (T_REGNO_P (REGNO) ? T_REGS : \
4458+  (A_REGNO_P (REGNO) ? A_REGS : \
4459+  (S_REGNO_P (REGNO) ? S_REGS : \
4460+  (P_REGNO_P (REGNO) ? P_REGS : \
4461+  (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS))))))))))))))
4462+
4463+#define D_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, D_REGSET))
4464+#define ACC_A_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, ACC_A_REGSET))
4465+#define ACC_B_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, ACC_B_REGSET))
4466+#define X_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, X_REGSET))
4467+#define Z_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, Z_REGSET))
4468+#define Q_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, Q_REGSET))
4469+#define M_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, M_REGSET))
4470+#define CC_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, CC_REGSET))
4471+#define I_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, I_REGSET))
4472+#define T_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, T_REGSET))
4473+#define A_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, A_REGSET))
4474+#define S_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, S_REGSET))
4475+#define P_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, P_REGSET))
4476+#define G_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, G_REGSET))
4477+
4478+/* Macros that test an rtx 'X' to see if it's in a particular
4479+ * register class.  'X' need not be a REG necessarily. */
4480+
4481+#define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
4482+#define ACC_A_REG_P(X) (REG_P (X) && ACC_A_REGNO_P (REGNO (X)))
4483+#define ACC_B_REG_P(X) (REG_P (X) && ACC_B_REGNO_P (REGNO (X)))
4484+#define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X)))
4485+#define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X)))
4486+#define I_REG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
4487+#define T_REG_P(X) (REG_P (X) && T_REGNO_P (REGNO (X)))
4488+#define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
4489+#define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))
4490+#define P_REG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
4491+#define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X)))
4492+#define M_REG_P(X) (REG_P (X) && M_REGNO_P (REGNO (X)))
4493+#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
4494+
4495+/* Redefine this in terms of BYTE_REGSET */
4496+#define BYTE_REGNO_P(REGNO) (REGSET_CONTAINS_P (REGNO, BYTE_REGSET))
4497+
4498+/* The class value for index registers, and the one for base regs.  */
4499+#define INDEX_REG_CLASS I_REGS
4500+#define BASE_REG_CLASS A_REGS
4501+
4502+/* Get reg_class from a letter in the machine description.  */
4503+#define REG_CLASS_FROM_LETTER(C) \
4504+  (((C) == 'a' ? A_REGS : \
4505+   ((C) == 'd' ? D_REGS : \
4506+	((C) == 'x' ? I_REGS : \
4507+	((C) == 't' ? M_REGS : \
4508+	((C) == 'c' ? CC_REGS : \
4509+	((C) == 'A' ? ACC_A_REGS : \
4510+	((C) == 'B' ? ACC_B_REGS : \
4511+	((C) == 'v' ? X_REGS : \
4512+	((C) == 'u' ? S_REGS : \
4513+	((C) == 'U' ? P_REGS : \
4514+	((C) == 'T' ? T_REGS : \
4515+	((C) == 'z' ? Z_REGS : \
4516+   ((C) == 'q' ? Q_REGS : NO_REGS))))))))))))))
4517+
4518+/*--------------------------------------------------------------
4519+   The letters I through O in a register constraint string
4520+   can be used to stand for particular ranges of immediate operands.
4521+   This macro defines what the ranges are.
4522+   C is the letter, and VALUE is a constant value.
4523+   Return 1 if VALUE is in the range specified by C.
4524+
4525+   For the 6809, J, K, L are used for indexed addressing.
4526+   `I' is used for the constant 1.
4527+   `J' is used for the 5-bit offsets.
4528+   `K' is used for the 8-bit offsets.
4529+   `L' is used for the range of signed numbers that fit in 16 bits.
4530+   `M' is used for the exact value '8'.
4531+   `N' is used for the constant -1.
4532+   `O' is used for the constant 0.
4533+--------------------------------------------------------------*/
4534+
4535+#define CONST_OK_FOR_LETTER_P(VALUE, C) \
4536+  ((C) == 'I' ? ((VALUE) == 1) : \
4537+   (C) == 'J' ? ((VALUE) >= -16 && (VALUE) <= 15) : \
4538+   (C) == 'K' ? ((VALUE) >= -128 && (VALUE) <= 127) : \
4539+   (C) == 'L' ? ((VALUE) >= -32768 && (VALUE) <= 32767) : \
4540+   (C) == 'M' ? ((VALUE) == 8) : \
4541+   (C) == 'N' ? ((VALUE) == -1) : \
4542+   (C) == 'O' ? ((VALUE) == 0) : 0)
4543+
4544+/* Similar, but for floating constants, and defining letters G and H.
4545+   No floating-point constants are valid on MC6809.  */
4546+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
4547+   ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
4548+     && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0)
4549+
4550+/* Given an rtx X being reloaded into a reg required to be
4551+   in class CLASS, return the class of reg to actually use.
4552+   In general this is just CLASS; but on some machines
4553+   in some cases it is preferable to use a more restrictive class.  */
4554+#define PREFERRED_RELOAD_CLASS(X,CLASS) m6809_preferred_reload_class(X,CLASS)
4555+
4556+#define SMALL_REGISTER_CLASSES  1
4557+
4558+/* Return the maximum number of consecutive registers
4559+   needed to represent mode MODE in a register of class CLASS.  */
4560+#define CLASS_MAX_NREGS(CLASS, MODE) \
4561+    ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4562+
4563+/*--------------------------------------------------------------
4564+	Stack layout; function entry, exit and calling.
4565+--------------------------------------------------------------*/
4566+
4567+/* Define this if pushing a word on the stack
4568+   makes the stack pointer a smaller address.  */
4569+#define STACK_GROWS_DOWNWARD
4570+
4571+
4572+/* Define this if the nominal address of the stack frame
4573+   is at the high-address end of the local variables;
4574+   that is, each additional local variable allocated
4575+   goes at a more negative offset in the frame.  */
4576+#define FRAME_GROWS_DOWNWARD 1
4577+
4578+
4579+/* Offset within stack frame to start allocating local variables at.
4580+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
4581+   first local allocated.  Otherwise, it is the offset to the BEGINNING
4582+   of the first local allocated.  */
4583+#define STARTING_FRAME_OFFSET 0
4584+
4585+
4586+/* Always push stack arguments for now.  Accumulation is not yet working. */
4587+#define PUSH_ROUNDING(BYTES) (BYTES)
4588+
4589+
4590+/* Offset of first parameter from the argument pointer register value.
4591+ * ARG_POINTER_REGNUM is defined to point to the return address pushed
4592+ * onto the stack, so we must offset by 2 bytes to get to the arguments. */
4593+#define FIRST_PARM_OFFSET(FNDECL) 2
4594+
4595+/* Value is 1 if returning from a function call automatically
4596+   pops the arguments described by the number-of-args field in the call.
4597+   FUNTYPE is the data type of the function (as a tree),
4598+   or for a library call it is an identifier node for the subroutine name. */
4599+/* #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 */
4600+
4601+/* Define how to find the value returned by a function.
4602+   VALTYPE is the data type of the value (as a tree).
4603+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
4604+   otherwise, FUNC is 0.  */
4605+#define FUNCTION_VALUE(VALTYPE, FUNC) m6809_function_value (VALTYPE, FUNC)
4606+
4607+/* Define how to find the value returned by a library function
4608+   assuming the value has mode MODE.  */
4609+
4610+/* All return values are in the X-register. */
4611+#define LIBCALL_VALUE(MODE)  gen_rtx_REG (MODE, HARD_X_REGNUM)
4612+
4613+/* Define this if using the nonreentrant convention for returning
4614+   structure and union values.  No; it is inefficient and buggy. */
4615+#undef PCC_STATIC_STRUCT_RETURN
4616+
4617+/* 1 if N is a possible register number for a function value. */
4618+#define FUNCTION_VALUE_REGNO_P(N) m6809_function_value_regno_p (N)
4619+
4620+/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
4621+   more than one register.  */
4622+#define NEEDS_UNTYPED_CALL 1
4623+
4624+/* 1 if N is a possible register number for function argument passing. */
4625+#define FUNCTION_ARG_REGNO_P(N) \
4626+	((m6809_abi_version != M6809_ABI_VERSION_STACK) ? \
4627+   	(((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM)) : \
4628+		0)
4629+
4630+/*--------------------------------------------------------------
4631+	Argument Lists
4632+--------------------------------------------------------------*/
4633+
4634+/* Cumulative arguments are tracked in a single integer, 
4635+ * which is the number of bytes of arguments scanned so far,
4636+ * plus which registers have already been used.  The register
4637+ * info is kept in some of the upper bits */
4638+#define CUMULATIVE_ARGS unsigned int
4639+
4640+#define CUM_STACK_ONLY 0x80000000
4641+#define CUM_X_MASK     0x40000000
4642+#define CUM_B_MASK     0x20000000
4643+#define CUM_STACK_INVALID 0x10000000
4644+#define CUM_STACK_MASK 0xFFFFFFF
4645+
4646+#define CUM_ADVANCE_8BIT(cum) \
4647+	(((cum) & CUM_B_MASK) ? (cum)++ : ((cum) |= CUM_B_MASK))
4648+
4649+#define CUM_ADVANCE_16BIT(cum) \
4650+	(((cum) & CUM_X_MASK) ? (cum) += 2 : ((cum) |= CUM_X_MASK))
4651+
4652+/* Initialize a variable CUM of type CUMULATIVE_ARGS
4653+   for a call to a function whose data type is FNTYPE.
4654+   For a library call, FNTYPE is 0.
4655+	N_NAMED was added in gcc 3.4 and is not used currently. */
4656+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED) \
4657+	((CUM) = m6809_init_cumulative_args (CUM, FNTYPE, LIBNAME))
4658+
4659+#define FUNCTION_ARG_SIZE(MODE, TYPE)	\
4660+  ((MODE) != BLKmode ? GET_MODE_SIZE (MODE)	\
4661+   : (unsigned) int_size_in_bytes (TYPE))
4662+
4663+/* Update the data in CUM to advance over an argument
4664+   of mode MODE and data type TYPE.
4665+   (TYPE is null for libcalls where that information may not be available.)  */
4666+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
4667+	 (((MODE == QImode) && !((CUM) & CUM_STACK_ONLY)) ? \
4668+		CUM_ADVANCE_8BIT (CUM) : \
4669+	  ((MODE == HImode) && !((CUM) & CUM_STACK_ONLY)) ? \
4670+		CUM_ADVANCE_16BIT (CUM) : \
4671+	  ((CUM) = ((CUM) + (TYPE ? int_size_in_bytes (TYPE) : 2))))
4672+
4673+/* Define where to put the arguments to a function.
4674+   Value is zero to push the argument on the stack,
4675+   or a hard register rtx in which to store the argument.
4676+	This macro is used _before_ FUNCTION_ARG_ADVANCE.
4677+
4678+	For the 6809, the first 8-bit function argument can be placed into B,
4679+	and the first 16-bit arg can go into X.  All other arguments
4680+	will be pushed onto the stack.
4681+
4682+	Command-line options can adjust this behavior somewhat.
4683+ */
4684+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
4685+	((MODE == VOIDmode) ? NULL_RTX : \
4686+	((MODE == BLKmode) || (GET_MODE_SIZE (MODE) > 2)) ? NULL_RTX : \
4687+	((MODE == QImode) && !((CUM) & (CUM_STACK_ONLY | CUM_B_MASK))) ? \
4688+		gen_rtx_REG (QImode, HARD_D_REGNUM) : \
4689+	((MODE == HImode) && !((CUM) & (CUM_STACK_ONLY | CUM_X_MASK))) ?  \
4690+		gen_rtx_REG (HImode, HARD_X_REGNUM) : m6809_function_arg_on_stack (&CUM))
4691+
4692+/* Output assembler code to FILE to increment profiler label # LABELNO
4693+   for profiling a function entry.  */
4694+#define FUNCTION_PROFILER(FILE, LABELNO) \
4695+   fprintf (FILE, "\tldd\t#LP%u\n\tjsr\tmcount\n", (LABELNO));
4696+
4697+/* Stack pointer must be correct on function exit */
4698+#define EXIT_IGNORE_STACK 0
4699+
4700+/*****************************************************************************
4701+**
4702+** Trampolines for Nested Functions
4703+**
4704+*****************************************************************************/
4705+
4706+/* Length in units of the trampoline for entering a nested function.  */
4707+#define TRAMPOLINE_SIZE 7
4708+
4709+/*--------------------------------------------------------------
4710+	Addressing modes,
4711+	and classification of registers for them.
4712+--------------------------------------------------------------*/
4713+
4714+/* 6809 has postincrement and predecrement addressing modes */
4715+#define HAVE_POST_INCREMENT  1
4716+#define HAVE_PRE_DECREMENT  1
4717+
4718+/* Whether or not to use index registers is configurable.
4719+ * Experiments show that things work better when this is off, so
4720+ * that's the way it is for now. */
4721+#undef USE_INDEX_REGISTERS
4722+
4723+
4724+/* Macros to check register numbers against specific register classes.  */
4725+#define REG_VALID_FOR_BASE_P(REGNO) \
4726+	(((REGNO) < FIRST_PSEUDO_REGISTER) && A_REGNO_P (REGNO))
4727+
4728+/* MC6809 index registers do not allow scaling, */
4729+/* but there is "accumulator-offset" mode. */
4730+#ifdef USE_INDEX_REGISTERS
4731+#define REG_VALID_FOR_INDEX_P(REGNO) \
4732+	(((REGNO) < FIRST_PSEUDO_REGISTER) && I_REGNO_P (REGNO))
4733+#else
4734+#define REG_VALID_FOR_INDEX_P(REGNO) 0
4735+#endif
4736+
4737+/* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P */
4738+#define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
4739+   ((REGNO) >= FIRST_PSEUDO_REGISTER \
4740+	|| REG_VALID_FOR_BASE_P (REGNO) \
4741+	|| (REGNO) == FRAME_POINTER_REGNUM \
4742+	|| (REGNO) == HARD_FRAME_POINTER_REGNUM \
4743+	|| (REGNO) == ARG_POINTER_REGNUM \
4744+	|| (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO])))
4745+
4746+/* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P */
4747+#define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
4748+   ((REGNO) >= FIRST_PSEUDO_REGISTER \
4749+	|| REG_VALID_FOR_INDEX_P (REGNO) \
4750+	|| (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))
4751+
4752+
4753+/* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P */
4754+#define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \
4755+	((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \
4756+	: (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO])))
4757+
4758+
4759+/* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P */
4760+#define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \
4761+	((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \
4762+	: (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))
4763+
4764+
4765+#define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO)
4766+
4767+#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO)
4768+
4769+#define REG_OK_FOR_BASE_STRICT_P(X)     REGNO_OK_FOR_BASE_STRICT_P (REGNO (X))
4770+#define REG_OK_FOR_BASE_NONSTRICT_P(X)  REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X))
4771+#define REG_OK_FOR_INDEX_STRICT_P(X)    REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X))
4772+#define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X))
4773+
4774+#ifndef REG_OK_STRICT
4775+#define REG_OK_FOR_BASE_P(X)     REG_OK_FOR_BASE_NONSTRICT_P(X)
4776+#ifdef USE_INDEX_REGISTERS
4777+#define REG_OK_FOR_INDEX_P(X)    REG_OK_FOR_INDEX_NONSTRICT_P(X)
4778+#else
4779+#define REG_OK_FOR_INDEX_P(X)    0
4780+#endif
4781+#else
4782+#define REG_OK_FOR_BASE_P(X)     REG_OK_FOR_BASE_STRICT_P (X)
4783+#ifdef USE_INDEX_REGISTERS
4784+#define REG_OK_FOR_INDEX_P(X)    REG_OK_FOR_INDEX_STRICT_P (X)
4785+#else
4786+#define REG_OK_FOR_INDEX_P(X)    0
4787+#endif
4788+#endif
4789+
4790+/* Maximum number of registers that can appear in a valid memory address */
4791+#ifdef USE_INDEX_REGISTERS
4792+#define MAX_REGS_PER_ADDRESS 2
4793+#else
4794+#define MAX_REGS_PER_ADDRESS 1
4795+#endif
4796+
4797+/* 1 if X is an rtx for a constant that is a valid address.
4798+ * We allow any constant, plus the sum of any two constants (this allows
4799+ * offsetting a symbol ref) */
4800+#define CONSTANT_ADDRESS_P(X) \
4801+	((CONSTANT_P (X)) \
4802+	|| ((GET_CODE (X) == PLUS) \
4803+	      && (CONSTANT_P (XEXP (X, 0))) && (CONSTANT_P (XEXP (X, 1)))))
4804+
4805+/* Nonzero if the constant value X is a legitimate general operand.
4806+   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
4807+/* Any single-word constant is ok; the only contexts
4808+   allowing general_operand of mode DI or DF are movdi and movdf. */
4809+#define LEGITIMATE_CONSTANT_P(X) (GET_CODE (X) != CONST_DOUBLE)
4810+
4811+/* Nonzero if the X is a legitimate immediate operand in PIC mode. */
4812+#define LEGITIMATE_PIC_OPERAND_P(X)	!symbolic_operand (X, VOIDmode)
4813+
4814+/*--------------------------------------------------------------
4815+	Test for valid memory addresses
4816+--------------------------------------------------------------*/
4817+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
4818+   that is a valid memory address for an instruction.
4819+   The MODE argument is the machine mode for the MEM expression
4820+   that wants to use this address. */
4821+
4822+/*--------------------------------------------------------------
4823+   Valid addresses are either direct or indirect (MEM) versions
4824+   of the following forms.
4825+	constant		N
4826+	register		,X
4827+	constant indexed	N,X
4828+	accumulator indexed	D,X
4829+	auto_increment		,X++
4830+	auto_decrement		,--X
4831+--------------------------------------------------------------*/
4832+
4833+#define REGISTER_ADDRESS_P(X) \
4834+  (REG_P (X) && REG_OK_FOR_BASE_P (X))
4835+
4836+#define EXTENDED_ADDRESS_P(X) \
4837+    CONSTANT_ADDRESS_P (X) \
4838+
4839+#define LEGITIMATE_BASE_P(X) \
4840+  ((REG_P (X) && REG_OK_FOR_BASE_P (X))	\
4841+   || (GET_CODE (X) == SIGN_EXTEND			\
4842+       && GET_CODE (XEXP (X, 0)) == REG			\
4843+       && GET_MODE (XEXP (X, 0)) == HImode		\
4844+       && REG_OK_FOR_BASE_P (XEXP (X, 0))))
4845+
4846+#define LEGITIMATE_OFFSET_P(X) \
4847+    (CONSTANT_ADDRESS_P (X) || (REG_P (X) && REG_OK_FOR_INDEX_P (X)))
4848+
4849+/* 1 if X is the sum of a base register and an offset. */
4850+#define INDEXED_ADDRESS(X) \
4851+   ((GET_CODE (X) == PLUS \
4852+       && LEGITIMATE_BASE_P (XEXP (X, 0)) \
4853+       && LEGITIMATE_OFFSET_P (XEXP (X, 1))) \
4854+   || (GET_CODE (X) == PLUS \
4855+       && LEGITIMATE_BASE_P (XEXP (X, 1)) \
4856+       && LEGITIMATE_OFFSET_P (XEXP (X, 0))))
4857+
4858+#define STACK_REG_P(X) (REG_P(X) && REGNO(X) == HARD_S_REGNUM)
4859+
4860+#define STACK_PUSH_P(X) \
4861+   (MEM_P (X) && GET_CODE (XEXP (X, 0)) == PRE_DEC && STACK_REG_P (XEXP (XEXP (X, 0), 0)))
4862+
4863+#define STACK_POP_P(X) \
4864+   (MEM_P (X) && GET_CODE (XEXP (X, 0)) == POST_INC && STACK_REG_P (XEXP (XEXP (X, 0), 0)))
4865+
4866+#define PUSH_POP_ADDRESS_P(X) \
4867+    (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \
4868+	&& (LEGITIMATE_BASE_P (XEXP (X, 0))))
4869+
4870+/* Go to ADDR if X is a valid address. */
4871+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
4872+{ \
4873+  if (REGISTER_ADDRESS_P(X)) goto ADDR; \
4874+  if (PUSH_POP_ADDRESS_P (X)) goto ADDR; \
4875+  if (EXTENDED_ADDRESS_P (X)) goto ADDR; \
4876+  if (INDEXED_ADDRESS (X)) goto ADDR; \
4877+  if (MEM_P (X) && REGISTER_ADDRESS_P(XEXP (X, 0))) goto ADDR; \
4878+  if (MEM_P (X) && PUSH_POP_ADDRESS_P (XEXP (X, 0))) goto ADDR; \
4879+  if (MEM_P (X) && EXTENDED_ADDRESS_P (XEXP (X, 0))) goto ADDR; \
4880+  if (MEM_P (X) && INDEXED_ADDRESS (XEXP (X, 0))) goto ADDR; \
4881+}
4882+
4883+/*--------------------------------------------------------------
4884+	Address Fix-up
4885+--------------------------------------------------------------*/
4886+/* Go to LABEL if ADDR (a legitimate address expression)
4887+   has an effect that depends on the machine mode it is used for.
4888+	In the latest GCC, this case is already handled by the core code
4889+	so no action is required here. */
4890+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
4891+
4892+
4893+/*--------------------------------------------------------------
4894+	Miscellaneous Parameters
4895+--------------------------------------------------------------*/
4896+/* Specify the machine mode that this machine uses
4897+   for the index in the tablejump instruction.  */
4898+#define CASE_VECTOR_MODE Pmode
4899+
4900+/* Define this as 1 if `char' should by default be signed; else as 0.  */
4901+#define DEFAULT_SIGNED_CHAR 0
4902+
4903+/* This flag, if defined, says the same insns that convert to a signed fixnum
4904+   also convert validly to an unsigned one.  */
4905+#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
4906+
4907+/* Max number of bytes we can move from memory to memory/register
4908+   in one reasonably fast instruction.  */
4909+#define MOVE_MAX 2
4910+
4911+/* Int can be 8 or 16 bits (default is 16) */
4912+#define INT_TYPE_SIZE (TARGET_BYTE_INT ? 8 : 16)
4913+
4914+/* Short is always 16 bits */
4915+#define SHORT_TYPE_SIZE (TARGET_BYTE_INT ? 8 : 16)
4916+
4917+/* Size (bits) of the type "long" on target machine */
4918+#define LONG_TYPE_SIZE (TARGET_BYTE_INT ? 16 : 32)
4919+
4920+/* Size (bits) of the type "long long" on target machine */
4921+#define LONG_LONG_TYPE_SIZE 32
4922+
4923+/* Size (bits) of the type "char" on target machine */
4924+#define CHAR_TYPE_SIZE 8
4925+
4926+/* Size (bits) of the type "float" on target machine */
4927+#define FLOAT_TYPE_SIZE 32
4928+
4929+/* Size (bits) of the type "double" on target machine.
4930+ * Note that the C standard does not require that doubles
4931+ * hold any more bits than float.  Since the 6809 has so few
4932+ * registers, we cannot really support more than 32-bits. */
4933+#define DOUBLE_TYPE_SIZE 32 
4934+
4935+/* Size (bits) of the type "long double" on target machine */
4936+#define LONG_DOUBLE_TYPE_SIZE 32
4937+
4938+/* Define the type used for "size_t".  With a 64KB address space,
4939+ * only a 16-bit value here makes sense. */
4940+#define SIZE_TYPE (TARGET_BYTE_INT ? "long unsigned int" : "unsigned int")
4941+
4942+/* Likewise, the difference between two pointers is also a 16-bit
4943+ * signed value. */
4944+#define PTRDIFF_TYPE (TARGET_BYTE_INT ? "long int" : "int")
4945+
4946+/* Nonzero if access to memory by bytes is slow and undesirable.  */
4947+#define SLOW_BYTE_ACCESS 0
4948+
4949+/* Define if shifts truncate the shift count
4950+   which implies one can omit a sign-extension or zero-extension
4951+   of a shift count.  */
4952+#define SHIFT_COUNT_TRUNCATED 0
4953+
4954+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
4955+   is done just by pretending it is already truncated.  */
4956+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
4957+
4958+/* It is as good to call a constant function address as to
4959+   call an address kept in a register. */
4960+#define NO_FUNCTION_CSE
4961+
4962+/* Specify the machine mode that pointers have.
4963+   After generation of rtl, the compiler makes no further distinction
4964+   between pointers and any other objects of this machine mode.  */
4965+#define Pmode HImode
4966+
4967+/* A function address in a call instruction
4968+   is a byte address (for indexing purposes)
4969+   so give the MEM rtx a byte's mode.  */
4970+#define FUNCTION_MODE HImode
4971+
4972+/* Define the cost of moving a value from a register in CLASS1
4973+ * to CLASS2, of a given MODE.
4974+ *
4975+ * On the 6809, hard register transfers are all basically equivalent.
4976+ * But soft register moves are treated more like memory moves. */
4977+#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
4978+	(((CLASS1 == M_REGS) || (CLASS2 == M_REGS)) ? 4 : 7)
4979+
4980+/* Define the cost of moving a value between a register and memory. */
4981+#define MEMORY_MOVE_COST(MODE, CLASS, IN) 5
4982+
4983+/* Check a `double' value for validity for a particular machine mode.  */
4984+
4985+#define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
4986+  ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
4987+
4988+
4989+/*--------------------------------------------------------------
4990+	machine-dependent
4991+--------------------------------------------------------------*/
4992+/* Tell final.c how to eliminate redundant test instructions.  */
4993+
4994+/* Here we define machine-dependent flags and fields in cc_status
4995+   (see `conditions.h').  */
4996+
4997+/* Store in cc_status the expressions
4998+   that the condition codes will describe
4999+   after execution of an instruction whose pattern is EXP.
5000+   Do not alter them if the instruction would not alter the cc's.  */
5001+
5002+/* On the 6809, most of the insns to store in an address register
5003+   fail to set the cc's.  However, in some cases these instructions
5004+   can make it possibly invalid to use the saved cc's.  In those
5005+   cases we clear out some or all of the saved cc's so they won't be used.  */
5006+
5007+#define NOTICE_UPDATE_CC(EXP, INSN) \
5008+  notice_update_cc((EXP), (INSN))
5009+
5010+/*****************************************************************************
5011+**
5012+** pragma support
5013+**
5014+*****************************************************************************/
5015+
5016+#if 0
5017+#define REGISTER_TARGET_PRAGMAS() \
5018+do { \
5019+	extern void pragma_section PARAMS ((cpp_reader *)); \
5020+	c_register_pragma (0, "section", pragma_section); \
5021+} while (0)
5022+
5023+#endif
5024+
5025+/*--------------------------------------------------------------
5026+	ASSEMBLER FORMAT
5027+--------------------------------------------------------------*/
5028+
5029+#define FMT_HOST_WIDE_INT "%ld"
5030+
5031+/* Output to assembler file text saying following lines
5032+   may contain character constants, extra white space, comments, etc.  */
5033+#define ASM_APP_ON ";----- asm -----\n"
5034+
5035+/* Output to assembler file text saying following lines
5036+   no longer contain unusual constructs.  */
5037+#define ASM_APP_OFF ";--- end asm ---\n"
5038+
5039+/* Use a semicolon to begin a comment. */
5040+#define ASM_COMMENT_START "; "
5041+
5042+/* Output assembly directives to switch to section 'name' */
5043+#undef TARGET_ASM_NAMED_SECTION
5044+#define TARGET_ASM_NAMED_SECTION	m6809_asm_named_section
5045+
5046+#undef TARGET_HAVE_NAMED_SECTION
5047+#define TARGET_HAVE_NAMED_SECTION m6809_have_named_section
5048+
5049+/* Output before read-only data.  */
5050+#define TEXT_SECTION_ASM_OP (code_section_op)
5051+
5052+/* Output before writable data.  */
5053+#define DATA_SECTION_ASM_OP (data_section_op)
5054+
5055+/* Output before uninitialized data.  */
5056+#define BSS_SECTION_ASM_OP (bss_section_op)
5057+
5058+/* Support the ctors and dtors sections for g++.  */
5059+ 
5060+#undef CTORS_SECTION_ASM_OP
5061+#define CTORS_SECTION_ASM_OP    "\t.area .ctors"
5062+#undef DTORS_SECTION_ASM_OP
5063+#define DTORS_SECTION_ASM_OP    "\t.area .dtors"
5064+
5065+
5066+#undef DO_GLOBAL_CTORS_BODY
5067+#undef DO_GLOBAL_DTORS_BODY
5068+
5069+#define HAS_INIT_SECTION
5070+
5071+/* This is how to output an assembler line
5072+   that says to advance the location counter
5073+   to a multiple of 2**LOG bytes.  */
5074+
5075+#define ASM_OUTPUT_ALIGN(FILE,LOG) \
5076+  if ((LOG) > 1) \
5077+    fprintf (FILE, "\t.bndry %u\n", 1 << (LOG))
5078+
5079+/* The .set foo,bar construct doesn't work by default */
5080+#undef SET_ASM_OP
5081+#define ASM_OUTPUT_DEF(FILE, LABEL1, LABEL2)			\
5082+  do								\
5083+    {								\
5084+      fputc ('\t', FILE);					\
5085+      assemble_name (FILE, LABEL1);				\
5086+      fputs (" = ", FILE);					\
5087+      assemble_name (FILE, LABEL2);				\
5088+      fputc ('\n', FILE);					\
5089+    }								\
5090+  while (0)
5091+
5092+/* How to refer to registers in assembler output.
5093+   This sequence is indexed by compiler's hard-register-number (see above).  */
5094+#define MNAME(x) [SOFT_M0_REGNUM+(x)] = "*m" C_STRING(x) ,
5095+
5096+#define REGISTER_NAMES { \
5097+	[HARD_D_REGNUM]= "d", \
5098+	[HARD_X_REGNUM]= "x", \
5099+	[HARD_Y_REGNUM]= "y", \
5100+	[HARD_U_REGNUM]= "u", \
5101+	[HARD_S_REGNUM]= "s", \
5102+	[HARD_PC_REGNUM]= "pc", \
5103+	[HARD_A_REGNUM]= "a", \
5104+	[HARD_B_REGNUM]= "b", \
5105+	[HARD_CC_REGNUM]= "cc",\
5106+	[HARD_DP_REGNUM]= "dp", \
5107+	[SOFT_FP_REGNUM]= "soft_fp", \
5108+	[SOFT_AP_REGNUM]= "soft_ap", \
5109+	MNAME(0) MNAME(1) MNAME(2) MNAME(3) \
5110+	MNAME(4) MNAME(5) MNAME(6) MNAME(7) \
5111+	[HARD_RSVD1_REGNUM] = "-", \
5112+	[HARD_Z_REGNUM] = "z" /* bit 2 of CC */ }
5113+
5114+/*****************************************************************************
5115+**
5116+** Debug Support
5117+**
5118+*****************************************************************************/
5119+
5120+/* Default to DBX-style debugging */
5121+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
5122+
5123+#define DBX_DEBUGGING_INFO
5124+
5125+#define DEFAULT_GDB_EXTENSIONS 0
5126+
5127+#define ASM_STABS_OP ";\t.stabs\t"
5128+#define ASM_STABD_OP ";\t.stabd\t"
5129+#define ASM_STABN_OP ";\t.stabn\t"
5130+
5131+#define DBX_CONTIN_LENGTH 54
5132+
5133+#define DBX_OUTPUT_MAIN_SOURCE_FILENAME(ASMFILE, FILENAME) \
5134+do { \
5135+	const char *p = FILENAME; \
5136+	while ((p = strchr (p, '/')) != NULL) { \
5137+		p = FILENAME = p+1; \
5138+	} \
5139+  fprintf (ASMFILE, "%s", ASM_STABS_OP); \
5140+  output_quoted_string (ASMFILE, FILENAME); \
5141+  fprintf (ASMFILE, ",%d,0,0,", N_SO); \
5142+  assemble_name (ASMFILE, ltext_label_name); \
5143+  fputc ('\n', ASMFILE); \
5144+  switch_to_section (text_section); \
5145+  (*targetm.asm_out.internal_label) (ASMFILE, "Ltext", 0); \
5146+} while (0)
5147+
5148+/* With -g, GCC sometimes outputs string literals that are longer than
5149+ * the assembler can handle.  Without actual debug support, these are
5150+ * not really required.  Redefine the function to output strings to
5151+ * output as much as possible. */
5152+#define OUTPUT_QUOTED_STRING(FILE, STR) m6809_output_quoted_string (FILE, STR)
5153+
5154+/*****************************************************************************
5155+**
5156+** Output and Generation of Labels
5157+**
5158+*****************************************************************************/
5159+
5160+/* Prefixes for various assembly-time objects */
5161+
5162+#define REGISTER_PREFIX ""
5163+
5164+#define LOCAL_LABEL_PREFIX ""
5165+
5166+#define USER_LABEL_PREFIX "_"
5167+
5168+#define IMMEDIATE_PREFIX "#"
5169+
5170+/* This is how to output the definition of a user-level label named NAME,
5171+   such as the label on a static function or variable NAME.  */
5172+
5173+#define ASM_OUTPUT_LABEL(FILE,NAME) \
5174+do { \
5175+  if (section_changed) { \
5176+	  fprintf (FILE, "\n%s\n\n", code_section_op); \
5177+     section_changed = 0; \
5178+  } \
5179+  assemble_name (FILE, NAME); \
5180+  fputs (":\n", FILE); \
5181+} while (0)
5182+
5183+/* This is how to output the label for a function definition.  It
5184+   invokes ASM_OUTPUT_LABEL, but may examine the DECL tree node for
5185+	other properties. */
5186+#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
5187+  m6809_declare_function_name (FILE,NAME,DECL)
5188+
5189+/* This is how to output a command to make the user-level label
5190+    named NAME defined for reference from other files.  */
5191+
5192+#define GLOBAL_ASM_OP "\t.globl "
5193+
5194+/* This is how to output a reference to a user label named NAME. */
5195+#define ASM_OUTPUT_LABELREF(FILE,NAME) \
5196+  fprintf (FILE, "_%s", NAME)
5197+
5198+/* This is how to output a reference to a symbol ref
5199+ * Check to see if the symbol is in the direct page */
5200+#define ASM_OUTPUT_SYMBOL_REF(FILE,sym) \
5201+{ \
5202+	print_direct_prefix (FILE, sym); \
5203+	assemble_name (FILE, XSTR (sym, 0)); \
5204+}
5205+
5206+/* External references aren't necessary, so don't emit anything */
5207+#define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME)
5208+
5209+/* This is how to store into the string LABEL
5210+   the symbol_ref name of an internal numbered label where
5211+   PREFIX is the class of label and NUM is the number within the class.
5212+   This is suitable for output with `assemble_name'.  */
5213+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
5214+  sprintf (LABEL, "*%s%lu", PREFIX, (unsigned long int)NUM)
5215+
5216+/* This is how to output an assembler line defining an `int' constant.  */
5217+#define ASM_OUTPUT_INT(FILE,VALUE) \
5218+( fprintf (FILE, "\t.word "), \
5219+  output_addr_const (FILE, (VALUE)), \
5220+  fprintf (FILE, "\n"))
5221+
5222+/* Likewise for `char' and `short' constants.  */
5223+#define ASM_OUTPUT_SHORT(FILE,VALUE) \
5224+( fprintf (FILE, "\t.word "), \
5225+  output_addr_const (FILE, (VALUE)), \
5226+  fprintf (FILE, "\n"))
5227+
5228+/* This is how to output a string. */ 
5229+#define ASM_OUTPUT_ASCII(FILE,STR,SIZE) m6809_output_ascii (FILE, STR, SIZE)
5230+
5231+/* This is how to output an insn to push a register on the stack.
5232+   It need not be very fast code.  */
5233+
5234+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
5235+   fprintf (FILE, "\tpshs\t%s\n", reg_names[REGNO])
5236+
5237+/* This is how to output an insn to pop a register from the stack.
5238+   It need not be very fast code.  */
5239+
5240+#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
5241+   fprintf (FILE, "\tpuls\t%s\n", reg_names[REGNO])
5242+
5243+/* This is how to output an element of a case-vector that is absolute. */
5244+
5245+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
5246+  fprintf (FILE, "\t.word L%u\n", VALUE)
5247+
5248+/* This is how to output an element of a case-vector that is relative. */
5249+
5250+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
5251+  fprintf (FILE, "\t.word L%u-L%u\n", VALUE, REL)
5252+
5253+
5254+/*****************************************************************************
5255+**
5256+** Assembler Commands for Alignment
5257+**
5258+*****************************************************************************/
5259+
5260+/* ASM_OUTPUT_SKIP is supposed to zero initialize the data.
5261+ * So use the .byte and .word directives instead of .blkb */
5262+#define ASM_OUTPUT_SKIP(FILE,SIZE) \
5263+  do { \
5264+    int __size = SIZE; \
5265+    while (__size > 0) { \
5266+      if (__size >= 2) \
5267+      { \
5268+        fprintf (FILE, "\t.word\t0\t;skip space %d\n", __size); \
5269+        __size -= 2; \
5270+      } \
5271+      else \
5272+      { \
5273+        fprintf (FILE, "\t.byte\t0\t;skip space\n"); \
5274+        __size--; \
5275+      } \
5276+    } \
5277+  } while (0)
5278+
5279+/* This says how to output an assembler line
5280+   to define a global common symbol.  */
5281+
5282+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
5283+  do { \
5284+  switch_to_section (bss_section); \
5285+  fputs ("\t.globl\t", FILE); \
5286+  assemble_name ((FILE), (NAME)); \
5287+  fputs ("\n", FILE); \
5288+  assemble_name ((FILE), (NAME)); \
5289+  fprintf ((FILE), ":\t.blkb\t" FMT_HOST_WIDE_INT "\n", (ROUNDED));} while(0)
5290+
5291+/* This says how to output an assembler line
5292+   to define a local common symbol.  */
5293+
5294+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
5295+do { \
5296+  switch_to_section (bss_section); \
5297+  assemble_name ((FILE), (NAME)); \
5298+  fprintf ((FILE), ":\t.blkb\t" FMT_HOST_WIDE_INT "\n", (ROUNDED));} while(0)
5299+
5300+/* Store in OUTPUT a string (made with alloca) containing
5301+   an assembler-name for a local static variable named NAME.
5302+   LABELNO is an integer which is different for each call.  */
5303+
5304+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
5305+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
5306+  sprintf ((OUTPUT), "%s.%lu", (NAME), (unsigned long int)(LABELNO)))
5307+
5308+/* Print an instruction operand X on file FILE.
5309+   CODE is the code from the %-spec for printing this operand.
5310+   If `%z3' was used to print operand 3, then CODE is 'z'. */
5311+#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
5312+
5313+/* Print a memory operand whose address is X, on file FILE. */
5314+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
5315+
5316+/* Don't let stack pushes build up too much. */
5317+#define MAX_PENDING_STACK 8
5318+
5319+/* Define values for builtin operations */
5320+enum m6809_builtins
5321+{
5322+	M6809_SWI,
5323+	M6809_SWI2,
5324+	M6809_SWI3,
5325+	M6809_CWAI,
5326+	M6809_SYNC,
5327+	M6809_ADD_CARRY,
5328+	M6809_SUB_CARRY,
5329+	M6809_ADD_DECIMAL,
5330+	M6809_NOP,
5331+	M6809_BLOCKAGE
5332+};
5333+
5334diff --git a/gcc/config/m6809/m6809.md b/gcc/config/m6809/m6809.md
5335new file mode 100644
5336index 0000000..263aa0f
5337--- /dev/null
5338+++ b/gcc/config/m6809/m6809.md
5339@@ -0,0 +1,2358 @@
5340+;; GCC machine description for Motorola 6809
5341+;; Copyright (C) 1989, 2005, 2006, 2007, 2008,
5342+;; 2009 Free Software Foundation, Inc.
5343+;;
5344+;; Mostly by Brian Dominy (brian@oddchange.com) with substantial renovations
5345+;; by William Astle (lost@l-w.ca).
5346+;;
5347+;; Based on earlier work by Tom Jones (jones@sal.wisc.edu) and
5348+;; Matthias Doerfel (msdoerfe@informatik.uni-erlangen.de)
5349+;;
5350+;; This file is part of GCC.
5351+;;
5352+;; GCC is free software; you can redistribute it and/or modify
5353+;; it under the terms of the GNU General Public License as published by
5354+;; the Free Software Foundation; either version 3, or (at your option)
5355+;; any later version.
5356+;;
5357+;; GCC is distributed in the hope that it will be useful,
5358+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
5359+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5360+;; GNU General Public License for more details.
5361+;;
5362+;; You should have received a copy of the GNU General Public License
5363+;; along with GCC; see the file COPYING3.  If not see
5364+;; <http://www.gnu.org/licenses/>.
5365+;;
5366+;; General information:
5367+;; --------------------
5368+;; * This backend is mostly a rewrite from earlier (3.1.1 and before)
5369+;; versions.
5370+;;
5371+;; * The 'A' and 'B' registers are treated as a single register by the
5372+;; register allocator; hence, the instruction templates assume that
5373+;; both can be modified if either one is available for use.  No
5374+;; attempt is made to split instructions to refer to a particular half
5375+;; of the register.  It is always referred to as the 'D' register, even
5376+;; in QImode (when it will be displayed as 'B').
5377+;;
5378+;; * There is full support for proper branch instruction generation,
5379+;; based on instruction lengths.  However, many instruction patterns
5380+;; are still overloaded to emit lots of real instructions, which can
5381+;; make the length calculation difficult; in those cases, I've tried
5382+;; to be pessimistic and assume the worst-case.
5383+;;
5384+;; * The instruction type attributes are only defined for branch
5385+;; vs. non branch instructions for now, since there is seemingly no
5386+;; reason to define these for other types anyway.
5387+;;
5388+;; * The limited number of total registers presents the greatest
5389+;; challenge.  There are 'soft registers' -- memory locations
5390+;; used to simulate real regs -- which can be helpful.
5391+;;
5392+;; * Position-independent code (PIC) is supported and has been tested
5393+;; but not to the extent of absolute code generation.
5394+;;
5395+;; * All of the 6809 special opcodes, e.g. SWI and SYNC, are defined
5396+;; as UNSPEC instructions, and can be accessed from C code using
5397+;; __builtin_xxxx() style functions.
5398+;;
5399+;; What still needs to be done:
5400+;; ----------------------------
5401+;; * Replace remaining instances of (define_peephole) with
5402+;; (define_peephole2), or remove them completely if they are not
5403+;; matching anyway.  Add more peepholes for things actually encountered.
5404+;;
5405+;; * Indexing addressing can lead to crashes in complex functions when
5406+;; register pressure is high.  Only the 'D' register can actually be
5407+;; used as an index register, and its demand by other instructions
5408+;; can sometimes mean that it is impossible to satisfy constraints.
5409+;; Currently, indexing is completely disabled to avoid these types
5410+;; of problems, although code is slightly more inefficient in some
5411+;; working cases.
5412+;;
5413+;; * 32-bit math is terribly inefficient.
5414+;;
5415+
5416+
5417+;;--------------------------------------------------------------------
5418+;;-  Constants
5419+;;--------------------------------------------------------------------
5420+
5421+;
5422+; Define constants for hard register numbers.
5423+;
5424+(define_constants [
5425+  (HARD_RSVD1_REGNUM 0)
5426+  (HARD_X_REGNUM 1) (HARD_Y_REGNUM 2) (HARD_U_REGNUM 3)
5427+  (HARD_S_REGNUM 4) (HARD_PC_REGNUM 5) (HARD_D_REGNUM 6)
5428+  (HARD_Z_REGNUM 7)
5429+  (HARD_A_REGNUM 8) (HARD_B_REGNUM 9)
5430+  (HARD_CC_REGNUM 10) (HARD_DP_REGNUM 11)
5431+  (SOFT_FP_REGNUM 12) (SOFT_AP_REGNUM 13)
5432+  (SOFT_M0_REGNUM 14) (SOFT_M1_REGNUM 15)
5433+  (SOFT_M2_REGNUM 16) (SOFT_M3_REGNUM 17)
5434+])
5435+
5436+
5437+;
5438+; The range in which a short branch insn can be used.
5439+;
5440+(define_constants [
5441+  (MIN_SHORT_BRANCH_OFFSET -127)
5442+  (MAX_SHORT_BRANCH_OFFSET 128)
5443+])
5444+
5445+
5446+;
5447+; The lengths of various types of real 6809 instructions.
5448+;
5449+; By default, ordinary insns are 4 bytes long.  This is often not
5450+; right, and the insn patterns below will redefine this to the
5451+; correct value.
5452+;
5453+; Branch instruction lengths (conditional and unconditionals) are
5454+; well known and declared here.  The short insns are used when the
5455+; offset is within the range declared above (between MIN_SHORT
5456+; and MAX_SHORT) ; otherwise the long form is used.
5457+;
5458+(define_constants [
5459+  (DEFAULT_INSN_LENGTH 4)
5460+  (SHORT_CBRANCH_LENGTH 2)
5461+  (LONG_CBRANCH_LENGTH 4)
5462+  (SHORT_BRANCH_LENGTH 2)
5463+  (LONG_BRANCH_LENGTH 3)
5464+])
5465+
5466+
5467+;
5468+; Constants for insn cycle counts.
5469+; Note that these counts all assume 1-byte opcodes.  2-byte
5470+; opcodes require 1 extra cycles for fetching the extra byte.
5471+;
5472+(define_constants [
5473+  ;; The default insn length, when it cannot be calculated.
5474+  ;; Take a conservative approach and estimate high.
5475+  (DEFAULT_INSN_CYCLES 10)
5476+
5477+  ;; Cycle counts for ALU and load operations.
5478+  (ALU_INHERENT_CYCLES 2)
5479+  (ALU_IMMED_CYCLES 2)
5480+  (ALU_DIRECT_CYCLES 4)
5481+  (ALU_INDEXED_BASE_CYCLES 4)
5482+  (ALU_EXTENDED_CYCLES 5)
5483+
5484+  ;; If an ALU operation is on a 16-bit register (D), then
5485+  ;; add this number of cycles to the total count.
5486+  (ALU_16BIT_CYCLES 2)
5487+
5488+  ;; A load of a 16-bit register incurs this extra amount.
5489+  (LOAD_16BIT_CYCLES 1)
5490+
5491+  ;; Cycle counts for memory-only operations (bit shifts, clear, test)
5492+  (MEM_DIRECT_CYCLES 6)
5493+  (MEM_INDEXED_BASE_CYCLES 6)
5494+  (MEM_EXTENDED_CYCLES 7)
5495+
5496+  ;; Cycle count for any reg-reg transfer (regardless of size)
5497+  (EXG_CYCLES 8)
5498+  (TFR_CYCLES 6)
5499+
5500+  ;; Cycle count for a condition code update (andcc/orcc)
5501+  (CC_CYCLES 3)
5502+
5503+  (JMP_DIRECT_CYCLES 3)
5504+  (JMP_INDEXED_BASE_CYCLES 3)
5505+  (JMP_EXTENDED_CYCLES 4)
5506+
5507+  (JSR_DIRECT_CYCLES 7)
5508+  (JSR_INDEXED_BASE_CYCLES 7)
5509+  (JSR_EXTENDED_CYCLES 8)
5510+
5511+  (LEA_BASE_CYCLES 4)
5512+
5513+  ;; Cycle count for a psh/pul operations.  Add to this the
5514+  ;; total number of bytes moved for the correct count.
5515+  (PSH_PUL_CYCLES 5)
5516+
5517+  ;; Miscellaneous cycle counts
5518+  (CWAI_CYCLES 20)
5519+  (MUL_CYCLES 11)
5520+  (NOP_CYCLES 2)
5521+  (RTI_CYCLES 15)
5522+  (RTS_CYCLES 5)
5523+  (SWI_CYCLES 20)
5524+  (SYNC_CYCLES 4)
5525+])
5526+
5527+
5528+;
5529+; An enumeration of values for each "unspec"; i.e. unspecified
5530+; instruction.  These represent insns that are meaningful on the
5531+; 6809 but which have no intrinsic meaning to GCC itself.
5532+; These insns can be generated explicitly using the __builtin_xxx
5533+; syntax; they are also implicitly generated by the backend
5534+; as needed to implement other insns.
5535+;
5536+(define_constants [
5537+  (UNSPEC_BLOCKAGE 0)
5538+  (UNSPEC_PUSH_RS 1)
5539+  (UNSPEC_POP_RS 2)
5540+  (UNSPEC_SWI 3)
5541+  (UNSPEC_CWAI 4)
5542+  (UNSPEC_ADD_CARRY 5)
5543+  (UNSPEC_SUB_CARRY 6)
5544+  (UNSPEC_SYNC 7)
5545+  (UNSPEC_ADD_DECIMAL 8)
5546+])
5547+
5548+
5549+;;--------------------------------------------------------------------
5550+;;-  Predicates
5551+;;--------------------------------------------------------------------
5552+
5553+(include "predicates.md")
5554+
5555+;;--------------------------------------------------------------------
5556+;;-  Attributes
5557+;;--------------------------------------------------------------------
5558+
5559+;;
5560+;; The type attribute is used to distinguish between different
5561+;; types of branch instructions, so that their lengths can be
5562+;; calculated correctly.
5563+;;
5564+(define_attr "type" "branch,cbranch,unknown" (const_string "unknown"))
5565+
5566+;;
5567+;; The length of a branch instruction is calculated based on how
5568+;; far away the branch target is.  Lengths of other insns default
5569+;; to 4.  set_attr is used in instruction templates to specify
5570+;; the length when it is known exactly.  When not sure, err on
5571+;; the high side to avoid compile errors.
5572+;;
5573+(define_attr "length" ""
5574+  (cond [
5575+    (eq_attr "type" "branch")
5576+    (if_then_else (lt (minus (match_dup 0) (pc))
5577+                      (const_int MIN_SHORT_BRANCH_OFFSET))
5578+      (const_int LONG_BRANCH_LENGTH)
5579+        (if_then_else (gt (minus (match_dup 0) (pc))
5580+                          (const_int MAX_SHORT_BRANCH_OFFSET))
5581+          (const_int LONG_BRANCH_LENGTH)
5582+          (const_int SHORT_BRANCH_LENGTH)))
5583+    (eq_attr "type" "cbranch")
5584+    (if_then_else (lt (minus (match_dup 0) (pc))
5585+                      (const_int MIN_SHORT_BRANCH_OFFSET))
5586+      (const_int LONG_CBRANCH_LENGTH)
5587+        (if_then_else (gt (minus (match_dup 0) (pc))
5588+                          (const_int MAX_SHORT_BRANCH_OFFSET))
5589+          (const_int LONG_CBRANCH_LENGTH)
5590+          (const_int SHORT_CBRANCH_LENGTH)))
5591+  ] (const_int DEFAULT_INSN_LENGTH)))
5592+
5593+
5594+;;
5595+;; The default attributes for 'asm' statements.
5596+;; The default length is the longest possible single 6809 instruction,
5597+;; which is 5 bytes.  GCC will automatically multiply this by the
5598+;; number of real insns contained in an asm statement.
5599+;;
5600+(define_asm_attributes
5601+  [(set_attr "length" "5")
5602+   (set_attr "type" "unknown")])
5603+
5604+;;
5605+;; An attribute for the number of cycles that it takes an instruction
5606+;; to execute.
5607+;;
5608+(define_attr "cycles" "" (const_int DEFAULT_INSN_CYCLES))
5609+
5610+
5611+;;--------------------------------------------------------------------
5612+;;- Instruction patterns.  When multiple patterns apply,
5613+;;- the first one in the file is chosen.
5614+;;-
5615+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
5616+;;-
5617+;;- Note: NOTICE_UPDATE_CC in m6809.h handles condition code updates
5618+;;- for most instructions.
5619+;;--------------------------------------------------------------------
5620+
5621+;;--------------------------------------------------------------------
5622+;;-  Test
5623+;;--------------------------------------------------------------------
5624+
5625+;; cmpx is 3 bytes, not 4
5626+(define_insn "*tsthi_x"
5627+  [(set (cc0) (match_operand:HI 0 "register_operand_x" "v"))]
5628+  ""
5629+  "cmpx\t#0"
5630+  [(set_attr "length" "3")])
5631+
5632+;; subd #0 is 3 bytes, better than cmpd #0 which is 4 bytes
5633+(define_insn "*tsthi_d"
5634+  [(set (cc0) (match_operand:HI 0 "register_operand_d" "d"))]
5635+  ""
5636+  "subd\t#0"
5637+  [(set_attr "length" "3")])
5638+
5639+(define_insn "*tsthi"
5640+  [(set (cc0) (match_operand:HI 0 "register_operand" "a"))]
5641+  ""
5642+  "cmp%0\t#0"
5643+   [(set_attr "length" "4")])
5644+
5645+(define_insn "*bitqi3"
5646+  [(set (cc0)
5647+    (and:QI (match_operand:QI 0 "register_operand" "%q")
5648+      (match_operand:QI 1 "general_operand" "mi")))]
5649+  ""
5650+  "bit%0\t%1"
5651+  [(set_attr "length" "3")])
5652+
5653+
5654+(define_insn "tstqi"
5655+  [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "q,mt"))]
5656+  ""
5657+  "@
5658+   tst%0
5659+   tst\t%0"
5660+   [(set_attr "length" "1,3")])
5661+
5662+;;--------------------------------------------------------------------
5663+;;- Compare instructions
5664+;;--------------------------------------------------------------------
5665+
5666+;; - cmphi for register to memory or register compares
5667+(define_insn "cmphi"
5668+  [(set (cc0)
5669+    (compare
5670+      (match_operand:HI 0 "general_operand" "da, mi, ??Ud")
5671+      (match_operand:HI 1 "general_operand" "mi, da,  dU")))]
5672+  ""
5673+{
5674+  if ((REG_P (operands[0])) && (REG_P (operands[1]))) {
5675+    output_asm_insn ("pshs\t%1\t;cmphi: R:%1 with R:%0", operands);
5676+    return "cmp%0\t,s++\t;cmphi:";
5677+  }
5678+  if (GET_CODE (operands[0]) == REG)
5679+    return "cmp%0\t%1\t;cmphi:";
5680+  else {
5681+    cc_status.flags |= CC_REVERSED;
5682+    return "cmp%1\t%0\t;cmphi:(R)";
5683+  }
5684+}
5685+  [(set_attr "length" "5,5,7")])
5686+
5687+
5688+(define_insn "cmpqi"
5689+  [(set (cc0)
5690+    (compare (match_operand:QI 0 "whole_general_operand" "q,q, q,O,mt,K")
5691+    (match_operand:QI 1 "whole_general_operand"          "O,mt,K,q,q, q")))]
5692+  ""
5693+{
5694+    if (REG_P (operands[0]) && !M_REG_P (operands[0]))
5695+    {
5696+      if (operands[1] == const0_rtx)
5697+        return "tst%0\t;cmpqi:(ZERO)";
5698+      else
5699+        return "cmp%0\t%1\t;cmpqi:";
5700+    }
5701+    else
5702+    {
5703+      cc_status.flags |= CC_REVERSED;
5704+
5705+      if (operands[0] == const0_rtx)
5706+        return "tst%1\t;cmpqi:(RZERO)";
5707+      else
5708+        return "cmp%1\t%0\t;cmpqi:(R)";
5709+    }
5710+}
5711+   [(set_attr "length" "1,3,2,1,3,2")])
5712+
5713+
5714+;;--------------------------------------------------------------------
5715+;;- Compare/branch pattern
5716+;;--------------------------------------------------------------------
5717+
5718+(define_expand "cbranchhi4"
5719+  [(set (cc0)
5720+    (compare
5721+      (match_operand:HI 1 "general_operand" "da, mi, ??Ud")
5722+      (match_operand:HI 2 "general_operand" "mi, da,  dU")))
5723+   (set (pc)
5724+     (if_then_else
5725+        (match_operator 0 "ordered_comparison_operator" [(cc0) (const_int 0)])
5726+        (label_ref (match_operand 3 "" ""))
5727+        (pc)))]
5728+   ""
5729+   ""
5730+)
5731+
5732+(define_expand "cbranchqi4"
5733+  [(set (cc0)
5734+    (compare
5735+      (match_operand:QI 1 "whole_general_operand" "q,q, q,O,mt,K")
5736+      (match_operand:QI 2 "whole_general_operand" "O,mt,K,q,q, q")))
5737+   (set (pc)
5738+     (if_then_else
5739+        (match_operator 0 "ordered_comparison_operator" [(cc0) (const_int 0)])
5740+        (label_ref (match_operand 3 "" ""))
5741+        (pc)))]
5742+   ""
5743+   ""
5744+)
5745+
5746+;;--------------------------------------------------------------------
5747+;;-  Move
5748+;;--------------------------------------------------------------------
5749+
5750+; this looks good (obviously not finished) but I still see 'movsi'
5751+; places in udivsi3 where it's broken
5752+; (define_insn "pushsi1"
5753+;   [(set (mem:SI (pre_dec (reg:HI HARD_S_REGNUM)))
5754+;         (match_operand:SI 0 "general_operand" "o"))
5755+;    (set (reg:HI HARD_S_REGNUM)
5756+;         (plus:HI (reg:HI HARD_S_REGNUM) (const_int -4))) ]
5757+;   ""
5758+;   "; pushsi %0"
5759+;    [(set_attr "length" "12")])
5760+;
5761+; (define_insn "popsi1"
5762+;   [(set (match_operand:SI 0 "general_operand" "=o")
5763+;         (mem:SI (post_inc (reg:HI HARD_S_REGNUM))))
5764+;    (set (reg:HI HARD_S_REGNUM)
5765+;         (plus:HI (reg:HI HARD_S_REGNUM) (const_int 4))) ]
5766+;   ""
5767+;   "; popsi %0"
5768+;    [(set_attr "length" "12")])
5769+
5770+; (define_insn "movsi"
5771+;   [(set (match_operand:SI 0 "nonimmediate_operand" "=o")
5772+;         (match_operand:SI 1 "general_operand"      " oi"))]
5773+;   ""
5774+;   "; movsi %0 <- %1"
5775+;    [(set_attr "length" "1")])
5776+
5777+; this doesn't work
5778+; (define_expand "movsi"
5779+;   [(parallel [
5780+;      (set (match_operand:SI 0 "nonimmediate_operand" "")
5781+;           (match_operand:SI 1 "general_operand" ""))
5782+;      (clobber (match_scratch:HI 2 ""))])]
5783+;   ""
5784+; {
5785+;   rtx insn;
5786+;   if (STACK_PUSH_P (operands[0]) || STACK_POP_P (operands[1]))
5787+;   {
5788+;     REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
5789+;   }
5790+;   insn = emit_move_multi_word (SImode, operands[0], operands[1]);
5791+;   DONE;
5792+; })
5793+
5794+
5795+(define_expand "movhi"
5796+  [(set (match_operand:HI 0 "nonimmediate_operand" "")
5797+    (match_operand:HI 1 "general_operand" ""))]
5798+  ""
5799+{
5800+  /* One of the ops has to be in a register prior to reload */
5801+  if (!register_operand (operand0, HImode) &&
5802+      !register_operand (operand1, HImode))
5803+    operands[1] = copy_to_mode_reg (HImode, operand1);
5804+})
5805+
5806+;;; Try a splitter to handle failure cases where we try to move
5807+;;; an immediate constant (zero usually) directly to memory.
5808+;;; This absolutely requires an intermediate register.
5809+(define_split
5810+  [(set (match_operand:HI 0 "memory_operand" "")
5811+    (match_operand:HI 1 "immediate_operand"  ""))
5812+   (clobber (match_operand:HI 2 "register_operand" ""))]
5813+  ""
5814+  [(set (match_dup 2) (match_dup 1))
5815+   (set (match_dup 0) (match_dup 2))]
5816+  "")
5817+
5818+
5819+;;; This would be a nice method for loading from a word array,
5820+;;; but it is never generated because the combiner cannot merge
5821+;;; more than 3 instructions (there are four here).  This is
5822+;;; perhaps better done via a peephole.
5823+(define_insn "*movhi_array_load"
5824+  [(set (match_operand:HI 0 "nonimmediate_operand" "=da")
5825+    (mem:HI (plus:HI (ashift:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%B")) (const_int 1))
5826+                     (match_operand:HI 2 "immediate_operand" "i"))))
5827+   (clobber (match_scratch:HI 3 "=X"))]
5828+  ""
5829+  "ldx\t%2\;abx\;abx\;ld%0\t,x"
5830+   [(set_attr "length" "7")])
5831+
5832+
5833+;;; Optimize the move of a byte to the stack using the pshs instruction
5834+;;; instead of a store with pre-increment.
5835+(define_insn "movhi_push"
5836+  [(set (match_operand:HI 0 "push_operand" "=m")
5837+    (match_operand:HI 1 "register_operand" "U"))]
5838+  ""
5839+  "pshs\t%1"
5840+  [(set_attr "length" "2")])
5841+
5842+
5843+(define_insn "*movhi_pic_symbolref"
5844+  [(set (match_operand:HI 0 "register_operand" "=a")
5845+    (match_operand:HI 1 "symbolic_operand" ""))]
5846+  "flag_pic"
5847+  "lea%0\t%c1,pcr"
5848+   [(set_attr "length" "4")])
5849+
5850+
5851+(define_insn "*movhi_1"
5852+  [(set (match_operand:HI 0 "nonimmediate_operand" "=a,d,a,ad,mu")
5853+    (match_operand:HI 1 "general_operand"          " a,a,d,miu,ad"))]
5854+  ""
5855+  "@
5856+   lea%0\t,%1
5857+   tfr\t%1,%0
5858+   tfr\t%1,%0
5859+   ld%0\t%1
5860+   st%1\t%0"
5861+   [(set_attr "length" "2,2,2,*,*")])
5862+
5863+
5864+;;; Generated by the combiner to merge an address calculation with
5865+;;; a byte load.  We can use the 'abx' instruction here.
5866+(define_insn "*movqi_array_load"
5867+  [(set (match_operand:QI 0 "nonimmediate_operand" "=q")
5868+    (mem:QI (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%B"))
5869+                     (match_operand:HI 2 "immediate_operand" "i"))))
5870+   (clobber (match_scratch:HI 3 "=X"))]
5871+  ""
5872+  "ldx\t%2\;abx\;ld%0\t,x"
5873+   [(set_attr "length" "6")])
5874+
5875+
5876+;;; Optimize the move of a byte to the stack using the pshs instruction
5877+;;; instead of a store with pre-increment.
5878+(define_insn "movqi_push"
5879+  [(set (match_operand:QI 0 "push_operand" "=m")
5880+    (match_operand:QI 1 "register_operand" " q"))]
5881+  ""
5882+  "pshs\t%1"
5883+  [(set_attr "length" "2")])
5884+
5885+
5886+;;; Optimize the move of a byte from the stack using the puls instruction
5887+;;; instead of a store with post-decrement.
5888+(define_insn "movqi_pop"
5889+  [(set (match_operand:QI 0 "register_operand" "=q")
5890+    (match_operand:QI 1 "pop_operand" "m"))]
5891+  ""
5892+  "puls\t%0"
5893+  [(set_attr "length" "2")])
5894+
5895+
5896+;;- load low byte of 16-bit data into 8-bit register/memory
5897+(define_insn "*mov_lsb"
5898+  [(set (match_operand:QI 0 "nonimmediate_operand"    "=q,q,q,m,!q")
5899+      (subreg:QI (match_operand:HI 1 "general_operand" "d,m,a,d, U") 1))]
5900+  ""
5901+  "@
5902+   \t;movlsbqihi: D->B
5903+   ld%0\t%L1\t;movlsbqihi: msb:%1 -> R:%0
5904+   tfr\t%1,d\t;movlsbqihi: R:%1 -> R:%0
5905+   stb\t%0\t;movlsbqihi: R:%1 -> %0
5906+   pshs\t%1\t;movlsbqihi: R:%1 -> R:%0\;leas\t1,s\;puls\t%0"
5907+   [(set_attr "length" "0,*,2,*,6")])
5908+
5909+
5910+;;- load high byte of 16-bit data into 8-bit register/memory
5911+(define_insn "*mov_msb"
5912+  [(set (match_operand:QI 0 "nonimmediate_operand"    "=q,q,q,q,m,!q")
5913+      (subreg:QI (match_operand:HI 1 "general_operand" "d,O,a,m,d, U") 0))]
5914+  ""
5915+  "@
5916+   tfr\ta,b\t;movmsbqihi: D->B
5917+   clr%0\t\t;movmsbqihi: ZERO -> R:%0
5918+   tfr\t%1,d\t;movmsbqihi: R:%1 -> R:%0\;tfr\ta,b
5919+   ld%0\t%L1\t;movmsbqihi: lsb:%1 -> R:%0
5920+   sta\t%0\t;movmsbqihi: R:%1 -> %0
5921+   pshs\t%1\t;movmsbqihi: R:%1 -> R:%0\;puls\t%0\;leas\t1,s"
5922+  [(set_attr "length" "2,1,4,*,*,6")])
5923+
5924+
5925+(define_insn "*movqi_boolean"
5926+  [(set (reg:QI HARD_Z_REGNUM)
5927+    (match_operand:QI 0 "general_operand" "q,O,i,m"))]
5928+  ""
5929+  "@
5930+   tst%0
5931+   andcc\t#~4
5932+   orcc\t#4
5933+   tst\t%0")
5934+
5935+
5936+(define_insn "movqi"
5937+  [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q,m,q,m,q,z")
5938+    (match_operand:QI 1 "general_operand"          " q,O,O,mi,q,z,q"))]
5939+  ""
5940+  "@
5941+   tfr\t%1,%0
5942+   clr%0
5943+   clr\t%0
5944+   ld%0\t%1
5945+   st%1\t%0
5946+   tfr\tcc,%0\;and%0\t#4
5947+   tst%0"
5948+   [(set_attr "length" "2,1,3,*,*,4,1")])
5949+
5950+
5951+;;--------------------------------------------------------------------
5952+;;-  Swap registers
5953+;;--------------------------------------------------------------------
5954+
5955+; Note: 8-bit swap is never needed so it is not defined.
5956+
5957+(define_insn "swaphi"
5958+  [(set (match_operand:HI 0 "register_operand" "+r")
5959+    (match_operand:HI 1 "register_operand" "+r"))
5960+   (set (match_dup 1) (match_dup 0))]
5961+  ""
5962+  "exg\t%1,%0"
5963+  [(set_attr "length" "2")
5964+   (set (attr "cycles") (const_int EXG_CYCLES))])
5965+
5966+
5967+(define_insn "bswaphi2"
5968+  [(set (match_operand:HI 0 "register_operand" "=d")
5969+    (bswap:HI (match_operand:HI 1 "register_operand" "0")))]
5970+  ""
5971+  "exg\ta,b"
5972+  [(set_attr "length" "2")])
5973+
5974+
5975+;;--------------------------------------------------------------------
5976+;;-  Extension and truncation insns.
5977+;;--------------------------------------------------------------------
5978+
5979+(define_insn "extendqihi2"
5980+  [(set (match_operand:HI 0 "register_operand" "=d")
5981+        (sign_extend:HI (match_operand:QI 1 "general_operand" "B")))]
5982+  ""
5983+  "sex\t\t;extendqihi2: R:%1 -> R:%0"
5984+  [(set_attr "length" "1")])
5985+
5986+
5987+(define_insn "zero_extendqihi2"
5988+  [(set (match_operand:HI 0 "register_operand" "=d")
5989+        (zero_extend:HI (match_operand:QI 1 "general_operand" "B")))]
5990+  ""
5991+  "clra\t\t;zero_extendqihi: R:%1 -> R:%0"
5992+  [(set_attr "length" "1")])
5993+
5994+
5995+;;--------------------------------------------------------------------
5996+;;- All kinds of add instructions.
5997+;;--------------------------------------------------------------------
5998+
5999+
6000+;;
6001+;; gcc's automatic version of addsi3 doesn't know about adcb,adca
6002+;; so it is MUCH less efficient.  Define this one ourselves.
6003+;;
6004+;; TODO - can't always get 'd' for the clobber... allow other registers
6005+;; as well and use exg d,R ... exg R,d around the code sequence to
6006+;; use others, at a price.  Also consider libcall for this when
6007+;; optimizing for size.
6008+;;
6009+(define_insn "addsi3"
6010+  [(set (match_operand:SI 0 "nonimmediate_operand"  "=o")
6011+     (plus:SI (match_operand:SI 1 "general_operand" "%o")
6012+        (match_operand:SI 2 "general_operand"       " oi")))
6013+   (clobber (match_scratch:HI 3 "=d"))]
6014+  ""
6015+{
6016+  m6809_output_addsi3 (PLUS, operands);
6017+  return "";
6018+}
6019+  [(set_attr "length" "21")])
6020+
6021+
6022+; Increment of a 16-bit MEM by 1 can be done without a register.
6023+(define_insn "*addhi_mem_1"
6024+  [(set (match_operand:HI 0 "memory_operand" "=m")
6025+        (plus:HI (match_dup 0) (const_int 1)))]
6026+   "GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF"
6027+{
6028+  rtx xoperands[2];
6029+
6030+  xoperands[0] = operands[0];
6031+  xoperands[1] = adjust_address (operands[0], QImode, 1);
6032+
6033+  output_asm_insn ("inc\t%1", xoperands);
6034+  output_asm_insn ("bne\t__IL%=", xoperands);
6035+  output_asm_insn ("inc\t%0\;__IL%=:", xoperands);
6036+  return "";
6037+}
6038+  [(set_attr "length" "7")])
6039+
6040+
6041+; Decrement of a 16-bit MEM by 1 can be done without a register.
6042+(define_insn "*addhi_mem_minus1"
6043+  [(set (match_operand:HI 0 "memory_operand" "=m")
6044+        (plus:HI (match_dup 0) (const_int -1)))]
6045+   "GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF"
6046+{
6047+  rtx xoperands[2];
6048+
6049+  xoperands[0] = operands[0];
6050+  xoperands[1] = adjust_address (operands[0], QImode, 1);
6051+
6052+  output_asm_insn ("tst\t%1", xoperands);
6053+  output_asm_insn ("bne\t__IL%=", xoperands);
6054+  output_asm_insn ("dec\t%0", xoperands);
6055+  output_asm_insn ("__IL%=:", xoperands);
6056+  output_asm_insn ("dec\t%1", xoperands);
6057+  return "";
6058+}
6059+  [(set_attr "length" "7")])
6060+
6061+
6062+; Allow the addition of an 8-bit quantity to a 16-bit quantity
6063+; using the LEAX B,Y addressing mode, where X and Y are both
6064+; index registers.  This will only get generated via the peephole
6065+; which removes a sign extension.
6066+(define_insn "*addhi_b"
6067+  [(set (match_operand:HI 0 "index_register_operand"       "=a")
6068+    (plus:HI(match_operand:HI 1 "index_register_operand"   "%a")
6069+    (match_operand:QI 2 "register_operand"                  "q")
6070+  ))]
6071+  ""
6072+  "lea%0\t%2,%1\t;addhi_b: R:%0 = R:%2 + R:%1"
6073+  [(set_attr "length" "*")])
6074+
6075+
6076+; Splitter for addhi pattern #5 below
6077+(define_split
6078+  [(set (match_operand:HI 0 "index_register_operand" "")
6079+    (plus:HI (match_dup 0) (match_operand:HI 1 "memory_operand" "")))]
6080+  "reload_completed"
6081+  [
6082+   (parallel [(set (match_dup 0) (reg:HI HARD_D_REGNUM))
6083+              (set (reg:HI HARD_D_REGNUM) (match_dup 0))])
6084+   (set (reg:HI HARD_D_REGNUM)
6085+        (plus:HI (reg:HI HARD_D_REGNUM) (match_dup 1)))
6086+   (parallel [(set (match_dup 0) (reg:HI HARD_D_REGNUM))
6087+              (set (reg:HI HARD_D_REGNUM) (match_dup 0))])
6088+   ]
6089+{
6090+})
6091+
6092+
6093+; Splitter for addhi pattern #7 below
6094+(define_split
6095+  [(set (match_operand:HI 0 "index_register_operand" "")
6096+    (plus:HI (match_dup 0) (match_operand:HI 1 "index_register_operand" "")))]
6097+  "reload_completed"
6098+  [
6099+   (parallel [(set (match_dup 1) (reg:HI HARD_D_REGNUM))
6100+              (set (reg:HI HARD_D_REGNUM) (match_dup 1))])
6101+   (set (match_dup 0)
6102+        (plus:HI (reg:HI HARD_D_REGNUM) (match_dup 0)))
6103+   (parallel [(set (match_dup 1) (reg:HI HARD_D_REGNUM))
6104+              (set (reg:HI HARD_D_REGNUM) (match_dup 1))])
6105+   ]
6106+{
6107+})
6108+
6109+
6110+; TODO - this is ugly.  During RTL generation, we don't know what registers
6111+; are available, so the multiple-insn sequences can only be solved
6112+; via 'define_split's during matching.  See andhi3 for an example.
6113+; Keep the constraints with ? modifiers to help reload pick the right
6114+; registers.
6115+;
6116+; The forms are:
6117+; 1. D += D, expand this into a shift instead. (rtx costs should be corrected
6118+; to avoid this even happening...)
6119+; 2. D += U, require U to be pushed to memory.  (Lots of patterns do this
6120+; now, is this a better way?)
6121+; 3. Best choice: 'addd'
6122+; 4. Next best choice: 'lea'
6123+; 5. Hybrid of 3 and 4
6124+; 6. Same as 4, not bad
6125+; 7. BAD, no D register at all
6126+; 8. 'lea', as good as 4.
6127+(define_insn "addhi3"
6128+  [(set (match_operand:HI 0 "nonimmediate_operand"      "=d, d,  d,  a,?a, a,???T,a")
6129+    (plus:HI(match_operand:HI 1 "add_general_operand"   "%0, 0,  0,  d, 0, a, 0, a")
6130+    (match_operand:HI 2 "general_operand"               " 0, !U, mi, a, m, d, T, i")
6131+  ))]
6132+  ""
6133+  "@
6134+   lslb\t\t;addhi: R:%0 += R:%2\;rola\t\t;also R:%0 *= 2
6135+   pshs\t%2\t;addhi: R:%0 += R:%2\;add%0\t,s++
6136+   add%0\t%2
6137+   lea%0\t%1,%2
6138+   #
6139+   lea%0\t%2,%1
6140+   #
6141+   lea%0\t%a2,%1"
6142+   [(set_attr "length" "2,6,*,*,7,*,7,*")])
6143+
6144+
6145+(define_insn "addqi3_carry"
6146+  [(set (match_operand:QI 0 "nonimmediate_operand" "=q")
6147+    (unspec:QI [
6148+      (match_operand:QI 1 "whole_general_operand" "%0")
6149+      (match_operand:QI 2 "whole_general_operand" "tmi")] UNSPEC_ADD_CARRY))]
6150+  ""
6151+  "adc%0\t%2\t;addqi_carry: R:%0 += %2"
6152+  [(set_attr "length" "*")])
6153+
6154+
6155+; TODO: specifying 'A' for the first constraint, to force into the A register
6156+; is not working because of the way registers are currently set up.  This will
6157+; take some work to get right.  Thus the second alternative as a backup.
6158+(define_insn "addqi3_decimal"
6159+  [(set (match_operand:QI 0 "nonimmediate_operand" "=A,?q")
6160+    (unspec:QI [
6161+      (match_operand:QI 1 "general_operand"        "%0,0")
6162+      (match_operand:QI 2 "general_operand"        "mi,mi")] UNSPEC_ADD_DECIMAL))]
6163+  ""
6164+  "@
6165+   adda\t%2\;daa
6166+   tfr\t%0,a\;adda\t%2\;daa\;tfr\ta,%0"
6167+  [(set_attr "length" "5,9")])
6168+
6169+
6170+(define_insn "addqi3"
6171+  [(set (match_operand:QI 0 "nonimmediate_operand"       "=q,q,q,m,m,q")
6172+    (plus:QI (match_operand:QI 1 "whole_general_operand" "%0,0,0,0,0,0")
6173+    (match_operand:QI 2 "whole_general_operand"          " 0,I,N,I,N,mi")))]
6174+  ""
6175+  "@
6176+   asl%0\t\t;addqi: R:%0 = R:%0 + R:%0
6177+   inc%0
6178+   dec%0
6179+   inc\t%0
6180+   dec\t%0
6181+   add%0\t%2"
6182+  [(set_attr "length" "1,1,1,3,3,*")])
6183+
6184+
6185+;;--------------------------------------------------------------------
6186+;;- Subtract instructions.
6187+;;--------------------------------------------------------------------
6188+
6189+(define_insn "subsi3"
6190+  [(set (match_operand:SI 0 "nonimmediate_operand"  "=o")
6191+     (minus:SI (match_operand:SI 1 "general_operand" " o")
6192+        (match_operand:SI 2 "general_operand"       " oi")))
6193+   (clobber (match_scratch:HI 3 "=d"))]
6194+  ""
6195+{
6196+  m6809_output_addsi3 (MINUS, operands);
6197+  return "";
6198+}
6199+  [(set_attr "length" "21")])
6200+
6201+
6202+(define_insn "subhi3"
6203+  [(set (match_operand:HI 0 "register_operand"      "=d,  d, a")
6204+    (minus:HI (match_operand:HI 1 "register_operand" "0,  0, 0")
6205+    (match_operand:HI 2 "general_operand"            "mi, ?U,n")))]
6206+  ""
6207+  "@
6208+   sub%0\t%2\t;subhi: R:%0 -= %2
6209+   pshs\t%2\t;subhi: R:%0 -= R:%2\;sub%0\t,s++
6210+   lea%0\t%n2,%1\t;subhi: R:%0 = R:%1 + %n2"
6211+   [(set_attr "length" "*,5,3")])
6212+
6213+
6214+(define_insn "subqi3_carry"
6215+  [(set (match_operand:QI 0 "register_operand" "=q")
6216+    (unspec:QI [
6217+      (match_operand:QI 1 "whole_general_operand" "%0")
6218+      (match_operand:QI 2 "whole_general_operand" "tmi")] UNSPEC_SUB_CARRY))]
6219+  ""
6220+  "sbc%0\t%2\t;subqi_carry: R:%0 += %2"
6221+  [(set_attr "length" "*")])
6222+
6223+
6224+(define_insn "subqi3"
6225+  [(set (match_operand:QI 0 "register_operand"            "=q, q, !q, q")
6226+    (minus:QI (match_operand:QI 1 "whole_register_operand" "0, 0,  I, 0")
6227+    (match_operand:QI 2 "whole_general_operand"            "I, mi, 0, t")))]
6228+  ""
6229+  "@
6230+   dec%0
6231+   sub%0\t%2
6232+   dec%0\;neg%0
6233+   sub%0\t%2"
6234+   [(set_attr "length" "1,3,2,3")])
6235+
6236+
6237+;;--------------------------------------------------------------------
6238+;;- Multiply instructions.
6239+;;--------------------------------------------------------------------
6240+
6241+; TODO - merge these two instructions, using 'extend_operator' to match
6242+; either signed or zero extension.  Everything else is the same.
6243+(define_insn "mulqihi3"
6244+   [(set (match_operand:HI 0 "register_operand" "=d")
6245+      (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%q"))
6246+      (match_operand:QI 2 "general_operand" "tmK")))]
6247+  ""
6248+  "lda\t%2\t;mulqihi3\;mul"
6249+  [(set_attr "length" "3")])
6250+
6251+
6252+(define_insn "umulqihi3"
6253+   [(set (match_operand:HI 0 "register_operand" "=d")
6254+    (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%q"))
6255+    (match_operand:QI 2 "general_operand" "tmK")))]
6256+  ""
6257+  "lda\t%2\t;umulqihi3\;mul"
6258+  [(set_attr "length" "3")])
6259+
6260+
6261+; Expand a 16x16 multiplication into either a libcall or a shift.
6262+; If the second operand is a small constant, use the above form.
6263+; Otherwise, do a libcall.
6264+(define_expand "mulhi3"
6265+  [(set (match_operand:HI 0 "nonimmediate_operand" "")
6266+    (mult:HI (match_operand:HI 1 "general_operand" "")
6267+    (match_operand:HI 2 "nonmemory_operand" "")))]
6268+  ""
6269+{
6270+  emit_libcall_insns (HImode, "mulhi3", operands, 2);
6271+  DONE;
6272+})
6273+
6274+
6275+;;--------------------------------------------------------------------
6276+;;- Divide instructions.
6277+;;--------------------------------------------------------------------
6278+
6279+(define_expand "divhi3"
6280+  [(set (match_operand:HI 0 "register_operand" "")
6281+    (div:HI (match_operand:HI 1 "register_operand" "")
6282+    (match_operand:HI 2 "register_operand" "")))]
6283+  ""
6284+{
6285+  emit_libcall_insns (HImode, "divhi3", operands, 2);
6286+  DONE;
6287+})
6288+
6289+
6290+(define_expand "divqi3"
6291+  [(set (match_operand:QI 0 "register_operand" "")
6292+    (div:QI (match_operand:QI 1 "register_operand" "")
6293+    (match_operand:QI 2 "register_operand" "")))]
6294+  ""
6295+{
6296+  emit_libcall_insns (QImode, "divqi3", operands, 2);
6297+  DONE;
6298+})
6299+
6300+
6301+(define_expand "udivhi3"
6302+  [(set (match_operand:HI 0 "register_operand" "")
6303+     (udiv:HI (match_operand:HI 1 "register_operand" "")
6304+              (match_operand:HI 2 "register_operand" "")))]
6305+  ""
6306+{
6307+  emit_libcall_insns (HImode, "udivhi3", operands, 2);
6308+  DONE;
6309+})
6310+
6311+
6312+;;--------------------------------------------------------------------
6313+;;- mod
6314+;;--------------------------------------------------------------------
6315+
6316+(define_expand "modhi3"
6317+  [(set (match_operand:HI 0 "register_operand" "")
6318+    (mod:HI (match_operand:HI 1 "register_operand" "")
6319+    (match_operand:HI 2 "register_operand" "")))]
6320+  ""
6321+{
6322+  emit_libcall_insns (HImode, "modhi3", operands, 2);
6323+  DONE;
6324+})
6325+
6326+
6327+(define_expand "modqi3"
6328+  [(set (match_operand:QI 0 "register_operand" "")
6329+    (mod:QI (match_operand:QI 1 "register_operand" "")
6330+    (match_operand:QI 2 "register_operand" "")))]
6331+  ""
6332+{
6333+  emit_libcall_insns (QImode, "modqi3", operands, 2);
6334+  DONE;
6335+})
6336+
6337+
6338+(define_expand "umodhi3"
6339+  [(set (match_operand:HI 0 "register_operand" "")
6340+    (umod:HI (match_operand:HI 1 "register_operand" "")
6341+    (match_operand:HI 2 "register_operand" "")))]
6342+  ""
6343+{
6344+  emit_libcall_insns (HImode, "umodhi3", operands, 2);
6345+  DONE;
6346+})
6347+
6348+
6349+
6350+;;--------------------------------------------------------------------
6351+;;- and, or, xor common patterns
6352+;;--------------------------------------------------------------------
6353+
6354+; Split a bitwise HImode into two QImode instructions, with one of
6355+; the sources in a pushable register.  The register is pushed onto
6356+; the stack and memory pop operands (,s+) are used in the QI forms.
6357+(define_split
6358+  [(set (match_operand:HI 0 "register_operand" "")
6359+    (match_operator:HI 3 "logical_bit_operator"
6360+      [(match_operand:HI 1 "register_operand" "")
6361+       (match_operand:HI 2 "register_operand" "")]))]
6362+  "reload_completed"
6363+  [(set (mem:HI (pre_dec:HI (reg:HI HARD_S_REGNUM))) (match_dup 2))
6364+   (set (reg:QI HARD_A_REGNUM) (match_op_dup:QI 3
6365+         [(reg:QI HARD_A_REGNUM)
6366+          (mem:QI (post_inc:QI (reg:HI HARD_S_REGNUM)))]))
6367+   (set (reg:QI HARD_D_REGNUM) (match_op_dup:QI 3
6368+         [(reg:QI HARD_D_REGNUM)
6369+          (mem:QI (post_inc:QI (reg:HI HARD_S_REGNUM)))]))
6370+   (use (reg:QI HARD_A_REGNUM))]
6371+{
6372+})
6373+
6374+; Split a bitwise HImode into two QImode instructions, with one
6375+; of the sources being a (MEM (MEM (...)); i.e. an indirect memory
6376+; reference.  This requires dereferencing the pointer into a
6377+; temporary register (X), which must be saved/restored around the
6378+; compute instructions.
6379+(define_split 
6380+  [(set (match_operand:HI 0 "register_operand" "")
6381+    (match_operator:HI 3 "logical_bit_operator"
6382+      [(match_operand:HI 1 "register_operand" "")
6383+       (mem:HI (match_operand:HI 2 "memory_operand" ""))]))]
6384+  "reload_completed"
6385+  [
6386+   (set (mem:HI (pre_dec:HI (reg:HI HARD_S_REGNUM))) (match_dup 4))
6387+   (set (match_dup 4) (match_dup 2))
6388+   (set (match_dup 4) (mem:HI (match_dup 4)))
6389+   (set (reg:QI HARD_A_REGNUM) (match_op_dup:QI 3
6390+         [(reg:QI HARD_A_REGNUM)
6391+          (mem:QI (post_inc:QI (match_dup 4)))]))
6392+   (set (reg:QI HARD_D_REGNUM) (match_op_dup:QI 3
6393+         [(reg:QI HARD_D_REGNUM)
6394+          (mem:QI (post_inc:QI (match_dup 4)))]))
6395+   (use (reg:QI HARD_A_REGNUM))
6396+   (set (match_dup 4) (mem:HI (post_inc:HI (reg:HI HARD_S_REGNUM))))
6397+   ]
6398+{
6399+  /* Use X for a temporary index register */
6400+  operands[4] = gen_rtx_REG (HImode, HARD_X_REGNUM);
6401+})
6402+
6403+
6404+; Split a bitwise HImode into two QImode instructions.  This is
6405+; the common case.  This handles splitting when neither of the
6406+; above two cases applies.
6407+(define_split 
6408+  [(set (match_operand:HI 0 "register_operand" "")
6409+    (match_operator:HI 3 "logical_bit_operator"
6410+      [(match_operand:HI 1 "register_operand" "")
6411+       (match_operand:HI 2 "general_operand" "")]))]
6412+  "reload_completed"
6413+  [(set (reg:QI HARD_A_REGNUM) (match_op_dup:QI 3
6414+      [(reg:QI HARD_A_REGNUM) (match_dup 4)]))
6415+   (set (reg:QI HARD_D_REGNUM) (match_op_dup:QI 3
6416+      [(reg:QI HARD_D_REGNUM) (match_dup 5)]))
6417+   (use (reg:QI HARD_A_REGNUM))]
6418+{
6419+  if (GET_CODE (operands[2]) == CONST_INT)
6420+  {
6421+    operands[4] = gen_rtx_const_high (operands[2]);
6422+    operands[5] = gen_rtx_const_low (operands[2]);
6423+  }
6424+  else if ((GET_CODE (operands[2]) == MEM)
6425+    && (GET_CODE (XEXP (operands[2], 0)) == MEM))
6426+  {
6427+    FAIL;
6428+  }
6429+  else
6430+  {
6431+    operands[4] = gen_highpart (QImode, operands[2]);
6432+    operands[5] = gen_lowpart (QImode, operands[2]);
6433+  }
6434+})
6435+
6436+; Below are the specific cases for each of the operators.
6437+; The QImode versions are the simplest and can be implemented
6438+; directly on the hardware.  The HImode cases are all output
6439+; using one of the above splitting techniques.
6440+
6441+;;--------------------------------------------------------------------
6442+;;- and
6443+;;--------------------------------------------------------------------
6444+
6445+(define_insn "andhi3"
6446+  [(set (match_operand:HI 0 "register_operand" "=d")
6447+    (and:HI (match_operand:HI 1 "register_operand" "%0")
6448+    (match_operand:HI 2 "general_operand" "mnU")))]
6449+  ""
6450+  "#")
6451+
6452+;; it is not clear that this is correct
6453+(define_insn "*andqi_2"
6454+  [(set
6455+   (match_operand:QI 0 "register_operand" "=q")
6456+   (and:QI (match_operand:QI 1 "register_operand" "q")
6457+     (match_operand 2 "const_int_operand" "i")))]
6458+  ""
6459+{
6460+  if (GET_CODE (operands[2]) == CONST_INT)
6461+  {
6462+    operands[3] = GEN_INT(INTVAL(operands[2]) & 0xff);
6463+    return "and%0 %3";
6464+  }
6465+
6466+  return "and%0 %2";
6467+}
6468+  [(set_attr "length" "2")])
6469+
6470+(define_insn "andqi3"
6471+  [(set (match_operand:QI 0 "register_operand"           "=q,q,q,qc")
6472+    (and:QI (match_operand:QI 1 "whole_register_operand" "%0,0,0,0")
6473+    (match_operand:QI 2 "whole_general_operand"          " O,N,m,i")))]
6474+  ""
6475+  "@
6476+   clr%0\t;andqi(ZERO)
6477+   \t;andqi(-1)
6478+   and%0\t%2
6479+   and%0\t%2"
6480+   [(set_attr "length" "1,0,3,2")])
6481+
6482+
6483+;;--------------------------------------------------------------------
6484+;;- or
6485+;;--------------------------------------------------------------------
6486+
6487+(define_insn "iorhi3"
6488+  [(set (match_operand:HI 0 "register_operand" "=d")
6489+    (ior:HI (match_operand:HI 1 "register_operand" "%0")
6490+    (match_operand:HI 2 "general_operand" "mnU")))]
6491+  ""
6492+  "#")
6493+
6494+
6495+(define_insn "iorqi3"
6496+  [(set (match_operand:QI 0 "register_operand"           "=q,q, qc")
6497+    (ior:QI (match_operand:QI 1 "whole_register_operand" "%0,0, 0")
6498+    (match_operand:QI 2 "whole_general_operand"          " O,m,i")))]
6499+  ""
6500+  "@
6501+   \t;iorqi(ZERO)
6502+   or%0\t%2
6503+   or%0\t%2"
6504+   [(set_attr "length" "0,3,2")])
6505+
6506+;;--------------------------------------------------------------------
6507+;;- xor
6508+;;--------------------------------------------------------------------
6509+
6510+(define_insn "xorhi3"
6511+  [(set (match_operand:HI 0 "register_operand" "=d")
6512+    (xor:HI (match_operand:HI 1 "register_operand" "%0")
6513+    (match_operand:HI 2 "general_operand" "mnU")))]
6514+  ""
6515+  "#")
6516+
6517+
6518+(define_insn "xorqi3"
6519+  [(set (match_operand:QI 0 "register_operand"           "=q,q,q,q")
6520+    (xor:QI (match_operand:QI 1 "whole_register_operand" "%0,0,0,0")
6521+    (match_operand:QI 2 "whole_general_operand"          " O,N,m,i")))]
6522+  ""
6523+  "@
6524+   \t;xorqi(ZERO)
6525+   com%0\t;xorqi(-1)
6526+   eor%0\t%2
6527+   eor%0\t%2"
6528+   [(set_attr "length" "0,1,3,2")])
6529+
6530+;;--------------------------------------------------------------------
6531+;;-  Two's Complements
6532+;;--------------------------------------------------------------------
6533+
6534+(define_insn "neghi2"
6535+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,!a")
6536+    (neg:HI (match_operand:HI 1 "general_operand"   "0, 0")))]
6537+  ""
6538+  "@
6539+   nega\;negb\;sbca\t#0
6540+   exg\td,%0\;nega\;negb\;sbca\t#0\;exg\td,%0"
6541+  [(set_attr "length" "5,9")])
6542+
6543+
6544+(define_insn "negqi2"
6545+  [(set (match_operand:QI 0 "nonimmediate_operand"    "=q,m")
6546+    (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
6547+  ""
6548+  "@
6549+   neg%0
6550+   neg\t%0"
6551+  [(set_attr "length" "1,3")])
6552+
6553+
6554+;;--------------------------------------------------------------------
6555+;;-  One's Complements
6556+;;--------------------------------------------------------------------
6557+
6558+(define_insn "one_cmplhi2"
6559+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,?tm,???a")
6560+    (not:HI (match_operand:HI 1 "general_operand"   "0,  0,   0")))]
6561+  ""
6562+  "@
6563+   coma\;comb
6564+   com\t%0\;com\t%L0
6565+   exg\td,%0\;coma\;comb\;exg\td,%0"
6566+  [(set_attr "length" "2,6,6")])
6567+
6568+
6569+(define_insn "one_cmplqi2"
6570+  [(set (match_operand:QI 0 "nonimmediate_operand"    "=q,m")
6571+    (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
6572+  ""
6573+  "@
6574+   com%0
6575+   com\t%0"
6576+  [(set_attr "length" "1,3")])
6577+
6578+;;--------------------------------------------------------------------
6579+;;- Shifts/rotates
6580+;;--------------------------------------------------------------------
6581+
6582+(define_code_iterator bit_code [ashift ashiftrt lshiftrt])
6583+(define_code_attr bit_code_name [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr")])
6584+
6585+(define_mode_iterator bit_mode [QI HI])
6586+(define_mode_attr bit_mode_name [(QI "qi3") (HI "hi3")])
6587+
6588+;; Emit RTL for any shift (handles all 3 opcodes and 2 mode sizes)
6589+
6590+(define_expand "<bit_code:bit_code_name><bit_mode:bit_mode_name>"
6591+  [(set (match_operand:bit_mode 0 "nonimmediate_operand" "")
6592+    (bit_code:bit_mode (match_operand:bit_mode 1 "general_operand" "")
6593+    (match_operand:bit_mode 2 "nonmemory_operand" "")))]
6594+  ""
6595+{
6596+})
6597+
6598+; Individual instructions implemented in the CPU.
6599+
6600+
6601+(define_insn "*ashift1"
6602+  [(set (match_operand:QI 0 "nonimmediate_operand" "=m,q")
6603+    (ashift:QI (match_operand:QI 1 "general_operand" "0,0") (const_int 1)))]
6604+  ""
6605+  "@
6606+   asl\t%0
6607+   asl%0"
6608+  [(set_attr "length" "3,1")])
6609+
6610+(define_insn "*lshiftrt1"
6611+  [(set (match_operand:QI 0 "nonimmediate_operand" "=m,q")
6612+    (lshiftrt:QI (match_operand:QI 1 "general_operand" "0,0") (const_int 1)))]
6613+  ""
6614+  "@
6615+   lsr\t%0
6616+   lsr%0"
6617+  [(set_attr "length" "3,1")])
6618+
6619+(define_insn "*ashiftrt1"
6620+  [(set (match_operand:QI 0 "nonimmediate_operand" "=m,q")
6621+    (ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0") (const_int 1)))]
6622+  ""
6623+  "@
6624+   asr\t%0
6625+   asr%0"
6626+  [(set_attr "length" "3,1")])
6627+
6628+(define_insn "*rotate1"
6629+  [(set (match_operand:QI 0 "nonimmediate_operand" "=m,q")
6630+    (rotate:QI (match_operand:QI 1 "general_operand" "0,0") (const_int 1)))]
6631+  ""
6632+  "@
6633+   rol\t%0
6634+   rol%0"
6635+  [(set_attr "length" "3,1")])
6636+
6637+
6638+(define_insn "*rotatert1"
6639+  [(set (match_operand:QI 0 "nonimmediate_operand" "=m,q")
6640+    (rotatert:QI (match_operand:QI 1 "general_operand" "0,0") (const_int 1)))]
6641+  ""
6642+  "@
6643+   ror\t%0
6644+   ror%0"
6645+  [(set_attr "length" "3,1")])
6646+
6647+
6648+; A shift by 8 for D reg can be optimized by just moving
6649+; between the A/B halves, and then zero/sign extending or
6650+; filling in zeroes.
6651+; Because GCC does not understand that 'A' and 'D' refer to
6652+; the same storage location, we must use 'USE' throughout
6653+; to prevent deletion of 'unnecessary' instructions.
6654+; Similar optimization for MEM would require a scratch register
6655+; so is not done here.
6656+
6657+(define_split
6658+  [(set (reg:HI HARD_D_REGNUM) (ashift:HI (reg:HI HARD_D_REGNUM) (const_int 8)))]
6659+  "reload_completed"
6660+  [
6661+   (use (reg:HI HARD_D_REGNUM))
6662+   (set (reg:QI HARD_A_REGNUM) (reg:QI HARD_D_REGNUM))
6663+   (use (reg:QI HARD_A_REGNUM))
6664+   (set (reg:QI HARD_D_REGNUM) (const_int 0))
6665+   ]
6666+  "")
6667+
6668+(define_split
6669+  [(set (reg:HI HARD_D_REGNUM) (lshiftrt:HI (reg:HI HARD_D_REGNUM) (const_int 8)))]
6670+  "reload_completed"
6671+  [
6672+   (use (reg:HI HARD_D_REGNUM))
6673+   (set (reg:QI HARD_D_REGNUM) (reg:QI HARD_A_REGNUM))
6674+   (use (reg:QI HARD_D_REGNUM))
6675+   (set (reg:HI HARD_D_REGNUM) (zero_extend:HI (reg:QI HARD_D_REGNUM)))
6676+   ]
6677+  "")
6678+
6679+(define_split
6680+  [(set (reg:HI HARD_D_REGNUM) (ashiftrt:HI (reg:HI HARD_D_REGNUM) (const_int 8)))]
6681+  "reload_completed"
6682+  [
6683+   (use (reg:HI HARD_D_REGNUM))
6684+   (set (reg:QI HARD_D_REGNUM) (reg:QI HARD_A_REGNUM))
6685+   (use (reg:QI HARD_D_REGNUM))
6686+   (set (reg:HI HARD_D_REGNUM) (sign_extend:HI (reg:QI HARD_D_REGNUM)))
6687+   ]
6688+  "")
6689+
6690+
6691+; On the WPC hardware, there is a shift register that can be used
6692+; to compute (1<<n) efficiently in two instructions.  Note that this
6693+; form only works when using -mint8 though, because C will promote
6694+; to 'int' when doing this operation.  TODO : we need a 16-bit form too.
6695+(define_insn "ashlqi3_wpc"
6696+  [(set (match_operand:QI 0 "nonimmediate_operand" "=q")
6697+    (ashift:QI (match_operand:QI 1 "immediate_operand" "I")
6698+    (match_operand:QI 2 "general_operand" "q")))]
6699+  "TARGET_WPC"
6700+  "st%2\t0x3FF7\;ld%0\t0x3FF7"
6701+  [(set_attr "length" "6")])
6702+
6703+
6704+; Internal instructions for shifting by a constant.
6705+; Two forms are provided, one for QImode, one for HImode.
6706+; These are always split into the above instructions
6707+; (except for QImode forms that directly match one of the
6708+; above instructions, in which the condition will not
6709+; allow the splitter to match).
6710+
6711+(define_insn_and_split "<bit_code:bit_code_name>hi3_const"
6712+  [(set (match_operand:HI 0 "nonimmediate_operand"     "=dm")
6713+    (bit_code:HI (match_operand:HI 1 "general_operand" "0")
6714+    (match_operand:HI 2 "immediate_operand"            "n")))]
6715+  ""
6716+  "#"
6717+  "reload_completed"
6718+  [(const_int 0)]
6719+{
6720+  m6809_split_shift (<bit_code:CODE>, operands);
6721+  DONE;
6722+})
6723+
6724+
6725+(define_insn_and_split "<bit_code:bit_code_name>qi3_const"
6726+  [(set (match_operand:QI 0 "nonimmediate_operand"     "=qm")
6727+    (bit_code:QI (match_operand:QI 1 "general_operand" "0")
6728+    (match_operand:QI 2 "immediate_operand"            "n")))]
6729+  "INTVAL (operands[2]) > 1"
6730+  "#"
6731+  "&& reload_completed"
6732+  [(const_int 0)]
6733+{
6734+  m6809_split_shift (<bit_code:CODE>, operands);
6735+  DONE;
6736+})
6737+
6738+; Internal instructions for shifting by a nonconstant.
6739+; These expand into complex assembly.
6740+
6741+(define_insn "<bit_code:bit_code_name>hi3_reg"
6742+  [(set (match_operand:HI 0 "nonimmediate_operand"     "=d")
6743+    (bit_code:HI (match_operand:HI 1 "general_operand" "0")
6744+    (match_operand:HI 2 "nonimmediate_operand"         "v")))]
6745+  ""
6746+{
6747+  m6809_output_shift_insn (<bit_code:CODE>, operands);
6748+  return "";
6749+}
6750+  [(set_attr "length" "20")])
6751+
6752+
6753+(define_insn "<bit_code:bit_code_name>qi3_reg"
6754+  [(set (match_operand:QI 0 "nonimmediate_operand"    "=q")
6755+    (bit_code:QI (match_operand:QI 1 "general_operand" "0")
6756+    (match_operand:QI 2 "nonimmediate_operand"         "v")))]
6757+  ""
6758+{
6759+  m6809_output_shift_insn (<bit_code:CODE>, operands);
6760+  return "";
6761+}
6762+  [(set_attr "length" "16")])
6763+
6764+
6765+
6766+;;--------------------------------------------------------------------
6767+;;-  Jumps and transfers
6768+;;--------------------------------------------------------------------
6769+
6770+;;; The casesi pattern is normally *not* defined; see 'tablejump' instead.
6771+(define_expand "casesi"
6772+  [(match_operand:HI 0 "register_operand" "")   ; index to jump on
6773+   (match_operand:HI 1 "immediate_operand" "")   ; lower bound
6774+   (match_operand:HI 2 "immediate_operand" "")   ; total range
6775+   (match_operand 3 "" "")   ; table label
6776+   (match_operand 4 "" "")]  ; out of range label
6777+  "TARGET_BYTE_INT && TARGET_CASESI"
6778+{
6779+  m6809_do_casesi (operands[0], operands[1], operands[2],
6780+                   operands[3], operands[4]);
6781+  DONE;
6782+})
6783+
6784+(define_insn "tablejump_short_offset"
6785+  [(set (pc)
6786+       (mem:HI (plus:HI (match_operand:HI 1 "register_operand" "U")
6787+                (zero_extend:HI (match_operand:QI 0 "register_operand" "q")))))]
6788+  ""
6789+  "jmp\t[b,x]\t;tablejump_short_offset"
6790+  [(set_attr "length" "3")])
6791+
6792+(define_insn "tablejump_long_offset"
6793+  [(set (pc)
6794+       (mem:HI (plus:HI (match_operand:HI 1 "register_operand" "U")
6795+                (match_operand:HI 0 "register_operand" "d"))))]
6796+  ""
6797+  "jmp\t[d,x]\t;tablejump_long_offset"
6798+  [(set_attr "length" "3")])
6799+
6800+
6801+ ;; A tablejump operation gives the address in operand 0, with the
6802+ ;; CODE_LABEL for the table in operand 1.  The 'define_expand'
6803+ ;; shows the arguments as GCC presents them.  For a register
6804+ ;; operand, the assembly code is straightforward.  For a MEM,
6805+ ;; assumed to be a SYMBOL_REF, two forms are given, one normal
6806+ ;; and one for PIC mode.
6807+ (define_expand "tablejump"
6808+    [(parallel [
6809+     (set (pc) (match_operand:HI 0 "" ""))
6810+     (use (label_ref (match_operand 1 "" "")))
6811+     (clobber (match_scratch:HI 2 ""))
6812+     ])]
6813+    ""
6814+ {
6815+ })
6816+
6817+
6818+(define_insn "*tablejump_reg"
6819+   [(parallel [
6820+      (set (pc)
6821+         (match_operand:HI 0 "register_operand" "a"))
6822+      (use (label_ref (match_operand 1 "" "")))
6823+      (clobber (match_scratch:HI 2 ""))
6824+      ])]
6825+   ""
6826+   "jmp\t,%0"
6827+   [(set_attr "length" "3")])
6828+
6829+
6830+(define_insn "*tablejump_symbol"
6831+  [(parallel [
6832+     (set (pc)
6833+        (mem:HI
6834+           (plus:HI (match_operand:HI 0 "register_operand" "a")
6835+                    (label_ref (match_operand 1 "" "")))))
6836+     (use (label_ref (match_dup 1)))
6837+     (clobber (match_scratch:HI 2 ""))
6838+     ])]
6839+  "!flag_pic"
6840+{
6841+  output_asm_insn ("jmp\t[%a1,%0]", operands);
6842+  return "";
6843+}
6844+  [(set_attr "length" "4")])
6845+
6846+
6847+(define_insn "*tablejump_symbol_pic"
6848+  [(parallel [
6849+     (set (pc)
6850+        (mem:HI
6851+           (plus:HI (match_operand:HI 0 "register_operand" "d")
6852+                    (label_ref (match_operand 1 "" "")))))
6853+     (use (label_ref (match_dup 1)))
6854+     (clobber (match_scratch:HI 2 "=&a"))
6855+     ])]
6856+  "flag_pic"
6857+{
6858+  output_asm_insn ("lea%2\t%a1,pcr", operands);
6859+  output_asm_insn ("ld%0\t%0,%2", operands);
6860+  output_asm_insn ("jmp\t%0,%2", operands);
6861+  return "";
6862+}
6863+  [(set_attr "length" "8")])
6864+
6865+
6866+(define_insn "indirect_jump"
6867+  [(set (pc)
6868+    (match_operand:HI 0 "register_operand" "a"))]
6869+  ""
6870+  "jmp\t,%0"
6871+  [(set_attr "length" "3")])
6872+
6873+
6874+(define_insn "jump"
6875+  [(set (pc) (label_ref (match_operand 0 "" "")))]
6876+  ""
6877+{
6878+  return output_branch_insn ( LABEL_REF, operands, get_attr_length (insn));
6879+}
6880+  [(set (attr "type") (const_string "branch"))])
6881+
6882+; Output assembly for a condition branch instruction.
6883+(define_insn "*cond_branch"
6884+  [(set (pc)
6885+    (if_then_else
6886+      (match_operator 1 "comparison_operator" [(cc0) (const_int 0)])
6887+        (label_ref (match_operand 0 "" "")) (pc)))]
6888+  ""
6889+{
6890+  return output_branch_insn ( GET_CODE(operands[1]),
6891+    operands, get_attr_length (insn));
6892+}
6893+  [(set (attr "type") (const_string "cbranch"))])
6894+
6895+
6896+; Similar to above, but for a condition branch instruction that
6897+; had its operands reversed at some point.
6898+(define_insn "*cond_branch_reverse"
6899+  [(set (pc)
6900+    (if_then_else
6901+      (match_operator 1 "comparison_operator" [(cc0) (const_int 0)])
6902+      (pc) (label_ref (match_operand 0 "" ""))))]
6903+  ""
6904+{
6905+  return output_branch_insn ( reverse_condition (GET_CODE(operands[1])),
6906+    operands, get_attr_length (insn));
6907+}
6908+  [(set (attr "type") (const_string "cbranch"))])
6909+
6910+
6911+
6912+;;--------------------------------------------------------------------
6913+;;-  Calls
6914+;;--------------------------------------------------------------------
6915+
6916+;; Generate a call instruction for a function that does not
6917+;; return a value.  The expander is used during RTL generation.
6918+;; The instructions below are used during matching; only one
6919+;; of them will be used, depending on the type of function
6920+;; being called.  The different conditions are:
6921+;;
6922+;;    1) far_functionp - is this a far function?  Those need
6923+;;    to be output as indirect calls through a far-function
6924+;;    handler.
6925+;;
6926+;;    2) noreturn_functionp - if the function does not return,
6927+;;    we can use a 'jmp' instead of a 'jsr' to call it.
6928+;;
6929+;;    3) is PIC mode enabled?  If so, we'll always use
6930+;;    relative calls (lbsr or lbra).
6931+;;
6932+;; Note: not all combinations are fully supported, especially
6933+;; relating to PIC.
6934+;;
6935+;; The 'bsr' instruction is never generated.
6936+
6937+(define_expand "call"
6938+  [(call (match_operand:HI 0 "memory_operand" "")
6939+    (match_operand:HI 1 "general_operand" ""))]
6940+  ""
6941+  "")
6942+
6943+(define_insn "*call_nopic_far"
6944+  [(call (match_operand:HI 0 "memory_operand" "m")
6945+    (match_operand:HI 1 "general_operand" "g"))]
6946+  "far_functionp (operands[0])"
6947+{
6948+  output_far_call_insn (operands, 0);
6949+  return "";
6950+}
6951+  [(set_attr "length" "6")])
6952+
6953+
6954+; PIC forms come first, and should only match
6955+; (MEM (SYMBOL_REF)).  Other MEM forms are treated as usual.
6956+(define_insn "*call_pic"
6957+  [(call (mem:HI (match_operand:HI 0 "symbolic_operand" ""))
6958+    (match_operand:HI 1 "general_operand" "g"))]
6959+  "flag_pic && !noreturn_functionp (operands[0])"
6960+  "lbsr\t%C0"
6961+  [(set_attr "length" "4")])
6962+
6963+
6964+(define_insn "*call_nopic"
6965+  [(call (match_operand:HI 0 "memory_operand" "m")
6966+    (match_operand:HI 1 "general_operand" "g"))]
6967+  "!noreturn_functionp (operands[0])"
6968+  "jsr\t%0"
6969+  [(set_attr "length" "3")
6970+   (set (attr "cycles") (const_int JSR_EXTENDED_CYCLES))])
6971+
6972+
6973+(define_insn "*call_noreturn_pic"
6974+  [(call (mem:HI (match_operand:HI 0 "symbolic_operand" ""))
6975+    (match_operand:HI 1 "general_operand" "g"))]
6976+  "flag_pic && noreturn_functionp (operands[0])"
6977+  "lbra\t%C0"
6978+  [(set_attr "length" "4")])
6979+
6980+
6981+(define_insn "*call_noreturn_nopic"
6982+  [(call (match_operand:HI 0 "memory_operand" "m")
6983+    (match_operand:HI 1 "general_operand" "g"))]
6984+  "noreturn_functionp (operands[0])"
6985+  "jmp\t%0"
6986+  [(set_attr "length" "3")])
6987+
6988+
6989+;;
6990+;; Same as above, but for functions that do return a value.
6991+;;
6992+(define_expand "call_value"
6993+  [(set (match_operand 0 "" "")
6994+    (call (match_operand:HI 1 "memory_operand" "")
6995+    (match_operand:HI 2 "general_operand" "")))]
6996+  ""
6997+  "")
6998+
6999+
7000+(define_insn "*call_value_far"
7001+  [(set (match_operand 0 "" "=gz")
7002+    (call (match_operand:HI 1 "memory_operand" "m")
7003+    (match_operand:HI 2 "general_operand" "g")))]
7004+  "far_functionp (operands[1])"
7005+{
7006+  output_far_call_insn (operands, 1);
7007+  return "";
7008+}
7009+  [(set_attr "length" "6")])
7010+
7011+
7012+(define_insn "*call_value_pic"
7013+  [(set (match_operand 0 "" "=gz")
7014+    (call (mem:HI (match_operand:HI 1 "symbolic_operand" ""))
7015+    (match_operand:HI 2 "general_operand" "g")))]
7016+  "flag_pic"
7017+  "lbsr\t%C1"
7018+  [(set_attr "length" "4")])
7019+
7020+
7021+(define_insn "*call_value_nopic"
7022+  [(set (match_operand 0 "" "=gz")
7023+    (call (match_operand:HI 1 "memory_operand" "m")
7024+    (match_operand:HI 2 "general_operand" "g")))]
7025+  ""
7026+  "jsr\t%1"
7027+  [(set_attr "length" "3")
7028+   (set (attr "cycles") (const_int JSR_EXTENDED_CYCLES))])
7029+
7030+
7031+
7032+;;
7033+;; How to generate an untyped call.
7034+;;
7035+(define_expand "untyped_call"
7036+  [(parallel [(call (match_operand 0 "" "")
7037+        (const_int 0))
7038+      (match_operand 1 "" "")
7039+      (match_operand 2 "" "")])]
7040+  ""
7041+{
7042+  int i;
7043+
7044+  emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7045+  for (i=0; i < XVECLEN (operands[2], 0); i++)
7046+  {
7047+    rtx set = XVECEXP (operands[2], 0, i);
7048+    emit_move_insn (SET_DEST (set), SET_SRC (set));
7049+  }
7050+  emit_insn (gen_blockage ());
7051+  DONE;
7052+})
7053+
7054+
7055+(define_expand "sibcall"
7056+  [(parallel
7057+     [(call (match_operand:HI 0 "memory_operand" "")
7058+            (match_operand:HI 1 "immediate_operand" ""))
7059+      (use (reg:HI HARD_PC_REGNUM))])]
7060+  ""
7061+  "")
7062+
7063+(define_insn "*sibcall_1"
7064+  [(parallel
7065+     [(call (match_operand:HI 0 "memory_operand" "m")
7066+            (match_operand:HI 1 "immediate_operand" "i"))
7067+      (use (reg:HI HARD_PC_REGNUM))])]
7068+  "SIBLING_CALL_P(insn)"
7069+  "jmp\t%0"
7070+  [(set_attr "length" "4")])
7071+
7072+
7073+(define_expand "sibcall_value"
7074+  [(parallel
7075+     [(set (match_operand 0 "" "")
7076+         (call (match_operand:HI 1 "memory_operand" "")
7077+               (match_operand:HI 2 "immediate_operand" "")))
7078+      (use (reg:HI HARD_PC_REGNUM))])]
7079+  ""
7080+  "")
7081+
7082+(define_insn "*sibcall_value_1"
7083+  [(parallel
7084+     [(set (match_operand 0 "" "=gz")
7085+         (call (match_operand:HI 1 "memory_operand" "m")
7086+               (match_operand:HI 2 "immediate_operand" "i")))
7087+      (use (reg:HI HARD_PC_REGNUM))])]
7088+  "SIBLING_CALL_P(insn)"
7089+  "jmp\t%1"
7090+  [(set_attr "length" "4")])
7091+
7092+
7093+;;--------------------------------------------------------------------
7094+;;-  Function Entry and Exit
7095+;;--------------------------------------------------------------------
7096+
7097+;; On entry to a function, the stack frame looks as follows:
7098+;; - return address (pushed by the caller)
7099+;; - saved registers
7100+;; - local variable storage
7101+;;
7102+;; If the function does not modify the stack after that, then
7103+;; any of these can be accessed directly as an offset from
7104+;; STACK_POINTER_REGNUM.  Otherwise, a frame pointer is required.
7105+;; In that case, the prologue must also initialize HARD_FRAME_POINTER_REGNUM
7106+;; and all references to the stack frame will use that as a base instead.
7107+;;
7108+(define_expand "prologue"
7109+  [(const_int 0)]
7110+  "prologue_epilogue_required ()"
7111+{
7112+  emit_prologue_insns ();
7113+  DONE;
7114+})
7115+
7116+
7117+;; The function epilogue does exactly the reverse of the prologue,
7118+;; deallocating local variable space, restoring saved registers,
7119+;; and returning.
7120+;;
7121+;; For the 6809, the return may be 'rti' if the function was
7122+;; declared as an interrupt function, but is normally 'rts'.
7123+;;
7124+;; Also, as an optimization, the register restore and the 'rts'
7125+;; can be combined into a single instruction, by adding 'PC' to the
7126+;; list of registers to be restored.  This is only done if there are
7127+;; any saved registers, as 'rts' is more efficient by itself.
7128+;;
7129+(define_expand "epilogue"
7130+  [(const_int 0)]
7131+  "prologue_epilogue_required ()"
7132+{
7133+  emit_epilogue_insns (false);
7134+  DONE;
7135+})
7136+
7137+
7138+(define_expand "sibcall_epilogue"
7139+  [(const_int 0)]
7140+  "prologue_epilogue_required ()"
7141+{
7142+  emit_epilogue_insns (true);
7143+  DONE;
7144+})
7145+
7146+
7147+;; The RTS instruction
7148+(define_insn "return_rts"
7149+  [(return)
7150+   (use (reg:HI HARD_PC_REGNUM))]
7151+  "!m6809_current_function_has_type_attr_p (\"interrupt\")
7152+   && m6809_get_live_regs () == 0"
7153+  "rts"
7154+  [(set_attr "length" "1")
7155+   (set (attr "cycles") (const_int RTS_CYCLES))])
7156+
7157+(define_insn "return_puls_pc"
7158+  [(return)
7159+   (use (reg:HI HARD_PC_REGNUM))]
7160+  "!m6809_current_function_has_type_attr_p (\"interrupt\")
7161+   && m6809_get_live_regs () != 0"
7162+  ""
7163+  [(set_attr "length" "1")
7164+   (set (attr "cycles") (const_int RTS_CYCLES))])
7165+
7166+;; The RTI instruction
7167+(define_insn "return_rti"
7168+  [(return)
7169+   (use (reg:HI HARD_PC_REGNUM))]
7170+  "m6809_current_function_has_type_attr_p (\"interrupt\")"
7171+  "rti"
7172+  [(set_attr "length" "1")
7173+   (set (attr "cycles") (const_int RTI_CYCLES))])
7174+
7175+
7176+;;--------------------------------------------------------------------
7177+;;-  Unspecified instructions
7178+;;--------------------------------------------------------------------
7179+
7180+;; An instruction that has the effect of an unspec_volatile, but
7181+;; which doesn't require emitting any assembly code.
7182+(define_insn "blockage"
7183+  [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
7184+  ""
7185+  ""
7186+  [(set_attr "length" "0")
7187+   (set (attr "cycles") (const_int 0))])
7188+
7189+
7190+;; Say how to push multiple registers onto the stack, using
7191+;; the 6809 'pshs' instruction.  The operand is a regset
7192+;; specifying which registers to push.
7193+;;
7194+;; The operand mode is not given intentionally, so as to allow
7195+;; any possible integer mode for the regset.
7196+;;
7197+;; See below for a peephole that can combine consecutive push
7198+;; instructions that qualify for merging.
7199+(define_insn "register_push"
7200+  [(use (reg:HI HARD_S_REGNUM))
7201+    (unspec_volatile
7202+      [(match_operand 0 "immediate_operand" "")] UNSPEC_PUSH_RS)
7203+    (clobber (reg:HI HARD_S_REGNUM))]
7204+  ""
7205+  "pshs\t%R0"
7206+  [(set_attr "length" "2")
7207+   (set (attr "cycles") (const_int PSH_PUL_CYCLES))])
7208+
7209+
7210+;; Say how to pop multiple registers from the stack, using
7211+;; the 6809 'puls' instruction.  The operand is the register
7212+;; bitset value.
7213+(define_insn "register_pop"
7214+  [(use (reg:HI HARD_S_REGNUM))
7215+    (unspec_volatile
7216+      [(match_operand 0 "immediate_operand" "")] UNSPEC_POP_RS)
7217+    (clobber (reg:HI HARD_S_REGNUM))]
7218+  ""
7219+  "puls\t%R0"
7220+  [(set_attr "length" "2")
7221+   (set (attr "cycles") (const_int PSH_PUL_CYCLES))])
7222+
7223+
7224+(define_insn "m6809_swi"
7225+  [(unspec_volatile
7226+    [(match_operand:QI 0 "immediate_operand" "I,n")] UNSPEC_SWI)]
7227+  ""
7228+  "@
7229+   swi
7230+   swi%c0"
7231+  [(set_attr "length" "1,2")
7232+   (set (attr "cycles") (const_int SWI_CYCLES))])
7233+
7234+
7235+;; Generate the CWAI instruction
7236+(define_insn "m6809_cwai"
7237+  [(unspec_volatile
7238+    [(match_operand:QI 0 "immediate_operand" "")] UNSPEC_CWAI)]
7239+  ""
7240+  "cwai\t%0"
7241+  [(set_attr "length" "2")
7242+   (set (attr "cycles") (const_int CWAI_CYCLES))])
7243+
7244+
7245+;; Generate the SYNC instruction
7246+(define_insn "m6809_sync"
7247+  [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
7248+  ""
7249+  "sync"
7250+  [(set_attr "length" "1")
7251+   (set (attr "cycles") (const_int SYNC_CYCLES))])
7252+
7253+
7254+;; Generate the NOP instruction
7255+(define_insn "nop"
7256+  [(const_int 0)]
7257+  ""
7258+  "nop"
7259+   [(set_attr "length" "1")
7260+   (set (attr "cycles") (const_int NOP_CYCLES))])
7261+
7262+
7263+;;--------------------------------------------------------------------
7264+;;- Peepholes
7265+;;--------------------------------------------------------------------
7266+
7267+;;; Each peephole has an ID that is used for debugging.
7268+;;; Each peephole condition is bracketed by calls to
7269+;;; m6809_match_peephole2() also for debugging.
7270+(define_constants [
7271+  (PEEP_END 0)
7272+  (PEEP_COND 1)
7273+
7274+  (PEEP_STACK_STORE_INC 0)
7275+  (PEEP_STACK_CLEAR_INC 1)
7276+  (PEEP_LSRB_ADCB 2)
7277+  (PEEP_ABX 3)
7278+  (PEEP_ABX2 4)
7279+  (PEEP_INDEXED_INC 5)
7280+  (PEEP_MEM_DEC 6)
7281+  (PEEP_MEM_INC 7)
7282+  (PEEP_MEM_DEC_CMP 8)
7283+  (PEEP_PUSH2 9)
7284+  (PEEP_STORE_IMPLIES_CC 10)
7285+  (PEEP_DEC_IMPLIES_CC 11)
7286+  (PEEP_LEAB 12)
7287+  (PEEP_LDX_INDIRECT 13)
7288+  (PEEP_POP_JUNK 14)
7289+])
7290+
7291+
7292+;;; Optimize 'leas -1,s' followed by 'stb ,s'.  This can happen if the
7293+;;; function prologue needs to allocate stack space and 'b' is placed
7294+;;; into that local right away.  Combine the stack allocation with the
7295+;;; store using preincrement mode.
7296+(define_peephole2
7297+  [(set (reg:HI HARD_S_REGNUM)
7298+        (plus:HI (reg:HI HARD_S_REGNUM) (const_int -1)))
7299+   (set (mem:QI (reg:HI HARD_S_REGNUM))
7300+        (match_operand:QI 0 "register_operand" ""))]
7301+  "m6809_match_peephole2 (PEEP_STACK_STORE_INC, PEEP_END)"
7302+  [(set (mem:QI (pre_dec:HI (reg:HI HARD_S_REGNUM))) (match_dup 0))]
7303+  "")
7304+
7305+
7306+;;; Same as above, but for a 'clr ,s' that follows the prologue.
7307+(define_peephole2
7308+  [(set (reg:HI HARD_S_REGNUM) (plus:HI (reg:HI HARD_S_REGNUM) (const_int -1)))
7309+   (set (mem:QI (reg:HI HARD_S_REGNUM)) (const_int 0))]
7310+  "m6809_match_peephole2 (PEEP_STACK_CLEAR_INC, PEEP_END)"
7311+  [(set (mem:QI (pre_dec:HI (reg:HI HARD_S_REGNUM))) (const_int 0))]
7312+  "")
7313+
7314+
7315+;;; Merge two consecutive push instructions into a single register_push.
7316+(define_peephole2
7317+  [(set (match_operand 0 "push_operand" "")
7318+    (match_operand 1 "register_operand" ""))
7319+   (set (match_operand 2 "push_operand" "")
7320+    (match_operand 3 "register_operand" ""))]
7321+  "m6809_match_peephole2 (PEEP_PUSH2, PEEP_COND)
7322+   && reload_completed
7323+   && GET_MODE (operands[1]) == GET_MODE (operands[3])
7324+   && m6809_can_merge_pushpop_p (UNSPEC_PUSH_RS, 1 << REGNO (operands[1]), 1 << REGNO (operands[3]))
7325+   && m6809_match_peephole2 (PEEP_PUSH2, PEEP_END)"
7326+  [(parallel [
7327+    (use (reg:HI HARD_S_REGNUM))
7328+    (unspec_volatile [(match_dup 4)] UNSPEC_PUSH_RS)
7329+    (clobber (reg:HI HARD_S_REGNUM))])
7330+   (use (match_dup 1))
7331+   (use (match_dup 3))]
7332+{
7333+  operands[4] = gen_rtx_CONST_INT (QImode,
7334+    (1 << REGNO (operands[1])) | (1 << REGNO (operands[3])));
7335+})
7336+
7337+
7338+;;; Convert 'stX ,--s' into a push instruction.  Use the regset
7339+;;; notation, so that it may be combined with an adjacent regset.
7340+;;; TBD - this doesn't compile some code cleanly.
7341+;(define_peephole2
7342+;  [(set (mem:HI (pre_dec:HI (reg:HI HARD_S_REGNUM)))
7343+;        (reg:HI HARD_X_REGNUM))]
7344+;  "reload_completed"
7345+;  [(parallel [
7346+;    (use (reg:HI HARD_S_REGNUM))
7347+;    (unspec_volatile [(match_dup 0)] UNSPEC_PUSH_RS)
7348+;    (clobber (reg:HI HARD_S_REGNUM))])]
7349+;{
7350+;  operands[0] = gen_rtx_CONST_INT (HImode, X_REGBIT);
7351+;})
7352+
7353+
7354+;;;
7355+;;; q = (q+1)/2 can be optimized as "lsrb; adcb".  This also
7356+;;; won't overflow when q=0xFF.
7357+;;; TODO : this form isn't accounting for promotion when
7358+;;; using 16-bit ints.
7359+;;;
7360+(define_peephole
7361+  [(set (reg:QI HARD_D_REGNUM)
7362+    (lshiftrt:QI (plus:HI (match_dup 0) (const_int 1)) (const_int 1)))]
7363+  "m6809_match_peephole2 (PEEP_LSRB_ADCB, PEEP_END)"
7364+  "lsrb\;adcb\t#0; peephole"
7365+  [(set_attr "length" "2")])
7366+
7367+
7368+;;
7369+;; Optimize the case of following a register store with a test
7370+;; of reg or mem just moved.
7371+;;
7372+(define_peephole
7373+  [(set (match_operand:HI 0 "memory_operand" "=m")
7374+  (match_operand:HI 1 "register_operand" "r"))
7375+   (set (cc0) (match_operand:HI 2 "general_operand" "g"))]
7376+  "m6809_match_peephole2 (PEEP_STORE_IMPLIES_CC, PEEP_COND)
7377+   && (operands[2] == operands[0] || operands[2] == operands[1])
7378+   && m6809_match_peephole2 (PEEP_STORE_IMPLIES_CC, PEEP_END)"
7379+  "st%1\t%0\t;movhi: R:%1 -> %0 w/ implied test of %2"
7380+  [(set_attr "length" "4")])
7381+
7382+
7383+;; Optimize a pair of SET instructions in which the second insn
7384+;; is the reverse of the first one.  I.e.
7385+;;
7386+;; A = B
7387+;;        ---->  A = B
7388+;; B = A
7389+;;
7390+;; The second insn is redundant.  Define two patterns, one for QI, one for HI.
7391+;; But don't do this if either is a VOLATILE MEM.
7392+(define_peephole2
7393+  [(set (match_operand:HI 0 "nonimmediate_operand" "")
7394+        (match_operand:HI 1 "nonimmediate_operand" ""))
7395+  (set (match_dup 1) (match_dup 0))]
7396+  "!MEM_P (operands[0]) || !MEM_P (operands[1]) || (!MEM_VOLATILE_P (operands[0]) && !MEM_VOLATILE_P (operands[1]))"
7397+  [(set (match_dup 0) (match_dup 1))]
7398+  "")
7399+
7400+(define_peephole2
7401+  [(set (match_operand:QI 0 "nonimmediate_operand" "")
7402+        (match_operand:QI 1 "nonimmediate_operand" ""))
7403+  (set (match_dup 1) (match_dup 0))]
7404+  "!MEM_P (operands[0]) || !MEM_P (operands[1]) || (!MEM_VOLATILE_P (operands[0]) && !MEM_VOLATILE_P (operands[1]))"
7405+  [(set (match_dup 0) (match_dup 1))]
7406+  "")
7407+
7408+
7409+;;
7410+;; Optimize the sum of an 8-bit and 16-bit using the 'abx' instruction
7411+;; if B and X can be used.  Two patterns are provided to catch both
7412+;; X=X+D and X=D+X.
7413+;;
7414+(define_peephole
7415+  [(set (reg:HI HARD_D_REGNUM)
7416+    (zero_extend:HI (match_operand:QI 0 "general_operand" "q")))
7417+   (set (reg:HI HARD_X_REGNUM)
7418+    (plus:HI (reg:HI HARD_D_REGNUM) (reg:HI HARD_X_REGNUM)))]
7419+  "m6809_match_peephole2 (PEEP_ABX, PEEP_END)"
7420+  "abx"
7421+  [(set_attr "length" "1")])
7422+
7423+(define_peephole
7424+  [(set (reg:HI HARD_D_REGNUM)
7425+    (zero_extend:HI (match_operand:QI 0 "general_operand" "q")))
7426+   (set (reg:HI HARD_X_REGNUM)
7427+    (plus:HI (reg:HI HARD_X_REGNUM) (reg:HI HARD_D_REGNUM)))]
7428+  "m6809_match_peephole2 (PEEP_ABX, PEEP_END)"
7429+  "abx"
7430+  [(set_attr "length" "1")])
7431+
7432+;;; Likewise, handle when B is scaled by 2 prior to the add.
7433+;;; Instead of shifting B in 4 cycles, just do the ABX a second
7434+;;; time, in only 3 cycles.
7435+
7436+(define_peephole
7437+  [(set (reg:HI HARD_D_REGNUM)
7438+    (zero_extend:HI (match_operand:QI 0 "general_operand" "q")))
7439+   (set (reg:HI HARD_D_REGNUM)
7440+    (ashift:HI (reg:HI HARD_D_REGNUM) (const_int 1)))
7441+   (set (reg:HI HARD_X_REGNUM)
7442+    (plus:HI (reg:HI HARD_D_REGNUM) (reg:HI HARD_X_REGNUM)))]
7443+  "m6809_match_peephole2 (PEEP_ABX2, PEEP_END)"
7444+  "abx\;abx"
7445+  [(set_attr "length" "2")])
7446+
7447+(define_peephole
7448+  [(set (reg:HI HARD_D_REGNUM)
7449+    (zero_extend:HI (match_operand:QI 0 "general_operand" "q")))
7450+   (set (reg:HI HARD_D_REGNUM)
7451+    (ashift:HI (reg:HI HARD_D_REGNUM) (const_int 1)))
7452+   (set (reg:HI HARD_X_REGNUM)
7453+    (plus:HI (reg:HI HARD_X_REGNUM) (reg:HI HARD_D_REGNUM)))]
7454+  "m6809_match_peephole2 (PEEP_ABX2, PEEP_END)"
7455+  "abx\;abx"
7456+  [(set_attr "length" "2")])
7457+
7458+
7459+;;
7460+;; Work around a compiler bug that generates bad code when copying
7461+;; between 32-bit memory addresses after a libcall.  The problem seen is
7462+;; that the source is MEM (REG X), but X is used as the reload register.
7463+;; The second half of the copy therefore fails.
7464+;;
7465+;; The solution is to switch the reload register to D, since that is guaranteed
7466+;; not to be in use right after a libcall.
7467+;;
7468+(define_peephole2
7469+  [(set (reg:HI HARD_X_REGNUM) (mem:HI (reg:HI HARD_X_REGNUM)))
7470+   (set (match_operand:HI 0 "nonimmediate_operand" "") (reg:HI HARD_X_REGNUM))
7471+   (set (reg:HI HARD_X_REGNUM)
7472+      (mem:HI (plus:HI (reg:HI HARD_X_REGNUM) (const_int 2))))
7473+   (set (match_operand:HI 1 "nonimmediate_operand" "") (reg:HI HARD_X_REGNUM))]
7474+  "reload_completed"
7475+  [(set (reg:HI HARD_D_REGNUM) (mem:HI (reg:HI HARD_X_REGNUM)))
7476+   (set (match_dup 0) (reg:HI HARD_D_REGNUM))
7477+   (set (reg:HI HARD_X_REGNUM)
7478+      (mem:HI (plus:HI (reg:HI HARD_X_REGNUM) (const_int 2))))
7479+   (set (match_dup 1) (reg:HI HARD_X_REGNUM))]
7480+  "")
7481+
7482+
7483+;; Turn "and then test" into a "bit test" operation.
7484+;; Provide variants for immediate and memory sources
7485+;; This is the most used peephople.
7486+; (define_peephole
7487+;   [(set (match_operand:QI 0 "register_operand" "=q")
7488+;     (and:QI (match_operand:QI 1 "register_operand" "0")
7489+;       (match_operand:QI 2 "immediate_operand" "i")))
7490+;    (set (cc0) (match_dup 0))]
7491+;   ""
7492+;   "bit%0\t%2"
7493+;   [(set_attr "length" "3")])
7494+; 
7495+; (define_peephole
7496+;   [(set (match_operand:QI 0 "register_operand" "=q")
7497+;     (and:QI (match_operand:QI 1 "register_operand" "0")
7498+;       (match_operand:QI 2 "memory_operand" "m")))
7499+;    (set (cc0) (match_dup 0))]
7500+;   ""
7501+;   "bit%0\t%2"
7502+;   [(set_attr "length" "4")])
7503+
7504+
7505+;; Turn a "decrement, then test" sequence into just a "decrement".
7506+;; The test can be omitted, since it is implicitly done.
7507+(define_peephole2
7508+  [(set (match_operand:QI 0 "nonimmediate_operand" "")
7509+    (plus:QI (match_operand:QI 1 "whole_general_operand" "")
7510+    (match_operand:QI 2 "immediate_operand" "")))
7511+   (set (cc0) (match_dup 0))]
7512+  "m6809_match_peephole2 (PEEP_DEC_IMPLIES_CC, PEEP_END)"
7513+  [(set (match_dup 0) (plus:QI (match_dup 1) (match_dup 2)))]
7514+  "")
7515+
7516+
7517+;; Merge an indexed register increment with a previous usage.
7518+;; This is usually done automatically, but not always
7519+;; The 'use' should be optional; in all cases where this has been
7520+;; seen, it is required though.
7521+(define_peephole2
7522+  [(set (match_operand:QI 0 "register_operand" "")
7523+     (mem:QI (match_operand:HI 1 "index_register_operand" "")))
7524+   (use (match_dup 0))
7525+   (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))]
7526+  "m6809_match_peephole2 (PEEP_INDEXED_INC, PEEP_END)"
7527+  [(set (match_dup 0) (mem:QI (post_inc:HI (match_dup 1))))
7528+   (use (match_dup 0))]
7529+  "")
7530+
7531+
7532+;;; Merge "ldX MEM; ldX ,X" into a single instruction using
7533+;;; the indirect mode.
7534+(define_peephole2
7535+  [(set (reg:HI HARD_X_REGNUM)
7536+    (mem:HI (match_operand:HI 0 "general_operand" "")))
7537+   (set (reg:HI HARD_X_REGNUM) (mem:HI (reg:HI HARD_X_REGNUM)))]
7538+  "reload_completed && m6809_match_peephole2 (PEEP_LDX_INDIRECT, PEEP_END)"
7539+  [(set (reg:HI HARD_X_REGNUM)
7540+    (mem:HI (mem:HI (match_dup 0))))]
7541+  "")
7542+
7543+
7544+;;; Reorder a store followed by a unary operation on that memory
7545+;;; so that the unary is performed and then the store.  Consider
7546+;;; a binary shift operation, which will be decomposed into
7547+;;; identical single shifts, also.
7548+;;; TODO - recognize more than just 'ashift' here.
7549+(define_peephole2
7550+  [(set (match_operand:QI 0 "memory_operand" "")
7551+        (match_operand:QI 1 "register_operand" ""))
7552+   (set (match_dup 0)
7553+        (ashift:QI (match_dup 0) (match_operand:QI 2 "immediate_operand")))]
7554+  "reload_completed"
7555+  [(set (match_dup 1)
7556+        (ashift:QI (match_dup 1) (match_operand:QI 2 "immediate_operand")))
7557+   (set (match_dup 0) (match_dup 1))]
7558+  "")
7559+
7560+;;; Likewise, reorder a unary MEM followed by a load, so that the load
7561+;;; is done first, then use the REG instead of the MEM.
7562+;;;(define_peephole2
7563+;;;  [(set (match_dup 0)
7564+;;;        (ashift:QI (match_dup 0) (match_operand:QI 2 "immediate_operand")))
7565+;;;   (set (match_operand:QI 0 "register_operand" "")
7566+;;;        (match_operand:QI 1 "memory_operand" ""))]
7567+;;;  "reload_completed"
7568+;;;  [(set (match_dup 0) (match_dup 1))
7569+;;;   (set (match_dup 0)
7570+;;;        (ashift:QI (match_dup 0) (match_operand:QI 2 "immediate_operand")))]
7571+;;;  "")
7572+
7573+
7574+;;; Replace sex; leaX d,Y with leaX b,Y.
7575+;;;
7576+(define_peephole2
7577+  [(set (reg:HI HARD_D_REGNUM) (sign_extend:HI (reg:QI HARD_D_REGNUM)))
7578+   (set (match_operand:HI 0 "index_register_operand" "")
7579+        (plus:HI (match_operand:HI 1 "index_register_operand" "")
7580+                 (reg:HI HARD_D_REGNUM)))]
7581+  "reload_completed && m6809_match_peephole2 (PEEP_LEAB, PEEP_END)"
7582+  [(set (match_dup 0)
7583+        (plus:HI (match_dup 1) (reg:QI HARD_D_REGNUM)))]
7584+  "")
7585+
7586+(define_peephole2
7587+  [(set (reg:HI HARD_D_REGNUM) (sign_extend:HI (reg:QI HARD_D_REGNUM)))
7588+   (set (match_operand:HI 0 "index_register_operand" "")
7589+        (plus:HI (reg:HI HARD_D_REGNUM)
7590+          (match_operand:HI 1 "index_register_operand" "")))]
7591+  "reload_completed && m6809_match_peephole2 (PEEP_LEAB, PEEP_END)"
7592+  [(set (match_dup 0)
7593+        (plus:HI (match_dup 1) (reg:QI HARD_D_REGNUM)))]
7594+  "")
7595+
7596+
7597+;;; Replace ldb; decb; stb; tstb with dec(mem).  If the
7598+;;; register is not needed, then the load will get deleted
7599+;;; automatically, but it may be needed for comparisons.
7600+;;; Same for incb/inc.
7601+(define_peephole2
7602+  [(set (match_operand:QI 0 "register_operand" "")
7603+        (match_operand:QI 1 "nonimmediate_operand" ""))
7604+   (set (match_dup 0) (plus:QI (match_dup 0) (const_int -1)))
7605+   (set (match_dup 1) (match_dup 0))
7606+   (set (cc0) (match_dup 0))]
7607+  "m6809_match_peephole2 (PEEP_MEM_DEC_CMP, PEEP_END)"
7608+  [(set (match_dup 1) (plus:QI (match_dup 1) (const_int -1)))]
7609+  "")
7610+
7611+
7612+;;; Replace ldb; decb; stb with dec(mem); ldb.  If the
7613+;;; register is not needed, then the load will get deleted
7614+;;; automatically, but it may be needed for comparisons.
7615+;;; Same for incb/inc.
7616+(define_peephole2
7617+  [(set (match_operand:QI 0 "register_operand" "")
7618+        (match_operand:QI 1 "nonimmediate_operand" ""))
7619+   (set (match_dup 0) (plus:QI (match_dup 0) (const_int -1)))
7620+   (set (match_dup 1) (match_dup 0))]
7621+  "m6809_match_peephole2 (PEEP_MEM_DEC, PEEP_END)"
7622+  [(set (match_dup 1) (plus:QI (match_dup 1) (const_int -1)))
7623+   (set (match_dup 0) (match_dup 1))]
7624+  "")
7625+
7626+(define_peephole2
7627+  [(set (match_operand:QI 0 "register_operand" "")
7628+        (match_operand:QI 1 "nonimmediate_operand" ""))
7629+   (set (match_dup 0) (plus:QI (match_dup 0) (const_int 1)))
7630+   (set (match_dup 1) (match_dup 0))]
7631+  "m6809_match_peephole2 (PEEP_MEM_INC, PEEP_END)"
7632+  [(set (match_dup 1) (plus:QI (match_dup 1) (const_int 1)))
7633+   (set (match_dup 0) (match_dup 1))]
7634+  "")
7635+
7636+
7637+;;; Replace "andb #N; cmpb #N; bhi" with "andb #N", if it can be proven
7638+;;; that the branch can never occur because of the limited range of B.
7639+;;; N must be a power of two for this to make sense.  This helps with
7640+;;; the default cases of switch statements on a value (x & N).
7641+(define_peephole2
7642+  [(set (match_operand:QI 0 "register_operand" "")
7643+    (and:QI (match_dup 0) (match_operand:QI 1 "immediate_operand" "")))
7644+   (set (cc0)
7645+    (compare (match_dup 0) (match_dup 1)))
7646+   (set (pc) (if_then_else (gtu (cc0) (const_int 0)) (match_operand 2 "" "") (match_operand 3 "" "")))
7647+   ]
7648+  "reload_completed && power_of_two_p (INTVAL (operands[1]) + 1)"
7649+  [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
7650+  "")
7651+
7652+;;; Replace ldd <mem>; addd #1; std <mem> with 16-bit increment
7653+;;; of the mem, but only if D is dead.  Same for 16-bit decrement.
7654+;;; <mem> must be offsettable for the instruction to match.
7655+(define_peephole2
7656+  [(set (match_operand:HI 0 "register_operand" "") (match_operand:HI 1 "memory_operand" ""))
7657+   (set (match_dup 0) (plus:HI (match_dup 0) (const_int 1)))
7658+   (set (match_dup 1) (match_dup 0))]
7659+   "reload_completed
7660+    && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7661+    && peep2_reg_dead_p (3, operands[0])"
7662+  [(set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))]
7663+  "")
7664+
7665+(define_peephole2
7666+  [(set (match_operand:HI 0 "register_operand" "") (match_operand:HI 1 "memory_operand" ""))
7667+   (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))
7668+   (set (match_dup 1) (match_dup 0))]
7669+   "reload_completed
7670+    && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7671+    && peep2_reg_dead_p (3, operands[0])"
7672+  [(set (match_dup 1) (plus:HI (match_dup 1) (const_int -1)))]
7673+  "")
7674+
7675+
7676+;;; Replace a load or store using an indexed register, followed by an increment of that
7677+;;; register, with the combined form using autoincrement.
7678+(define_peephole2
7679+  [(set (match_operand:QI 0 "register_operand" "")
7680+        (mem:QI (match_operand:HI 1 "index_register_operand" "")))
7681+   (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))]
7682+   "reload_completed"
7683+  [(set (match_dup 0) (mem:QI (post_inc (match_dup 1))))]
7684+  "")
7685+
7686+
7687+;;- mode:emacs-lisp
7688+;;- comment-start: ";;- "
7689+;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
7690+;;- eval: (modify-syntax-entry ?[ "(]")
7691+;;- eval: (modify-syntax-entry ?] ")[")
7692+;;- eval: (modify-syntax-entry ?{ "(}")
7693+;;- eval: (modify-syntax-entry ?} "){")
7694+;-; vim: set ts=2:
7695+;-; vim: set expandtab:
7696+;-; vim: set filetype=lisp:
7697+;;- End:
7698diff --git a/gcc/config/m6809/m6809.opt b/gcc/config/m6809/m6809.opt
7699new file mode 100644
7700index 0000000..6270917
7701--- /dev/null
7702+++ b/gcc/config/m6809/m6809.opt
7703@@ -0,0 +1,98 @@
7704+; Options for the M6809 port of the compiler
7705+;
7706+; Copyright (C) 2005 Free Software Foundation, Inc.
7707+;
7708+; This file is part of GCC.
7709+;
7710+; GCC is free software; you can redistribute it and/or modify it under
7711+; the terms of the GNU General Public License as published by the Free
7712+; Software Foundation; either version 2, or (at your option) any later
7713+; version.
7714+;
7715+; GCC is distributed in the hope that it will be useful, but WITHOUT
7716+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
7717+; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
7718+; License for more details.
7719+;
7720+; You should have received a copy of the GNU General Public License
7721+; along with GCC; see the file COPYING.  If not, write to the Free
7722+; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
7723+; 02110-1301, USA.
7724+
7725+margcount
7726+Target Mask(ARGCOUNT)
7727+Push argument count
7728+
7729+mint8
7730+Target RejectNegative Mask(BYTE_INT)
7731+Use 8-bit integers
7732+
7733+mint16
7734+Target RejectNegative
7735+Use 16-bit integers InverseMask(BYTE_INT)
7736+
7737+mreg-args
7738+Target Mask(REG_ARGS)
7739+Use registers for function arguments
7740+
7741+mshort_size 
7742+Target RejectNegative Mask(SMALL_SIZE_T)
7743+Use 8-bit size_t
7744+
7745+mlong_size
7746+Target RejectNegative InverseMask(SMALL_SIZE_T)
7747+Use 16-bit size_t
7748+
7749+mdirect
7750+Target Mask(DIRECT)
7751+Enable direct addressing
7752+
7753+mwpc
7754+Target RejectNegative Mask(WPC)
7755+Enable WPC platform extensions
7756+
7757+mexperiment
7758+Target RejectNegative Mask(EXPERIMENT)
7759+Enable current experimental feature
7760+
7761+m6309
7762+Target RejectNegative Mask(6309)
7763+Enable Hitachi 6309 extensions
7764+
7765+mcasesi
7766+Target RejectNegative Mask(CASESI)
7767+Enable the casesi pattern
7768+
7769+mfar-code-page=
7770+Target RejectNegative Joined Var(far_code_page_option)
7771+Sets the far code page value for this compilation unit
7772+
7773+mcode-section=
7774+Target RejectNegative Joined Var(code_section_ptr)
7775+Sets the name of the section for code
7776+
7777+mdata-section=
7778+Target RejectNegative Joined Var(data_section_ptr)
7779+Sets the name of the section for initialized data
7780+
7781+mbss-section=
7782+Target RejectNegative Joined Var(bss_section_ptr)
7783+Sets the name of the section for uninitialized data
7784+
7785+mabi_version=
7786+Target RejectNegative Joined Var(m6809_abi_version_ptr)
7787+Sets the calling convention
7788+
7789+msoft-reg-count=
7790+Target RejectNegative Joined Var(m6809_soft_reg_count)
7791+Sets the number of soft registers that can be used
7792+
7793+mdret
7794+Target RejectNegative Mask(DRET)
7795+Put function call results in D, not X
7796+
7797+mfar-stack-param
7798+Target Mask(FAR_STACK_PARAM)
7799+Enable stack parameters to a farcall
7800+
7801+
7802diff --git a/gcc/config/m6809/predicates.md b/gcc/config/m6809/predicates.md
7803new file mode 100644
7804index 0000000..0e257ec
7805--- /dev/null
7806+++ b/gcc/config/m6809/predicates.md
7807@@ -0,0 +1,78 @@
7808+;; Predicate definitions for Motorola 6809
7809+;; Copyright (C) 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
7810+;;
7811+;; This file is part of GCC.
7812+;;
7813+;; GCC is free software; you can redistribute it and/or modify
7814+;; it under the terms of the GNU General Public License as published by
7815+;; the Free Software Foundation; either version 3, or (at your option)
7816+;; any later version.
7817+;;
7818+;; GCC is distributed in the hope that it will be useful,
7819+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
7820+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
7821+;; GNU General Public License for more details.
7822+;;
7823+;; You should have received a copy of the GNU General Public License
7824+;; along with GCC; see the file COPYING3.  If not see
7825+;; <http://www.gnu.org/licenses/>.
7826+
7827+;; whole_register_operand is like register_operand, but it
7828+;; does not allow SUBREGs.
7829+(define_predicate "whole_register_operand"
7830+  (and (match_code "reg")
7831+       (match_operand 0 "register_operand")))
7832+
7833+
7834+;; A predicate that matches any index register.  This can be used in nameless
7835+;; patterns and peepholes which need a 16-bit reg, but not D.
7836+(define_predicate "index_register_operand"
7837+  (and (match_code "reg")
7838+       (match_test "REGNO (op) == HARD_X_REGNUM || REGNO (op) == HARD_Y_REGNUM || REGNO (op) == HARD_U_REGNUM")))
7839+
7840+
7841+;; match only X
7842+(define_predicate "register_operand_x"
7843+  (and (match_code "reg")
7844+       (match_test "REGNO (op) == HARD_X_REGNUM")))
7845+
7846+;; match only D
7847+(define_predicate "register_operand_d"
7848+  (and (match_code "reg")
7849+       (match_test "REGNO (op) == HARD_D_REGNUM")))
7850+
7851+
7852+;; Likwise, a replacement for general_operand which excludes
7853+;; SUBREGs.
7854+(define_predicate "whole_general_operand"
7855+  (and (match_code "const_int,const_double,const,symbol_ref,label_ref,reg,mem")
7856+       (match_operand 0 "general_operand")))
7857+
7858+
7859+(define_predicate "add_general_operand"
7860+  (and (match_code "const_int,const_double,const,symbol_ref,label_ref,reg,mem")
7861+       (match_operand 0 "general_operand")
7862+		 (match_test "REGNO (op) != SOFT_AP_REGNUM")))
7863+
7864+
7865+(define_predicate "shift_count_operand"
7866+  (and (match_code "const_int")
7867+     (and (match_operand 0 "const_int_operand")
7868+       (match_test "INTVAL (op) == 1 || INTVAL (op) == 8"))))
7869+
7870+
7871+;; A predicate that matches any bitwise logical operator.  This
7872+;; allows for a single RTL pattern to be used for multiple operations.
7873+(define_predicate "logical_bit_operator"
7874+	(ior (match_code "and") (match_code "ior") (match_code "xor")))
7875+
7876+
7877+;; A predicate that matches any shift or rotate operator.  This
7878+;; allows for a single RTL pattern to be used for multiple operations.
7879+(define_predicate "shift_rotate_operator"
7880+	(ior (match_code "ashift") (match_code "ashiftrt") (match_code "lshiftrt")
7881+	     (match_code "rotate") (match_code "rotatert")))
7882+
7883+
7884+(define_predicate "symbolic_operand" (match_code "symbol_ref"))
7885+
7886diff --git a/gcc/config/m6809/t-coco b/gcc/config/m6809/t-coco
7887new file mode 100644
7888index 0000000..b1fa507
7889--- /dev/null
7890+++ b/gcc/config/m6809/t-coco
7891@@ -0,0 +1,6 @@
7892+# For a few minor differences in code generation on the CoCo...
7893+T_CFLAGS = -DTARGET_COCO
7894+
7895+# For doing the startup differently on the CoCo...
7896+CRT0STUFF_T_CFLAGS += -Wa,--globalize-symbols -DTARGET_COCO
7897+# vim: set filetype=make:
7898diff --git a/gcc/config/m6809/t-m6809 b/gcc/config/m6809/t-m6809
7899new file mode 100644
7900index 0000000..2b38a8f
7901--- /dev/null
7902+++ b/gcc/config/m6809/t-m6809
7903@@ -0,0 +1,64 @@
7904+
7905+# ranlib doesn't exist, so define it to 'true' to make it a no-op
7906+RANLIB_FOR_TARGET = true
7907+
7908+# Stubs for libgcc defined by m6809 are here
7909+LIB1ASMSRC = m6809/libgcc1.s
7910+
7911+# Here are the functions that are implemented within libgcc1.s
7912+LIB1ASMFUNCS = _mulhi3 _divhi3 _modhi3 _udivhi3 _umodhi3 \
7913+	_euclid _seuclid _clzsi2 _clzdi2 _ctzsi2 _ctzdi2 _softregs \
7914+	_ashlhi3 _ashrhi3 _lshrhi3
7915+
7916+# Flags to use when building libgcc.  IN_GCC does not seem necessary,
7917+# although the compile breaks without it.  -DDF=SF is required to set
7918+# the size of "double" to the same as the size of a "float".
7919+TARGET_LIBGCC2_CFLAGS =-DIN_GCC -Dinhibit_libc -DDF=SF -DLIBGCC2_HAS_SF_MODE=0 -DLIBGCC2_HAS_DF_MODE=0
7920+
7921+LIB2ADDEH =
7922+LIB2ADDEHSTATIC =
7923+LIB2ADDEHSHARED =
7924+
7925+LIBGCC2_DEBUG_CFLAGS =
7926+LIBGCC2_CFLAGS = -Os $(LIBGCC2_INCLUDES) $(TARGET_LIBGCC2_CFLAGS) $(LIBGCC2_DEBUG_CFLAGS) $(GTHREAD_FLAGS) -DIN_LIBGCC2
7927+
7928+# Multilib information
7929+# This creates multiple versions of libgcc.a for each set of incompatible
7930+# -mxxx options.
7931+MULTILIB_OPTIONS  = fpic mdret
7932+MULTILIB_DIRNAMES =
7933+MULTILIB_MATCHES  =
7934+MULTILIB_EXCEPTIONS =
7935+EXTRA_MULTILIB_PARTS = crt0.o
7936+
7937+LIBGCC = stmp-multilib
7938+INSTALL_LIBGCC = install-multilib
7939+
7940+# We want fine grained libraries, so use the new code to build the
7941+# floating point emulation libraries.
7942+FPBIT = fp-bit.c
7943+
7944+fp-bit.c: $(srcdir)/config/fp-bit.c
7945+	echo '#define FLOAT' > fp-bit.c
7946+	echo '#define FLOAT_ONLY' >> fp-bit.c
7947+	echo '#define CMPtype HItype' >> fp-bit.c
7948+	echo '#define SMALL_MACHINE' >> fp-bit.c
7949+	echo '#ifdef __LITTLE_ENDIAN__' >> fp-bit.c
7950+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>fp-bit.c
7951+	echo '#endif' 		>> fp-bit.c
7952+	echo '#define DI SI'	>> fp-bit.c
7953+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
7954+
7955+# crt0.o is built from the following source file
7956+CRT0_S = $(srcdir)/config/m6809/crt0.S
7957+MCRT0_S = $(srcdir)/config/m6809/crt0.S
7958+
7959+# Flags to use when building crt0.o
7960+CRT0STUFF_T_CFLAGS += -fno-builtin -nostartfiles -nostdlib
7961+
7962+# Assemble startup files.
7963+$(T)crt0.o: $(CRT0_S) $(GCC_PASSES)
7964+	$(GCC_FOR_TARGET) $(CRT0STUFF_T_CFLAGS) $(MULTILIB_CFLAGS) -c -o $(T)crt0.o -x assembler-with-cpp $(CRT0_S)
7965+
7966+$(T)mcrt0.o: $(MCRT0_S) $(GCC_PASSES)
7967+	$(GCC_FOR_TARGET) $(CRT0STUFF_T_CFLAGS) $(MULTILIB_CFLAGS) -c -o $(T)mcrt0.o -x assembler-with-cpp $(MCRT0_S)
7968diff --git a/gcc/config/m6809/t-sim b/gcc/config/m6809/t-sim
7969new file mode 100644
7970index 0000000..cd3b094
7971--- /dev/null
7972+++ b/gcc/config/m6809/t-sim
7973@@ -0,0 +1 @@
7974+CRT0STUFF_T_CFLAGS += -DTARGET_SIM
7975diff --git a/gcc/gcse.c b/gcc/gcse.c
7976index 27f7e8f..1079c6f 100644
7977--- a/gcc/gcse.c
7978+++ b/gcc/gcse.c
7979@@ -833,7 +833,6 @@ want_to_gcse_p (rtx x, int *max_distance_ptr)
7980 	      max_distance = (GCSE_COST_DISTANCE_RATIO * cost) / 10;
7981 	      if (max_distance == 0)
7982 		return 0;
7983-
7984 	      gcc_assert (max_distance > 0);
7985 	    }
7986 	  else
7987diff --git a/gcc/libgcc2.c b/gcc/libgcc2.c
7988index 78d53f0..b5b8c84 100644
7989--- a/gcc/libgcc2.c
7990+++ b/gcc/libgcc2.c
7991@@ -485,6 +485,7 @@ __ashrdi3 (DWtype u, shift_count_type b)
7992 #endif
7993 
7994 #ifdef L_bswapsi2
7995+#if MIN_UNITS_PER_WORD > 1
7996 SItype
7997 __bswapsi2 (SItype u)
7998 {
7999@@ -494,7 +495,9 @@ __bswapsi2 (SItype u)
8000 	  | (((u) & 0x000000ff) << 24));
8001 }
8002 #endif
8003+#endif
8004 #ifdef L_bswapdi2
8005+#if LONG_LONG_TYPE_SIZE > 32
8006 DItype
8007 __bswapdi2 (DItype u)
8008 {
8009@@ -508,6 +511,7 @@ __bswapdi2 (DItype u)
8010 	  | (((u) & 0x00000000000000ffull) << 56));
8011 }
8012 #endif
8013+#endif
8014 #ifdef L_ffssi2
8015 #undef int
8016 int
8017@@ -1280,7 +1284,7 @@ __fixdfdi (DFtype a)
8018 UDWtype
8019 __fixunssfDI (SFtype a)
8020 {
8021-#if LIBGCC2_HAS_DF_MODE
8022+#if LIBGCC2_HAS_DF_MODE || (FLT_MANT_DIG >= W_TYPE_SIZE)
8023   /* Convert the SFtype to a DFtype, because that is surely not going
8024      to lose any bits.  Some day someone else can write a faster version
8025      that avoids converting to DFtype, and verify it really works right.  */
8026@@ -1298,7 +1302,7 @@ __fixunssfDI (SFtype a)
8027 
8028   /* Assemble result from the two parts.  */
8029   return ((UDWtype) hi << W_TYPE_SIZE) | lo;
8030-#elif FLT_MANT_DIG < W_TYPE_SIZE
8031+#else
8032   if (a < 1)
8033     return 0;
8034   if (a < Wtype_MAXp1_F)
8035@@ -1334,8 +1338,6 @@ __fixunssfDI (SFtype a)
8036       return (DWtype)counter << shift;
8037     }
8038   return -1;
8039-#else
8040-# error
8041 #endif
8042 }
8043 #endif
8044diff --git a/gcc/longlong.h b/gcc/longlong.h
8045index acb3185..20dd0ef 100644
8046--- a/gcc/longlong.h
8047+++ b/gcc/longlong.h
8048@@ -528,6 +528,11 @@ UDItype __umulsidi3 (USItype, USItype);
8049 	   : "cbit")
8050 #endif /* __M32R__ */
8051 
8052+#if defined (__m6309__) || defined (__m6809__)
8053+#define count_leading_zeros(COUNT,X)	((COUNT) = __builtin_clz (X))
8054+#define count_trailing_zeros(COUNT,X)	((COUNT) = __builtin_ctz (X))
8055+#endif
8056+
8057 #if defined (__mc68000__) && W_TYPE_SIZE == 32
8058 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
8059   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
8060diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
8061index c3f6c04..63936c0 100644
8062--- a/gcc/opth-gen.awk
8063+++ b/gcc/opth-gen.awk
8064@@ -121,7 +121,7 @@ BEGIN {
8065 END {
8066 print "/* This file is auto-generated by opth-gen.awk.  */"
8067 print ""
8068-print "#ifndef OPTIONS_H"
8069+print "#if !defined(OPTIONS_H) && !defined(IN_LIBGCC2)"
8070 print "#define OPTIONS_H"
8071 print ""
8072 print "#include \"flag-types.h\""
8073@@ -432,18 +432,9 @@ print ""
8074 
8075 for (i = 0; i < n_opts; i++) {
8076 	opt = opt_args("InverseMask", flags[i])
8077-	if (opt ~ ",") {
8078-		vname = var_name(flags[i])
8079-		macro = "OPTION_"
8080-		mask = "OPTION_MASK_"
8081-		if (vname == "") {
8082-			vname = "target_flags"
8083-			macro = "TARGET_"
8084-			mask = "MASK_"
8085-		}
8086-		print "#define " macro nth_arg(1, opt) \
8087-		      " ((" vname " & " mask nth_arg(0, opt) ") == 0)"
8088-	}
8089+	if (opt ~ ",")
8090+		print "#define TARGET_" nth_arg(1, opt) \
8091+		      " ((target_flags & MASK_" nth_arg(0, opt) ") == 0)"
8092 }
8093 print ""
8094 
8095diff --git a/gcc/tree.h b/gcc/tree.h
8096index ece68b4..d0ec9d6 100644
8097--- a/gcc/tree.h
8098+++ b/gcc/tree.h
8099@@ -3563,6 +3563,8 @@ enum tree_index
8100   TI_UINTDI_TYPE,
8101   TI_UINTTI_TYPE,
8102 
8103+  TI_UINT8_TYPE,
8104+  TI_UINT16_TYPE,
8105   TI_UINT32_TYPE,
8106   TI_UINT64_TYPE,
8107 
8108diff --git a/gcc/version.c b/gcc/version.c
8109index 9744449..1a1e7e0 100644
8110--- a/gcc/version.c
8111+++ b/gcc/version.c
8112@@ -21,16 +21,16 @@ along with GCC; see the file COPYING3.  If not see
8113 
8114 /* This is the location of the online document giving instructions for
8115    reporting bugs.  If you distribute a modified version of GCC,
8116-   please configure with --with-bugurl pointing to a document giving
8117-   instructions for reporting bugs to you, not us.  (You are of course
8118-   welcome to forward us bugs reported to you, if you determine that
8119-   they are not bugs in your modifications.)  */
8120+   please change this to refer to a document giving instructions for
8121+   reporting bugs to you, not us.  (You are of course welcome to
8122+   forward us bugs reported to you, if you determine that they are
8123+   not bugs in your modifications.)  */
8124 
8125-const char bug_report_url[] = BUGURL;
8126+const char bug_report_url[] = "<URL:http://lost.l-w.ca/coco/lwtools/>";
8127 
8128 /* The complete version string, assembled from several pieces.
8129    BASEVER, DATESTAMP, DEVPHASE, and REVISION are defined by the
8130    Makefile.  */
8131 
8132-const char version_string[] = BASEVER DATESTAMP DEVPHASE REVISION;
8133+const char version_string[] = BASEVER DATESTAMP DEVPHASE REVISION " (gcc6809lw pl6)";
8134 const char pkgversion_string[] = PKGVERSION;
8135diff --git a/libgcc/Makefile.in b/libgcc/Makefile.in
8136index b57aeb6..940c286 100644
8137--- a/libgcc/Makefile.in
8138+++ b/libgcc/Makefile.in
8139@@ -374,8 +374,8 @@ endif
8140 # Build lib2funcs.  For the static library also include LIB2FUNCS_ST.
8141 lib2funcs-o = $(patsubst %,%$(objext),$(lib2funcs) $(LIB2FUNCS_ST))
8142 $(lib2funcs-o): %$(objext): $(gcc_srcdir)/libgcc2.c
8143-	$(gcc_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \
8144-	  $(vis_hide)
8145+	ln -sf $(gcc_srcdir)/libgcc2.c $*.c && \
8146+	$(gcc_compile) -DL$* -c $*.c $(vis_hide) -save-temps
8147 libgcc-objects += $(lib2funcs-o)
8148 
8149 ifeq ($(enable_shared),yes)
8150@@ -410,8 +410,9 @@ endif
8151 # Build LIB2_DIVMOD_FUNCS.
8152 lib2-divmod-o = $(patsubst %,%$(objext),$(LIB2_DIVMOD_FUNCS))
8153 $(lib2-divmod-o): %$(objext): $(gcc_srcdir)/libgcc2.c
8154-	$(gcc_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \
8155-	  -fexceptions -fnon-call-exceptions $(vis_hide)
8156+	ln -sf $(gcc_srcdir)/libgcc2.c $*.c && \
8157+	$(gcc_compile) -DL$* -c $*.c \
8158+	  -fexceptions -fnon-call-exceptions $(vis_hide) -save-temps
8159 libgcc-objects += $(lib2-divmod-o)
8160 
8161 ifeq ($(enable_shared),yes)
8162@@ -443,7 +444,8 @@ endif
8163 ifneq ($(FPBIT),)
8164 fpbit-o = $(patsubst %,%$(objext),$(FPBIT_FUNCS))
8165 $(fpbit-o): %$(objext): $(FPBIT)
8166-	$(gcc_compile) -DFINE_GRAINED_LIBRARIES -DL$* -c $(FPBIT) $(vis_hide)
8167+	ln -sf $(FPBIT) $*.c && \
8168+	$(gcc_compile) -DFINE_GRAINED_LIBRARIES -DL$* -c $*.c $(vis_hide) -save-temps
8169 libgcc-objects += $(fpbit-o)
8170 
8171 ifeq ($(enable_shared),yes)
8172@@ -458,7 +460,8 @@ endif
8173 ifneq ($(DPBIT),)
8174 dpbit-o = $(patsubst %,%$(objext),$(DPBIT_FUNCS))
8175 $(dpbit-o): %$(objext): $(DPBIT)
8176-	$(gcc_compile) -DFINE_GRAINED_LIBRARIES -DL$* -c $(DPBIT) $(vis_hide)
8177+	ln -sf $(DPBIT) $*.c && \
8178+	$(gcc_compile) -DFINE_GRAINED_LIBRARIES -DL$* -c $*.c $(vis_hide) -save-temps
8179 libgcc-objects += $(dpbit-o)
8180 
8181 ifeq ($(enable_shared),yes)
8182diff --git a/libgcc/config.host b/libgcc/config.host
8183index 25e949e..7154892 100644
8184--- a/libgcc/config.host
8185+++ b/libgcc/config.host
8186@@ -371,6 +371,8 @@ m32r-*-linux*)
8187  	;;
8188 m32rle-*-linux*)
8189 	;;
8190+m6809*)
8191+	;;
8192 m68hc11-*-*|m6811-*-*)
8193         ;;
8194 m68hc12-*-*|m6812-*-*)
8195diff --git a/libgcc/fixed-obj.mk b/libgcc/fixed-obj.mk
8196index 3c7c2f3..eb3aa3a 100644
8197--- a/libgcc/fixed-obj.mk
8198+++ b/libgcc/fixed-obj.mk
8199@@ -23,7 +23,7 @@ endif
8200 #$(info $o$(objext): -DL$($o-label) $($o-opt))
8201 
8202 $o$(objext): %$(objext): $(gcc_srcdir)/config/fixed-bit.c
8203-	$(gcc_compile) -DL$($*-label) $($*-opt) -c $(gcc_srcdir)/config/fixed-bit.c $(vis_hide)
8204+	$(gcc_compile) -DL$($*-label) $($*-opt) -c $(gcc_srcdir)/config/fixed-bit.c $(vis_hide) -save-temps
8205 
8206 ifeq ($(enable_shared),yes)
8207 $(o)_s$(objext): %_s$(objext): $(gcc_srcdir)/config/fixed-bit.c
8208-- 
82092.7.0
8210
8211
8212From 696169dbc7af549e249c5122554a1ced664bb980 Mon Sep 17 00:00:00 2001
8213From: Adrien Destugues <pulkomandy@pulkomandy.tk>
8214Date: Sun, 15 Jan 2017 21:34:56 +0100
8215Subject: Fix build with gcc5.
8216
8217From
8218https://github.com/DragonFlyBSD/DPorts/commit/a680cc6ef758e2f15be8bf8209da51658e02d710
8219
8220diff --git a/gcc/cp/cfns.h b/gcc/cp/cfns.h
8221index 62cdfab..6bbc8c9 100644
8222--- a/gcc/cp/cfns.h
8223+++ b/gcc/cp/cfns.h
8224@@ -53,6 +53,9 @@ __inline
8225 static unsigned int hash (const char *, unsigned int);
8226 #ifdef __GNUC__
8227 __inline
8228+#ifdef __GNUC_STDC_INLINE__
8229+__attribute__ ((__gnu_inline__))
8230+#endif
8231 #endif
8232 const char * libc_name_p (const char *, unsigned int);
8233 /* maximum key range = 391, duplicates = 0 */
8234@@ -96,7 +99,7 @@ hash (register const char *str, register unsigned int len)
8235       400, 400, 400, 400, 400, 400, 400, 400, 400, 400,
8236       400, 400, 400, 400, 400, 400, 400
8237     };
8238-  register int hval = len;
8239+  register int hval = (int) len;
8240 
8241   switch (hval)
8242     {
8243-- 
82442.7.0
8245
8246