135afac07SIthamar R. Adema/*
235afac07SIthamar R. Adema * Device Tree Source for OMAP3 SoC
335afac07SIthamar R. Adema *
435afac07SIthamar R. Adema * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
535afac07SIthamar R. Adema *
635afac07SIthamar R. Adema * This file is licensed under the terms of the GNU General Public License
735afac07SIthamar R. Adema * version 2.  This program is licensed "as is" without any warranty of any
835afac07SIthamar R. Adema * kind, whether express or implied.
935afac07SIthamar R. Adema */
1035afac07SIthamar R. Adema
1135afac07SIthamar R. Adema#include <dt-bindings/gpio/gpio.h>
1235afac07SIthamar R. Adema#include <dt-bindings/interrupt-controller/irq.h>
1335afac07SIthamar R. Adema#include <dt-bindings/pinctrl/omap.h>
1435afac07SIthamar R. Adema
1535afac07SIthamar R. Adema#include "skeleton.dtsi"
1635afac07SIthamar R. Adema
1735afac07SIthamar R. Adema/ {
1835afac07SIthamar R. Adema	compatible = "ti,omap3430", "ti,omap3";
1935afac07SIthamar R. Adema	interrupt-parent = <&intc>;
2035afac07SIthamar R. Adema
2135afac07SIthamar R. Adema	aliases {
2235afac07SIthamar R. Adema		i2c0 = &i2c1;
2335afac07SIthamar R. Adema		i2c1 = &i2c2;
2435afac07SIthamar R. Adema		i2c2 = &i2c3;
2535afac07SIthamar R. Adema		serial0 = &uart1;
2635afac07SIthamar R. Adema		serial1 = &uart2;
2735afac07SIthamar R. Adema		serial2 = &uart3;
2835afac07SIthamar R. Adema	};
2935afac07SIthamar R. Adema
3035afac07SIthamar R. Adema	cpus {
3135afac07SIthamar R. Adema		#address-cells = <1>;
3235afac07SIthamar R. Adema		#size-cells = <0>;
3335afac07SIthamar R. Adema
3435afac07SIthamar R. Adema		cpu@0 {
3535afac07SIthamar R. Adema			compatible = "arm,cortex-a8";
3635afac07SIthamar R. Adema			device_type = "cpu";
3735afac07SIthamar R. Adema			reg = <0x0>;
3835afac07SIthamar R. Adema
3935afac07SIthamar R. Adema			clocks = <&dpll1_ck>;
4035afac07SIthamar R. Adema			clock-names = "cpu";
4135afac07SIthamar R. Adema
4235afac07SIthamar R. Adema			clock-latency = <300000>; /* From omap-cpufreq driver */
4335afac07SIthamar R. Adema		};
4435afac07SIthamar R. Adema	};
4535afac07SIthamar R. Adema
4635afac07SIthamar R. Adema	pmu {
4735afac07SIthamar R. Adema		compatible = "arm,cortex-a8-pmu";
4835afac07SIthamar R. Adema		reg = <0x54000000 0x800000>;
4935afac07SIthamar R. Adema		interrupts = <3>;
5035afac07SIthamar R. Adema		ti,hwmods = "debugss";
5135afac07SIthamar R. Adema	};
5235afac07SIthamar R. Adema
5335afac07SIthamar R. Adema	/*
5435afac07SIthamar R. Adema	 * The soc node represents the soc top level view. It is used for IPs
5535afac07SIthamar R. Adema	 * that are not memory mapped in the MPU view or for the MPU itself.
5635afac07SIthamar R. Adema	 */
5735afac07SIthamar R. Adema	soc {
5835afac07SIthamar R. Adema		compatible = "ti,omap-infra";
5935afac07SIthamar R. Adema		mpu {
6035afac07SIthamar R. Adema			compatible = "ti,omap3-mpu";
6135afac07SIthamar R. Adema			ti,hwmods = "mpu";
6235afac07SIthamar R. Adema		};
6335afac07SIthamar R. Adema
6435afac07SIthamar R. Adema		iva: iva {
6535afac07SIthamar R. Adema			compatible = "ti,iva2.2";
6635afac07SIthamar R. Adema			ti,hwmods = "iva";
6735afac07SIthamar R. Adema
6835afac07SIthamar R. Adema			dsp {
6935afac07SIthamar R. Adema				compatible = "ti,omap3-c64";
7035afac07SIthamar R. Adema			};
7135afac07SIthamar R. Adema		};
7235afac07SIthamar R. Adema	};
7335afac07SIthamar R. Adema
7435afac07SIthamar R. Adema	/*
7535afac07SIthamar R. Adema	 * XXX: Use a flat representation of the OMAP3 interconnect.
7635afac07SIthamar R. Adema	 * The real OMAP interconnect network is quite complex.
7735afac07SIthamar R. Adema	 * Since it will not bring real advantage to represent that in DT for
7835afac07SIthamar R. Adema	 * the moment, just use a fake OCP bus entry to represent the whole bus
7935afac07SIthamar R. Adema	 * hierarchy.
8035afac07SIthamar R. Adema	 */
8135afac07SIthamar R. Adema	ocp {
8235afac07SIthamar R. Adema		compatible = "simple-bus";
8335afac07SIthamar R. Adema		reg = <0x68000000 0x10000>;
8435afac07SIthamar R. Adema		interrupts = <9 10>;
8535afac07SIthamar R. Adema		#address-cells = <1>;
8635afac07SIthamar R. Adema		#size-cells = <1>;
8735afac07SIthamar R. Adema		ranges;
8835afac07SIthamar R. Adema		ti,hwmods = "l3_main";
8935afac07SIthamar R. Adema
9035afac07SIthamar R. Adema		aes: aes@480c5000 {
9135afac07SIthamar R. Adema			compatible = "ti,omap3-aes";
9235afac07SIthamar R. Adema			ti,hwmods = "aes";
9335afac07SIthamar R. Adema			reg = <0x480c5000 0x50>;
9435afac07SIthamar R. Adema			interrupts = <0>;
9535afac07SIthamar R. Adema		};
9635afac07SIthamar R. Adema
9735afac07SIthamar R. Adema		prm: prm@48306000 {
9835afac07SIthamar R. Adema			compatible = "ti,omap3-prm";
9935afac07SIthamar R. Adema			reg = <0x48306000 0x4000>;
10035afac07SIthamar R. Adema			interrupts = <11>;
10135afac07SIthamar R. Adema
10235afac07SIthamar R. Adema			prm_clocks: clocks {
10335afac07SIthamar R. Adema				#address-cells = <1>;
10435afac07SIthamar R. Adema				#size-cells = <0>;
10535afac07SIthamar R. Adema			};
10635afac07SIthamar R. Adema
10735afac07SIthamar R. Adema			prm_clockdomains: clockdomains {
10835afac07SIthamar R. Adema			};
10935afac07SIthamar R. Adema		};
11035afac07SIthamar R. Adema
11135afac07SIthamar R. Adema		cm: cm@48004000 {
11235afac07SIthamar R. Adema			compatible = "ti,omap3-cm";
11335afac07SIthamar R. Adema			reg = <0x48004000 0x4000>;
11435afac07SIthamar R. Adema
11535afac07SIthamar R. Adema			cm_clocks: clocks {
11635afac07SIthamar R. Adema				#address-cells = <1>;
11735afac07SIthamar R. Adema				#size-cells = <0>;
11835afac07SIthamar R. Adema			};
11935afac07SIthamar R. Adema
12035afac07SIthamar R. Adema			cm_clockdomains: clockdomains {
12135afac07SIthamar R. Adema			};
12235afac07SIthamar R. Adema		};
12335afac07SIthamar R. Adema
12435afac07SIthamar R. Adema		scrm: scrm@48002000 {
12535afac07SIthamar R. Adema			compatible = "ti,omap3-scrm";
12635afac07SIthamar R. Adema			reg = <0x48002000 0x2000>;
12735afac07SIthamar R. Adema
12835afac07SIthamar R. Adema			scrm_clocks: clocks {
12935afac07SIthamar R. Adema				#address-cells = <1>;
13035afac07SIthamar R. Adema				#size-cells = <0>;
13135afac07SIthamar R. Adema			};
13235afac07SIthamar R. Adema
13335afac07SIthamar R. Adema			scrm_clockdomains: clockdomains {
13435afac07SIthamar R. Adema			};
13535afac07SIthamar R. Adema		};
13635afac07SIthamar R. Adema
13735afac07SIthamar R. Adema		counter32k: counter@48320000 {
13835afac07SIthamar R. Adema			compatible = "ti,omap-counter32k";
13935afac07SIthamar R. Adema			reg = <0x48320000 0x20>;
14035afac07SIthamar R. Adema			ti,hwmods = "counter_32k";
14135afac07SIthamar R. Adema		};
14235afac07SIthamar R. Adema
14335afac07SIthamar R. Adema		intc: interrupt-controller@48200000 {
14435afac07SIthamar R. Adema			compatible = "ti,omap3-intc";
14535afac07SIthamar R. Adema			interrupt-controller;
14635afac07SIthamar R. Adema			#interrupt-cells = <1>;
14735afac07SIthamar R. Adema			reg = <0x48200000 0x1000>;
14835afac07SIthamar R. Adema		};
14935afac07SIthamar R. Adema
15035afac07SIthamar R. Adema		sdma: dma-controller@48056000 {
15135afac07SIthamar R. Adema			compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
15235afac07SIthamar R. Adema			reg = <0x48056000 0x1000>;
15335afac07SIthamar R. Adema			interrupts = <12>,
15435afac07SIthamar R. Adema				     <13>,
15535afac07SIthamar R. Adema				     <14>,
15635afac07SIthamar R. Adema				     <15>;
15735afac07SIthamar R. Adema			#dma-cells = <1>;
15835afac07SIthamar R. Adema			#dma-channels = <32>;
15935afac07SIthamar R. Adema			#dma-requests = <96>;
16035afac07SIthamar R. Adema		};
16135afac07SIthamar R. Adema
16235afac07SIthamar R. Adema		omap3_pmx_core: pinmux@48002030 {
16335afac07SIthamar R. Adema			compatible = "ti,omap3-padconf", "pinctrl-single";
16435afac07SIthamar R. Adema			reg = <0x48002030 0x0238>;
16535afac07SIthamar R. Adema			#address-cells = <1>;
16635afac07SIthamar R. Adema			#size-cells = <0>;
16735afac07SIthamar R. Adema			#interrupt-cells = <1>;
16835afac07SIthamar R. Adema			interrupt-controller;
16935afac07SIthamar R. Adema			pinctrl-single,register-width = <16>;
17035afac07SIthamar R. Adema			pinctrl-single,function-mask = <0xff1f>;
17135afac07SIthamar R. Adema		};
17235afac07SIthamar R. Adema
17335afac07SIthamar R. Adema		omap3_pmx_wkup: pinmux@48002a00 {
17435afac07SIthamar R. Adema			compatible = "ti,omap3-padconf", "pinctrl-single";
17535afac07SIthamar R. Adema			reg = <0x48002a00 0x5c>;
17635afac07SIthamar R. Adema			#address-cells = <1>;
17735afac07SIthamar R. Adema			#size-cells = <0>;
17835afac07SIthamar R. Adema			#interrupt-cells = <1>;
17935afac07SIthamar R. Adema			interrupt-controller;
18035afac07SIthamar R. Adema			pinctrl-single,register-width = <16>;
18135afac07SIthamar R. Adema			pinctrl-single,function-mask = <0xff1f>;
18235afac07SIthamar R. Adema		};
18335afac07SIthamar R. Adema
18435afac07SIthamar R. Adema		omap3_scm_general: tisyscon@48002270 {
18535afac07SIthamar R. Adema			compatible = "syscon";
18635afac07SIthamar R. Adema			reg = <0x48002270 0x2f0>;
18735afac07SIthamar R. Adema		};
18835afac07SIthamar R. Adema
18935afac07SIthamar R. Adema		pbias_regulator: pbias_regulator {
19035afac07SIthamar R. Adema			compatible = "ti,pbias-omap";
19135afac07SIthamar R. Adema			reg = <0x2b0 0x4>;
19235afac07SIthamar R. Adema			syscon = <&omap3_scm_general>;
19335afac07SIthamar R. Adema			pbias_mmc_reg: pbias_mmc_omap2430 {
19435afac07SIthamar R. Adema				regulator-name = "pbias_mmc_omap2430";
19535afac07SIthamar R. Adema				regulator-min-microvolt = <1800000>;
19635afac07SIthamar R. Adema				regulator-max-microvolt = <3000000>;
19735afac07SIthamar R. Adema			};
19835afac07SIthamar R. Adema		};
19935afac07SIthamar R. Adema
20035afac07SIthamar R. Adema		gpio1: gpio@48310000 {
20135afac07SIthamar R. Adema			compatible = "ti,omap3-gpio";
20235afac07SIthamar R. Adema			reg = <0x48310000 0x200>;
20335afac07SIthamar R. Adema			interrupts = <29>;
20435afac07SIthamar R. Adema			ti,hwmods = "gpio1";
20535afac07SIthamar R. Adema			ti,gpio-always-on;
20635afac07SIthamar R. Adema			gpio-controller;
20735afac07SIthamar R. Adema			#gpio-cells = <2>;
20835afac07SIthamar R. Adema			interrupt-controller;
20935afac07SIthamar R. Adema			#interrupt-cells = <2>;
21035afac07SIthamar R. Adema		};
21135afac07SIthamar R. Adema
21235afac07SIthamar R. Adema		gpio2: gpio@49050000 {
21335afac07SIthamar R. Adema			compatible = "ti,omap3-gpio";
21435afac07SIthamar R. Adema			reg = <0x49050000 0x200>;
21535afac07SIthamar R. Adema			interrupts = <30>;
21635afac07SIthamar R. Adema			ti,hwmods = "gpio2";
21735afac07SIthamar R. Adema			gpio-controller;
21835afac07SIthamar R. Adema			#gpio-cells = <2>;
21935afac07SIthamar R. Adema			interrupt-controller;
22035afac07SIthamar R. Adema			#interrupt-cells = <2>;
22135afac07SIthamar R. Adema		};
22235afac07SIthamar R. Adema
22335afac07SIthamar R. Adema		gpio3: gpio@49052000 {
22435afac07SIthamar R. Adema			compatible = "ti,omap3-gpio";
22535afac07SIthamar R. Adema			reg = <0x49052000 0x200>;
22635afac07SIthamar R. Adema			interrupts = <31>;
22735afac07SIthamar R. Adema			ti,hwmods = "gpio3";
22835afac07SIthamar R. Adema			gpio-controller;
22935afac07SIthamar R. Adema			#gpio-cells = <2>;
23035afac07SIthamar R. Adema			interrupt-controller;
23135afac07SIthamar R. Adema			#interrupt-cells = <2>;
23235afac07SIthamar R. Adema		};
23335afac07SIthamar R. Adema
23435afac07SIthamar R. Adema		gpio4: gpio@49054000 {
23535afac07SIthamar R. Adema			compatible = "ti,omap3-gpio";
23635afac07SIthamar R. Adema			reg = <0x49054000 0x200>;
23735afac07SIthamar R. Adema			interrupts = <32>;
23835afac07SIthamar R. Adema			ti,hwmods = "gpio4";
23935afac07SIthamar R. Adema			gpio-controller;
24035afac07SIthamar R. Adema			#gpio-cells = <2>;
24135afac07SIthamar R. Adema			interrupt-controller;
24235afac07SIthamar R. Adema			#interrupt-cells = <2>;
24335afac07SIthamar R. Adema		};
24435afac07SIthamar R. Adema
24535afac07SIthamar R. Adema		gpio5: gpio@49056000 {
24635afac07SIthamar R. Adema			compatible = "ti,omap3-gpio";
24735afac07SIthamar R. Adema			reg = <0x49056000 0x200>;
24835afac07SIthamar R. Adema			interrupts = <33>;
24935afac07SIthamar R. Adema			ti,hwmods = "gpio5";
25035afac07SIthamar R. Adema			gpio-controller;
25135afac07SIthamar R. Adema			#gpio-cells = <2>;
25235afac07SIthamar R. Adema			interrupt-controller;
25335afac07SIthamar R. Adema			#interrupt-cells = <2>;
25435afac07SIthamar R. Adema		};
25535afac07SIthamar R. Adema
25635afac07SIthamar R. Adema		gpio6: gpio@49058000 {
25735afac07SIthamar R. Adema			compatible = "ti,omap3-gpio";
25835afac07SIthamar R. Adema			reg = <0x49058000 0x200>;
25935afac07SIthamar R. Adema			interrupts = <34>;
26035afac07SIthamar R. Adema			ti,hwmods = "gpio6";
26135afac07SIthamar R. Adema			gpio-controller;
26235afac07SIthamar R. Adema			#gpio-cells = <2>;
26335afac07SIthamar R. Adema			interrupt-controller;
26435afac07SIthamar R. Adema			#interrupt-cells = <2>;
26535afac07SIthamar R. Adema		};
26635afac07SIthamar R. Adema
26735afac07SIthamar R. Adema		uart1: serial@4806a000 {
26835afac07SIthamar R. Adema			compatible = "ti,omap3-uart";
26935afac07SIthamar R. Adema			reg = <0x4806a000 0x2000>;
27035afac07SIthamar R. Adema			interrupts-extended = <&intc 72>;
27135afac07SIthamar R. Adema			dmas = <&sdma 49 &sdma 50>;
27235afac07SIthamar R. Adema			dma-names = "tx", "rx";
27335afac07SIthamar R. Adema			ti,hwmods = "uart1";
27435afac07SIthamar R. Adema			clock-frequency = <48000000>;
27535afac07SIthamar R. Adema		};
27635afac07SIthamar R. Adema
27735afac07SIthamar R. Adema		uart2: serial@4806c000 {
27835afac07SIthamar R. Adema			compatible = "ti,omap3-uart";
27935afac07SIthamar R. Adema			reg = <0x4806c000 0x400>;
28035afac07SIthamar R. Adema			interrupts-extended = <&intc 73>;
28135afac07SIthamar R. Adema			dmas = <&sdma 51 &sdma 52>;
28235afac07SIthamar R. Adema			dma-names = "tx", "rx";
28335afac07SIthamar R. Adema			ti,hwmods = "uart2";
28435afac07SIthamar R. Adema			clock-frequency = <48000000>;
28535afac07SIthamar R. Adema		};
28635afac07SIthamar R. Adema
28735afac07SIthamar R. Adema		uart3: serial@49020000 {
28835afac07SIthamar R. Adema			compatible = "ti,omap3-uart";
28935afac07SIthamar R. Adema			reg = <0x49020000 0x400>;
29035afac07SIthamar R. Adema			interrupts-extended = <&intc 74>;
29135afac07SIthamar R. Adema			dmas = <&sdma 53 &sdma 54>;
29235afac07SIthamar R. Adema			dma-names = "tx", "rx";
29335afac07SIthamar R. Adema			ti,hwmods = "uart3";
29435afac07SIthamar R. Adema			clock-frequency = <48000000>;
29535afac07SIthamar R. Adema		};
29635afac07SIthamar R. Adema
29735afac07SIthamar R. Adema		i2c1: i2c@48070000 {
29835afac07SIthamar R. Adema			compatible = "ti,omap3-i2c";
29935afac07SIthamar R. Adema			reg = <0x48070000 0x80>;
30035afac07SIthamar R. Adema			interrupts = <56>;
30135afac07SIthamar R. Adema			dmas = <&sdma 27 &sdma 28>;
30235afac07SIthamar R. Adema			dma-names = "tx", "rx";
30335afac07SIthamar R. Adema			#address-cells = <1>;
30435afac07SIthamar R. Adema			#size-cells = <0>;
30535afac07SIthamar R. Adema			ti,hwmods = "i2c1";
30635afac07SIthamar R. Adema		};
30735afac07SIthamar R. Adema
30835afac07SIthamar R. Adema		i2c2: i2c@48072000 {
30935afac07SIthamar R. Adema			compatible = "ti,omap3-i2c";
31035afac07SIthamar R. Adema			reg = <0x48072000 0x80>;
31135afac07SIthamar R. Adema			interrupts = <57>;
31235afac07SIthamar R. Adema			dmas = <&sdma 29 &sdma 30>;
31335afac07SIthamar R. Adema			dma-names = "tx", "rx";
31435afac07SIthamar R. Adema			#address-cells = <1>;
31535afac07SIthamar R. Adema			#size-cells = <0>;
31635afac07SIthamar R. Adema			ti,hwmods = "i2c2";
31735afac07SIthamar R. Adema		};
31835afac07SIthamar R. Adema
31935afac07SIthamar R. Adema		i2c3: i2c@48060000 {
32035afac07SIthamar R. Adema			compatible = "ti,omap3-i2c";
32135afac07SIthamar R. Adema			reg = <0x48060000 0x80>;
32235afac07SIthamar R. Adema			interrupts = <61>;
32335afac07SIthamar R. Adema			dmas = <&sdma 25 &sdma 26>;
32435afac07SIthamar R. Adema			dma-names = "tx", "rx";
32535afac07SIthamar R. Adema			#address-cells = <1>;
32635afac07SIthamar R. Adema			#size-cells = <0>;
32735afac07SIthamar R. Adema			ti,hwmods = "i2c3";
32835afac07SIthamar R. Adema		};
32935afac07SIthamar R. Adema
33035afac07SIthamar R. Adema		mailbox: mailbox@48094000 {
33135afac07SIthamar R. Adema			compatible = "ti,omap3-mailbox";
33235afac07SIthamar R. Adema			ti,hwmods = "mailbox";
33335afac07SIthamar R. Adema			reg = <0x48094000 0x200>;
33435afac07SIthamar R. Adema			interrupts = <26>;
33535afac07SIthamar R. Adema			ti,mbox-num-users = <2>;
33635afac07SIthamar R. Adema			ti,mbox-num-fifos = <2>;
33735afac07SIthamar R. Adema			mbox_dsp: dsp {
33835afac07SIthamar R. Adema				ti,mbox-tx = <0 0 0>;
33935afac07SIthamar R. Adema				ti,mbox-rx = <1 0 0>;
34035afac07SIthamar R. Adema			};
34135afac07SIthamar R. Adema		};
34235afac07SIthamar R. Adema
34335afac07SIthamar R. Adema		mcspi1: spi@48098000 {
34435afac07SIthamar R. Adema			compatible = "ti,omap2-mcspi";
34535afac07SIthamar R. Adema			reg = <0x48098000 0x100>;
34635afac07SIthamar R. Adema			interrupts = <65>;
34735afac07SIthamar R. Adema			#address-cells = <1>;
34835afac07SIthamar R. Adema			#size-cells = <0>;
34935afac07SIthamar R. Adema			ti,hwmods = "mcspi1";
35035afac07SIthamar R. Adema			ti,spi-num-cs = <4>;
35135afac07SIthamar R. Adema			dmas = <&sdma 35>,
35235afac07SIthamar R. Adema			       <&sdma 36>,
35335afac07SIthamar R. Adema			       <&sdma 37>,
35435afac07SIthamar R. Adema			       <&sdma 38>,
35535afac07SIthamar R. Adema			       <&sdma 39>,
35635afac07SIthamar R. Adema			       <&sdma 40>,
35735afac07SIthamar R. Adema			       <&sdma 41>,
35835afac07SIthamar R. Adema			       <&sdma 42>;
35935afac07SIthamar R. Adema			dma-names = "tx0", "rx0", "tx1", "rx1",
36035afac07SIthamar R. Adema				    "tx2", "rx2", "tx3", "rx3";
36135afac07SIthamar R. Adema		};
36235afac07SIthamar R. Adema
36335afac07SIthamar R. Adema		mcspi2: spi@4809a000 {
36435afac07SIthamar R. Adema			compatible = "ti,omap2-mcspi";
36535afac07SIthamar R. Adema			reg = <0x4809a000 0x100>;
36635afac07SIthamar R. Adema			interrupts = <66>;
36735afac07SIthamar R. Adema			#address-cells = <1>;
36835afac07SIthamar R. Adema			#size-cells = <0>;
36935afac07SIthamar R. Adema			ti,hwmods = "mcspi2";
37035afac07SIthamar R. Adema			ti,spi-num-cs = <2>;
37135afac07SIthamar R. Adema			dmas = <&sdma 43>,
37235afac07SIthamar R. Adema			       <&sdma 44>,
37335afac07SIthamar R. Adema			       <&sdma 45>,
37435afac07SIthamar R. Adema			       <&sdma 46>;
37535afac07SIthamar R. Adema			dma-names = "tx0", "rx0", "tx1", "rx1";
37635afac07SIthamar R. Adema		};
37735afac07SIthamar R. Adema
37835afac07SIthamar R. Adema		mcspi3: spi@480b8000 {
37935afac07SIthamar R. Adema			compatible = "ti,omap2-mcspi";
38035afac07SIthamar R. Adema			reg = <0x480b8000 0x100>;
38135afac07SIthamar R. Adema			interrupts = <91>;
38235afac07SIthamar R. Adema			#address-cells = <1>;
38335afac07SIthamar R. Adema			#size-cells = <0>;
38435afac07SIthamar R. Adema			ti,hwmods = "mcspi3";
38535afac07SIthamar R. Adema			ti,spi-num-cs = <2>;
38635afac07SIthamar R. Adema			dmas = <&sdma 15>,
38735afac07SIthamar R. Adema			       <&sdma 16>,
38835afac07SIthamar R. Adema			       <&sdma 23>,
38935afac07SIthamar R. Adema			       <&sdma 24>;
39035afac07SIthamar R. Adema			dma-names = "tx0", "rx0", "tx1", "rx1";
39135afac07SIthamar R. Adema		};
39235afac07SIthamar R. Adema
39335afac07SIthamar R. Adema		mcspi4: spi@480ba000 {
39435afac07SIthamar R. Adema			compatible = "ti,omap2-mcspi";
39535afac07SIthamar R. Adema			reg = <0x480ba000 0x100>;
39635afac07SIthamar R. Adema			interrupts = <48>;
39735afac07SIthamar R. Adema			#address-cells = <1>;
39835afac07SIthamar R. Adema			#size-cells = <0>;
39935afac07SIthamar R. Adema			ti,hwmods = "mcspi4";
40035afac07SIthamar R. Adema			ti,spi-num-cs = <1>;
40135afac07SIthamar R. Adema			dmas = <&sdma 70>, <&sdma 71>;
40235afac07SIthamar R. Adema			dma-names = "tx0", "rx0";
40335afac07SIthamar R. Adema		};
40435afac07SIthamar R. Adema
40535afac07SIthamar R. Adema		hdqw1w: 1w@480b2000 {
40635afac07SIthamar R. Adema			compatible = "ti,omap3-1w";
40735afac07SIthamar R. Adema			reg = <0x480b2000 0x1000>;
40835afac07SIthamar R. Adema			interrupts = <58>;
40935afac07SIthamar R. Adema			ti,hwmods = "hdq1w";
41035afac07SIthamar R. Adema		};
41135afac07SIthamar R. Adema
41235afac07SIthamar R. Adema		mmc1: mmc@4809c000 {
41335afac07SIthamar R. Adema			compatible = "ti,omap3-hsmmc";
41435afac07SIthamar R. Adema			reg = <0x4809c000 0x200>;
41535afac07SIthamar R. Adema			interrupts = <83>;
41635afac07SIthamar R. Adema			ti,hwmods = "mmc1";
41735afac07SIthamar R. Adema			ti,dual-volt;
41835afac07SIthamar R. Adema			dmas = <&sdma 61>, <&sdma 62>;
41935afac07SIthamar R. Adema			dma-names = "tx", "rx";
42035afac07SIthamar R. Adema			pbias-supply = <&pbias_mmc_reg>;
42135afac07SIthamar R. Adema		};
42235afac07SIthamar R. Adema
42335afac07SIthamar R. Adema		mmc2: mmc@480b4000 {
42435afac07SIthamar R. Adema			compatible = "ti,omap3-hsmmc";
42535afac07SIthamar R. Adema			reg = <0x480b4000 0x200>;
42635afac07SIthamar R. Adema			interrupts = <86>;
42735afac07SIthamar R. Adema			ti,hwmods = "mmc2";
42835afac07SIthamar R. Adema			dmas = <&sdma 47>, <&sdma 48>;
42935afac07SIthamar R. Adema			dma-names = "tx", "rx";
43035afac07SIthamar R. Adema		};
43135afac07SIthamar R. Adema
43235afac07SIthamar R. Adema		mmc3: mmc@480ad000 {
43335afac07SIthamar R. Adema			compatible = "ti,omap3-hsmmc";
43435afac07SIthamar R. Adema			reg = <0x480ad000 0x200>;
43535afac07SIthamar R. Adema			interrupts = <94>;
43635afac07SIthamar R. Adema			ti,hwmods = "mmc3";
43735afac07SIthamar R. Adema			dmas = <&sdma 77>, <&sdma 78>;
43835afac07SIthamar R. Adema			dma-names = "tx", "rx";
43935afac07SIthamar R. Adema		};
44035afac07SIthamar R. Adema
44135afac07SIthamar R. Adema		mmu_isp: mmu@480bd400 {
44235afac07SIthamar R. Adema			compatible = "ti,omap2-iommu";
44335afac07SIthamar R. Adema			reg = <0x480bd400 0x80>;
44435afac07SIthamar R. Adema			interrupts = <24>;
44535afac07SIthamar R. Adema			ti,hwmods = "mmu_isp";
44635afac07SIthamar R. Adema			ti,#tlb-entries = <8>;
44735afac07SIthamar R. Adema		};
44835afac07SIthamar R. Adema
44935afac07SIthamar R. Adema		mmu_iva: mmu@5d000000 {
45035afac07SIthamar R. Adema			compatible = "ti,omap2-iommu";
45135afac07SIthamar R. Adema			reg = <0x5d000000 0x80>;
45235afac07SIthamar R. Adema			interrupts = <28>;
45335afac07SIthamar R. Adema			ti,hwmods = "mmu_iva";
45435afac07SIthamar R. Adema			status = "disabled";
45535afac07SIthamar R. Adema		};
45635afac07SIthamar R. Adema
45735afac07SIthamar R. Adema		wdt2: wdt@48314000 {
45835afac07SIthamar R. Adema			compatible = "ti,omap3-wdt";
45935afac07SIthamar R. Adema			reg = <0x48314000 0x80>;
46035afac07SIthamar R. Adema			ti,hwmods = "wd_timer2";
46135afac07SIthamar R. Adema		};
46235afac07SIthamar R. Adema
46335afac07SIthamar R. Adema		mcbsp1: mcbsp@48074000 {
46435afac07SIthamar R. Adema			compatible = "ti,omap3-mcbsp";
46535afac07SIthamar R. Adema			reg = <0x48074000 0xff>;
46635afac07SIthamar R. Adema			reg-names = "mpu";
46735afac07SIthamar R. Adema			interrupts = <16>, /* OCP compliant interrupt */
46835afac07SIthamar R. Adema				     <59>, /* TX interrupt */
46935afac07SIthamar R. Adema				     <60>; /* RX interrupt */
47035afac07SIthamar R. Adema			interrupt-names = "common", "tx", "rx";
47135afac07SIthamar R. Adema			ti,buffer-size = <128>;
47235afac07SIthamar R. Adema			ti,hwmods = "mcbsp1";
47335afac07SIthamar R. Adema			dmas = <&sdma 31>,
47435afac07SIthamar R. Adema			       <&sdma 32>;
47535afac07SIthamar R. Adema			dma-names = "tx", "rx";
47635afac07SIthamar R. Adema			status = "disabled";
47735afac07SIthamar R. Adema		};
47835afac07SIthamar R. Adema
47935afac07SIthamar R. Adema		mcbsp2: mcbsp@49022000 {
48035afac07SIthamar R. Adema			compatible = "ti,omap3-mcbsp";
48135afac07SIthamar R. Adema			reg = <0x49022000 0xff>,
48235afac07SIthamar R. Adema			      <0x49028000 0xff>;
48335afac07SIthamar R. Adema			reg-names = "mpu", "sidetone";
48435afac07SIthamar R. Adema			interrupts = <17>, /* OCP compliant interrupt */
48535afac07SIthamar R. Adema				     <62>, /* TX interrupt */
48635afac07SIthamar R. Adema				     <63>, /* RX interrupt */
48735afac07SIthamar R. Adema				     <4>;  /* Sidetone */
48835afac07SIthamar R. Adema			interrupt-names = "common", "tx", "rx", "sidetone";
48935afac07SIthamar R. Adema			ti,buffer-size = <1280>;
49035afac07SIthamar R. Adema			ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
49135afac07SIthamar R. Adema			dmas = <&sdma 33>,
49235afac07SIthamar R. Adema			       <&sdma 34>;
49335afac07SIthamar R. Adema			dma-names = "tx", "rx";
49435afac07SIthamar R. Adema			status = "disabled";
49535afac07SIthamar R. Adema		};
49635afac07SIthamar R. Adema
49735afac07SIthamar R. Adema		mcbsp3: mcbsp@49024000 {
49835afac07SIthamar R. Adema			compatible = "ti,omap3-mcbsp";
49935afac07SIthamar R. Adema			reg = <0x49024000 0xff>,
50035afac07SIthamar R. Adema			      <0x4902a000 0xff>;
50135afac07SIthamar R. Adema			reg-names = "mpu", "sidetone";
50235afac07SIthamar R. Adema			interrupts = <22>, /* OCP compliant interrupt */
50335afac07SIthamar R. Adema				     <89>, /* TX interrupt */
50435afac07SIthamar R. Adema				     <90>, /* RX interrupt */
50535afac07SIthamar R. Adema				     <5>;  /* Sidetone */
50635afac07SIthamar R. Adema			interrupt-names = "common", "tx", "rx", "sidetone";
50735afac07SIthamar R. Adema			ti,buffer-size = <128>;
50835afac07SIthamar R. Adema			ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
50935afac07SIthamar R. Adema			dmas = <&sdma 17>,
51035afac07SIthamar R. Adema			       <&sdma 18>;
51135afac07SIthamar R. Adema			dma-names = "tx", "rx";
51235afac07SIthamar R. Adema			status = "disabled";
51335afac07SIthamar R. Adema		};
51435afac07SIthamar R. Adema
51535afac07SIthamar R. Adema		mcbsp4: mcbsp@49026000 {
51635afac07SIthamar R. Adema			compatible = "ti,omap3-mcbsp";
51735afac07SIthamar R. Adema			reg = <0x49026000 0xff>;
51835afac07SIthamar R. Adema			reg-names = "mpu";
51935afac07SIthamar R. Adema			interrupts = <23>, /* OCP compliant interrupt */
52035afac07SIthamar R. Adema				     <54>, /* TX interrupt */
52135afac07SIthamar R. Adema				     <55>; /* RX interrupt */
52235afac07SIthamar R. Adema			interrupt-names = "common", "tx", "rx";
52335afac07SIthamar R. Adema			ti,buffer-size = <128>;
52435afac07SIthamar R. Adema			ti,hwmods = "mcbsp4";
52535afac07SIthamar R. Adema			dmas = <&sdma 19>,
52635afac07SIthamar R. Adema			       <&sdma 20>;
52735afac07SIthamar R. Adema			dma-names = "tx", "rx";
52835afac07SIthamar R. Adema			status = "disabled";
52935afac07SIthamar R. Adema		};
53035afac07SIthamar R. Adema
53135afac07SIthamar R. Adema		mcbsp5: mcbsp@48096000 {
53235afac07SIthamar R. Adema			compatible = "ti,omap3-mcbsp";
53335afac07SIthamar R. Adema			reg = <0x48096000 0xff>;
53435afac07SIthamar R. Adema			reg-names = "mpu";
53535afac07SIthamar R. Adema			interrupts = <27>, /* OCP compliant interrupt */
53635afac07SIthamar R. Adema				     <81>, /* TX interrupt */
53735afac07SIthamar R. Adema				     <82>; /* RX interrupt */
53835afac07SIthamar R. Adema			interrupt-names = "common", "tx", "rx";
53935afac07SIthamar R. Adema			ti,buffer-size = <128>;
54035afac07SIthamar R. Adema			ti,hwmods = "mcbsp5";
54135afac07SIthamar R. Adema			dmas = <&sdma 21>,
54235afac07SIthamar R. Adema			       <&sdma 22>;
54335afac07SIthamar R. Adema			dma-names = "tx", "rx";
54435afac07SIthamar R. Adema			status = "disabled";
54535afac07SIthamar R. Adema		};
54635afac07SIthamar R. Adema
54735afac07SIthamar R. Adema		sham: sham@480c3000 {
54835afac07SIthamar R. Adema			compatible = "ti,omap3-sham";
54935afac07SIthamar R. Adema			ti,hwmods = "sham";
55035afac07SIthamar R. Adema			reg = <0x480c3000 0x64>;
55135afac07SIthamar R. Adema			interrupts = <49>;
55235afac07SIthamar R. Adema		};
55335afac07SIthamar R. Adema
55435afac07SIthamar R. Adema		smartreflex_core: smartreflex@480cb000 {
55535afac07SIthamar R. Adema			compatible = "ti,omap3-smartreflex-core";
55635afac07SIthamar R. Adema			ti,hwmods = "smartreflex_core";
55735afac07SIthamar R. Adema			reg = <0x480cb000 0x400>;
55835afac07SIthamar R. Adema			interrupts = <19>;
55935afac07SIthamar R. Adema		};
56035afac07SIthamar R. Adema
56135afac07SIthamar R. Adema		smartreflex_mpu_iva: smartreflex@480c9000 {
56235afac07SIthamar R. Adema			compatible = "ti,omap3-smartreflex-iva";
56335afac07SIthamar R. Adema			ti,hwmods = "smartreflex_mpu_iva";
56435afac07SIthamar R. Adema			reg = <0x480c9000 0x400>;
56535afac07SIthamar R. Adema			interrupts = <18>;
56635afac07SIthamar R. Adema		};
56735afac07SIthamar R. Adema
56835afac07SIthamar R. Adema		timer1: timer@48318000 {
56935afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
57035afac07SIthamar R. Adema			reg = <0x48318000 0x400>;
57135afac07SIthamar R. Adema			interrupts = <37>;
57235afac07SIthamar R. Adema			ti,hwmods = "timer1";
57335afac07SIthamar R. Adema			ti,timer-alwon;
57435afac07SIthamar R. Adema		};
57535afac07SIthamar R. Adema
57635afac07SIthamar R. Adema		timer2: timer@49032000 {
57735afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
57835afac07SIthamar R. Adema			reg = <0x49032000 0x400>;
57935afac07SIthamar R. Adema			interrupts = <38>;
58035afac07SIthamar R. Adema			ti,hwmods = "timer2";
58135afac07SIthamar R. Adema		};
58235afac07SIthamar R. Adema
58335afac07SIthamar R. Adema		timer3: timer@49034000 {
58435afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
58535afac07SIthamar R. Adema			reg = <0x49034000 0x400>;
58635afac07SIthamar R. Adema			interrupts = <39>;
58735afac07SIthamar R. Adema			ti,hwmods = "timer3";
58835afac07SIthamar R. Adema		};
58935afac07SIthamar R. Adema
59035afac07SIthamar R. Adema		timer4: timer@49036000 {
59135afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
59235afac07SIthamar R. Adema			reg = <0x49036000 0x400>;
59335afac07SIthamar R. Adema			interrupts = <40>;
59435afac07SIthamar R. Adema			ti,hwmods = "timer4";
59535afac07SIthamar R. Adema		};
59635afac07SIthamar R. Adema
59735afac07SIthamar R. Adema		timer5: timer@49038000 {
59835afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
59935afac07SIthamar R. Adema			reg = <0x49038000 0x400>;
60035afac07SIthamar R. Adema			interrupts = <41>;
60135afac07SIthamar R. Adema			ti,hwmods = "timer5";
60235afac07SIthamar R. Adema			ti,timer-dsp;
60335afac07SIthamar R. Adema		};
60435afac07SIthamar R. Adema
60535afac07SIthamar R. Adema		timer6: timer@4903a000 {
60635afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
60735afac07SIthamar R. Adema			reg = <0x4903a000 0x400>;
60835afac07SIthamar R. Adema			interrupts = <42>;
60935afac07SIthamar R. Adema			ti,hwmods = "timer6";
61035afac07SIthamar R. Adema			ti,timer-dsp;
61135afac07SIthamar R. Adema		};
61235afac07SIthamar R. Adema
61335afac07SIthamar R. Adema		timer7: timer@4903c000 {
61435afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
61535afac07SIthamar R. Adema			reg = <0x4903c000 0x400>;
61635afac07SIthamar R. Adema			interrupts = <43>;
61735afac07SIthamar R. Adema			ti,hwmods = "timer7";
61835afac07SIthamar R. Adema			ti,timer-dsp;
61935afac07SIthamar R. Adema		};
62035afac07SIthamar R. Adema
62135afac07SIthamar R. Adema		timer8: timer@4903e000 {
62235afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
62335afac07SIthamar R. Adema			reg = <0x4903e000 0x400>;
62435afac07SIthamar R. Adema			interrupts = <44>;
62535afac07SIthamar R. Adema			ti,hwmods = "timer8";
62635afac07SIthamar R. Adema			ti,timer-pwm;
62735afac07SIthamar R. Adema			ti,timer-dsp;
62835afac07SIthamar R. Adema		};
62935afac07SIthamar R. Adema
63035afac07SIthamar R. Adema		timer9: timer@49040000 {
63135afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
63235afac07SIthamar R. Adema			reg = <0x49040000 0x400>;
63335afac07SIthamar R. Adema			interrupts = <45>;
63435afac07SIthamar R. Adema			ti,hwmods = "timer9";
63535afac07SIthamar R. Adema			ti,timer-pwm;
63635afac07SIthamar R. Adema		};
63735afac07SIthamar R. Adema
63835afac07SIthamar R. Adema		timer10: timer@48086000 {
63935afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
64035afac07SIthamar R. Adema			reg = <0x48086000 0x400>;
64135afac07SIthamar R. Adema			interrupts = <46>;
64235afac07SIthamar R. Adema			ti,hwmods = "timer10";
64335afac07SIthamar R. Adema			ti,timer-pwm;
64435afac07SIthamar R. Adema		};
64535afac07SIthamar R. Adema
64635afac07SIthamar R. Adema		timer11: timer@48088000 {
64735afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
64835afac07SIthamar R. Adema			reg = <0x48088000 0x400>;
64935afac07SIthamar R. Adema			interrupts = <47>;
65035afac07SIthamar R. Adema			ti,hwmods = "timer11";
65135afac07SIthamar R. Adema			ti,timer-pwm;
65235afac07SIthamar R. Adema		};
65335afac07SIthamar R. Adema
65435afac07SIthamar R. Adema		timer12: timer@48304000 {
65535afac07SIthamar R. Adema			compatible = "ti,omap3430-timer";
65635afac07SIthamar R. Adema			reg = <0x48304000 0x400>;
65735afac07SIthamar R. Adema			interrupts = <95>;
65835afac07SIthamar R. Adema			ti,hwmods = "timer12";
65935afac07SIthamar R. Adema			ti,timer-alwon;
66035afac07SIthamar R. Adema			ti,timer-secure;
66135afac07SIthamar R. Adema		};
66235afac07SIthamar R. Adema
66335afac07SIthamar R. Adema		usbhstll: usbhstll@48062000 {
66435afac07SIthamar R. Adema			compatible = "ti,usbhs-tll";
66535afac07SIthamar R. Adema			reg = <0x48062000 0x1000>;
66635afac07SIthamar R. Adema			interrupts = <78>;
66735afac07SIthamar R. Adema			ti,hwmods = "usb_tll_hs";
66835afac07SIthamar R. Adema		};
66935afac07SIthamar R. Adema
67035afac07SIthamar R. Adema		usbhshost: usbhshost@48064000 {
67135afac07SIthamar R. Adema			compatible = "ti,usbhs-host";
67235afac07SIthamar R. Adema			reg = <0x48064000 0x400>;
67335afac07SIthamar R. Adema			ti,hwmods = "usb_host_hs";
67435afac07SIthamar R. Adema			#address-cells = <1>;
67535afac07SIthamar R. Adema			#size-cells = <1>;
67635afac07SIthamar R. Adema			ranges;
67735afac07SIthamar R. Adema
67835afac07SIthamar R. Adema			usbhsohci: ohci@48064400 {
67935afac07SIthamar R. Adema				compatible = "ti,ohci-omap3";
68035afac07SIthamar R. Adema				reg = <0x48064400 0x400>;
68135afac07SIthamar R. Adema				interrupt-parent = <&intc>;
68235afac07SIthamar R. Adema				interrupts = <76>;
68335afac07SIthamar R. Adema			};
68435afac07SIthamar R. Adema
68535afac07SIthamar R. Adema			usbhsehci: ehci@48064800 {
68635afac07SIthamar R. Adema				compatible = "ti,ehci-omap";
68735afac07SIthamar R. Adema				reg = <0x48064800 0x400>;
68835afac07SIthamar R. Adema				interrupt-parent = <&intc>;
68935afac07SIthamar R. Adema				interrupts = <77>;
69035afac07SIthamar R. Adema			};
69135afac07SIthamar R. Adema		};
69235afac07SIthamar R. Adema
69335afac07SIthamar R. Adema		gpmc: gpmc@6e000000 {
69435afac07SIthamar R. Adema			compatible = "ti,omap3430-gpmc";
69535afac07SIthamar R. Adema			ti,hwmods = "gpmc";
69635afac07SIthamar R. Adema			reg = <0x6e000000 0x02d0>;
69735afac07SIthamar R. Adema			interrupts = <20>;
69835afac07SIthamar R. Adema			gpmc,num-cs = <8>;
69935afac07SIthamar R. Adema			gpmc,num-waitpins = <4>;
70035afac07SIthamar R. Adema			#address-cells = <2>;
70135afac07SIthamar R. Adema			#size-cells = <1>;
70235afac07SIthamar R. Adema		};
70335afac07SIthamar R. Adema
70435afac07SIthamar R. Adema		usb_otg_hs: usb_otg_hs@480ab000 {
70535afac07SIthamar R. Adema			compatible = "ti,omap3-musb";
70635afac07SIthamar R. Adema			reg = <0x480ab000 0x1000>;
70735afac07SIthamar R. Adema			interrupts = <92>, <93>;
70835afac07SIthamar R. Adema			interrupt-names = "mc", "dma";
70935afac07SIthamar R. Adema			ti,hwmods = "usb_otg_hs";
71035afac07SIthamar R. Adema			multipoint = <1>;
71135afac07SIthamar R. Adema			num-eps = <16>;
71235afac07SIthamar R. Adema			ram-bits = <12>;
71335afac07SIthamar R. Adema		};
71435afac07SIthamar R. Adema
71535afac07SIthamar R. Adema		dss: dss@48050000 {
71635afac07SIthamar R. Adema			compatible = "ti,omap3-dss";
71735afac07SIthamar R. Adema			reg = <0x48050000 0x200>;
71835afac07SIthamar R. Adema			status = "disabled";
71935afac07SIthamar R. Adema			ti,hwmods = "dss_core";
72035afac07SIthamar R. Adema			clocks = <&dss1_alwon_fck>;
72135afac07SIthamar R. Adema			clock-names = "fck";
72235afac07SIthamar R. Adema			#address-cells = <1>;
72335afac07SIthamar R. Adema			#size-cells = <1>;
72435afac07SIthamar R. Adema			ranges;
72535afac07SIthamar R. Adema
72635afac07SIthamar R. Adema			dispc@48050400 {
72735afac07SIthamar R. Adema				compatible = "ti,omap3-dispc";
72835afac07SIthamar R. Adema				reg = <0x48050400 0x400>;
72935afac07SIthamar R. Adema				interrupts = <25>;
73035afac07SIthamar R. Adema				ti,hwmods = "dss_dispc";
73135afac07SIthamar R. Adema				clocks = <&dss1_alwon_fck>;
73235afac07SIthamar R. Adema				clock-names = "fck";
73335afac07SIthamar R. Adema			};
73435afac07SIthamar R. Adema
73535afac07SIthamar R. Adema			dsi: encoder@4804fc00 {
73635afac07SIthamar R. Adema				compatible = "ti,omap3-dsi";
73735afac07SIthamar R. Adema				reg = <0x4804fc00 0x200>,
73835afac07SIthamar R. Adema				      <0x4804fe00 0x40>,
73935afac07SIthamar R. Adema				      <0x4804ff00 0x20>;
74035afac07SIthamar R. Adema				reg-names = "proto", "phy", "pll";
74135afac07SIthamar R. Adema				interrupts = <25>;
74235afac07SIthamar R. Adema				status = "disabled";
74335afac07SIthamar R. Adema				ti,hwmods = "dss_dsi1";
74435afac07SIthamar R. Adema				clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
74535afac07SIthamar R. Adema				clock-names = "fck", "sys_clk";
74635afac07SIthamar R. Adema			};
74735afac07SIthamar R. Adema
74835afac07SIthamar R. Adema			rfbi: encoder@48050800 {
74935afac07SIthamar R. Adema				compatible = "ti,omap3-rfbi";
75035afac07SIthamar R. Adema				reg = <0x48050800 0x100>;
75135afac07SIthamar R. Adema				status = "disabled";
75235afac07SIthamar R. Adema				ti,hwmods = "dss_rfbi";
75335afac07SIthamar R. Adema				clocks = <&dss1_alwon_fck>, <&dss_ick>;
75435afac07SIthamar R. Adema				clock-names = "fck", "ick";
75535afac07SIthamar R. Adema			};
75635afac07SIthamar R. Adema
75735afac07SIthamar R. Adema			venc: encoder@48050c00 {
75835afac07SIthamar R. Adema				compatible = "ti,omap3-venc";
75935afac07SIthamar R. Adema				reg = <0x48050c00 0x100>;
76035afac07SIthamar R. Adema				status = "disabled";
76135afac07SIthamar R. Adema				ti,hwmods = "dss_venc";
76235afac07SIthamar R. Adema				clocks = <&dss_tv_fck>;
76335afac07SIthamar R. Adema				clock-names = "fck";
76435afac07SIthamar R. Adema			};
76535afac07SIthamar R. Adema		};
76635afac07SIthamar R. Adema
76735afac07SIthamar R. Adema		ssi: ssi-controller@48058000 {
76835afac07SIthamar R. Adema			compatible = "ti,omap3-ssi";
76935afac07SIthamar R. Adema			ti,hwmods = "ssi";
77035afac07SIthamar R. Adema
77135afac07SIthamar R. Adema			status = "disabled";
77235afac07SIthamar R. Adema
77335afac07SIthamar R. Adema			reg = <0x48058000 0x1000>,
77435afac07SIthamar R. Adema			      <0x48059000 0x1000>;
77535afac07SIthamar R. Adema			reg-names = "sys",
77635afac07SIthamar R. Adema				    "gdd";
77735afac07SIthamar R. Adema
77835afac07SIthamar R. Adema			interrupts = <71>;
77935afac07SIthamar R. Adema			interrupt-names = "gdd_mpu";
78035afac07SIthamar R. Adema
78135afac07SIthamar R. Adema			#address-cells = <1>;
78235afac07SIthamar R. Adema			#size-cells = <1>;
78335afac07SIthamar R. Adema			ranges;
78435afac07SIthamar R. Adema
78535afac07SIthamar R. Adema			ssi_port1: ssi-port@4805a000 {
78635afac07SIthamar R. Adema				compatible = "ti,omap3-ssi-port";
78735afac07SIthamar R. Adema
78835afac07SIthamar R. Adema				reg = <0x4805a000 0x800>,
78935afac07SIthamar R. Adema				      <0x4805a800 0x800>;
79035afac07SIthamar R. Adema				reg-names = "tx",
79135afac07SIthamar R. Adema					    "rx";
79235afac07SIthamar R. Adema
79335afac07SIthamar R. Adema				interrupt-parent = <&intc>;
79435afac07SIthamar R. Adema				interrupts = <67>,
79535afac07SIthamar R. Adema					     <68>;
79635afac07SIthamar R. Adema			};
79735afac07SIthamar R. Adema
79835afac07SIthamar R. Adema			ssi_port2: ssi-port@4805b000 {
79935afac07SIthamar R. Adema				compatible = "ti,omap3-ssi-port";
80035afac07SIthamar R. Adema
80135afac07SIthamar R. Adema				reg = <0x4805b000 0x800>,
80235afac07SIthamar R. Adema				      <0x4805b800 0x800>;
80335afac07SIthamar R. Adema				reg-names = "tx",
80435afac07SIthamar R. Adema					    "rx";
80535afac07SIthamar R. Adema
80635afac07SIthamar R. Adema				interrupt-parent = <&intc>;
80735afac07SIthamar R. Adema				interrupts = <69>,
80835afac07SIthamar R. Adema					     <70>;
80935afac07SIthamar R. Adema			};
81035afac07SIthamar R. Adema		};
81135afac07SIthamar R. Adema	};
81235afac07SIthamar R. Adema};
81335afac07SIthamar R. Adema
81435afac07SIthamar R. Adema/include/ "omap3xxx-clocks.dtsi"
815