1/*-
2 * SPDX-License-Identifier: ISC
3 *
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 * $FreeBSD: releng/12.0/sys/dev/ath/ath_hal/ah_internal.h 326695 2017-12-08 15:57:29Z pfg $
20 */
21#ifndef _ATH_AH_INTERAL_H_
22#define _ATH_AH_INTERAL_H_
23/*
24 * Atheros Device Hardware Access Layer (HAL).
25 *
26 * Internal definitions.
27 */
28#define	AH_NULL	0
29#define	AH_MIN(a,b)	((a)<(b)?(a):(b))
30#define	AH_MAX(a,b)	((a)>(b)?(a):(b))
31
32#include <net80211/_ieee80211.h>
33#include <sys/queue.h>			/* XXX for reasons */
34
35#ifndef NBBY
36#define	NBBY	8			/* number of bits/byte */
37#endif
38
39#ifndef roundup
40#define	roundup(x, y)	((((x)+((y)-1))/(y))*(y))  /* to any y */
41#endif
42#ifndef howmany
43#define	howmany(x, y)	(((x)+((y)-1))/(y))
44#endif
45
46#ifndef offsetof
47#define	offsetof(type, field)	((size_t)(&((type *)0)->field))
48#endif
49
50typedef struct {
51	uint32_t	start;		/* first register */
52	uint32_t	end;		/* ending register or zero */
53} HAL_REGRANGE;
54
55typedef struct {
56	uint32_t	addr;		/* regiser address/offset */
57	uint32_t	value;		/* value to write */
58} HAL_REGWRITE;
59
60/*
61 * Transmit power scale factor.
62 *
63 * NB: This is not public because we want to discourage the use of
64 *     scaling; folks should use the tx power limit interface.
65 */
66typedef enum {
67	HAL_TP_SCALE_MAX	= 0,		/* no scaling (default) */
68	HAL_TP_SCALE_50		= 1,		/* 50% of max (-3 dBm) */
69	HAL_TP_SCALE_25		= 2,		/* 25% of max (-6 dBm) */
70	HAL_TP_SCALE_12		= 3,		/* 12% of max (-9 dBm) */
71	HAL_TP_SCALE_MIN	= 4,		/* min, but still on */
72} HAL_TP_SCALE;
73
74typedef enum {
75 	HAL_CAP_RADAR		= 0,		/* Radar capability */
76 	HAL_CAP_AR		= 1,		/* AR capability */
77} HAL_PHYDIAG_CAPS;
78
79/*
80 * Enable/disable strong signal fast diversity
81 */
82#define	HAL_CAP_STRONG_DIV		2
83
84/*
85 * Each chip or class of chips registers to offer support.
86 *
87 * Compiled-in versions will include a linker set to iterate through the
88 * linked in code.
89 *
90 * Modules will have to register HAL backends separately.
91 */
92struct ath_hal_chip {
93	const char	*name;
94	const char	*(*probe)(uint16_t vendorid, uint16_t devid);
95	struct ath_hal	*(*attach)(uint16_t devid, HAL_SOFTC,
96			    HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
97			    HAL_OPS_CONFIG *ah,
98			    HAL_STATUS *error);
99	TAILQ_ENTRY(ath_hal_chip) node;
100};
101#ifndef AH_CHIP
102#define	AH_CHIP(_name, _probe, _attach)				\
103struct ath_hal_chip _name##_chip = {				\
104	.name		= #_name,				\
105	.probe		= _probe,				\
106	.attach		= _attach,				\
107};								\
108OS_DATA_SET(ah_chips, _name##_chip)
109#endif
110
111/*
112 * Each RF backend registers to offer support; this is mostly
113 * used by multi-chip 5212 solutions.  Single-chip solutions
114 * have a fixed idea about which RF to use.
115 *
116 * Compiled in versions will include this linker set to iterate through
117 * the linked in code.
118 *
119 * Modules will have to register RF backends separately.
120 */
121struct ath_hal_rf {
122	const char	*name;
123	HAL_BOOL	(*probe)(struct ath_hal *ah);
124	HAL_BOOL	(*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
125	TAILQ_ENTRY(ath_hal_rf) node;
126};
127#ifndef AH_RF
128#define	AH_RF(_name, _probe, _attach)				\
129struct ath_hal_rf _name##_rf = {				\
130	.name		= __STRING(_name),			\
131	.probe		= _probe,				\
132	.attach		= _attach,				\
133};								\
134OS_DATA_SET(ah_rfs, _name##_rf)
135#endif
136
137struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
138
139/*
140 * Maximum number of internal channels.  Entries are per unique
141 * frequency so this might be need to be increased to handle all
142 * usage cases; typically no more than 32 are really needed but
143 * dynamically allocating the data structures is a bit painful
144 * right now.
145 */
146#ifndef AH_MAXCHAN
147#define	AH_MAXCHAN	128
148#endif
149
150#define	HAL_NF_CAL_HIST_LEN_FULL	5
151#define	HAL_NF_CAL_HIST_LEN_SMALL	1
152#define	HAL_NUM_NF_READINGS		6	/* 3 chains * (ctl + ext) */
153#define	HAL_NF_LOAD_DELAY		1000
154
155/*
156 * PER_CHAN doesn't work for now, as it looks like the device layer
157 * has to pre-populate the per-channel list with nominal values.
158 */
159//#define	ATH_NF_PER_CHAN		1
160
161typedef struct {
162    u_int8_t    curr_index;
163    int8_t      invalidNFcount; /* TO DO: REMOVE THIS! */
164    int16_t     priv_nf[HAL_NUM_NF_READINGS];
165} HAL_NFCAL_BASE;
166
167typedef struct {
168    HAL_NFCAL_BASE base;
169    int16_t     nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS];
170} HAL_NFCAL_HIST_FULL;
171
172typedef struct {
173    HAL_NFCAL_BASE base;
174    int16_t     nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS];
175} HAL_NFCAL_HIST_SMALL;
176
177#ifdef	ATH_NF_PER_CHAN
178typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST;
179#define	AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL)
180#else
181typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST;
182#define	AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist)
183#endif	/* ATH_NF_PER_CHAN */
184
185/*
186 * Internal per-channel state.  These are found
187 * using ic_devdata in the ieee80211_channel.
188 */
189typedef struct {
190	uint16_t	channel;	/* h/w frequency, NB: may be mapped */
191	uint8_t		privFlags;
192#define	CHANNEL_IQVALID		0x01	/* IQ calibration valid */
193#define	CHANNEL_ANI_INIT	0x02	/* ANI state initialized */
194#define	CHANNEL_ANI_SETUP	0x04	/* ANI state setup */
195#define	CHANNEL_MIMO_NF_VALID	0x04	/* Mimo NF values are valid */
196	uint8_t		calValid;	/* bitmask of cal types */
197	int8_t		iCoff;
198	int8_t		qCoff;
199	int16_t		rawNoiseFloor;
200	int16_t		noiseFloorAdjust;
201	int16_t		noiseFloorCtl[AH_MAX_CHAINS];
202	int16_t		noiseFloorExt[AH_MAX_CHAINS];
203	uint16_t	mainSpur;	/* cached spur value for this channel */
204
205	/*XXX TODO: make these part of privFlags */
206	uint8_t  paprd_done:1,           /* 1: PAPRD DONE, 0: PAPRD Cal not done */
207	       paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */
208	int		one_time_cals_done;
209	HAL_CHAN_NFCAL_HIST nf_cal_hist;
210} HAL_CHANNEL_INTERNAL;
211
212/* channel requires noise floor check */
213#define	CHANNEL_NFCREQUIRED	IEEE80211_CHAN_PRIV0
214
215/* all full-width channels */
216#define	IEEE80211_CHAN_ALLFULL \
217	(IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
218#define	IEEE80211_CHAN_ALLTURBOFULL \
219	(IEEE80211_CHAN_ALLTURBO - \
220	 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
221
222typedef struct {
223	uint32_t	halChanSpreadSupport 		: 1,
224			halSleepAfterBeaconBroken	: 1,
225			halCompressSupport		: 1,
226			halBurstSupport			: 1,
227			halFastFramesSupport		: 1,
228			halChapTuningSupport		: 1,
229			halTurboGSupport		: 1,
230			halTurboPrimeSupport		: 1,
231			halMicAesCcmSupport		: 1,
232			halMicCkipSupport		: 1,
233			halMicTkipSupport		: 1,
234			halTkipMicTxRxKeySupport	: 1,
235			halCipherAesCcmSupport		: 1,
236			halCipherCkipSupport		: 1,
237			halCipherTkipSupport		: 1,
238			halPSPollBroken			: 1,
239			halVEOLSupport			: 1,
240			halBssIdMaskSupport		: 1,
241			halMcastKeySrchSupport		: 1,
242			halTsfAddSupport		: 1,
243			halChanHalfRate			: 1,
244			halChanQuarterRate		: 1,
245			halHTSupport			: 1,
246			halHTSGI20Support		: 1,
247			halRfSilentSupport		: 1,
248			halHwPhyCounterSupport		: 1,
249			halWowSupport			: 1,
250			halWowMatchPatternExact		: 1,
251			halAutoSleepSupport		: 1,
252			halFastCCSupport		: 1,
253			halBtCoexSupport		: 1;
254	uint32_t	halRxStbcSupport		: 1,
255			halTxStbcSupport		: 1,
256			halGTTSupport			: 1,
257			halCSTSupport			: 1,
258			halRifsRxSupport		: 1,
259			halRifsTxSupport		: 1,
260			hal4AddrAggrSupport		: 1,
261			halExtChanDfsSupport		: 1,
262			halUseCombinedRadarRssi		: 1,
263			halForcePpmSupport		: 1,
264			halEnhancedPmSupport		: 1,
265			halEnhancedDfsSupport		: 1,
266			halMbssidAggrSupport		: 1,
267			halBssidMatchSupport		: 1,
268			hal4kbSplitTransSupport		: 1,
269			halHasRxSelfLinkedTail		: 1,
270			halSupportsFastClock5GHz	: 1,
271			halHasBBReadWar			: 1,
272			halSerialiseRegWar		: 1,
273			halMciSupport			: 1,
274			halRxTxAbortSupport		: 1,
275			halPaprdEnabled			: 1,
276			halHasUapsdSupport		: 1,
277			halWpsPushButtonSupport		: 1,
278			halBtCoexApsmWar		: 1,
279			halGenTimerSupport		: 1,
280			halLDPCSupport			: 1,
281			halHwBeaconProcSupport		: 1,
282			halEnhancedDmaSupport		: 1;
283	uint32_t	halIsrRacSupport		: 1,
284			halApmEnable			: 1,
285			halIntrMitigation		: 1,
286			hal49GhzSupport			: 1,
287			halAntDivCombSupport		: 1,
288			halAntDivCombSupportOrg		: 1,
289			halRadioRetentionSupport	: 1,
290			halSpectralScanSupport		: 1,
291			halRxUsingLnaMixing		: 1,
292			halRxDoMyBeacon			: 1,
293			halHwUapsdTrig			: 1;
294
295	uint32_t	halWirelessModes;
296	uint16_t	halTotalQueues;
297	uint16_t	halKeyCacheSize;
298	uint16_t	halLow5GhzChan, halHigh5GhzChan;
299	uint16_t	halLow2GhzChan, halHigh2GhzChan;
300	int		halTxTstampPrecision;
301	int		halRxTstampPrecision;
302	int		halRtsAggrLimit;
303	uint8_t		halTxChainMask;
304	uint8_t		halRxChainMask;
305	uint8_t		halNumGpioPins;
306	uint8_t		halNumAntCfg2GHz;
307	uint8_t		halNumAntCfg5GHz;
308	uint32_t	halIntrMask;
309	uint8_t		halTxStreams;
310	uint8_t		halRxStreams;
311	HAL_MFP_OPT_T	halMfpSupport;
312
313	/* AR9300 HAL porting capabilities */
314	int		hal_paprd_enabled;
315	int		hal_pcie_lcr_offset;
316	int		hal_pcie_lcr_extsync_en;
317	int		halNumTxMaps;
318	int		halTxDescLen;
319	int		halTxStatusLen;
320	int		halRxStatusLen;
321	int		halRxHpFifoDepth;
322	int		halRxLpFifoDepth;
323	uint32_t	halRegCap;		/* XXX needed? */
324	int		halNumMRRetries;
325	int		hal_ani_poll_interval;
326	int		hal_channel_switch_time_usec;
327} HAL_CAPABILITIES;
328
329struct regDomain;
330
331/*
332 * Definitions for ah_flags in ath_hal_private
333 */
334#define		AH_USE_EEPROM	0x1
335#define		AH_IS_HB63	0x2
336
337/*
338 * The ``private area'' follows immediately after the ``public area''
339 * in the data structure returned by ath_hal_attach.  Private data are
340 * used by device-independent code such as the regulatory domain support.
341 * In general, code within the HAL should never depend on data in the
342 * public area.  Instead any public data needed internally should be
343 * shadowed here.
344 *
345 * When declaring a device-specific ath_hal data structure this structure
346 * is assumed to at the front; e.g.
347 *
348 *	struct ath_hal_5212 {
349 *		struct ath_hal_private	ah_priv;
350 *		...
351 *	};
352 *
353 * It might be better to manage the method pointers in this structure
354 * using an indirect pointer to a read-only data structure but this would
355 * disallow class-style method overriding.
356 */
357struct ath_hal_private {
358	struct ath_hal	h;			/* public area */
359
360	/* NB: all methods go first to simplify initialization */
361	HAL_BOOL	(*ah_getChannelEdges)(struct ath_hal*,
362				uint16_t channelFlags,
363				uint16_t *lowChannel, uint16_t *highChannel);
364	u_int		(*ah_getWirelessModes)(struct ath_hal*);
365	HAL_BOOL	(*ah_eepromRead)(struct ath_hal *, u_int off,
366				uint16_t *data);
367	HAL_BOOL	(*ah_eepromWrite)(struct ath_hal *, u_int off,
368				uint16_t data);
369	HAL_BOOL	(*ah_getChipPowerLimits)(struct ath_hal *,
370				struct ieee80211_channel *);
371	int16_t		(*ah_getNfAdjust)(struct ath_hal *,
372				const HAL_CHANNEL_INTERNAL*);
373	void		(*ah_getNoiseFloor)(struct ath_hal *,
374				int16_t nfarray[]);
375
376	void		*ah_eeprom;		/* opaque EEPROM state */
377	uint16_t	ah_eeversion;		/* EEPROM version */
378	void		(*ah_eepromDetach)(struct ath_hal *);
379	HAL_STATUS	(*ah_eepromGet)(struct ath_hal *, int, void *);
380	HAL_STATUS	(*ah_eepromSet)(struct ath_hal *, int, int);
381	uint16_t	(*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
382	HAL_BOOL	(*ah_eepromDiag)(struct ath_hal *, int request,
383			    const void *args, uint32_t argsize,
384			    void **result, uint32_t *resultsize);
385
386	/*
387	 * Device revision information.
388	 */
389	uint16_t	ah_devid;		/* PCI device ID */
390	uint16_t	ah_subvendorid;		/* PCI subvendor ID */
391	uint32_t	ah_macVersion;		/* MAC version id */
392	uint16_t	ah_macRev;		/* MAC revision */
393	uint16_t	ah_phyRev;		/* PHY revision */
394	uint16_t	ah_analog5GhzRev;	/* 2GHz radio revision */
395	uint16_t	ah_analog2GhzRev;	/* 5GHz radio revision */
396	uint32_t	ah_flags;		/* misc flags */
397	uint8_t		ah_ispcie;		/* PCIE, special treatment */
398	uint8_t		ah_devType;		/* card type - CB, PCI, PCIe */
399
400	HAL_OPMODE	ah_opmode;		/* operating mode from reset */
401	const struct ieee80211_channel *ah_curchan;/* operating channel */
402	HAL_CAPABILITIES ah_caps;		/* device capabilities */
403	uint32_t	ah_diagreg;		/* user-specified AR_DIAG_SW */
404	int16_t		ah_powerLimit;		/* tx power cap */
405	uint16_t	ah_maxPowerLevel;	/* calculated max tx power */
406	u_int		ah_tpScale;		/* tx power scale factor */
407	u_int16_t	ah_extraTxPow;		/* low rates extra-txpower */
408	uint32_t	ah_11nCompat;		/* 11n compat controls */
409
410	/*
411	 * State for regulatory domain handling.
412	 */
413	HAL_REG_DOMAIN	ah_currentRD;		/* EEPROM regulatory domain */
414	HAL_REG_DOMAIN	ah_currentRDext;	/* EEPROM extended regdomain flags */
415	HAL_DFS_DOMAIN	ah_dfsDomain;		/* current DFS domain */
416	HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */
417	u_int		ah_nchan;		/* valid items in ah_channels */
418	const struct regDomain *ah_rd2GHz;	/* reg state for 2G band */
419	const struct regDomain *ah_rd5GHz;	/* reg state for 5G band */
420
421	uint8_t    	ah_coverageClass;   	/* coverage class */
422	/*
423	 * RF Silent handling; setup according to the EEPROM.
424	 */
425	uint16_t	ah_rfsilent;		/* GPIO pin + polarity */
426	HAL_BOOL	ah_rfkillEnabled;	/* enable/disable RfKill */
427	/*
428	 * Diagnostic support for discriminating HIUERR reports.
429	 */
430	uint32_t	ah_fatalState[6];	/* AR_ISR+shadow regs */
431	int		ah_rxornIsFatal;	/* how to treat HAL_INT_RXORN */
432
433	/* Only used if ATH_NF_PER_CHAN is defined */
434	HAL_NFCAL_HIST_FULL	nf_cal_hist;
435
436	/*
437	 * Channel survey history - current channel only.
438	 */
439	 HAL_CHANNEL_SURVEY	ah_chansurvey;	/* channel survey */
440};
441
442#define	AH_PRIVATE(_ah)	((struct ath_hal_private *)(_ah))
443
444#define	ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
445	AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
446#define	ath_hal_getWirelessModes(_ah) \
447	AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
448#define	ath_hal_eepromRead(_ah, _off, _data) \
449	AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
450#define	ath_hal_eepromWrite(_ah, _off, _data) \
451	AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
452#define	ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
453	(_ah)->ah_gpioCfgOutput(_ah, _gpio, _type)
454#define	ath_hal_gpioCfgInput(_ah, _gpio) \
455	(_ah)->ah_gpioCfgInput(_ah, _gpio)
456#define	ath_hal_gpioGet(_ah, _gpio) \
457	(_ah)->ah_gpioGet(_ah, _gpio)
458#define	ath_hal_gpioSet(_ah, _gpio, _val) \
459	(_ah)->ah_gpioSet(_ah, _gpio, _val)
460#define	ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
461	(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
462#define	ath_hal_getpowerlimits(_ah, _chan) \
463	AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan)
464#define ath_hal_getNfAdjust(_ah, _c) \
465	AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
466#define	ath_hal_getNoiseFloor(_ah, _nfArray) \
467	AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
468#define	ath_hal_configPCIE(_ah, _reset, _poweroff) \
469	(_ah)->ah_configPCIE(_ah, _reset, _poweroff)
470#define	ath_hal_disablePCIE(_ah) \
471	(_ah)->ah_disablePCIE(_ah)
472#define	ath_hal_setInterrupts(_ah, _mask) \
473	(_ah)->ah_setInterrupts(_ah, _mask)
474
475#define ath_hal_isrfkillenabled(_ah)  \
476    (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK)
477#define ath_hal_enable_rfkill(_ah, _v) \
478    ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL)
479#define ath_hal_hasrfkill_int(_ah)  \
480    (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK)
481
482#define	ath_hal_eepromDetach(_ah) do {				\
483	if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL)	\
484		AH_PRIVATE(_ah)->ah_eepromDetach(_ah);		\
485} while (0)
486#define	ath_hal_eepromGet(_ah, _param, _val) \
487	AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
488#define	ath_hal_eepromSet(_ah, _param, _val) \
489	AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
490#define	ath_hal_eepromGetFlag(_ah, _param) \
491	(AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
492#define ath_hal_getSpurChan(_ah, _ix, _is2G) \
493	AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
494#define	ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
495	AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize,  _r, _rsize)
496
497#ifndef _NET_IF_IEEE80211_H_
498/*
499 * Stuff that would naturally come from _ieee80211.h
500 */
501#define	IEEE80211_ADDR_LEN		6
502
503#define	IEEE80211_WEP_IVLEN			3	/* 24bit */
504#define	IEEE80211_WEP_KIDLEN			1	/* 1 octet */
505#define	IEEE80211_WEP_CRCLEN			4	/* CRC-32 */
506
507#define	IEEE80211_CRC_LEN			4
508
509#define	IEEE80211_MAX_LEN			(2300 + IEEE80211_CRC_LEN + \
510    (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
511#endif /* _NET_IF_IEEE80211_H_ */
512
513#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS	0x00000001
514
515#define INIT_AIFS		2
516#define INIT_CWMIN		15
517#define INIT_CWMIN_11B		31
518#define INIT_CWMAX		1023
519#define INIT_SH_RETRY		10
520#define INIT_LG_RETRY		10
521#define INIT_SSH_RETRY		32
522#define INIT_SLG_RETRY		32
523
524typedef struct {
525	uint32_t	tqi_ver;		/* HAL TXQ verson */
526	HAL_TX_QUEUE	tqi_type;		/* hw queue type*/
527	HAL_TX_QUEUE_SUBTYPE tqi_subtype;	/* queue subtype, if applicable */
528	HAL_TX_QUEUE_FLAGS tqi_qflags;		/* queue flags */
529	uint32_t	tqi_priority;
530	uint32_t	tqi_aifs;		/* aifs */
531	uint32_t	tqi_cwmin;		/* cwMin */
532	uint32_t	tqi_cwmax;		/* cwMax */
533	uint16_t	tqi_shretry;		/* frame short retry limit */
534	uint16_t	tqi_lgretry;		/* frame long retry limit */
535	uint32_t	tqi_cbrPeriod;
536	uint32_t	tqi_cbrOverflowLimit;
537	uint32_t	tqi_burstTime;
538	uint32_t	tqi_readyTime;
539	uint32_t	tqi_physCompBuf;
540	uint32_t	tqi_intFlags;		/* flags for internal use */
541} HAL_TX_QUEUE_INFO;
542
543extern	HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
544		HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
545extern	HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
546		HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
547
548#define	HAL_SPUR_VAL_MASK		0x3FFF
549#define	HAL_SPUR_CHAN_WIDTH		87
550#define	HAL_BIN_WIDTH_BASE_100HZ	3125
551#define	HAL_BIN_WIDTH_TURBO_100HZ	6250
552#define	HAL_MAX_BINS_ALLOWED		28
553
554#define	IS_CHAN_5GHZ(_c)	((_c)->channel > 4900)
555#define	IS_CHAN_2GHZ(_c)	(!IS_CHAN_5GHZ(_c))
556
557#define	IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
558
559/*
560 * Deduce if the host cpu has big- or litt-endian byte order.
561 */
562static __inline__ int
563isBigEndian(void)
564{
565	union {
566		int32_t i;
567		char c[4];
568	} u;
569	u.i = 1;
570	return (u.c[0] == 0);
571}
572
573/* unalligned little endian access */
574#define LE_READ_2(p)							\
575	((uint16_t)							\
576	 ((((const uint8_t *)(p))[0]    ) | (((const uint8_t *)(p))[1]<< 8)))
577#define LE_READ_4(p)							\
578	((uint32_t)							\
579	 ((((const uint8_t *)(p))[0]    ) | (((const uint8_t *)(p))[1]<< 8) |\
580	  (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
581
582/*
583 * Register manipulation macros that expect bit field defines
584 * to follow the convention that an _S suffix is appended for
585 * a shift count, while the field mask has no suffix.
586 */
587#define	SM(_v, _f)	(((_v) << _f##_S) & (_f))
588#define	MS(_v, _f)	(((_v) & (_f)) >> _f##_S)
589#define OS_REG_RMW(_a, _r, _set, _clr)    \
590	OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
591#define	OS_REG_RMW_FIELD(_a, _r, _f, _v) \
592	OS_REG_WRITE(_a, _r, \
593		(OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
594#define	OS_REG_SET_BIT(_a, _r, _f) \
595	OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
596#define	OS_REG_CLR_BIT(_a, _r, _f) \
597	OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
598#define OS_REG_IS_BIT_SET(_a, _r, _f) \
599	    ((OS_REG_READ(_a, _r) & (_f)) != 0)
600#define	OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \
601	    OS_REG_WRITE(_a, _r, \
602	    (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \
603	    (((_v) << _f##_S) & (_f<<_f##_S)))
604#define	OS_REG_READ_FIELD(_a, _r, _f) \
605	    (((OS_REG_READ(_a, _r) & _f) >> _f##_S))
606#define	OS_REG_READ_FIELD_ALT(_a, _r, _f) \
607	    ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f))
608
609/* Analog register writes may require a delay between each one (eg Merlin?) */
610#define	OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
611	do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \
612	    (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
613#define	OS_A_REG_WRITE(_a, _r, _v) \
614	do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0)
615
616/* wait for the register contents to have the specified value */
617extern	HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
618		uint32_t mask, uint32_t val);
619extern	HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg,
620		uint32_t mask, uint32_t val, uint32_t timeout);
621
622/* return the first n bits in val reversed */
623extern	uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
624
625/* printf interfaces */
626extern	void ath_hal_printf(struct ath_hal *, const char*, ...)
627		__printflike(2,3);
628extern	void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
629		__printflike(2, 0);
630extern	const char* ath_hal_ether_sprintf(const uint8_t *mac);
631
632/* allocate and free memory */
633extern	void *ath_hal_malloc(size_t);
634extern	void ath_hal_free(void *);
635
636/* common debugging interfaces */
637#ifdef AH_DEBUG
638#include "ah_debug.h"
639extern	int ath_hal_debug;	/* Global debug flags */
640
641/*
642 * The typecast is purely because some callers will pass in
643 * AH_NULL directly rather than using a NULL ath_hal pointer.
644 */
645#define	HALDEBUG(_ah, __m, ...) \
646	do {							\
647		if ((__m) == HAL_DEBUG_UNMASKABLE ||		\
648		    ath_hal_debug & (__m) ||			\
649		    ((_ah) != NULL &&				\
650		      ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) {	\
651			DO_HALDEBUG((_ah), (__m), __VA_ARGS__);	\
652		}						\
653	} while(0);
654
655extern	void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
656	__printflike(3,4);
657#else
658#define HALDEBUG(_ah, __m, ...)
659#endif /* AH_DEBUG */
660
661/*
662 * Register logging definitions shared with ardecode.
663 */
664#include "ah_decode.h"
665
666/*
667 * Common assertion interface.  Note: it is a bad idea to generate
668 * an assertion failure for any recoverable event.  Instead catch
669 * the violation and, if possible, fix it up or recover from it; either
670 * with an error return value or a diagnostic messages.  System software
671 * does not panic unless the situation is hopeless.
672 */
673#ifdef AH_ASSERT
674extern	void ath_hal_assert_failed(const char* filename,
675		int lineno, const char* msg);
676
677#define	HALASSERT(_x) do {					\
678	if (!(_x)) {						\
679		ath_hal_assert_failed(__FILE__, __LINE__, #_x);	\
680	}							\
681} while (0)
682#else
683#define	HALASSERT(_x)
684#endif /* AH_ASSERT */
685
686/*
687 * Regulatory domain support.
688 */
689
690/*
691 * Return the max allowed antenna gain and apply any regulatory
692 * domain specific changes.
693 */
694u_int	ath_hal_getantennareduction(struct ath_hal *ah,
695	    const struct ieee80211_channel *chan, u_int twiceGain);
696
697/*
698 * Return the test group for the specific channel based on
699 * the current regulatory setup.
700 */
701u_int	ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *);
702
703/*
704 * Map a public channel definition to the corresponding
705 * internal data structure.  This implicitly specifies
706 * whether or not the specified channel is ok to use
707 * based on the current regulatory domain constraints.
708 */
709#ifndef AH_DEBUG
710static OS_INLINE HAL_CHANNEL_INTERNAL *
711ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
712{
713	HAL_CHANNEL_INTERNAL *cc;
714
715	HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);
716	cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];
717	HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c));
718	return cc;
719}
720#else
721/* NB: non-inline version that checks state */
722HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
723		const struct ieee80211_channel *);
724#endif /* AH_DEBUG */
725
726/*
727 * Return the h/w frequency for a channel.  This may be
728 * different from ic_freq if this is a GSM device that
729 * takes 2.4GHz frequencies and down-converts them.
730 */
731static OS_INLINE uint16_t
732ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
733{
734	return ath_hal_checkchannel(ah, c)->channel;
735}
736
737/*
738 * Generic get/set capability support.  Each chip overrides
739 * this routine to support chip-specific capabilities.
740 */
741extern	HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
742		HAL_CAPABILITY_TYPE type, uint32_t capability,
743		uint32_t *result);
744extern	HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
745		HAL_CAPABILITY_TYPE type, uint32_t capability,
746		uint32_t setting, HAL_STATUS *status);
747
748/* The diagnostic codes used to be internally defined here -adrian */
749#include "ah_diagcodes.h"
750
751/*
752 * The AR5416 and later HALs have MAC and baseband hang checking.
753 */
754typedef struct {
755	uint32_t hang_reg_offset;
756	uint32_t hang_val;
757	uint32_t hang_mask;
758	uint32_t hang_offset;
759} hal_hw_hang_check_t;
760
761typedef struct {
762	uint32_t dma_dbg_3;
763	uint32_t dma_dbg_4;
764	uint32_t dma_dbg_5;
765	uint32_t dma_dbg_6;
766} mac_dbg_regs_t;
767
768typedef enum {
769	dcu_chain_state		= 0x1,
770	dcu_complete_state	= 0x2,
771	qcu_state		= 0x4,
772	qcu_fsp_ok		= 0x8,
773	qcu_fsp_state		= 0x10,
774	qcu_stitch_state	= 0x20,
775	qcu_fetch_state		= 0x40,
776	qcu_complete_state	= 0x80
777} hal_mac_hangs_t;
778
779typedef struct {
780	int states;
781	uint8_t dcu_chain_state;
782	uint8_t dcu_complete_state;
783	uint8_t qcu_state;
784	uint8_t qcu_fsp_ok;
785	uint8_t qcu_fsp_state;
786	uint8_t qcu_stitch_state;
787	uint8_t qcu_fetch_state;
788	uint8_t qcu_complete_state;
789} hal_mac_hang_check_t;
790
791enum {
792    HAL_BB_HANG_DFS		= 0x0001,
793    HAL_BB_HANG_RIFS		= 0x0002,
794    HAL_BB_HANG_RX_CLEAR	= 0x0004,
795    HAL_BB_HANG_UNKNOWN		= 0x0080,
796
797    HAL_MAC_HANG_SIG1		= 0x0100,
798    HAL_MAC_HANG_SIG2		= 0x0200,
799    HAL_MAC_HANG_UNKNOWN	= 0x8000,
800
801    HAL_BB_HANGS = HAL_BB_HANG_DFS
802		 | HAL_BB_HANG_RIFS
803		 | HAL_BB_HANG_RX_CLEAR
804		 | HAL_BB_HANG_UNKNOWN,
805    HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
806		 | HAL_MAC_HANG_SIG2
807		 | HAL_MAC_HANG_UNKNOWN,
808};
809
810/* Merge these with above */
811typedef enum hal_hw_hangs {
812    HAL_DFS_BB_HANG_WAR          = 0x1,
813    HAL_RIFS_BB_HANG_WAR         = 0x2,
814    HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4,
815    HAL_MAC_HANG_WAR             = 0x8,
816    HAL_PHYRESTART_CLR_WAR       = 0x10,
817    HAL_MAC_HANG_DETECTED        = 0x40000000,
818    HAL_BB_HANG_DETECTED         = 0x80000000
819} hal_hw_hangs_t;
820
821/*
822 * Device revision information.
823 */
824typedef struct {
825	uint16_t	ah_devid;		/* PCI device ID */
826	uint16_t	ah_subvendorid;		/* PCI subvendor ID */
827	uint32_t	ah_macVersion;		/* MAC version id */
828	uint16_t	ah_macRev;		/* MAC revision */
829	uint16_t	ah_phyRev;		/* PHY revision */
830	uint16_t	ah_analog5GhzRev;	/* 2GHz radio revision */
831	uint16_t	ah_analog2GhzRev;	/* 5GHz radio revision */
832} HAL_REVS;
833
834/*
835 * Argument payload for HAL_DIAG_SETKEY.
836 */
837typedef struct {
838	HAL_KEYVAL	dk_keyval;
839	uint16_t	dk_keyix;	/* key index */
840	uint8_t		dk_mac[IEEE80211_ADDR_LEN];
841	int		dk_xor;		/* XOR key data */
842} HAL_DIAG_KEYVAL;
843
844/*
845 * Argument payload for HAL_DIAG_EEWRITE.
846 */
847typedef struct {
848	uint16_t	ee_off;		/* eeprom offset */
849	uint16_t	ee_data;	/* write data */
850} HAL_DIAG_EEVAL;
851
852
853typedef struct {
854	u_int offset;		/* reg offset */
855	uint32_t val;		/* reg value  */
856} HAL_DIAG_REGVAL;
857
858/*
859 * 11n compatibility tweaks.
860 */
861#define	HAL_DIAG_11N_SERVICES	0x00000003
862#define	HAL_DIAG_11N_SERVICES_S	0
863#define	HAL_DIAG_11N_TXSTOMP	0x0000000c
864#define	HAL_DIAG_11N_TXSTOMP_S	2
865
866typedef struct {
867	int		maxNoiseImmunityLevel;	/* [0..4] */
868	int		totalSizeDesired[5];
869	int		coarseHigh[5];
870	int		coarseLow[5];
871	int		firpwr[5];
872
873	int		maxSpurImmunityLevel;	/* [0..7] */
874	int		cycPwrThr1[8];
875
876	int		maxFirstepLevel;	/* [0..2] */
877	int		firstep[3];
878
879	uint32_t	ofdmTrigHigh;
880	uint32_t	ofdmTrigLow;
881	int32_t		cckTrigHigh;
882	int32_t		cckTrigLow;
883	int32_t		rssiThrLow;
884	int32_t		rssiThrHigh;
885
886	int		period;			/* update listen period */
887} HAL_ANI_PARAMS;
888
889extern	HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
890			const void *args, uint32_t argsize,
891			void **result, uint32_t *resultsize);
892
893/*
894 * Setup a h/w rate table for use.
895 */
896extern	void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
897
898/*
899 * Common routine for implementing getChanNoise api.
900 */
901int16_t	ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *);
902
903/*
904 * Initialization support.
905 */
906typedef struct {
907	const uint32_t	*data;
908	int		rows, cols;
909} HAL_INI_ARRAY;
910
911#define	HAL_INI_INIT(_ia, _data, _cols) do {			\
912	(_ia)->data = (const uint32_t *)(_data);		\
913	(_ia)->rows = sizeof(_data) / sizeof((_data)[0]);	\
914	(_ia)->cols = (_cols);					\
915} while (0)
916#define	HAL_INI_VAL(_ia, _r, _c) \
917	((_ia)->data[((_r)*(_ia)->cols) + (_c)])
918
919/*
920 * OS_DELAY() does a PIO READ on the PCI bus which allows
921 * other cards' DMA reads to complete in the middle of our reset.
922 */
923#define DMA_YIELD(x) do {		\
924	if ((++(x) % 64) == 0)		\
925		OS_DELAY(1);		\
926} while (0)
927
928#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do {             	\
929	int r;								\
930	for (r = 0; r < N(regArray); r++) {				\
931		OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]);	\
932		DMA_YIELD(regWr);					\
933	}								\
934} while (0)
935
936#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do {		\
937	int r;								\
938	for (r = 0; r < N(regArray); r++) {				\
939		OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]);	\
940		DMA_YIELD(regWr);					\
941	}								\
942} while (0)
943
944extern	int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
945		int col, int regWr);
946extern	void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
947		int col);
948extern	int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
949		const uint32_t data[], int regWr);
950
951#define	CCK_SIFS_TIME		10
952#define	CCK_PREAMBLE_BITS	144
953#define	CCK_PLCP_BITS		48
954
955#define	OFDM_SIFS_TIME		16
956#define	OFDM_PREAMBLE_TIME	20
957#define	OFDM_PLCP_BITS		22
958#define	OFDM_SYMBOL_TIME	4
959
960#define	OFDM_HALF_SIFS_TIME	32
961#define	OFDM_HALF_PREAMBLE_TIME	40
962#define	OFDM_HALF_PLCP_BITS	22
963#define	OFDM_HALF_SYMBOL_TIME	8
964
965#define	OFDM_QUARTER_SIFS_TIME 		64
966#define	OFDM_QUARTER_PREAMBLE_TIME	80
967#define	OFDM_QUARTER_PLCP_BITS		22
968#define	OFDM_QUARTER_SYMBOL_TIME	16
969
970#define	TURBO_SIFS_TIME		8
971#define	TURBO_PREAMBLE_TIME	14
972#define	TURBO_PLCP_BITS		22
973#define	TURBO_SYMBOL_TIME	4
974
975#define	WLAN_CTRL_FRAME_SIZE	(2+2+6+4)	/* ACK+FCS */
976
977/* Generic EEPROM board value functions */
978extern	HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList,
979	uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
980extern	HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
981	uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts,
982	uint8_t *pRetVpdList);
983extern	int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft,
984	uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
985
986/* Whether 5ghz fast clock is needed */
987/*
988 * The chipset (Merlin, AR9300/later) should set the capability flag below;
989 * this flag simply says that the hardware can do it, not that the EEPROM
990 * says it can.
991 *
992 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock
993 *   if the relevant eeprom flag is set.
994 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock
995 *   by default.
996 */
997#define	IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \
998	(IEEE80211_IS_CHAN_5GHZ(_c) && \
999	 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \
1000	ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G))
1001
1002/*
1003 * Fetch the maximum regulatory domain power for the given channel
1004 * in 1/2dBm steps.
1005 */
1006static inline int
1007ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp,
1008    const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan)
1009{
1010	struct ath_hal *ah = &ahp->h;
1011
1012	if (! chan) {
1013		ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__);
1014		return (0);
1015	}
1016	return (chan->ic_maxpower);
1017}
1018
1019/*
1020 * Get the maximum antenna gain allowed, in 1/2dBm steps.
1021 */
1022static inline int
1023ath_hal_getantennaallowed(struct ath_hal *ah,
1024    const struct ieee80211_channel *chan)
1025{
1026
1027	if (! chan)
1028		return (0);
1029
1030	return (chan->ic_maxantgain);
1031}
1032
1033/*
1034 * Map the given 2GHz channel to an IEEE number.
1035 */
1036extern	int ath_hal_mhz2ieee_2ghz(struct ath_hal *, int freq);
1037
1038/*
1039 * Clear the channel survey data.
1040 */
1041extern	void ath_hal_survey_clear(struct ath_hal *ah);
1042
1043/*
1044 * Add a sample to the channel survey data.
1045 */
1046extern	void ath_hal_survey_add_sample(struct ath_hal *ah,
1047	    HAL_SURVEY_SAMPLE *hs);
1048
1049/*
1050 * Chip registration - for modules.
1051 */
1052extern	int ath_hal_add_chip(struct ath_hal_chip *ahc);
1053extern	int ath_hal_remove_chip(struct ath_hal_chip *ahc);
1054extern	int ath_hal_add_rf(struct ath_hal_rf *arf);
1055extern	int ath_hal_remove_rf(struct ath_hal_rf *arf);
1056
1057#endif /* _ATH_AH_INTERAL_H_ */
1058