1cafbf72dSSiarzhuk Zharski/*-
2eababbb4SAugustin Cavalier * SPDX-License-Identifier: BSD-4-Clause
3eababbb4SAugustin Cavalier *
4cafbf72dSSiarzhuk Zharski * Copyright (c) 2004
5cafbf72dSSiarzhuk Zharski *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
6cafbf72dSSiarzhuk Zharski *
7cafbf72dSSiarzhuk Zharski * Redistribution and use in source and binary forms, with or without
8cafbf72dSSiarzhuk Zharski * modification, are permitted provided that the following conditions
9cafbf72dSSiarzhuk Zharski * are met:
10cafbf72dSSiarzhuk Zharski * 1. Redistributions of source code must retain the above copyright
11cafbf72dSSiarzhuk Zharski *    notice, this list of conditions and the following disclaimer.
12cafbf72dSSiarzhuk Zharski * 2. Redistributions in binary form must reproduce the above copyright
13cafbf72dSSiarzhuk Zharski *    notice, this list of conditions and the following disclaimer in the
14cafbf72dSSiarzhuk Zharski *    documentation and/or other materials provided with the distribution.
15cafbf72dSSiarzhuk Zharski * 3. All advertising materials mentioning features or use of this software
16cafbf72dSSiarzhuk Zharski *    must display the following acknowledgement:
17cafbf72dSSiarzhuk Zharski *	This product includes software developed by Bill Paul.
18cafbf72dSSiarzhuk Zharski * 4. Neither the name of the author nor the names of any co-contributors
19cafbf72dSSiarzhuk Zharski *    may be used to endorse or promote products derived from this software
20cafbf72dSSiarzhuk Zharski *    without specific prior written permission.
21cafbf72dSSiarzhuk Zharski *
22cafbf72dSSiarzhuk Zharski * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23cafbf72dSSiarzhuk Zharski * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24cafbf72dSSiarzhuk Zharski * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25cafbf72dSSiarzhuk Zharski * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26cafbf72dSSiarzhuk Zharski * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27cafbf72dSSiarzhuk Zharski * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28cafbf72dSSiarzhuk Zharski * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29cafbf72dSSiarzhuk Zharski * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30cafbf72dSSiarzhuk Zharski * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31cafbf72dSSiarzhuk Zharski * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32cafbf72dSSiarzhuk Zharski * THE POSSIBILITY OF SUCH DAMAGE.
33cafbf72dSSiarzhuk Zharski */
34cafbf72dSSiarzhuk Zharski
35cafbf72dSSiarzhuk Zharski#include <sys/cdefs.h>
36eababbb4SAugustin Cavalier__FBSDID("$FreeBSD: releng/12.0/sys/dev/mii/ciphy.c 325966 2017-11-18 14:26:50Z pfg $");
37cafbf72dSSiarzhuk Zharski
38cafbf72dSSiarzhuk Zharski/*
39b1312c5cSSiarzhuk Zharski * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY.
40cafbf72dSSiarzhuk Zharski */
41cafbf72dSSiarzhuk Zharski
42cafbf72dSSiarzhuk Zharski#include <sys/param.h>
43cafbf72dSSiarzhuk Zharski#include <sys/systm.h>
44cafbf72dSSiarzhuk Zharski#include <sys/kernel.h>
45cafbf72dSSiarzhuk Zharski#include <sys/module.h>
46cafbf72dSSiarzhuk Zharski#include <sys/socket.h>
47cafbf72dSSiarzhuk Zharski#include <sys/bus.h>
48cafbf72dSSiarzhuk Zharski
49cafbf72dSSiarzhuk Zharski#include <net/if.h>
50cafbf72dSSiarzhuk Zharski#include <net/if_arp.h>
51cafbf72dSSiarzhuk Zharski#include <net/if_media.h>
52cafbf72dSSiarzhuk Zharski
53cafbf72dSSiarzhuk Zharski#include <dev/mii/mii.h>
54cafbf72dSSiarzhuk Zharski#include <dev/mii/miivar.h>
55cafbf72dSSiarzhuk Zharski#include "miidevs.h"
56cafbf72dSSiarzhuk Zharski
57cafbf72dSSiarzhuk Zharski#include <dev/mii/ciphyreg.h>
58cafbf72dSSiarzhuk Zharski
59cafbf72dSSiarzhuk Zharski#include "miibus_if.h"
60cafbf72dSSiarzhuk Zharski
61cafbf72dSSiarzhuk Zharski#include <machine/bus.h>
62b1312c5cSSiarzhuk Zharski
63cafbf72dSSiarzhuk Zharskistatic int ciphy_probe(device_t);
64cafbf72dSSiarzhuk Zharskistatic int ciphy_attach(device_t);
65cafbf72dSSiarzhuk Zharski
66cafbf72dSSiarzhuk Zharskistatic device_method_t ciphy_methods[] = {
67cafbf72dSSiarzhuk Zharski	/* device interface */
68cafbf72dSSiarzhuk Zharski	DEVMETHOD(device_probe,		ciphy_probe),
69cafbf72dSSiarzhuk Zharski	DEVMETHOD(device_attach,	ciphy_attach),
70cafbf72dSSiarzhuk Zharski	DEVMETHOD(device_detach,	mii_phy_detach),
71cafbf72dSSiarzhuk Zharski	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
72648db733SJérôme Duval	DEVMETHOD_END
73cafbf72dSSiarzhuk Zharski};
74cafbf72dSSiarzhuk Zharski
75cafbf72dSSiarzhuk Zharskistatic devclass_t ciphy_devclass;
76cafbf72dSSiarzhuk Zharski
77cafbf72dSSiarzhuk Zharskistatic driver_t ciphy_driver = {
78cafbf72dSSiarzhuk Zharski	"ciphy",
79cafbf72dSSiarzhuk Zharski	ciphy_methods,
80cafbf72dSSiarzhuk Zharski	sizeof(struct mii_softc)
81cafbf72dSSiarzhuk Zharski};
82cafbf72dSSiarzhuk Zharski
83cafbf72dSSiarzhuk ZharskiDRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
84cafbf72dSSiarzhuk Zharski
85cafbf72dSSiarzhuk Zharskistatic int	ciphy_service(struct mii_softc *, struct mii_data *, int);
86cafbf72dSSiarzhuk Zharskistatic void	ciphy_status(struct mii_softc *);
87cafbf72dSSiarzhuk Zharskistatic void	ciphy_reset(struct mii_softc *);
88cafbf72dSSiarzhuk Zharskistatic void	ciphy_fixup(struct mii_softc *);
89cafbf72dSSiarzhuk Zharski
90b1312c5cSSiarzhuk Zharskistatic const struct mii_phydesc ciphys[] = {
918060e778SJérôme Duval	MII_PHY_DESC(xxCICADA, CS8201),
928060e778SJérôme Duval	MII_PHY_DESC(xxCICADA, CS8201A),
938060e778SJérôme Duval	MII_PHY_DESC(xxCICADA, CS8201B),
948060e778SJérôme Duval	MII_PHY_DESC(xxCICADA, CS8204),
958060e778SJérôme Duval	MII_PHY_DESC(xxCICADA, VSC8211),
96853a76f1SJérôme Duval	MII_PHY_DESC(xxCICADA, VSC8221),
978060e778SJérôme Duval	MII_PHY_DESC(xxCICADA, CS8244),
988060e778SJérôme Duval	MII_PHY_DESC(xxVITESSE, VSC8601),
99853a76f1SJérôme Duval	MII_PHY_DESC(xxVITESSE, VSC8641),
100b1312c5cSSiarzhuk Zharski	MII_PHY_END
101b1312c5cSSiarzhuk Zharski};
102b1312c5cSSiarzhuk Zharski
1038060e778SJérôme Duvalstatic const struct mii_phy_funcs ciphy_funcs = {
1048060e778SJérôme Duval	ciphy_service,
1058060e778SJérôme Duval	ciphy_status,
1068060e778SJérôme Duval	ciphy_reset
1078060e778SJérôme Duval};
1088060e778SJérôme Duval
109cafbf72dSSiarzhuk Zharskistatic int
110b1312c5cSSiarzhuk Zharskiciphy_probe(device_t dev)
111cafbf72dSSiarzhuk Zharski{
112cafbf72dSSiarzhuk Zharski
113b1312c5cSSiarzhuk Zharski	return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
114cafbf72dSSiarzhuk Zharski}
115cafbf72dSSiarzhuk Zharski
116cafbf72dSSiarzhuk Zharskistatic int
117b1312c5cSSiarzhuk Zharskiciphy_attach(device_t dev)
118cafbf72dSSiarzhuk Zharski{
1198060e778SJérôme Duval
1208060e778SJérôme Duval	mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
1218060e778SJérôme Duval	    &ciphy_funcs, 1);
122b1312c5cSSiarzhuk Zharski	return (0);
123cafbf72dSSiarzhuk Zharski}
124cafbf72dSSiarzhuk Zharski
125cafbf72dSSiarzhuk Zharskistatic int
126b1312c5cSSiarzhuk Zharskiciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
127cafbf72dSSiarzhuk Zharski{
128cafbf72dSSiarzhuk Zharski	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
129cafbf72dSSiarzhuk Zharski	int reg, speed, gig;
130cafbf72dSSiarzhuk Zharski
131cafbf72dSSiarzhuk Zharski	switch (cmd) {
132cafbf72dSSiarzhuk Zharski	case MII_POLLSTAT:
133cafbf72dSSiarzhuk Zharski		break;
134cafbf72dSSiarzhuk Zharski
135cafbf72dSSiarzhuk Zharski	case MII_MEDIACHG:
136cafbf72dSSiarzhuk Zharski		ciphy_fixup(sc);	/* XXX hardware bug work-around */
137cafbf72dSSiarzhuk Zharski
138cafbf72dSSiarzhuk Zharski		switch (IFM_SUBTYPE(ife->ifm_media)) {
139cafbf72dSSiarzhuk Zharski		case IFM_AUTO:
140cafbf72dSSiarzhuk Zharski#ifdef foo
141cafbf72dSSiarzhuk Zharski			/*
142cafbf72dSSiarzhuk Zharski			 * If we're already in auto mode, just return.
143cafbf72dSSiarzhuk Zharski			 */
144cafbf72dSSiarzhuk Zharski			if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
145cafbf72dSSiarzhuk Zharski				return (0);
146cafbf72dSSiarzhuk Zharski#endif
147b1312c5cSSiarzhuk Zharski			(void)mii_phy_auto(sc);
148cafbf72dSSiarzhuk Zharski			break;
149cafbf72dSSiarzhuk Zharski		case IFM_1000_T:
150cafbf72dSSiarzhuk Zharski			speed = CIPHY_S1000;
151cafbf72dSSiarzhuk Zharski			goto setit;
152cafbf72dSSiarzhuk Zharski		case IFM_100_TX:
153cafbf72dSSiarzhuk Zharski			speed = CIPHY_S100;
154cafbf72dSSiarzhuk Zharski			goto setit;
155cafbf72dSSiarzhuk Zharski		case IFM_10_T:
156cafbf72dSSiarzhuk Zharski			speed = CIPHY_S10;
157cafbf72dSSiarzhuk Zharskisetit:
1588060e778SJérôme Duval			if ((ife->ifm_media & IFM_FDX) != 0) {
159cafbf72dSSiarzhuk Zharski				speed |= CIPHY_BMCR_FDX;
160cafbf72dSSiarzhuk Zharski				gig = CIPHY_1000CTL_AFD;
1618060e778SJérôme Duval			} else
162cafbf72dSSiarzhuk Zharski				gig = CIPHY_1000CTL_AHD;
163cafbf72dSSiarzhuk Zharski
1648060e778SJérôme Duval			if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
1658060e778SJérôme Duval				gig |= CIPHY_1000CTL_MSE;
1668060e778SJérôme Duval				if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
1678060e778SJérôme Duval					gig |= CIPHY_1000CTL_MSC;
1688060e778SJérôme Duval				speed |=
1698060e778SJérôme Duval				    CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG;
1708060e778SJérôme Duval			} else
1718060e778SJérôme Duval				gig = 0;
1728060e778SJérôme Duval			PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
173cafbf72dSSiarzhuk Zharski			PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
174cafbf72dSSiarzhuk Zharski			PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
175cafbf72dSSiarzhuk Zharski			break;
176cafbf72dSSiarzhuk Zharski		case IFM_NONE:
177b1312c5cSSiarzhuk Zharski			PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
178cafbf72dSSiarzhuk Zharski			break;
179cafbf72dSSiarzhuk Zharski		default:
180cafbf72dSSiarzhuk Zharski			return (EINVAL);
181cafbf72dSSiarzhuk Zharski		}
182cafbf72dSSiarzhuk Zharski		break;
183cafbf72dSSiarzhuk Zharski
184cafbf72dSSiarzhuk Zharski	case MII_TICK:
185cafbf72dSSiarzhuk Zharski		/*
186cafbf72dSSiarzhuk Zharski		 * Only used for autonegotiation.
187cafbf72dSSiarzhuk Zharski		 */
188cafbf72dSSiarzhuk Zharski		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
189cafbf72dSSiarzhuk Zharski			break;
190cafbf72dSSiarzhuk Zharski
191cafbf72dSSiarzhuk Zharski		/*
192cafbf72dSSiarzhuk Zharski		 * Check to see if we have link.  If we do, we don't
193cafbf72dSSiarzhuk Zharski		 * need to restart the autonegotiation process.  Read
194cafbf72dSSiarzhuk Zharski		 * the BMSR twice in case it's latched.
195cafbf72dSSiarzhuk Zharski		 */
196cafbf72dSSiarzhuk Zharski		reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
197cafbf72dSSiarzhuk Zharski		if (reg & BMSR_LINK)
198cafbf72dSSiarzhuk Zharski			break;
199cafbf72dSSiarzhuk Zharski
200b1312c5cSSiarzhuk Zharski		/* Announce link loss right after it happens. */
201b1312c5cSSiarzhuk Zharski		if (++sc->mii_ticks == 0)
202b1312c5cSSiarzhuk Zharski			break;
203cafbf72dSSiarzhuk Zharski		/*
204b1312c5cSSiarzhuk Zharski		 * Only retry autonegotiation every mii_anegticks seconds.
205cafbf72dSSiarzhuk Zharski		 */
206b1312c5cSSiarzhuk Zharski		if (sc->mii_ticks <= sc->mii_anegticks)
207cafbf72dSSiarzhuk Zharski			break;
208b1312c5cSSiarzhuk Zharski
209cafbf72dSSiarzhuk Zharski		sc->mii_ticks = 0;
210cafbf72dSSiarzhuk Zharski		mii_phy_auto(sc);
211b1312c5cSSiarzhuk Zharski		break;
212cafbf72dSSiarzhuk Zharski	}
213cafbf72dSSiarzhuk Zharski
214cafbf72dSSiarzhuk Zharski	/* Update the media status. */
2158060e778SJérôme Duval	PHY_STATUS(sc);
216cafbf72dSSiarzhuk Zharski
217cafbf72dSSiarzhuk Zharski	/*
218cafbf72dSSiarzhuk Zharski	 * Callback if something changed. Note that we need to poke
219cafbf72dSSiarzhuk Zharski	 * apply fixups for certain PHY revs.
220cafbf72dSSiarzhuk Zharski	 */
221b1312c5cSSiarzhuk Zharski	if (sc->mii_media_active != mii->mii_media_active ||
222cafbf72dSSiarzhuk Zharski	    sc->mii_media_status != mii->mii_media_status ||
223cafbf72dSSiarzhuk Zharski	    cmd == MII_MEDIACHG) {
224cafbf72dSSiarzhuk Zharski		ciphy_fixup(sc);
225cafbf72dSSiarzhuk Zharski	}
226cafbf72dSSiarzhuk Zharski	mii_phy_update(sc, cmd);
227cafbf72dSSiarzhuk Zharski	return (0);
228cafbf72dSSiarzhuk Zharski}
229cafbf72dSSiarzhuk Zharski
230cafbf72dSSiarzhuk Zharskistatic void
231b1312c5cSSiarzhuk Zharskiciphy_status(struct mii_softc *sc)
232cafbf72dSSiarzhuk Zharski{
233cafbf72dSSiarzhuk Zharski	struct mii_data *mii = sc->mii_pdata;
234cafbf72dSSiarzhuk Zharski	int bmsr, bmcr;
235cafbf72dSSiarzhuk Zharski
236cafbf72dSSiarzhuk Zharski	mii->mii_media_status = IFM_AVALID;
237cafbf72dSSiarzhuk Zharski	mii->mii_media_active = IFM_ETHER;
238cafbf72dSSiarzhuk Zharski
239cafbf72dSSiarzhuk Zharski	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
240cafbf72dSSiarzhuk Zharski
241cafbf72dSSiarzhuk Zharski	if (bmsr & BMSR_LINK)
242cafbf72dSSiarzhuk Zharski		mii->mii_media_status |= IFM_ACTIVE;
243cafbf72dSSiarzhuk Zharski
244cafbf72dSSiarzhuk Zharski	bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
245cafbf72dSSiarzhuk Zharski
246cafbf72dSSiarzhuk Zharski	if (bmcr & CIPHY_BMCR_LOOP)
247cafbf72dSSiarzhuk Zharski		mii->mii_media_active |= IFM_LOOP;
248cafbf72dSSiarzhuk Zharski
249cafbf72dSSiarzhuk Zharski	if (bmcr & CIPHY_BMCR_AUTOEN) {
250cafbf72dSSiarzhuk Zharski		if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
251cafbf72dSSiarzhuk Zharski			/* Erg, still trying, I guess... */
252cafbf72dSSiarzhuk Zharski			mii->mii_media_active |= IFM_NONE;
253cafbf72dSSiarzhuk Zharski			return;
254cafbf72dSSiarzhuk Zharski		}
255cafbf72dSSiarzhuk Zharski	}
256cafbf72dSSiarzhuk Zharski
257cafbf72dSSiarzhuk Zharski	bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
258cafbf72dSSiarzhuk Zharski	switch (bmsr & CIPHY_AUXCSR_SPEED) {
259cafbf72dSSiarzhuk Zharski	case CIPHY_SPEED10:
260cafbf72dSSiarzhuk Zharski		mii->mii_media_active |= IFM_10_T;
261cafbf72dSSiarzhuk Zharski		break;
262cafbf72dSSiarzhuk Zharski	case CIPHY_SPEED100:
263cafbf72dSSiarzhuk Zharski		mii->mii_media_active |= IFM_100_TX;
264cafbf72dSSiarzhuk Zharski		break;
265cafbf72dSSiarzhuk Zharski	case CIPHY_SPEED1000:
266cafbf72dSSiarzhuk Zharski		mii->mii_media_active |= IFM_1000_T;
267cafbf72dSSiarzhuk Zharski		break;
268cafbf72dSSiarzhuk Zharski	default:
269cafbf72dSSiarzhuk Zharski		device_printf(sc->mii_dev, "unknown PHY speed %x\n",
270cafbf72dSSiarzhuk Zharski		    bmsr & CIPHY_AUXCSR_SPEED);
271cafbf72dSSiarzhuk Zharski		break;
272cafbf72dSSiarzhuk Zharski	}
273cafbf72dSSiarzhuk Zharski
274cafbf72dSSiarzhuk Zharski	if (bmsr & CIPHY_AUXCSR_FDX)
2758060e778SJérôme Duval		mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
276b1312c5cSSiarzhuk Zharski	else
277b1312c5cSSiarzhuk Zharski		mii->mii_media_active |= IFM_HDX;
278cafbf72dSSiarzhuk Zharski
279b1312c5cSSiarzhuk Zharski	if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
280b1312c5cSSiarzhuk Zharski	   (PHY_READ(sc, CIPHY_MII_1000STS) & CIPHY_1000STS_MSR) != 0)
281b1312c5cSSiarzhuk Zharski		mii->mii_media_active |= IFM_ETH_MASTER;
282cafbf72dSSiarzhuk Zharski}
283cafbf72dSSiarzhuk Zharski
284cafbf72dSSiarzhuk Zharskistatic void
285cafbf72dSSiarzhuk Zharskiciphy_reset(struct mii_softc *sc)
286cafbf72dSSiarzhuk Zharski{
287b1312c5cSSiarzhuk Zharski
288cafbf72dSSiarzhuk Zharski	mii_phy_reset(sc);
289cafbf72dSSiarzhuk Zharski	DELAY(1000);
290cafbf72dSSiarzhuk Zharski}
291cafbf72dSSiarzhuk Zharski
292cafbf72dSSiarzhuk Zharski#define PHY_SETBIT(x, y, z) \
293cafbf72dSSiarzhuk Zharski	PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
294cafbf72dSSiarzhuk Zharski#define PHY_CLRBIT(x, y, z) \
295cafbf72dSSiarzhuk Zharski	PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
296cafbf72dSSiarzhuk Zharski
297cafbf72dSSiarzhuk Zharskistatic void
298cafbf72dSSiarzhuk Zharskiciphy_fixup(struct mii_softc *sc)
299cafbf72dSSiarzhuk Zharski{
300cafbf72dSSiarzhuk Zharski	uint16_t		model;
301cafbf72dSSiarzhuk Zharski	uint16_t		status, speed;
302b1312c5cSSiarzhuk Zharski	uint16_t		val;
303cafbf72dSSiarzhuk Zharski
304cafbf72dSSiarzhuk Zharski	model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
305cafbf72dSSiarzhuk Zharski	status = PHY_READ(sc, CIPHY_MII_AUXCSR);
306cafbf72dSSiarzhuk Zharski	speed = status & CIPHY_AUXCSR_SPEED;
307cafbf72dSSiarzhuk Zharski
308853a76f1SJérôme Duval	if (mii_phy_mac_match(sc, "nfe")) {
309b1312c5cSSiarzhuk Zharski		/* need to set for 2.5V RGMII for NVIDIA adapters */
310b1312c5cSSiarzhuk Zharski		val = PHY_READ(sc, CIPHY_MII_ECTL1);
311b1312c5cSSiarzhuk Zharski		val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
312b1312c5cSSiarzhuk Zharski		val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
313b1312c5cSSiarzhuk Zharski		PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
314b1312c5cSSiarzhuk Zharski		/* From Linux. */
315b1312c5cSSiarzhuk Zharski		val = PHY_READ(sc, CIPHY_MII_AUXCSR);
316b1312c5cSSiarzhuk Zharski		val |= CIPHY_AUXCSR_MDPPS;
317b1312c5cSSiarzhuk Zharski		PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
318b1312c5cSSiarzhuk Zharski		val = PHY_READ(sc, CIPHY_MII_10BTCSR);
319b1312c5cSSiarzhuk Zharski		val |= CIPHY_10BTCSR_ECHO;
320b1312c5cSSiarzhuk Zharski		PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
321b1312c5cSSiarzhuk Zharski	}
322b1312c5cSSiarzhuk Zharski
323cafbf72dSSiarzhuk Zharski	switch (model) {
3248060e778SJérôme Duval	case MII_MODEL_xxCICADA_CS8204:
3258060e778SJérôme Duval	case MII_MODEL_xxCICADA_CS8201:
326cafbf72dSSiarzhuk Zharski
327cafbf72dSSiarzhuk Zharski		/* Turn off "aux mode" (whatever that means) */
328cafbf72dSSiarzhuk Zharski		PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
329cafbf72dSSiarzhuk Zharski
330cafbf72dSSiarzhuk Zharski		/*
331cafbf72dSSiarzhuk Zharski		 * Work around speed polling bug in VT3119/VT3216
332cafbf72dSSiarzhuk Zharski		 * when using MII in full duplex mode.
333cafbf72dSSiarzhuk Zharski		 */
334cafbf72dSSiarzhuk Zharski		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
335cafbf72dSSiarzhuk Zharski		    (status & CIPHY_AUXCSR_FDX)) {
336cafbf72dSSiarzhuk Zharski			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
337cafbf72dSSiarzhuk Zharski		} else {
338cafbf72dSSiarzhuk Zharski			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
339cafbf72dSSiarzhuk Zharski		}
340cafbf72dSSiarzhuk Zharski
341cafbf72dSSiarzhuk Zharski		/* Enable link/activity LED blink. */
342cafbf72dSSiarzhuk Zharski		PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
343cafbf72dSSiarzhuk Zharski
344cafbf72dSSiarzhuk Zharski		break;
345cafbf72dSSiarzhuk Zharski
3468060e778SJérôme Duval	case MII_MODEL_xxCICADA_CS8201A:
3478060e778SJérôme Duval	case MII_MODEL_xxCICADA_CS8201B:
348cafbf72dSSiarzhuk Zharski
349cafbf72dSSiarzhuk Zharski		/*
350cafbf72dSSiarzhuk Zharski		 * Work around speed polling bug in VT3119/VT3216
351cafbf72dSSiarzhuk Zharski		 * when using MII in full duplex mode.
352cafbf72dSSiarzhuk Zharski		 */
353cafbf72dSSiarzhuk Zharski		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
354cafbf72dSSiarzhuk Zharski		    (status & CIPHY_AUXCSR_FDX)) {
355cafbf72dSSiarzhuk Zharski			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
356cafbf72dSSiarzhuk Zharski		} else {
357cafbf72dSSiarzhuk Zharski			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
358cafbf72dSSiarzhuk Zharski		}
359cafbf72dSSiarzhuk Zharski
360b1312c5cSSiarzhuk Zharski		break;
3618060e778SJérôme Duval	case MII_MODEL_xxCICADA_VSC8211:
362853a76f1SJérôme Duval	case MII_MODEL_xxCICADA_VSC8221:
3638060e778SJérôme Duval	case MII_MODEL_xxCICADA_CS8244:
3648060e778SJérôme Duval	case MII_MODEL_xxVITESSE_VSC8601:
365853a76f1SJérôme Duval	case MII_MODEL_xxVITESSE_VSC8641:
366cafbf72dSSiarzhuk Zharski		break;
367cafbf72dSSiarzhuk Zharski	default:
368cafbf72dSSiarzhuk Zharski		device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
369cafbf72dSSiarzhuk Zharski		    model);
370cafbf72dSSiarzhuk Zharski		break;
371cafbf72dSSiarzhuk Zharski	}
372cafbf72dSSiarzhuk Zharski}
373