1ab64e1faSKarsten Heimrich/******************************************************************************
267a0cb89SAugustin Cavalier  SPDX-License-Identifier: BSD-3-Clause
3ab64e1faSKarsten Heimrich
4b3fb200fSJérôme Duval  Copyright (c) 2001-2015, Intel Corporation
5ab64e1faSKarsten Heimrich  All rights reserved.
6ab64e1faSKarsten Heimrich
7ab64e1faSKarsten Heimrich  Redistribution and use in source and binary forms, with or without
8ab64e1faSKarsten Heimrich  modification, are permitted provided that the following conditions are met:
9ab64e1faSKarsten Heimrich
10ab64e1faSKarsten Heimrich   1. Redistributions of source code must retain the above copyright notice,
11ab64e1faSKarsten Heimrich      this list of conditions and the following disclaimer.
12ab64e1faSKarsten Heimrich
13ab64e1faSKarsten Heimrich   2. Redistributions in binary form must reproduce the above copyright
14ab64e1faSKarsten Heimrich      notice, this list of conditions and the following disclaimer in the
15ab64e1faSKarsten Heimrich      documentation and/or other materials provided with the distribution.
16ab64e1faSKarsten Heimrich
17ab64e1faSKarsten Heimrich   3. Neither the name of the Intel Corporation nor the names of its
18ab64e1faSKarsten Heimrich      contributors may be used to endorse or promote products derived from
19ab64e1faSKarsten Heimrich      this software without specific prior written permission.
20ab64e1faSKarsten Heimrich
21ab64e1faSKarsten Heimrich  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22ab64e1faSKarsten Heimrich  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23ab64e1faSKarsten Heimrich  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24ab64e1faSKarsten Heimrich  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25ab64e1faSKarsten Heimrich  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26ab64e1faSKarsten Heimrich  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27ab64e1faSKarsten Heimrich  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28ab64e1faSKarsten Heimrich  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29ab64e1faSKarsten Heimrich  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30ab64e1faSKarsten Heimrich  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31ab64e1faSKarsten Heimrich  POSSIBILITY OF SUCH DAMAGE.
32ab64e1faSKarsten Heimrich
33ab64e1faSKarsten Heimrich******************************************************************************/
3467a0cb89SAugustin Cavalier/*$FreeBSD: releng/12.0/sys/dev/e1000/e1000_hw.h 333345 2018-05-08 01:39:45Z mmacy $*/
35ab64e1faSKarsten Heimrich
36ab64e1faSKarsten Heimrich#ifndef _E1000_HW_H_
37ab64e1faSKarsten Heimrich#define _E1000_HW_H_
38ab64e1faSKarsten Heimrich
39ab64e1faSKarsten Heimrich#include "e1000_osdep.h"
40ab64e1faSKarsten Heimrich#include "e1000_regs.h"
41ab64e1faSKarsten Heimrich#include "e1000_defines.h"
42ab64e1faSKarsten Heimrich
43ab64e1faSKarsten Heimrichstruct e1000_hw;
44ab64e1faSKarsten Heimrich
45648db733SJérôme Duval#define E1000_DEV_ID_82542			0x1000
46648db733SJérôme Duval#define E1000_DEV_ID_82543GC_FIBER		0x1001
47648db733SJérôme Duval#define E1000_DEV_ID_82543GC_COPPER		0x1004
48648db733SJérôme Duval#define E1000_DEV_ID_82544EI_COPPER		0x1008
49648db733SJérôme Duval#define E1000_DEV_ID_82544EI_FIBER		0x1009
50648db733SJérôme Duval#define E1000_DEV_ID_82544GC_COPPER		0x100C
51648db733SJérôme Duval#define E1000_DEV_ID_82544GC_LOM		0x100D
52648db733SJérôme Duval#define E1000_DEV_ID_82540EM			0x100E
53648db733SJérôme Duval#define E1000_DEV_ID_82540EM_LOM		0x1015
54648db733SJérôme Duval#define E1000_DEV_ID_82540EP_LOM		0x1016
55648db733SJérôme Duval#define E1000_DEV_ID_82540EP			0x1017
56648db733SJérôme Duval#define E1000_DEV_ID_82540EP_LP			0x101E
57648db733SJérôme Duval#define E1000_DEV_ID_82545EM_COPPER		0x100F
58648db733SJérôme Duval#define E1000_DEV_ID_82545EM_FIBER		0x1011
59648db733SJérôme Duval#define E1000_DEV_ID_82545GM_COPPER		0x1026
60648db733SJérôme Duval#define E1000_DEV_ID_82545GM_FIBER		0x1027
61648db733SJérôme Duval#define E1000_DEV_ID_82545GM_SERDES		0x1028
62648db733SJérôme Duval#define E1000_DEV_ID_82546EB_COPPER		0x1010
63648db733SJérôme Duval#define E1000_DEV_ID_82546EB_FIBER		0x1012
64648db733SJérôme Duval#define E1000_DEV_ID_82546EB_QUAD_COPPER	0x101D
65648db733SJérôme Duval#define E1000_DEV_ID_82546GB_COPPER		0x1079
66648db733SJérôme Duval#define E1000_DEV_ID_82546GB_FIBER		0x107A
67648db733SJérôme Duval#define E1000_DEV_ID_82546GB_SERDES		0x107B
68648db733SJérôme Duval#define E1000_DEV_ID_82546GB_PCIE		0x108A
69648db733SJérôme Duval#define E1000_DEV_ID_82546GB_QUAD_COPPER	0x1099
70648db733SJérôme Duval#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3	0x10B5
71648db733SJérôme Duval#define E1000_DEV_ID_82541EI			0x1013
72648db733SJérôme Duval#define E1000_DEV_ID_82541EI_MOBILE		0x1018
73648db733SJérôme Duval#define E1000_DEV_ID_82541ER_LOM		0x1014
74648db733SJérôme Duval#define E1000_DEV_ID_82541ER			0x1078
75648db733SJérôme Duval#define E1000_DEV_ID_82541GI			0x1076
76648db733SJérôme Duval#define E1000_DEV_ID_82541GI_LF			0x107C
77648db733SJérôme Duval#define E1000_DEV_ID_82541GI_MOBILE		0x1077
78648db733SJérôme Duval#define E1000_DEV_ID_82547EI			0x1019
79648db733SJérôme Duval#define E1000_DEV_ID_82547EI_MOBILE		0x101A
80648db733SJérôme Duval#define E1000_DEV_ID_82547GI			0x1075
81648db733SJérôme Duval#define E1000_DEV_ID_82571EB_COPPER		0x105E
82648db733SJérôme Duval#define E1000_DEV_ID_82571EB_FIBER		0x105F
83648db733SJérôme Duval#define E1000_DEV_ID_82571EB_SERDES		0x1060
84648db733SJérôme Duval#define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
85648db733SJérôme Duval#define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
86648db733SJérôme Duval#define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
87648db733SJérôme Duval#define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
88648db733SJérôme Duval#define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
89648db733SJérôme Duval#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
90648db733SJérôme Duval#define E1000_DEV_ID_82572EI_COPPER		0x107D
91648db733SJérôme Duval#define E1000_DEV_ID_82572EI_FIBER		0x107E
92648db733SJérôme Duval#define E1000_DEV_ID_82572EI_SERDES		0x107F
93648db733SJérôme Duval#define E1000_DEV_ID_82572EI			0x10B9
94648db733SJérôme Duval#define E1000_DEV_ID_82573E			0x108B
95648db733SJérôme Duval#define E1000_DEV_ID_82573E_IAMT		0x108C
96648db733SJérôme Duval#define E1000_DEV_ID_82573L			0x109A
97648db733SJérôme Duval#define E1000_DEV_ID_82574L			0x10D3
98648db733SJérôme Duval#define E1000_DEV_ID_82574LA			0x10F6
99648db733SJérôme Duval#define E1000_DEV_ID_82583V			0x150C
100648db733SJérôme Duval#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
101648db733SJérôme Duval#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
102648db733SJérôme Duval#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
103648db733SJérôme Duval#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
104648db733SJérôme Duval#define E1000_DEV_ID_ICH8_82567V_3		0x1501
105648db733SJérôme Duval#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
106648db733SJérôme Duval#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
107648db733SJérôme Duval#define E1000_DEV_ID_ICH8_IGP_C			0x104B
108648db733SJérôme Duval#define E1000_DEV_ID_ICH8_IFE			0x104C
109648db733SJérôme Duval#define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
110648db733SJérôme Duval#define E1000_DEV_ID_ICH8_IFE_G			0x10C5
111648db733SJérôme Duval#define E1000_DEV_ID_ICH8_IGP_M			0x104D
112648db733SJérôme Duval#define E1000_DEV_ID_ICH9_IGP_M			0x10BF
113648db733SJérôme Duval#define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
114648db733SJérôme Duval#define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
115648db733SJérôme Duval#define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
116648db733SJérôme Duval#define E1000_DEV_ID_ICH9_BM			0x10E5
117648db733SJérôme Duval#define E1000_DEV_ID_ICH9_IGP_C			0x294C
118648db733SJérôme Duval#define E1000_DEV_ID_ICH9_IFE			0x10C0
119648db733SJérôme Duval#define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
120648db733SJérôme Duval#define E1000_DEV_ID_ICH9_IFE_G			0x10C2
121648db733SJérôme Duval#define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
122648db733SJérôme Duval#define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
123648db733SJérôme Duval#define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
124648db733SJérôme Duval#define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
125648db733SJérôme Duval#define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
126648db733SJérôme Duval#define E1000_DEV_ID_ICH10_D_BM_V		0x1525
127648db733SJérôme Duval#define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
128648db733SJérôme Duval#define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
129648db733SJérôme Duval#define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
130648db733SJérôme Duval#define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
131648db733SJérôme Duval#define E1000_DEV_ID_PCH2_LV_LM			0x1502
132648db733SJérôme Duval#define E1000_DEV_ID_PCH2_LV_V			0x1503
133d57b6246SJérôme Duval#define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A
134d57b6246SJérôme Duval#define E1000_DEV_ID_PCH_LPT_I217_V		0x153B
135d57b6246SJérôme Duval#define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A
136d57b6246SJérôme Duval#define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559
137b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_I218_LM2		0x15A0
138b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_I218_V2		0x15A1
139b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_I218_LM3		0x15A2 /* Wildcat Point PCH */
140b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_I218_V3		0x15A3 /* Wildcat Point PCH */
141b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_SPT_I219_LM		0x156F /* Sunrise Point PCH */
142b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_SPT_I219_V		0x1570 /* Sunrise Point PCH */
143b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_SPT_I219_LM2		0x15B7 /* Sunrise Point-H PCH */
144b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_SPT_I219_V2		0x15B8 /* Sunrise Point-H PCH */
145b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_LBG_I219_LM3		0x15B9 /* LEWISBURG PCH */
146b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_SPT_I219_LM4		0x15D7
147b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_SPT_I219_V4		0x15D8
148b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_SPT_I219_LM5		0x15E3
149b3fb200fSJérôme Duval#define E1000_DEV_ID_PCH_SPT_I219_V5		0x15D6
15067a0cb89SAugustin Cavalier#define E1000_DEV_ID_PCH_CNP_I219_LM6		0x15BD
15167a0cb89SAugustin Cavalier#define E1000_DEV_ID_PCH_CNP_I219_V6		0x15BE
15267a0cb89SAugustin Cavalier#define E1000_DEV_ID_PCH_CNP_I219_LM7		0x15BB
15367a0cb89SAugustin Cavalier#define E1000_DEV_ID_PCH_CNP_I219_V7		0x15BC
15467a0cb89SAugustin Cavalier#define E1000_DEV_ID_PCH_ICP_I219_LM8		0x15DF
15567a0cb89SAugustin Cavalier#define E1000_DEV_ID_PCH_ICP_I219_V8		0x15E0
15667a0cb89SAugustin Cavalier#define E1000_DEV_ID_PCH_ICP_I219_LM9		0x15E1
15767a0cb89SAugustin Cavalier#define E1000_DEV_ID_PCH_ICP_I219_V9		0x15E2
158648db733SJérôme Duval#define E1000_DEV_ID_82576			0x10C9
159648db733SJérôme Duval#define E1000_DEV_ID_82576_FIBER		0x10E6
160648db733SJérôme Duval#define E1000_DEV_ID_82576_SERDES		0x10E7
161648db733SJérôme Duval#define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
162648db733SJérôme Duval#define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526
163648db733SJérôme Duval#define E1000_DEV_ID_82576_NS			0x150A
164648db733SJérôme Duval#define E1000_DEV_ID_82576_NS_SERDES		0x1518
165648db733SJérôme Duval#define E1000_DEV_ID_82576_SERDES_QUAD		0x150D
166648db733SJérôme Duval#define E1000_DEV_ID_82576_VF			0x10CA
167d57b6246SJérôme Duval#define E1000_DEV_ID_82576_VF_HV		0x152D
168648db733SJérôme Duval#define E1000_DEV_ID_I350_VF			0x1520
169d57b6246SJérôme Duval#define E1000_DEV_ID_I350_VF_HV			0x152F
170648db733SJérôme Duval#define E1000_DEV_ID_82575EB_COPPER		0x10A7
171648db733SJérôme Duval#define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
172648db733SJérôme Duval#define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
173648db733SJérôme Duval#define E1000_DEV_ID_82580_COPPER		0x150E
174648db733SJérôme Duval#define E1000_DEV_ID_82580_FIBER		0x150F
175648db733SJérôme Duval#define E1000_DEV_ID_82580_SERDES		0x1510
176648db733SJérôme Duval#define E1000_DEV_ID_82580_SGMII		0x1511
177648db733SJérôme Duval#define E1000_DEV_ID_82580_COPPER_DUAL		0x1516
178648db733SJérôme Duval#define E1000_DEV_ID_82580_QUAD_FIBER		0x1527
179648db733SJérôme Duval#define E1000_DEV_ID_I350_COPPER		0x1521
180648db733SJérôme Duval#define E1000_DEV_ID_I350_FIBER			0x1522
181648db733SJérôme Duval#define E1000_DEV_ID_I350_SERDES		0x1523
182648db733SJérôme Duval#define E1000_DEV_ID_I350_SGMII			0x1524
183648db733SJérôme Duval#define E1000_DEV_ID_I350_DA4			0x1546
184648db733SJérôme Duval#define E1000_DEV_ID_I210_COPPER		0x1533
185648db733SJérôme Duval#define E1000_DEV_ID_I210_COPPER_OEM1		0x1534
186648db733SJérôme Duval#define E1000_DEV_ID_I210_COPPER_IT		0x1535
187648db733SJérôme Duval#define E1000_DEV_ID_I210_FIBER			0x1536
188648db733SJérôme Duval#define E1000_DEV_ID_I210_SERDES		0x1537
189648db733SJérôme Duval#define E1000_DEV_ID_I210_SGMII			0x1538
190b3fb200fSJérôme Duval#define E1000_DEV_ID_I210_COPPER_FLASHLESS	0x157B
191b3fb200fSJérôme Duval#define E1000_DEV_ID_I210_SERDES_FLASHLESS	0x157C
192648db733SJérôme Duval#define E1000_DEV_ID_I211_COPPER		0x1539
193b3fb200fSJérôme Duval#define E1000_DEV_ID_I354_BACKPLANE_1GBPS	0x1F40
194b3fb200fSJérôme Duval#define E1000_DEV_ID_I354_SGMII			0x1F41
195b3fb200fSJérôme Duval#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS	0x1F45
196648db733SJérôme Duval#define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
197648db733SJérôme Duval#define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
198648db733SJérôme Duval#define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
199648db733SJérôme Duval#define E1000_DEV_ID_DH89XXCC_SFP		0x0440
200d57b6246SJérôme Duval
201648db733SJérôme Duval#define E1000_REVISION_0	0
202648db733SJérôme Duval#define E1000_REVISION_1	1
203648db733SJérôme Duval#define E1000_REVISION_2	2
204648db733SJérôme Duval#define E1000_REVISION_3	3
205648db733SJérôme Duval#define E1000_REVISION_4	4
206648db733SJérôme Duval
207648db733SJérôme Duval#define E1000_FUNC_0		0
208648db733SJérôme Duval#define E1000_FUNC_1		1
209648db733SJérôme Duval#define E1000_FUNC_2		2
210648db733SJérôme Duval#define E1000_FUNC_3		3
211648db733SJérôme Duval
212648db733SJérôme Duval#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
213648db733SJérôme Duval#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3
214648db733SJérôme Duval#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2	6
215648db733SJérôme Duval#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3	9
216ab64e1faSKarsten Heimrich
217ab64e1faSKarsten Heimrichenum e1000_mac_type {
218ab64e1faSKarsten Heimrich	e1000_undefined = 0,
219ab64e1faSKarsten Heimrich	e1000_82542,
220ab64e1faSKarsten Heimrich	e1000_82543,
221ab64e1faSKarsten Heimrich	e1000_82544,
222ab64e1faSKarsten Heimrich	e1000_82540,
223ab64e1faSKarsten Heimrich	e1000_82545,
224ab64e1faSKarsten Heimrich	e1000_82545_rev_3,
225ab64e1faSKarsten Heimrich	e1000_82546,
226ab64e1faSKarsten Heimrich	e1000_82546_rev_3,
227ab64e1faSKarsten Heimrich	e1000_82541,
228ab64e1faSKarsten Heimrich	e1000_82541_rev_2,
229ab64e1faSKarsten Heimrich	e1000_82547,
230ab64e1faSKarsten Heimrich	e1000_82547_rev_2,
231ab64e1faSKarsten Heimrich	e1000_82571,
232ab64e1faSKarsten Heimrich	e1000_82572,
233ab64e1faSKarsten Heimrich	e1000_82573,
234ab64e1faSKarsten Heimrich	e1000_82574,
235d1e17090SSiarzhuk Zharski	e1000_82583,
236ab64e1faSKarsten Heimrich	e1000_80003es2lan,
237ab64e1faSKarsten Heimrich	e1000_ich8lan,
238ab64e1faSKarsten Heimrich	e1000_ich9lan,
239ab64e1faSKarsten Heimrich	e1000_ich10lan,
240d1e17090SSiarzhuk Zharski	e1000_pchlan,
241d1e17090SSiarzhuk Zharski	e1000_pch2lan,
242d57b6246SJérôme Duval	e1000_pch_lpt,
243b3fb200fSJérôme Duval	e1000_pch_spt,
24467a0cb89SAugustin Cavalier	e1000_pch_cnp,
245ab64e1faSKarsten Heimrich	e1000_82575,
246ab64e1faSKarsten Heimrich	e1000_82576,
247d1e17090SSiarzhuk Zharski	e1000_82580,
2488060e778SJérôme Duval	e1000_i350,
249b3fb200fSJérôme Duval	e1000_i354,
250648db733SJérôme Duval	e1000_i210,
251648db733SJérôme Duval	e1000_i211,
252ab64e1faSKarsten Heimrich	e1000_vfadapt,
2538060e778SJérôme Duval	e1000_vfadapt_i350,
254ab64e1faSKarsten Heimrich	e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
255ab64e1faSKarsten Heimrich};
256ab64e1faSKarsten Heimrich
257ab64e1faSKarsten Heimrichenum e1000_media_type {
258ab64e1faSKarsten Heimrich	e1000_media_type_unknown = 0,
259ab64e1faSKarsten Heimrich	e1000_media_type_copper = 1,
260ab64e1faSKarsten Heimrich	e1000_media_type_fiber = 2,
261ab64e1faSKarsten Heimrich	e1000_media_type_internal_serdes = 3,
262ab64e1faSKarsten Heimrich	e1000_num_media_types
263ab64e1faSKarsten Heimrich};
264ab64e1faSKarsten Heimrich
265ab64e1faSKarsten Heimrichenum e1000_nvm_type {
266ab64e1faSKarsten Heimrich	e1000_nvm_unknown = 0,
267ab64e1faSKarsten Heimrich	e1000_nvm_none,
268ab64e1faSKarsten Heimrich	e1000_nvm_eeprom_spi,
269ab64e1faSKarsten Heimrich	e1000_nvm_eeprom_microwire,
270ab64e1faSKarsten Heimrich	e1000_nvm_flash_hw,
271b3fb200fSJérôme Duval	e1000_nvm_invm,
272ab64e1faSKarsten Heimrich	e1000_nvm_flash_sw
273ab64e1faSKarsten Heimrich};
274ab64e1faSKarsten Heimrich
275ab64e1faSKarsten Heimrichenum e1000_nvm_override {
276ab64e1faSKarsten Heimrich	e1000_nvm_override_none = 0,
277ab64e1faSKarsten Heimrich	e1000_nvm_override_spi_small,
278ab64e1faSKarsten Heimrich	e1000_nvm_override_spi_large,
279ab64e1faSKarsten Heimrich	e1000_nvm_override_microwire_small,
280ab64e1faSKarsten Heimrich	e1000_nvm_override_microwire_large
281ab64e1faSKarsten Heimrich};
282ab64e1faSKarsten Heimrich
283ab64e1faSKarsten Heimrichenum e1000_phy_type {
284ab64e1faSKarsten Heimrich	e1000_phy_unknown = 0,
285ab64e1faSKarsten Heimrich	e1000_phy_none,
286ab64e1faSKarsten Heimrich	e1000_phy_m88,
287ab64e1faSKarsten Heimrich	e1000_phy_igp,
288ab64e1faSKarsten Heimrich	e1000_phy_igp_2,
289ab64e1faSKarsten Heimrich	e1000_phy_gg82563,
290ab64e1faSKarsten Heimrich	e1000_phy_igp_3,
291ab64e1faSKarsten Heimrich	e1000_phy_ife,
292ab64e1faSKarsten Heimrich	e1000_phy_bm,
293d1e17090SSiarzhuk Zharski	e1000_phy_82578,
294d1e17090SSiarzhuk Zharski	e1000_phy_82577,
295d1e17090SSiarzhuk Zharski	e1000_phy_82579,
296d57b6246SJérôme Duval	e1000_phy_i217,
297d1e17090SSiarzhuk Zharski	e1000_phy_82580,
298ab64e1faSKarsten Heimrich	e1000_phy_vf,
299648db733SJérôme Duval	e1000_phy_i210,
300ab64e1faSKarsten Heimrich};
301ab64e1faSKarsten Heimrich
302ab64e1faSKarsten Heimrichenum e1000_bus_type {
303ab64e1faSKarsten Heimrich	e1000_bus_type_unknown = 0,
304ab64e1faSKarsten Heimrich	e1000_bus_type_pci,
305ab64e1faSKarsten Heimrich	e1000_bus_type_pcix,
306ab64e1faSKarsten Heimrich	e1000_bus_type_pci_express,
307ab64e1faSKarsten Heimrich	e1000_bus_type_reserved
308ab64e1faSKarsten Heimrich};
309ab64e1faSKarsten Heimrich
310ab64e1faSKarsten Heimrichenum e1000_bus_speed {
311ab64e1faSKarsten Heimrich	e1000_bus_speed_unknown = 0,
312ab64e1faSKarsten Heimrich	e1000_bus_speed_33,
313ab64e1faSKarsten Heimrich	e1000_bus_speed_66,
314ab64e1faSKarsten Heimrich	e1000_bus_speed_100,
315ab64e1faSKarsten Heimrich	e1000_bus_speed_120,
316ab64e1faSKarsten Heimrich	e1000_bus_speed_133,
317ab64e1faSKarsten Heimrich	e1000_bus_speed_2500,
318ab64e1faSKarsten Heimrich	e1000_bus_speed_5000,
319ab64e1faSKarsten Heimrich	e1000_bus_speed_reserved
320ab64e1faSKarsten Heimrich};
321ab64e1faSKarsten Heimrich
322ab64e1faSKarsten Heimrichenum e1000_bus_width {
323ab64e1faSKarsten Heimrich	e1000_bus_width_unknown = 0,
324ab64e1faSKarsten Heimrich	e1000_bus_width_pcie_x1,
325ab64e1faSKarsten Heimrich	e1000_bus_width_pcie_x2,
326ab64e1faSKarsten Heimrich	e1000_bus_width_pcie_x4 = 4,
327ab64e1faSKarsten Heimrich	e1000_bus_width_pcie_x8 = 8,
328ab64e1faSKarsten Heimrich	e1000_bus_width_32,
329ab64e1faSKarsten Heimrich	e1000_bus_width_64,
330ab64e1faSKarsten Heimrich	e1000_bus_width_reserved
331ab64e1faSKarsten Heimrich};
332ab64e1faSKarsten Heimrich
333ab64e1faSKarsten Heimrichenum e1000_1000t_rx_status {
334ab64e1faSKarsten Heimrich	e1000_1000t_rx_status_not_ok = 0,
335ab64e1faSKarsten Heimrich	e1000_1000t_rx_status_ok,
336ab64e1faSKarsten Heimrich	e1000_1000t_rx_status_undefined = 0xFF
337ab64e1faSKarsten Heimrich};
338ab64e1faSKarsten Heimrich
339ab64e1faSKarsten Heimrichenum e1000_rev_polarity {
340ab64e1faSKarsten Heimrich	e1000_rev_polarity_normal = 0,
341ab64e1faSKarsten Heimrich	e1000_rev_polarity_reversed,
342ab64e1faSKarsten Heimrich	e1000_rev_polarity_undefined = 0xFF
343ab64e1faSKarsten Heimrich};
344ab64e1faSKarsten Heimrich
345ab64e1faSKarsten Heimrichenum e1000_fc_mode {
346ab64e1faSKarsten Heimrich	e1000_fc_none = 0,
347ab64e1faSKarsten Heimrich	e1000_fc_rx_pause,
348ab64e1faSKarsten Heimrich	e1000_fc_tx_pause,
349ab64e1faSKarsten Heimrich	e1000_fc_full,
350ab64e1faSKarsten Heimrich	e1000_fc_default = 0xFF
351ab64e1faSKarsten Heimrich};
352ab64e1faSKarsten Heimrich
353ab64e1faSKarsten Heimrichenum e1000_ffe_config {
354ab64e1faSKarsten Heimrich	e1000_ffe_config_enabled = 0,
355ab64e1faSKarsten Heimrich	e1000_ffe_config_active,
356ab64e1faSKarsten Heimrich	e1000_ffe_config_blocked
357ab64e1faSKarsten Heimrich};
358ab64e1faSKarsten Heimrich
359ab64e1faSKarsten Heimrichenum e1000_dsp_config {
360ab64e1faSKarsten Heimrich	e1000_dsp_config_disabled = 0,
361ab64e1faSKarsten Heimrich	e1000_dsp_config_enabled,
362ab64e1faSKarsten Heimrich	e1000_dsp_config_activated,
363ab64e1faSKarsten Heimrich	e1000_dsp_config_undefined = 0xFF
364ab64e1faSKarsten Heimrich};
365ab64e1faSKarsten Heimrich
366ab64e1faSKarsten Heimrichenum e1000_ms_type {
367ab64e1faSKarsten Heimrich	e1000_ms_hw_default = 0,
368ab64e1faSKarsten Heimrich	e1000_ms_force_master,
369ab64e1faSKarsten Heimrich	e1000_ms_force_slave,
370ab64e1faSKarsten Heimrich	e1000_ms_auto
371ab64e1faSKarsten Heimrich};
372ab64e1faSKarsten Heimrich
373ab64e1faSKarsten Heimrichenum e1000_smart_speed {
374ab64e1faSKarsten Heimrich	e1000_smart_speed_default = 0,
375ab64e1faSKarsten Heimrich	e1000_smart_speed_on,
376ab64e1faSKarsten Heimrich	e1000_smart_speed_off
377ab64e1faSKarsten Heimrich};
378ab64e1faSKarsten Heimrich
379d1e17090SSiarzhuk Zharskienum e1000_serdes_link_state {
380d1e17090SSiarzhuk Zharski	e1000_serdes_link_down = 0,
381d1e17090SSiarzhuk Zharski	e1000_serdes_link_autoneg_progress,
382d1e17090SSiarzhuk Zharski	e1000_serdes_link_autoneg_complete,
383d1e17090SSiarzhuk Zharski	e1000_serdes_link_forced_up
384d1e17090SSiarzhuk Zharski};
385d1e17090SSiarzhuk Zharski
386d1e17090SSiarzhuk Zharski#define __le16 u16
387d1e17090SSiarzhuk Zharski#define __le32 u32
388d1e17090SSiarzhuk Zharski#define __le64 u64
389ab64e1faSKarsten Heimrich/* Receive Descriptor */
390ab64e1faSKarsten Heimrichstruct e1000_rx_desc {
391ab64e1faSKarsten Heimrich	__le64 buffer_addr; /* Address of the descriptor's data buffer */
392ab64e1faSKarsten Heimrich	__le16 length;      /* Length of data DMAed into data buffer */
393648db733SJérôme Duval	__le16 csum; /* Packet checksum */
394648db733SJérôme Duval	u8  status;  /* Descriptor status */
395648db733SJérôme Duval	u8  errors;  /* Descriptor Errors */
396ab64e1faSKarsten Heimrich	__le16 special;
397ab64e1faSKarsten Heimrich};
398ab64e1faSKarsten Heimrich
399ab64e1faSKarsten Heimrich/* Receive Descriptor - Extended */
400ab64e1faSKarsten Heimrichunion e1000_rx_desc_extended {
401ab64e1faSKarsten Heimrich	struct {
402ab64e1faSKarsten Heimrich		__le64 buffer_addr;
403ab64e1faSKarsten Heimrich		__le64 reserved;
404ab64e1faSKarsten Heimrich	} read;
405ab64e1faSKarsten Heimrich	struct {
406ab64e1faSKarsten Heimrich		struct {
407648db733SJérôme Duval			__le32 mrq; /* Multiple Rx Queues */
408ab64e1faSKarsten Heimrich			union {
409648db733SJérôme Duval				__le32 rss; /* RSS Hash */
410ab64e1faSKarsten Heimrich				struct {
411ab64e1faSKarsten Heimrich					__le16 ip_id;  /* IP id */
412ab64e1faSKarsten Heimrich					__le16 csum;   /* Packet Checksum */
413ab64e1faSKarsten Heimrich				} csum_ip;
414ab64e1faSKarsten Heimrich			} hi_dword;
415ab64e1faSKarsten Heimrich		} lower;
416ab64e1faSKarsten Heimrich		struct {
417ab64e1faSKarsten Heimrich			__le32 status_error;  /* ext status/error */
418ab64e1faSKarsten Heimrich			__le16 length;
419648db733SJérôme Duval			__le16 vlan; /* VLAN tag */
420ab64e1faSKarsten Heimrich		} upper;
421ab64e1faSKarsten Heimrich	} wb;  /* writeback */
422ab64e1faSKarsten Heimrich};
423ab64e1faSKarsten Heimrich
424ab64e1faSKarsten Heimrich#define MAX_PS_BUFFERS 4
425b3fb200fSJérôme Duval
426b3fb200fSJérôme Duval/* Number of packet split data buffers (not including the header buffer) */
427b3fb200fSJérôme Duval#define PS_PAGE_BUFFERS	(MAX_PS_BUFFERS - 1)
428b3fb200fSJérôme Duval
429ab64e1faSKarsten Heimrich/* Receive Descriptor - Packet Split */
430ab64e1faSKarsten Heimrichunion e1000_rx_desc_packet_split {
431ab64e1faSKarsten Heimrich	struct {
432ab64e1faSKarsten Heimrich		/* one buffer for protocol header(s), three data buffers */
433ab64e1faSKarsten Heimrich		__le64 buffer_addr[MAX_PS_BUFFERS];
434ab64e1faSKarsten Heimrich	} read;
435ab64e1faSKarsten Heimrich	struct {
436ab64e1faSKarsten Heimrich		struct {
437648db733SJérôme Duval			__le32 mrq;  /* Multiple Rx Queues */
438ab64e1faSKarsten Heimrich			union {
439648db733SJérôme Duval				__le32 rss; /* RSS Hash */
440ab64e1faSKarsten Heimrich				struct {
441ab64e1faSKarsten Heimrich					__le16 ip_id;    /* IP id */
442ab64e1faSKarsten Heimrich					__le16 csum;     /* Packet Checksum */
443ab64e1faSKarsten Heimrich				} csum_ip;
444ab64e1faSKarsten Heimrich			} hi_dword;
445ab64e1faSKarsten Heimrich		} lower;
446ab64e1faSKarsten Heimrich		struct {
447ab64e1faSKarsten Heimrich			__le32 status_error;  /* ext status/error */
448648db733SJérôme Duval			__le16 length0;  /* length of buffer 0 */
449648db733SJérôme Duval			__le16 vlan;  /* VLAN tag */
450ab64e1faSKarsten Heimrich		} middle;
451ab64e1faSKarsten Heimrich		struct {
452ab64e1faSKarsten Heimrich			__le16 header_status;
453b3fb200fSJérôme Duval			/* length of buffers 1-3 */
454b3fb200fSJérôme Duval			__le16 length[PS_PAGE_BUFFERS];
455ab64e1faSKarsten Heimrich		} upper;
456ab64e1faSKarsten Heimrich		__le64 reserved;
457ab64e1faSKarsten Heimrich	} wb; /* writeback */
458ab64e1faSKarsten Heimrich};
459ab64e1faSKarsten Heimrich
460ab64e1faSKarsten Heimrich/* Transmit Descriptor */
461ab64e1faSKarsten Heimrichstruct e1000_tx_desc {
462ab64e1faSKarsten Heimrich	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
463ab64e1faSKarsten Heimrich	union {
464ab64e1faSKarsten Heimrich		__le32 data;
465ab64e1faSKarsten Heimrich		struct {
466648db733SJérôme Duval			__le16 length;  /* Data buffer length */
467648db733SJérôme Duval			u8 cso;  /* Checksum offset */
468648db733SJérôme Duval			u8 cmd;  /* Descriptor control */
469ab64e1faSKarsten Heimrich		} flags;
470ab64e1faSKarsten Heimrich	} lower;
471ab64e1faSKarsten Heimrich	union {
472ab64e1faSKarsten Heimrich		__le32 data;
473ab64e1faSKarsten Heimrich		struct {
474648db733SJérôme Duval			u8 status; /* Descriptor status */
475648db733SJérôme Duval			u8 css;  /* Checksum start */
476ab64e1faSKarsten Heimrich			__le16 special;
477ab64e1faSKarsten Heimrich		} fields;
478ab64e1faSKarsten Heimrich	} upper;
479ab64e1faSKarsten Heimrich};
480ab64e1faSKarsten Heimrich
481ab64e1faSKarsten Heimrich/* Offload Context Descriptor */
482ab64e1faSKarsten Heimrichstruct e1000_context_desc {
483ab64e1faSKarsten Heimrich	union {
484ab64e1faSKarsten Heimrich		__le32 ip_config;
485ab64e1faSKarsten Heimrich		struct {
486648db733SJérôme Duval			u8 ipcss;  /* IP checksum start */
487648db733SJérôme Duval			u8 ipcso;  /* IP checksum offset */
488648db733SJérôme Duval			__le16 ipcse;  /* IP checksum end */
489ab64e1faSKarsten Heimrich		} ip_fields;
490ab64e1faSKarsten Heimrich	} lower_setup;
491ab64e1faSKarsten Heimrich	union {
492ab64e1faSKarsten Heimrich		__le32 tcp_config;
493ab64e1faSKarsten Heimrich		struct {
494648db733SJérôme Duval			u8 tucss;  /* TCP checksum start */
495648db733SJérôme Duval			u8 tucso;  /* TCP checksum offset */
496648db733SJérôme Duval			__le16 tucse;  /* TCP checksum end */
497ab64e1faSKarsten Heimrich		} tcp_fields;
498ab64e1faSKarsten Heimrich	} upper_setup;
499ab64e1faSKarsten Heimrich	__le32 cmd_and_length;
500ab64e1faSKarsten Heimrich	union {
501ab64e1faSKarsten Heimrich		__le32 data;
502ab64e1faSKarsten Heimrich		struct {
503648db733SJérôme Duval			u8 status;  /* Descriptor status */
504648db733SJérôme Duval			u8 hdr_len;  /* Header length */
505648db733SJérôme Duval			__le16 mss;  /* Maximum segment size */
506ab64e1faSKarsten Heimrich		} fields;
507ab64e1faSKarsten Heimrich	} tcp_seg_setup;
508ab64e1faSKarsten Heimrich};
509ab64e1faSKarsten Heimrich
510ab64e1faSKarsten Heimrich/* Offload data descriptor */
511ab64e1faSKarsten Heimrichstruct e1000_data_desc {
512648db733SJérôme Duval	__le64 buffer_addr;  /* Address of the descriptor's buffer address */
513ab64e1faSKarsten Heimrich	union {
514ab64e1faSKarsten Heimrich		__le32 data;
515ab64e1faSKarsten Heimrich		struct {
516648db733SJérôme Duval			__le16 length;  /* Data buffer length */
517ab64e1faSKarsten Heimrich			u8 typ_len_ext;
518ab64e1faSKarsten Heimrich			u8 cmd;
519ab64e1faSKarsten Heimrich		} flags;
520ab64e1faSKarsten Heimrich	} lower;
521ab64e1faSKarsten Heimrich	union {
522ab64e1faSKarsten Heimrich		__le32 data;
523ab64e1faSKarsten Heimrich		struct {
524648db733SJérôme Duval			u8 status;  /* Descriptor status */
525648db733SJérôme Duval			u8 popts;  /* Packet Options */
526ab64e1faSKarsten Heimrich			__le16 special;
527ab64e1faSKarsten Heimrich		} fields;
528ab64e1faSKarsten Heimrich	} upper;
529ab64e1faSKarsten Heimrich};
530ab64e1faSKarsten Heimrich
531ab64e1faSKarsten Heimrich/* Statistics counters collected by the MAC */
532ab64e1faSKarsten Heimrichstruct e1000_hw_stats {
533ab64e1faSKarsten Heimrich	u64 crcerrs;
534ab64e1faSKarsten Heimrich	u64 algnerrc;
535ab64e1faSKarsten Heimrich	u64 symerrs;
536ab64e1faSKarsten Heimrich	u64 rxerrc;
537ab64e1faSKarsten Heimrich	u64 mpc;
538ab64e1faSKarsten Heimrich	u64 scc;
539ab64e1faSKarsten Heimrich	u64 ecol;
540ab64e1faSKarsten Heimrich	u64 mcc;
541ab64e1faSKarsten Heimrich	u64 latecol;
542ab64e1faSKarsten Heimrich	u64 colc;
543ab64e1faSKarsten Heimrich	u64 dc;
544ab64e1faSKarsten Heimrich	u64 tncrs;
545ab64e1faSKarsten Heimrich	u64 sec;
546ab64e1faSKarsten Heimrich	u64 cexterr;
547ab64e1faSKarsten Heimrich	u64 rlec;
548ab64e1faSKarsten Heimrich	u64 xonrxc;
549ab64e1faSKarsten Heimrich	u64 xontxc;
550ab64e1faSKarsten Heimrich	u64 xoffrxc;
551ab64e1faSKarsten Heimrich	u64 xofftxc;
552ab64e1faSKarsten Heimrich	u64 fcruc;
553ab64e1faSKarsten Heimrich	u64 prc64;
554ab64e1faSKarsten Heimrich	u64 prc127;
555ab64e1faSKarsten Heimrich	u64 prc255;
556ab64e1faSKarsten Heimrich	u64 prc511;
557ab64e1faSKarsten Heimrich	u64 prc1023;
558ab64e1faSKarsten Heimrich	u64 prc1522;
559ab64e1faSKarsten Heimrich	u64 gprc;
560ab64e1faSKarsten Heimrich	u64 bprc;
561ab64e1faSKarsten Heimrich	u64 mprc;
562ab64e1faSKarsten Heimrich	u64 gptc;
563ab64e1faSKarsten Heimrich	u64 gorc;
564ab64e1faSKarsten Heimrich	u64 gotc;
565ab64e1faSKarsten Heimrich	u64 rnbc;
566ab64e1faSKarsten Heimrich	u64 ruc;
567ab64e1faSKarsten Heimrich	u64 rfc;
568ab64e1faSKarsten Heimrich	u64 roc;
569ab64e1faSKarsten Heimrich	u64 rjc;
570ab64e1faSKarsten Heimrich	u64 mgprc;
571ab64e1faSKarsten Heimrich	u64 mgpdc;
572ab64e1faSKarsten Heimrich	u64 mgptc;
573ab64e1faSKarsten Heimrich	u64 tor;
574ab64e1faSKarsten Heimrich	u64 tot;
575ab64e1faSKarsten Heimrich	u64 tpr;
576ab64e1faSKarsten Heimrich	u64 tpt;
577ab64e1faSKarsten Heimrich	u64 ptc64;
578ab64e1faSKarsten Heimrich	u64 ptc127;
579ab64e1faSKarsten Heimrich	u64 ptc255;
580ab64e1faSKarsten Heimrich	u64 ptc511;
581ab64e1faSKarsten Heimrich	u64 ptc1023;
582ab64e1faSKarsten Heimrich	u64 ptc1522;
583ab64e1faSKarsten Heimrich	u64 mptc;
584ab64e1faSKarsten Heimrich	u64 bptc;
585ab64e1faSKarsten Heimrich	u64 tsctc;
586ab64e1faSKarsten Heimrich	u64 tsctfc;
587ab64e1faSKarsten Heimrich	u64 iac;
588ab64e1faSKarsten Heimrich	u64 icrxptc;
589ab64e1faSKarsten Heimrich	u64 icrxatc;
590ab64e1faSKarsten Heimrich	u64 ictxptc;
591ab64e1faSKarsten Heimrich	u64 ictxatc;
592ab64e1faSKarsten Heimrich	u64 ictxqec;
593ab64e1faSKarsten Heimrich	u64 ictxqmtc;
594ab64e1faSKarsten Heimrich	u64 icrxdmtc;
595ab64e1faSKarsten Heimrich	u64 icrxoc;
596ab64e1faSKarsten Heimrich	u64 cbtmpc;
597ab64e1faSKarsten Heimrich	u64 htdpmc;
598ab64e1faSKarsten Heimrich	u64 cbrdpc;
599ab64e1faSKarsten Heimrich	u64 cbrmpc;
600ab64e1faSKarsten Heimrich	u64 rpthc;
601ab64e1faSKarsten Heimrich	u64 hgptc;
602ab64e1faSKarsten Heimrich	u64 htcbdpc;
603ab64e1faSKarsten Heimrich	u64 hgorc;
604ab64e1faSKarsten Heimrich	u64 hgotc;
605ab64e1faSKarsten Heimrich	u64 lenerrs;
606ab64e1faSKarsten Heimrich	u64 scvpc;
607ab64e1faSKarsten Heimrich	u64 hrmpc;
608ab64e1faSKarsten Heimrich	u64 doosync;
609648db733SJérôme Duval	u64 o2bgptc;
610648db733SJérôme Duval	u64 o2bspc;
611648db733SJérôme Duval	u64 b2ospc;
612648db733SJérôme Duval	u64 b2ogprc;
613ab64e1faSKarsten Heimrich};
614ab64e1faSKarsten Heimrich
615ab64e1faSKarsten Heimrichstruct e1000_vf_stats {
616ab64e1faSKarsten Heimrich	u64 base_gprc;
617ab64e1faSKarsten Heimrich	u64 base_gptc;
618ab64e1faSKarsten Heimrich	u64 base_gorc;
619ab64e1faSKarsten Heimrich	u64 base_gotc;
620ab64e1faSKarsten Heimrich	u64 base_mprc;
621ab64e1faSKarsten Heimrich	u64 base_gotlbc;
622ab64e1faSKarsten Heimrich	u64 base_gptlbc;
623ab64e1faSKarsten Heimrich	u64 base_gorlbc;
624ab64e1faSKarsten Heimrich	u64 base_gprlbc;
625ab64e1faSKarsten Heimrich
626ab64e1faSKarsten Heimrich	u32 last_gprc;
627ab64e1faSKarsten Heimrich	u32 last_gptc;
628ab64e1faSKarsten Heimrich	u32 last_gorc;
629ab64e1faSKarsten Heimrich	u32 last_gotc;
630ab64e1faSKarsten Heimrich	u32 last_mprc;
631ab64e1faSKarsten Heimrich	u32 last_gotlbc;
632ab64e1faSKarsten Heimrich	u32 last_gptlbc;
633ab64e1faSKarsten Heimrich	u32 last_gorlbc;
634ab64e1faSKarsten Heimrich	u32 last_gprlbc;
635ab64e1faSKarsten Heimrich
636ab64e1faSKarsten Heimrich	u64 gprc;
637ab64e1faSKarsten Heimrich	u64 gptc;
638ab64e1faSKarsten Heimrich	u64 gorc;
639ab64e1faSKarsten Heimrich	u64 gotc;
640ab64e1faSKarsten Heimrich	u64 mprc;
641ab64e1faSKarsten Heimrich	u64 gotlbc;
642ab64e1faSKarsten Heimrich	u64 gptlbc;
643ab64e1faSKarsten Heimrich	u64 gorlbc;
644ab64e1faSKarsten Heimrich	u64 gprlbc;
645ab64e1faSKarsten Heimrich};
646ab64e1faSKarsten Heimrich
647ab64e1faSKarsten Heimrichstruct e1000_phy_stats {
648ab64e1faSKarsten Heimrich	u32 idle_errors;
649ab64e1faSKarsten Heimrich	u32 receive_errors;
650ab64e1faSKarsten Heimrich};
651ab64e1faSKarsten Heimrich
652ab64e1faSKarsten Heimrichstruct e1000_host_mng_dhcp_cookie {
653ab64e1faSKarsten Heimrich	u32 signature;
654ab64e1faSKarsten Heimrich	u8  status;
655ab64e1faSKarsten Heimrich	u8  reserved0;
656ab64e1faSKarsten Heimrich	u16 vlan_id;
657ab64e1faSKarsten Heimrich	u32 reserved1;
658ab64e1faSKarsten Heimrich	u16 reserved2;
659ab64e1faSKarsten Heimrich	u8  reserved3;
660ab64e1faSKarsten Heimrich	u8  checksum;
661ab64e1faSKarsten Heimrich};
662ab64e1faSKarsten Heimrich
663ab64e1faSKarsten Heimrich/* Host Interface "Rev 1" */
664ab64e1faSKarsten Heimrichstruct e1000_host_command_header {
665ab64e1faSKarsten Heimrich	u8 command_id;
666ab64e1faSKarsten Heimrich	u8 command_length;
667ab64e1faSKarsten Heimrich	u8 command_options;
668ab64e1faSKarsten Heimrich	u8 checksum;
669ab64e1faSKarsten Heimrich};
670ab64e1faSKarsten Heimrich
671648db733SJérôme Duval#define E1000_HI_MAX_DATA_LENGTH	252
672ab64e1faSKarsten Heimrichstruct e1000_host_command_info {
673ab64e1faSKarsten Heimrich	struct e1000_host_command_header command_header;
674ab64e1faSKarsten Heimrich	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
675ab64e1faSKarsten Heimrich};
676ab64e1faSKarsten Heimrich
677ab64e1faSKarsten Heimrich/* Host Interface "Rev 2" */
678ab64e1faSKarsten Heimrichstruct e1000_host_mng_command_header {
679ab64e1faSKarsten Heimrich	u8  command_id;
680ab64e1faSKarsten Heimrich	u8  checksum;
681ab64e1faSKarsten Heimrich	u16 reserved1;
682ab64e1faSKarsten Heimrich	u16 reserved2;
683ab64e1faSKarsten Heimrich	u16 command_length;
684ab64e1faSKarsten Heimrich};
685ab64e1faSKarsten Heimrich
686648db733SJérôme Duval#define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8
687ab64e1faSKarsten Heimrichstruct e1000_host_mng_command_info {
688ab64e1faSKarsten Heimrich	struct e1000_host_mng_command_header command_header;
689ab64e1faSKarsten Heimrich	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
690ab64e1faSKarsten Heimrich};
691ab64e1faSKarsten Heimrich
692ab64e1faSKarsten Heimrich#include "e1000_mac.h"
693ab64e1faSKarsten Heimrich#include "e1000_phy.h"
694ab64e1faSKarsten Heimrich#include "e1000_nvm.h"
695ab64e1faSKarsten Heimrich#include "e1000_manage.h"
696d1e17090SSiarzhuk Zharski#include "e1000_mbx.h"
697ab64e1faSKarsten Heimrich
698d57b6246SJérôme Duval/* Function pointers for the MAC. */
699ab64e1faSKarsten Heimrichstruct e1000_mac_operations {
700ab64e1faSKarsten Heimrich	s32  (*init_params)(struct e1000_hw *);
701d1e17090SSiarzhuk Zharski	s32  (*id_led_init)(struct e1000_hw *);
702ab64e1faSKarsten Heimrich	s32  (*blink_led)(struct e1000_hw *);
703d57b6246SJérôme Duval	bool (*check_mng_mode)(struct e1000_hw *);
704ab64e1faSKarsten Heimrich	s32  (*check_for_link)(struct e1000_hw *);
705ab64e1faSKarsten Heimrich	s32  (*cleanup_led)(struct e1000_hw *);
706ab64e1faSKarsten Heimrich	void (*clear_hw_cntrs)(struct e1000_hw *);
707ab64e1faSKarsten Heimrich	void (*clear_vfta)(struct e1000_hw *);
708ab64e1faSKarsten Heimrich	s32  (*get_bus_info)(struct e1000_hw *);
709ab64e1faSKarsten Heimrich	void (*set_lan_id)(struct e1000_hw *);
710ab64e1faSKarsten Heimrich	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
711ab64e1faSKarsten Heimrich	s32  (*led_on)(struct e1000_hw *);
712ab64e1faSKarsten Heimrich	s32  (*led_off)(struct e1000_hw *);
713d1e17090SSiarzhuk Zharski	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
714ab64e1faSKarsten Heimrich	s32  (*reset_hw)(struct e1000_hw *);
715ab64e1faSKarsten Heimrich	s32  (*init_hw)(struct e1000_hw *);
716ab64e1faSKarsten Heimrich	void (*shutdown_serdes)(struct e1000_hw *);
717d1e17090SSiarzhuk Zharski	void (*power_up_serdes)(struct e1000_hw *);
718ab64e1faSKarsten Heimrich	s32  (*setup_link)(struct e1000_hw *);
719ab64e1faSKarsten Heimrich	s32  (*setup_physical_interface)(struct e1000_hw *);
720ab64e1faSKarsten Heimrich	s32  (*setup_led)(struct e1000_hw *);
721ab64e1faSKarsten Heimrich	void (*write_vfta)(struct e1000_hw *, u32, u32);
722ab64e1faSKarsten Heimrich	void (*config_collision_dist)(struct e1000_hw *);
723b3fb200fSJérôme Duval	int  (*rar_set)(struct e1000_hw *, u8*, u32);
724ab64e1faSKarsten Heimrich	s32  (*read_mac_addr)(struct e1000_hw *);
725ab64e1faSKarsten Heimrich	s32  (*validate_mdi_setting)(struct e1000_hw *);
726d57b6246SJérôme Duval	s32  (*set_obff_timer)(struct e1000_hw *, u32);
727648db733SJérôme Duval	s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
728648db733SJérôme Duval	void (*release_swfw_sync)(struct e1000_hw *, u16);
729648db733SJérôme Duval};
730648db733SJérôme Duval
731d57b6246SJérôme Duval/* When to use various PHY register access functions:
732648db733SJérôme Duval *
733648db733SJérôme Duval *                 Func   Caller
734648db733SJérôme Duval *   Function      Does   Does    When to use
735648db733SJérôme Duval *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
736648db733SJérôme Duval *   X_reg         L,P,A  n/a     for simple PHY reg accesses
737648db733SJérôme Duval *   X_reg_locked  P,A    L       for multiple accesses of different regs
738648db733SJérôme Duval *                                on different pages
739648db733SJérôme Duval *   X_reg_page    A      L,P     for multiple accesses of different regs
740648db733SJérôme Duval *                                on the same page
741648db733SJérôme Duval *
742648db733SJérôme Duval * Where X=[read|write], L=locking, P=sets page, A=register access
743648db733SJérôme Duval *
744648db733SJérôme Duval */
745ab64e1faSKarsten Heimrichstruct e1000_phy_operations {
746ab64e1faSKarsten Heimrich	s32  (*init_params)(struct e1000_hw *);
747ab64e1faSKarsten Heimrich	s32  (*acquire)(struct e1000_hw *);
748ab64e1faSKarsten Heimrich	s32  (*cfg_on_link_up)(struct e1000_hw *);
749ab64e1faSKarsten Heimrich	s32  (*check_polarity)(struct e1000_hw *);
750ab64e1faSKarsten Heimrich	s32  (*check_reset_block)(struct e1000_hw *);
751ab64e1faSKarsten Heimrich	s32  (*commit)(struct e1000_hw *);
752ab64e1faSKarsten Heimrich	s32  (*force_speed_duplex)(struct e1000_hw *);
753ab64e1faSKarsten Heimrich	s32  (*get_cfg_done)(struct e1000_hw *hw);
754ab64e1faSKarsten Heimrich	s32  (*get_cable_length)(struct e1000_hw *);
755ab64e1faSKarsten Heimrich	s32  (*get_info)(struct e1000_hw *);
756648db733SJérôme Duval	s32  (*set_page)(struct e1000_hw *, u16);
757ab64e1faSKarsten Heimrich	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
758d1e17090SSiarzhuk Zharski	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
759648db733SJérôme Duval	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
760ab64e1faSKarsten Heimrich	void (*release)(struct e1000_hw *);
761ab64e1faSKarsten Heimrich	s32  (*reset)(struct e1000_hw *);
762ab64e1faSKarsten Heimrich	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
763ab64e1faSKarsten Heimrich	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
764ab64e1faSKarsten Heimrich	s32  (*write_reg)(struct e1000_hw *, u32, u16);
765d1e17090SSiarzhuk Zharski	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
766648db733SJérôme Duval	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
767ab64e1faSKarsten Heimrich	void (*power_up)(struct e1000_hw *);
768ab64e1faSKarsten Heimrich	void (*power_down)(struct e1000_hw *);
769648db733SJérôme Duval	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
770648db733SJérôme Duval	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
771ab64e1faSKarsten Heimrich};
772ab64e1faSKarsten Heimrich
773d57b6246SJérôme Duval/* Function pointers for the NVM. */
774ab64e1faSKarsten Heimrichstruct e1000_nvm_operations {
775ab64e1faSKarsten Heimrich	s32  (*init_params)(struct e1000_hw *);
776ab64e1faSKarsten Heimrich	s32  (*acquire)(struct e1000_hw *);
777ab64e1faSKarsten Heimrich	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
778ab64e1faSKarsten Heimrich	void (*release)(struct e1000_hw *);
779ab64e1faSKarsten Heimrich	void (*reload)(struct e1000_hw *);
780ab64e1faSKarsten Heimrich	s32  (*update)(struct e1000_hw *);
781ab64e1faSKarsten Heimrich	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
782ab64e1faSKarsten Heimrich	s32  (*validate)(struct e1000_hw *);
783ab64e1faSKarsten Heimrich	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
784ab64e1faSKarsten Heimrich};
785ab64e1faSKarsten Heimrich
786ab64e1faSKarsten Heimrichstruct e1000_mac_info {
787ab64e1faSKarsten Heimrich	struct e1000_mac_operations ops;
7888060e778SJérôme Duval	u8 addr[ETH_ADDR_LEN];
7898060e778SJérôme Duval	u8 perm_addr[ETH_ADDR_LEN];
790ab64e1faSKarsten Heimrich
791ab64e1faSKarsten Heimrich	enum e1000_mac_type type;
792ab64e1faSKarsten Heimrich
793ab64e1faSKarsten Heimrich	u32 collision_delta;
794ab64e1faSKarsten Heimrich	u32 ledctl_default;
795ab64e1faSKarsten Heimrich	u32 ledctl_mode1;
796ab64e1faSKarsten Heimrich	u32 ledctl_mode2;
797ab64e1faSKarsten Heimrich	u32 mc_filter_type;
798ab64e1faSKarsten Heimrich	u32 tx_packet_delta;
799ab64e1faSKarsten Heimrich	u32 txcw;
800ab64e1faSKarsten Heimrich
801ab64e1faSKarsten Heimrich	u16 current_ifs_val;
802ab64e1faSKarsten Heimrich	u16 ifs_max_val;
803ab64e1faSKarsten Heimrich	u16 ifs_min_val;
804ab64e1faSKarsten Heimrich	u16 ifs_ratio;
805ab64e1faSKarsten Heimrich	u16 ifs_step_size;
806ab64e1faSKarsten Heimrich	u16 mta_reg_count;
807d1e17090SSiarzhuk Zharski	u16 uta_reg_count;
808d1e17090SSiarzhuk Zharski
809d1e17090SSiarzhuk Zharski	/* Maximum size of the MTA register table in all supported adapters */
810b3fb200fSJérôme Duval#define MAX_MTA_REG 128
811d1e17090SSiarzhuk Zharski	u32 mta_shadow[MAX_MTA_REG];
812ab64e1faSKarsten Heimrich	u16 rar_entry_count;
813ab64e1faSKarsten Heimrich
814ab64e1faSKarsten Heimrich	u8  forced_speed_duplex;
815ab64e1faSKarsten Heimrich
816ab64e1faSKarsten Heimrich	bool adaptive_ifs;
817d1e17090SSiarzhuk Zharski	bool has_fwsm;
818ab64e1faSKarsten Heimrich	bool arc_subsystem_valid;
819ab64e1faSKarsten Heimrich	bool asf_firmware_present;
820ab64e1faSKarsten Heimrich	bool autoneg;
821ab64e1faSKarsten Heimrich	bool autoneg_failed;
822ab64e1faSKarsten Heimrich	bool get_link_status;
823ab64e1faSKarsten Heimrich	bool in_ifs_mode;
824ab64e1faSKarsten Heimrich	bool report_tx_early;
825d1e17090SSiarzhuk Zharski	enum e1000_serdes_link_state serdes_link_state;
826ab64e1faSKarsten Heimrich	bool serdes_has_link;
827ab64e1faSKarsten Heimrich	bool tx_pkt_filtering;
828b3fb200fSJérôme Duval	u32  max_frame_size;
829ab64e1faSKarsten Heimrich};
830ab64e1faSKarsten Heimrich
831ab64e1faSKarsten Heimrichstruct e1000_phy_info {
832ab64e1faSKarsten Heimrich	struct e1000_phy_operations ops;
833ab64e1faSKarsten Heimrich	enum e1000_phy_type type;
834ab64e1faSKarsten Heimrich
835ab64e1faSKarsten Heimrich	enum e1000_1000t_rx_status local_rx;
836ab64e1faSKarsten Heimrich	enum e1000_1000t_rx_status remote_rx;
837ab64e1faSKarsten Heimrich	enum e1000_ms_type ms_type;
838ab64e1faSKarsten Heimrich	enum e1000_ms_type original_ms_type;
839ab64e1faSKarsten Heimrich	enum e1000_rev_polarity cable_polarity;
840ab64e1faSKarsten Heimrich	enum e1000_smart_speed smart_speed;
841ab64e1faSKarsten Heimrich
842ab64e1faSKarsten Heimrich	u32 addr;
843ab64e1faSKarsten Heimrich	u32 id;
844ab64e1faSKarsten Heimrich	u32 reset_delay_us; /* in usec */
845ab64e1faSKarsten Heimrich	u32 revision;
846ab64e1faSKarsten Heimrich
847ab64e1faSKarsten Heimrich	enum e1000_media_type media_type;
848ab64e1faSKarsten Heimrich
849ab64e1faSKarsten Heimrich	u16 autoneg_advertised;
850ab64e1faSKarsten Heimrich	u16 autoneg_mask;
851ab64e1faSKarsten Heimrich	u16 cable_length;
852ab64e1faSKarsten Heimrich	u16 max_cable_length;
853ab64e1faSKarsten Heimrich	u16 min_cable_length;
854ab64e1faSKarsten Heimrich
855ab64e1faSKarsten Heimrich	u8 mdix;
856ab64e1faSKarsten Heimrich
857ab64e1faSKarsten Heimrich	bool disable_polarity_correction;
858ab64e1faSKarsten Heimrich	bool is_mdix;
859ab64e1faSKarsten Heimrich	bool polarity_correction;
860ab64e1faSKarsten Heimrich	bool speed_downgraded;
861ab64e1faSKarsten Heimrich	bool autoneg_wait_to_complete;
862ab64e1faSKarsten Heimrich};
863ab64e1faSKarsten Heimrich
864ab64e1faSKarsten Heimrichstruct e1000_nvm_info {
865ab64e1faSKarsten Heimrich	struct e1000_nvm_operations ops;
866ab64e1faSKarsten Heimrich	enum e1000_nvm_type type;
867ab64e1faSKarsten Heimrich	enum e1000_nvm_override override;
868ab64e1faSKarsten Heimrich
869ab64e1faSKarsten Heimrich	u32 flash_bank_size;
870ab64e1faSKarsten Heimrich	u32 flash_base_addr;
871ab64e1faSKarsten Heimrich
872ab64e1faSKarsten Heimrich	u16 word_size;
873ab64e1faSKarsten Heimrich	u16 delay_usec;
874ab64e1faSKarsten Heimrich	u16 address_bits;
875ab64e1faSKarsten Heimrich	u16 opcode_bits;
876ab64e1faSKarsten Heimrich	u16 page_size;
877ab64e1faSKarsten Heimrich};
878ab64e1faSKarsten Heimrich
879ab64e1faSKarsten Heimrichstruct e1000_bus_info {
880ab64e1faSKarsten Heimrich	enum e1000_bus_type type;
881ab64e1faSKarsten Heimrich	enum e1000_bus_speed speed;
882ab64e1faSKarsten Heimrich	enum e1000_bus_width width;
883ab64e1faSKarsten Heimrich
884ab64e1faSKarsten Heimrich	u16 func;
885ab64e1faSKarsten Heimrich	u16 pci_cmd_word;
886ab64e1faSKarsten Heimrich};
887ab64e1faSKarsten Heimrich
888ab64e1faSKarsten Heimrichstruct e1000_fc_info {
889648db733SJérôme Duval	u32 high_water;  /* Flow control high-water mark */
890648db733SJérôme Duval	u32 low_water;  /* Flow control low-water mark */
891648db733SJérôme Duval	u16 pause_time;  /* Flow control pause timer */
892648db733SJérôme Duval	u16 refresh_time;  /* Flow control refresh timer */
893648db733SJérôme Duval	bool send_xon;  /* Flow control send XON */
894648db733SJérôme Duval	bool strict_ieee;  /* Strict IEEE mode */
895648db733SJérôme Duval	enum e1000_fc_mode current_mode;  /* FC mode in effect */
896648db733SJérôme Duval	enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
897ab64e1faSKarsten Heimrich};
898ab64e1faSKarsten Heimrich
899d1e17090SSiarzhuk Zharskistruct e1000_mbx_operations {
900d1e17090SSiarzhuk Zharski	s32 (*init_params)(struct e1000_hw *hw);
901d1e17090SSiarzhuk Zharski	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
902d1e17090SSiarzhuk Zharski	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
903d1e17090SSiarzhuk Zharski	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
904d1e17090SSiarzhuk Zharski	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
905d1e17090SSiarzhuk Zharski	s32 (*check_for_msg)(struct e1000_hw *, u16);
906d1e17090SSiarzhuk Zharski	s32 (*check_for_ack)(struct e1000_hw *, u16);
907d1e17090SSiarzhuk Zharski	s32 (*check_for_rst)(struct e1000_hw *, u16);
908d1e17090SSiarzhuk Zharski};
909d1e17090SSiarzhuk Zharski
910d1e17090SSiarzhuk Zharskistruct e1000_mbx_stats {
911d1e17090SSiarzhuk Zharski	u32 msgs_tx;
912d1e17090SSiarzhuk Zharski	u32 msgs_rx;
913d1e17090SSiarzhuk Zharski
914d1e17090SSiarzhuk Zharski	u32 acks;
915d1e17090SSiarzhuk Zharski	u32 reqs;
916d1e17090SSiarzhuk Zharski	u32 rsts;
917d1e17090SSiarzhuk Zharski};
918d1e17090SSiarzhuk Zharski
919d1e17090SSiarzhuk Zharskistruct e1000_mbx_info {
920d1e17090SSiarzhuk Zharski	struct e1000_mbx_operations ops;
921d1e17090SSiarzhuk Zharski	struct e1000_mbx_stats stats;
922d1e17090SSiarzhuk Zharski	u32 timeout;
923d1e17090SSiarzhuk Zharski	u32 usec_delay;
924d1e17090SSiarzhuk Zharski	u16 size;
925d1e17090SSiarzhuk Zharski};
926d1e17090SSiarzhuk Zharski
927ab64e1faSKarsten Heimrichstruct e1000_dev_spec_82541 {
928ab64e1faSKarsten Heimrich	enum e1000_dsp_config dsp_config;
929ab64e1faSKarsten Heimrich	enum e1000_ffe_config ffe_config;
930ab64e1faSKarsten Heimrich	u16 spd_default;
931ab64e1faSKarsten Heimrich	bool phy_init_script;
932ab64e1faSKarsten Heimrich};
933ab64e1faSKarsten Heimrich
934ab64e1faSKarsten Heimrichstruct e1000_dev_spec_82542 {
935ab64e1faSKarsten Heimrich	bool dma_fairness;
936ab64e1faSKarsten Heimrich};
937ab64e1faSKarsten Heimrich
938ab64e1faSKarsten Heimrichstruct e1000_dev_spec_82543 {
939ab64e1faSKarsten Heimrich	u32  tbi_compatibility;
940ab64e1faSKarsten Heimrich	bool dma_fairness;
941ab64e1faSKarsten Heimrich	bool init_phy_disabled;
942ab64e1faSKarsten Heimrich};
943ab64e1faSKarsten Heimrich
944ab64e1faSKarsten Heimrichstruct e1000_dev_spec_82571 {
945ab64e1faSKarsten Heimrich	bool laa_is_present;
946d1e17090SSiarzhuk Zharski	u32 smb_counter;
947d1e17090SSiarzhuk Zharski};
948d1e17090SSiarzhuk Zharski
949d1e17090SSiarzhuk Zharskistruct e1000_dev_spec_80003es2lan {
950d1e17090SSiarzhuk Zharski	bool  mdic_wa_enable;
951ab64e1faSKarsten Heimrich};
952ab64e1faSKarsten Heimrich
953ab64e1faSKarsten Heimrichstruct e1000_shadow_ram {
954ab64e1faSKarsten Heimrich	u16  value;
955ab64e1faSKarsten Heimrich	bool modified;
956ab64e1faSKarsten Heimrich};
957ab64e1faSKarsten Heimrich
958d57b6246SJérôme Duval#define E1000_SHADOW_RAM_WORDS		2048
959ab64e1faSKarsten Heimrich
960b3fb200fSJérôme Duval/* I218 PHY Ultra Low Power (ULP) states */
961b3fb200fSJérôme Duvalenum e1000_ulp_state {
962b3fb200fSJérôme Duval	e1000_ulp_state_unknown,
963b3fb200fSJérôme Duval	e1000_ulp_state_off,
964b3fb200fSJérôme Duval	e1000_ulp_state_on,
965b3fb200fSJérôme Duval};
966b3fb200fSJérôme Duval
967ab64e1faSKarsten Heimrichstruct e1000_dev_spec_ich8lan {
968ab64e1faSKarsten Heimrich	bool kmrn_lock_loss_workaround_enabled;
969ab64e1faSKarsten Heimrich	struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
970d1e17090SSiarzhuk Zharski	bool nvm_k1_enabled;
971b3fb200fSJérôme Duval	bool disable_k1_off;
972d1e17090SSiarzhuk Zharski	bool eee_disable;
973d57b6246SJérôme Duval	u16 eee_lp_ability;
974b3fb200fSJérôme Duval	enum e1000_ulp_state ulp_state;
975b3fb200fSJérôme Duval	bool ulp_capability_disabled;
976b3fb200fSJérôme Duval	bool during_suspend_flow;
977b3fb200fSJérôme Duval	bool during_dpg_exit;
978ab64e1faSKarsten Heimrich};
979ab64e1faSKarsten Heimrich
980ab64e1faSKarsten Heimrichstruct e1000_dev_spec_82575 {
981ab64e1faSKarsten Heimrich	bool sgmii_active;
982d1e17090SSiarzhuk Zharski	bool global_device_reset;
9838060e778SJérôme Duval	bool eee_disable;
984648db733SJérôme Duval	bool module_plugged;
985d57b6246SJérôme Duval	bool clear_semaphore_once;
986648db733SJérôme Duval	u32 mtu;
987d57b6246SJérôme Duval	struct sfp_e1000_flags eth_flags;
988b3fb200fSJérôme Duval	u8 media_port;
989b3fb200fSJérôme Duval	bool media_changed;
990ab64e1faSKarsten Heimrich};
991ab64e1faSKarsten Heimrich
992ab64e1faSKarsten Heimrichstruct e1000_dev_spec_vf {
9938060e778SJérôme Duval	u32 vf_number;
9948060e778SJérôme Duval	u32 v2p_mailbox;
995ab64e1faSKarsten Heimrich};
996ab64e1faSKarsten Heimrich
997ab64e1faSKarsten Heimrichstruct e1000_hw {
998ab64e1faSKarsten Heimrich	void *back;
999ab64e1faSKarsten Heimrich
1000ab64e1faSKarsten Heimrich	u8 *hw_addr;
1001ab64e1faSKarsten Heimrich	u8 *flash_address;
1002ab64e1faSKarsten Heimrich	unsigned long io_base;
1003ab64e1faSKarsten Heimrich
1004ab64e1faSKarsten Heimrich	struct e1000_mac_info  mac;
1005ab64e1faSKarsten Heimrich	struct e1000_fc_info   fc;
1006ab64e1faSKarsten Heimrich	struct e1000_phy_info  phy;
1007ab64e1faSKarsten Heimrich	struct e1000_nvm_info  nvm;
1008ab64e1faSKarsten Heimrich	struct e1000_bus_info  bus;
1009d1e17090SSiarzhuk Zharski	struct e1000_mbx_info mbx;
1010ab64e1faSKarsten Heimrich	struct e1000_host_mng_dhcp_cookie mng_cookie;
1011ab64e1faSKarsten Heimrich
1012ab64e1faSKarsten Heimrich	union {
10138060e778SJérôme Duval		struct e1000_dev_spec_82541 _82541;
10148060e778SJérôme Duval		struct e1000_dev_spec_82542 _82542;
10158060e778SJérôme Duval		struct e1000_dev_spec_82543 _82543;
10168060e778SJérôme Duval		struct e1000_dev_spec_82571 _82571;
1017d1e17090SSiarzhuk Zharski		struct e1000_dev_spec_80003es2lan _80003es2lan;
10188060e778SJérôme Duval		struct e1000_dev_spec_ich8lan ich8lan;
10198060e778SJérôme Duval		struct e1000_dev_spec_82575 _82575;
10208060e778SJérôme Duval		struct e1000_dev_spec_vf vf;
1021ab64e1faSKarsten Heimrich	} dev_spec;
1022ab64e1faSKarsten Heimrich
1023ab64e1faSKarsten Heimrich	u16 device_id;
1024ab64e1faSKarsten Heimrich	u16 subsystem_vendor_id;
1025ab64e1faSKarsten Heimrich	u16 subsystem_device_id;
1026ab64e1faSKarsten Heimrich