1a950a7ffSIthamar R. Adema/*
2a950a7ffSIthamar R. Adema** $Id: buslogic.h,v 1.2 1998/04/21 00:51:57 swetland Exp $
3a950a7ffSIthamar R. Adema**
4a950a7ffSIthamar R. Adema** Constants and Structures for BusLogic MultiMaster Controllers
5a950a7ffSIthamar R. Adema** Copyright 1998, Brian J. Swetland <swetland@frotz.net>
6a950a7ffSIthamar R. Adema**
7a950a7ffSIthamar R. Adema** This file may be used under the terms of the Be Sample Code License.
8a950a7ffSIthamar R. Adema*/
9a950a7ffSIthamar R. Adema
10a950a7ffSIthamar R. Adema#define PCI_VENDOR_BUSLOGIC     0x104b
11a950a7ffSIthamar R. Adema#define PCI_DEVICE_MULTIMASTER  0x1040
12a950a7ffSIthamar R. Adema
13a950a7ffSIthamar R. Adema
14a950a7ffSIthamar R. Adema/* BusLogic MultiMaster Register Definitions
15a950a7ffSIthamar R. Adema** cf. Technical Reference Manual, pp. 1-10 - 1-17
16a950a7ffSIthamar R. Adema*/
17a950a7ffSIthamar R. Adema#define BL_CONTROL_REG    (bl->iobase)
18a950a7ffSIthamar R. Adema#define BL_CONTROL_RHARD  0x80           /* Controller Hard Reset           */
19a950a7ffSIthamar R. Adema#define BL_CONTROL_RSOFT  0x40           /* Controller Soft Reset           */
20a950a7ffSIthamar R. Adema#define BL_CONTROL_RINT   0x20           /* Reset (Acknowledge) Interrupts  */
21a950a7ffSIthamar R. Adema#define BL_CONTROL_RSBUS  0x10           /* Reset SCSI Bus                  */
22a950a7ffSIthamar R. Adema
23a950a7ffSIthamar R. Adema#define BL_STATUS_REG     (bl->iobase)
24a950a7ffSIthamar R. Adema#define BL_STATUS_DACT    0x80           /* Diagnostic Active               */
25a950a7ffSIthamar R. Adema#define BL_STATUS_DFAIL   0x40           /* Diagnostic Failure              */
26a950a7ffSIthamar R. Adema#define BL_STATUS_INREQ   0x20           /* Initialization Required         */
27a950a7ffSIthamar R. Adema#define BL_STATUS_HARDY   0x10           /* Host Adapter Ready              */
28a950a7ffSIthamar R. Adema#define BL_STATUS_CPRBSY  0x08           /* Command/Param Out Register Busy */
29a950a7ffSIthamar R. Adema#define BL_STATUS_DIRRDY  0x04           /* Data In Register Ready          */
30a950a7ffSIthamar R. Adema#define BL_STATUS_CMDINV  0x01           /* Command Invalid                 */
31a950a7ffSIthamar R. Adema
32a950a7ffSIthamar R. Adema#define BL_COMMAND_REG    (bl->iobase + 1)
33a950a7ffSIthamar R. Adema#define BL_DATA_REG       (bl->iobase + 1)
34a950a7ffSIthamar R. Adema
35a950a7ffSIthamar R. Adema#define BL_INT_REG        (bl->iobase + 2)
36a950a7ffSIthamar R. Adema#define BL_INT_INTV       0x80           /* Interrupt Valid                 */
37a950a7ffSIthamar R. Adema#define BL_INT_RSTS       0x08           /* SCSI Reset State                */
38a950a7ffSIthamar R. Adema#define BL_INT_CMDC       0x04           /* Command Complete                */
39a950a7ffSIthamar R. Adema#define BL_INT_MBOR       0x02           /* Mailbox Out Ready               */
40a950a7ffSIthamar R. Adema#define BL_INT_IMBL       0x01           /* Incoming Mailbox Loaded         */
41a950a7ffSIthamar R. Adema
42a950a7ffSIthamar R. Adema
43a950a7ffSIthamar R. Adema#define MAX_SCATTER 130
44a950a7ffSIthamar R. Adema
45a950a7ffSIthamar R. Adematypedef struct _bl_ccb32
46a950a7ffSIthamar R. Adema{
47a950a7ffSIthamar R. Adema        /* buslogic ccb structure */
48a950a7ffSIthamar R. Adema    uchar   opcode;         /* operation code - see CCB_OP_* below         */
49a950a7ffSIthamar R. Adema    uchar   direction;      /* data direction control - see CCB_DIR_*      */
50a950a7ffSIthamar R. Adema    uchar   length_cdb;     /* length of the cdb                           */
51a950a7ffSIthamar R. Adema    uchar   length_sense;   /* length of sense data block                  */
52a950a7ffSIthamar R. Adema    uint32  length_data;    /* length of data block                        */
53a950a7ffSIthamar R. Adema    uint32  data;           /* 32bit physical pointer to data or s/g table */
54a950a7ffSIthamar R. Adema    uchar   _reserved1;     /* set to zero                                 */
55a950a7ffSIthamar R. Adema    uchar   _reserved2;     /* set to zero                                 */
56a950a7ffSIthamar R. Adema    uchar   btstat;         /* Host Adapter Status Return                  */
57a950a7ffSIthamar R. Adema    uchar   sdstat;         /* SCSI Device Status Return                   */
58a950a7ffSIthamar R. Adema    uchar   target_id;      /* Target SCSI ID                              */
59a950a7ffSIthamar R. Adema    uchar   lun_tag;        /* bits 0-2 = LUN, | with CCB_TAG_*            */
60a950a7ffSIthamar R. Adema    uchar   cdb[12];        /* SCSI CDB area                               */
61a950a7ffSIthamar R. Adema    uchar   ccb_control;    /* controle bits - see CCB_CONTROL_*           */
62a950a7ffSIthamar R. Adema    uchar   link_id;        /* id number for linked CCB's                  */
63a950a7ffSIthamar R. Adema    uint32  link;           /* 32bit physical pointer to a linked CCB      */
64a950a7ffSIthamar R. Adema    uint32  sense;          /* 32bit physical pointer to the sense datablk */
65a950a7ffSIthamar R. Adema
66a950a7ffSIthamar R. Adema        /* used by the driver */
67a950a7ffSIthamar R. Adema
68a950a7ffSIthamar R. Adema    sem_id  done;           /* used by ISR for completion notification     */
69a950a7ffSIthamar R. Adema    int completion_code;    /* completion code storage from mailbox        */
70a950a7ffSIthamar R. Adema    struct _bl_ccb32 *next; /* chain pointer for CCB32 freelist            */
71a950a7ffSIthamar R. Adema    uint _reserved[3];      /* padding                                     */
72a950a7ffSIthamar R. Adema} BL_CCB32;
73a950a7ffSIthamar R. Adema
74a950a7ffSIthamar R. Adematypedef struct
75a950a7ffSIthamar R. Adema{
76a950a7ffSIthamar R. Adema        /* used by the driver */
77a950a7ffSIthamar R. Adema    uchar sensedata[256];   /* data area for sense data return             */
78a950a7ffSIthamar R. Adema
79a950a7ffSIthamar R. Adema    struct {
80a950a7ffSIthamar R. Adema        uint length;        /* length of this SG segment (bytes)           */
81a950a7ffSIthamar R. Adema        uint phys;          /* physical address of this SG segment         */
82a950a7ffSIthamar R. Adema    } sg[MAX_SCATTER];      /* scatter/gather table                        */
83a950a7ffSIthamar R. Adema} BL_PRIV;
84a950a7ffSIthamar R. Adema
85a950a7ffSIthamar R. Adema#define BL_CCB_TAG_SIMPLE    0x20
86a950a7ffSIthamar R. Adema#define BL_CCB_TAG_HEAD      0x60
87a950a7ffSIthamar R. Adema#define BL_CCB_TAG_ORDERED   0xA0
88a950a7ffSIthamar R. Adema
89a950a7ffSIthamar R. Adema#define BL_CCB_OP_INITIATE           0x00
90a950a7ffSIthamar R. Adema#define BL_CCB_OP_INITIATE_SG        0x02
91a950a7ffSIthamar R. Adema
92a950a7ffSIthamar R. Adema/* returns dif between req/actual xmit bytecount */
93a950a7ffSIthamar R. Adema#define BL_CCB_OP_INITIATE_RETLEN    0x03
94a950a7ffSIthamar R. Adema#define BL_CCB_OP_INITIATE_RETLEN_SG 0x04
95a950a7ffSIthamar R. Adema#define BL_CCB_OP_SCSI_BUS_RESET     0x81
96a950a7ffSIthamar R. Adema
97a950a7ffSIthamar R. Adema#define BL_CCB_DIR_DEFAULT   0x00  /* transfer in direction native to scsi */
98a950a7ffSIthamar R. Adema#define BL_CCB_DIR_INBOUND   0x08
99a950a7ffSIthamar R. Adema#define BL_CCB_DIR_OUTBOUND  0x10
100a950a7ffSIthamar R. Adema#define BL_CCB_DIR_NO_XFER   0x18
101a950a7ffSIthamar R. Adema
102a950a7ffSIthamar R. Adematypedef struct
103a950a7ffSIthamar R. Adema{
104a950a7ffSIthamar R. Adema    uint32 ccb_phys;
105a950a7ffSIthamar R. Adema    uchar _reserved1;
106a950a7ffSIthamar R. Adema    uchar _reserved2;
107a950a7ffSIthamar R. Adema    uchar _reserved3;
108a950a7ffSIthamar R. Adema    uchar action_code;
109a950a7ffSIthamar R. Adema} BL_Out_Mailbox32;
110a950a7ffSIthamar R. Adema
111a950a7ffSIthamar R. Adema#define BL_ActionCode_NotInUse   0x00
112a950a7ffSIthamar R. Adema#define BL_ActionCode_Start      0x01
113a950a7ffSIthamar R. Adema#define BL_ActionCode_Abort      0x02
114a950a7ffSIthamar R. Adema
115a950a7ffSIthamar R. Adema
116a950a7ffSIthamar R. Adema
117a950a7ffSIthamar R. Adematypedef struct
118a950a7ffSIthamar R. Adema{
119a950a7ffSIthamar R. Adema    uint32 ccb_phys;
120a950a7ffSIthamar R. Adema    uchar btstat;
121a950a7ffSIthamar R. Adema    uchar sdstat;
122a950a7ffSIthamar R. Adema    uchar _reserved1;
123a950a7ffSIthamar R. Adema    uchar completion_code;
124a950a7ffSIthamar R. Adema} BL_In_Mailbox32;
125a950a7ffSIthamar R. Adema
126a950a7ffSIthamar R. Adema#define BL_CompletionCode_NotInUse     0x00
127a950a7ffSIthamar R. Adema#define BL_CompletionCode_NoError      0x01
128a950a7ffSIthamar R. Adema#define BL_CompletionCode_HostAbort    0x02
129a950a7ffSIthamar R. Adema#define BL_CompletionCode_NotFound     0x03
130a950a7ffSIthamar R. Adema#define BL_CompletionCode_Error        0x04
131a950a7ffSIthamar R. Adema
132a950a7ffSIthamar R. Adema#define MAX_CCB_COUNT 32
133a950a7ffSIthamar R. Adema
134a950a7ffSIthamar R. Adema/* Host Adapter State Structure
135a950a7ffSIthamar R. Adema**
136a950a7ffSIthamar R. Adema*/
137a950a7ffSIthamar R. Adematypedef struct
138a950a7ffSIthamar R. Adema{
139a950a7ffSIthamar R. Adema    int id;                         /* board id 0, 1, ...    */
140a950a7ffSIthamar R. Adema    int done;                       /* command complete from ISR */
141a950a7ffSIthamar R. Adema    int irq;                        /* board's irq */
142a950a7ffSIthamar R. Adema    int iobase;                     /* base io address */
143a950a7ffSIthamar R. Adema	int scsi_id;					/* board's SCSI id */
144a950a7ffSIthamar R. Adema	int wide;                       /* wide target id's allowed */
145a950a7ffSIthamar R. Adema    long reqid;                     /* request counter for debugging */
146a950a7ffSIthamar R. Adema
147a950a7ffSIthamar R. Adema	char productname[16];
148a950a7ffSIthamar R. Adema
149a950a7ffSIthamar R. Adema    uint32 phys_to_virt;            /* adjustment for mapping BL_CCB32's */
150a950a7ffSIthamar R. Adema    uint32 virt_to_phys;            /* between virt and phys addrs       */
151a950a7ffSIthamar R. Adema
152a950a7ffSIthamar R. Adema    uint32 phys_mailboxes;          /* phys addr of mailboxes */
153a950a7ffSIthamar R. Adema
154a950a7ffSIthamar R. Adema    sem_id hw_lock;                 /* lock for hardware and outbox access */
155a950a7ffSIthamar R. Adema    sem_id ccb_lock;                /* lock protecting the ccb chain */
156a950a7ffSIthamar R. Adema    sem_id ccb_count;               /* counting sem protecting the ccb chain */
157a950a7ffSIthamar R. Adema
158a950a7ffSIthamar R. Adema    int box_count;
159a950a7ffSIthamar R. Adema    int out_nextbox;
160a950a7ffSIthamar R. Adema    int in_nextbox;
161a950a7ffSIthamar R. Adema    BL_Out_Mailbox32  *out_boxes;
162a950a7ffSIthamar R. Adema    BL_In_Mailbox32   *in_boxes;
163a950a7ffSIthamar R. Adema
164a950a7ffSIthamar R. Adema    BL_CCB32 *ccb;                  /* table of MAX_CCB_COUNT CCB's */
165a950a7ffSIthamar R. Adema    BL_CCB32 *first_ccb;            /* head of ccb freelist         */
166a950a7ffSIthamar R. Adema} BusLogic;
167a950a7ffSIthamar R. Adema
168