1/*-
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the acknowledgement as bellow:
16 *
17 *    This product includes software developed by K. Kobayashi and H. Shimokawa
18 *
19 * 4. The name of the author may not be used to endorse or promote products
20 *    derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/dev/firewire/fwohcireg.h,v 1.23 2007/04/30 14:06:30 simokawa Exp $
35 *
36 */
37#define		PCI_CBMEM		PCIR_BAR(0)
38
39#define		FW_VENDORID_NATSEMI	0x100Bu
40#define		FW_VENDORID_NEC		0x1033u
41#define		FW_VENDORID_SIS		0x1039u
42#define		FW_VENDORID_TI		0x104cu
43#define		FW_VENDORID_SONY	0x104du
44#define		FW_VENDORID_VIA		0x1106u
45#define		FW_VENDORID_RICOH	0x1180u
46#define		FW_VENDORID_APPLE	0x106bu
47#define		FW_VENDORID_LUCENT	0x11c1u
48#define		FW_VENDORID_INTEL	0x8086u
49#define		FW_VENDORID_ADAPTEC	0x9004u
50#define		FW_VENDORID_SUN		0x108eu
51
52#define		FW_DEVICE_CS4210	(0x000fu << 16)
53#define		FW_DEVICE_UPD861	(0x0063u << 16)
54#define		FW_DEVICE_UPD871	(0x00ceu << 16)
55#define		FW_DEVICE_UPD72870	(0x00cdu << 16)
56#define		FW_DEVICE_UPD72873	(0x00e7u << 16)
57#define		FW_DEVICE_UPD72874	(0x00f2u << 16)
58#define		FW_DEVICE_TITSB22	(0x8009u << 16)
59#define		FW_DEVICE_TITSB23	(0x8019u << 16)
60#define		FW_DEVICE_TITSB26	(0x8020u << 16)
61#define		FW_DEVICE_TITSB43	(0x8021u << 16)
62#define		FW_DEVICE_TITSB43A	(0x8023u << 16)
63#define		FW_DEVICE_TITSB43AB23	(0x8024u << 16)
64#define		FW_DEVICE_TITSB82AA2	(0x8025u << 16)
65#define		FW_DEVICE_TITSB43AB21	(0x8026u << 16)
66#define		FW_DEVICE_TIPCI4410A	(0x8017u << 16)
67#define		FW_DEVICE_TIPCI4450	(0x8011u << 16)
68#define		FW_DEVICE_TIPCI4451	(0x8027u << 16)
69#define		FW_DEVICE_CXD1947	(0x8009u << 16)
70#define		FW_DEVICE_CXD3222	(0x8039u << 16)
71#define		FW_DEVICE_VT6306	(0x3044u << 16)
72#define		FW_DEVICE_R5C551	(0x0551u << 16)
73#define		FW_DEVICE_R5C552	(0x0552u << 16)
74#define		FW_DEVICE_PANGEA	(0x0030u << 16)
75#define		FW_DEVICE_UNINORTH	(0x0031u << 16)
76#define		FW_DEVICE_AIC5800	(0x5800u << 16)
77#define		FW_DEVICE_FW322		(0x5811u << 16)
78#define		FW_DEVICE_7007		(0x7007u << 16)
79#define		FW_DEVICE_82372FB	(0x7605u << 16)
80#define		FW_DEVICE_PCIO2FW	(0x1102u << 16)
81
82#define PCI_INTERFACE_OHCI	0x10
83
84#define FW_OHCI_BASE_REG	0x10
85
86#define		OHCI_DMA_ITCH		0x20
87#define		OHCI_DMA_IRCH		0x20
88
89#define		OHCI_MAX_DMA_CH		(0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH)
90
91
92typedef uint32_t 	fwohcireg_t;
93
94/* for PCI */
95#if BYTE_ORDER == BIG_ENDIAN
96#ifdef __HAIKU__
97#define htole32(x) ((uint32_t)__swap_int32(x))
98#define le32toh(x) ((uint32_t)__swap_int32(x))
99#endif
100#define FWOHCI_DMA_WRITE(x, y)	((x) = htole32(y))
101#define FWOHCI_DMA_READ(x)	le32toh(x)
102#define FWOHCI_DMA_SET(x, y)	((x) |= htole32(y))
103#define FWOHCI_DMA_CLEAR(x, y)	((x) &= htole32(~(y)))
104#else
105#define FWOHCI_DMA_WRITE(x, y)	((x) = (y))
106#define FWOHCI_DMA_READ(x)	(x)
107#define FWOHCI_DMA_SET(x, y)	((x) |= (y))
108#define FWOHCI_DMA_CLEAR(x, y)	((x) &= ~(y))
109#endif
110
111struct fwohcidb {
112	union {
113		struct {
114			uint32_t cmd;
115			uint32_t addr;
116			uint32_t depend;
117			uint32_t res;
118		} desc;
119		uint32_t immed[4];
120	} db;
121#define OHCI_STATUS_SHIFT	16
122#define OHCI_COUNT_MASK		0xffff
123#define OHCI_OUTPUT_MORE	(0 << 28)
124#define OHCI_OUTPUT_LAST	(1 << 28)
125#define OHCI_INPUT_MORE		(2 << 28)
126#define OHCI_INPUT_LAST		(3 << 28)
127#define OHCI_STORE_QUAD		(4 << 28)
128#define OHCI_LOAD_QUAD		(5 << 28)
129#define OHCI_NOP		(6 << 28)
130#define OHCI_STOP		(7 << 28)
131#define OHCI_STORE		(8 << 28)
132#define OHCI_CMD_MASK		(0xf << 28)
133
134#define	OHCI_UPDATE		(1 << 27)
135
136#define OHCI_KEY_ST0		(0 << 24)
137#define OHCI_KEY_ST1		(1 << 24)
138#define OHCI_KEY_ST2		(2 << 24)
139#define OHCI_KEY_ST3		(3 << 24)
140#define OHCI_KEY_REGS		(5 << 24)
141#define OHCI_KEY_SYS		(6 << 24)
142#define OHCI_KEY_DEVICE		(7 << 24)
143#define OHCI_KEY_MASK		(7 << 24)
144
145#define OHCI_INTERRUPT_NEVER	(0 << 20)
146#define OHCI_INTERRUPT_TRUE	(1 << 20)
147#define OHCI_INTERRUPT_FALSE	(2 << 20)
148#define OHCI_INTERRUPT_ALWAYS	(3 << 20)
149
150#define OHCI_BRANCH_NEVER	(0 << 18)
151#define OHCI_BRANCH_TRUE	(1 << 18)
152#define OHCI_BRANCH_FALSE	(2 << 18)
153#define OHCI_BRANCH_ALWAYS	(3 << 18)
154#define OHCI_BRANCH_MASK	(3 << 18)
155
156#define OHCI_WAIT_NEVER		(0 << 16)
157#define OHCI_WAIT_TRUE		(1 << 16)
158#define OHCI_WAIT_FALSE		(2 << 16)
159#define OHCI_WAIT_ALWAYS	(3 << 16)
160};
161
162#define OHCI_SPD_S100 0x4
163#define OHCI_SPD_S200 0x1
164#define OHCI_SPD_S400 0x2
165
166
167#define FWOHCIEV_NOSTAT 0
168#define FWOHCIEV_LONGP 2
169#define FWOHCIEV_MISSACK 3
170#define FWOHCIEV_UNDRRUN 4
171#define FWOHCIEV_OVRRUN 5
172#define FWOHCIEV_DESCERR 6
173#define FWOHCIEV_DTRDERR 7
174#define FWOHCIEV_DTWRERR 8
175#define FWOHCIEV_BUSRST 9
176#define FWOHCIEV_TIMEOUT 0xa
177#define FWOHCIEV_TCODERR 0xb
178#define FWOHCIEV_UNKNOWN 0xe
179#define FWOHCIEV_FLUSHED 0xf
180#define FWOHCIEV_ACKCOMPL 0x11
181#define FWOHCIEV_ACKPEND 0x12
182#define FWOHCIEV_ACKBSX 0x14
183#define FWOHCIEV_ACKBSA 0x15
184#define FWOHCIEV_ACKBSB 0x16
185#define FWOHCIEV_ACKTARD 0x1b
186#define FWOHCIEV_ACKDERR 0x1d
187#define FWOHCIEV_ACKTERR 0x1e
188
189#define FWOHCIEV_MASK 0x1f
190
191struct ohci_dma{
192	fwohcireg_t	cntl;
193
194#define	OHCI_CNTL_CYCMATCH_S	(0x1 << 31)
195
196#define	OHCI_CNTL_BUFFIL	(0x1 << 31)
197#define	OHCI_CNTL_ISOHDR	(0x1 << 30)
198#define	OHCI_CNTL_CYCMATCH_R	(0x1 << 29)
199#define	OHCI_CNTL_MULTICH	(0x1 << 28)
200
201#define	OHCI_CNTL_DMA_RUN	(0x1 << 15)
202#define	OHCI_CNTL_DMA_WAKE	(0x1 << 12)
203#define	OHCI_CNTL_DMA_DEAD	(0x1 << 11)
204#define	OHCI_CNTL_DMA_ACTIVE	(0x1 << 10)
205#define	OHCI_CNTL_DMA_BT	(0x1 << 8)
206#define	OHCI_CNTL_DMA_BAD	(0x1 << 7)
207#define	OHCI_CNTL_DMA_STAT	(0xff)
208
209	fwohcireg_t	cntl_clr;
210	fwohcireg_t	dummy0;
211	fwohcireg_t	cmd;
212	fwohcireg_t	match;
213	fwohcireg_t	dummy1;
214	fwohcireg_t	dummy2;
215	fwohcireg_t	dummy3;
216};
217
218struct ohci_itdma{
219	fwohcireg_t	cntl;
220	fwohcireg_t	cntl_clr;
221	fwohcireg_t	dummy0;
222	fwohcireg_t	cmd;
223};
224
225struct ohci_registers {
226	fwohcireg_t	ver;		/* Version No. 0x0 */
227	fwohcireg_t	guid;		/* GUID_ROM No. 0x4 */
228	fwohcireg_t	retry;		/* AT retries 0x8 */
229#define FWOHCI_RETRY	0x8
230	fwohcireg_t	csr_data;	/* CSR data   0xc */
231	fwohcireg_t	csr_cmp;	/* CSR compare 0x10 */
232	fwohcireg_t	csr_cntl;	/* CSR compare 0x14 */
233	fwohcireg_t	rom_hdr;	/* config ROM ptr. 0x18 */
234	fwohcireg_t	bus_id;		/* BUS_ID 0x1c */
235	fwohcireg_t	bus_opt;	/* BUS option 0x20 */
236#define	FWOHCIGUID_H	0x24
237#define	FWOHCIGUID_L	0x28
238	fwohcireg_t	guid_hi;	/* GUID hi 0x24 */
239	fwohcireg_t	guid_lo;	/* GUID lo 0x28 */
240	fwohcireg_t	dummy0[2];	/* dummy 0x2c-0x30 */
241	fwohcireg_t	config_rom;	/* config ROM map 0x34 */
242	fwohcireg_t	post_wr_lo;	/* post write addr lo 0x38 */
243	fwohcireg_t	post_wr_hi;	/* post write addr hi 0x3c */
244	fwohcireg_t	vender;		/* vender ID 0x40 */
245	fwohcireg_t	dummy1[3];	/* dummy 0x44-0x4c */
246	fwohcireg_t	hcc_cntl_set;	/* HCC control set 0x50 */
247	fwohcireg_t	hcc_cntl_clr;	/* HCC control clr 0x54 */
248#define	OHCI_HCC_BIBIV	(1 << 31)	/* BIBimage Valid */
249#define	OHCI_HCC_BIGEND	(1 << 30)	/* noByteSwapData */
250#define	OHCI_HCC_PRPHY	(1 << 23)	/* programPhyEnable */
251#define	OHCI_HCC_PHYEN	(1 << 22)	/* aPhyEnhanceEnable */
252#define	OHCI_HCC_LPS	(1 << 19)	/* LPS */
253#define	OHCI_HCC_POSTWR	(1 << 18)	/* postedWriteEnable */
254#define	OHCI_HCC_LINKEN	(1 << 17)	/* linkEnable */
255#define	OHCI_HCC_RESET	(1 << 16)	/* softReset */
256	fwohcireg_t	dummy2[2];	/* dummy 0x58-0x5c */
257	fwohcireg_t	dummy3[1];	/* dummy 0x60 */
258	fwohcireg_t	sid_buf;	/* self id buffer 0x64 */
259	fwohcireg_t	sid_cnt;	/* self id count 0x68 */
260	fwohcireg_t	dummy4[1];	/* dummy 0x6c */
261	fwohcireg_t	ir_mask_hi_set;	/* ir mask hi set 0x70 */
262	fwohcireg_t	ir_mask_hi_clr;	/* ir mask hi set 0x74 */
263	fwohcireg_t	ir_mask_lo_set;	/* ir mask hi set 0x78 */
264	fwohcireg_t	ir_mask_lo_clr;	/* ir mask hi set 0x7c */
265#define	FWOHCI_INTSTAT		0x80
266#define	FWOHCI_INTSTATCLR	0x84
267#define	FWOHCI_INTMASK		0x88
268#define	FWOHCI_INTMASKCLR	0x8c
269	fwohcireg_t	int_stat;   /*       0x80 */
270	fwohcireg_t	int_clear;  /*       0x84 */
271	fwohcireg_t	int_mask;   /*       0x88 */
272	fwohcireg_t	int_mask_clear;   /*       0x8c */
273	fwohcireg_t	it_int_stat;   /*       0x90 */
274	fwohcireg_t	it_int_clear;  /*       0x94 */
275	fwohcireg_t	it_int_mask;   /*       0x98 */
276	fwohcireg_t	it_mask_clear;   /*       0x9c */
277	fwohcireg_t	ir_int_stat;   /*       0xa0 */
278	fwohcireg_t	ir_int_clear;  /*       0xa4 */
279	fwohcireg_t	ir_int_mask;   /*       0xa8 */
280	fwohcireg_t	ir_mask_clear;   /*       0xac */
281	fwohcireg_t	dummy5[11];	/* dummy 0xb0-d8 */
282	fwohcireg_t	fairness;   /* fairness control      0xdc */
283	fwohcireg_t	link_cntl;		/* Chip control 0xe0*/
284	fwohcireg_t	link_cntl_clr;	/* Chip control clear 0xe4*/
285#define FWOHCI_NODEID	0xe8
286	fwohcireg_t	node;		/* Node ID 0xe8 */
287#define	OHCI_NODE_VALID	(1 << 31)
288#define	OHCI_NODE_ROOT	(1 << 30)
289
290#define	OHCI_ASYSRCBUS	1
291
292	fwohcireg_t	phy_access;	/* PHY cntl 0xec */
293#define	PHYDEV_RDDONE		(1<<31)
294#define	PHYDEV_RDCMD		(1<<15)
295#define	PHYDEV_WRCMD		(1<<14)
296#define	PHYDEV_REGADDR		8
297#define	PHYDEV_WRDATA		0
298#define	PHYDEV_RDADDR		24
299#define	PHYDEV_RDDATA		16
300
301	fwohcireg_t	cycle_timer;	/* Cycle Timer 0xf0 */
302	fwohcireg_t	dummy6[3];	/* dummy 0xf4-fc */
303	fwohcireg_t	areq_hi;	/* Async req. filter hi 0x100 */
304	fwohcireg_t	areq_hi_clr;	/* Async req. filter hi 0x104 */
305	fwohcireg_t	areq_lo;	/* Async req. filter lo 0x108 */
306	fwohcireg_t	areq_lo_clr;	/* Async req. filter lo 0x10c */
307	fwohcireg_t	preq_hi;	/* Async req. filter hi 0x110 */
308	fwohcireg_t	preq_hi_clr;	/* Async req. filter hi 0x114 */
309	fwohcireg_t	preq_lo;	/* Async req. filter lo 0x118 */
310	fwohcireg_t	preq_lo_clr;	/* Async req. filter lo 0x11c */
311
312	fwohcireg_t	pys_upper;	/* Physical Upper bound 0x120 */
313
314	fwohcireg_t	dummy7[23];	/* dummy 0x124-0x17c */
315
316	/*       0x180, 0x184, 0x188, 0x18c */
317	/*       0x190, 0x194, 0x198, 0x19c */
318	/*       0x1a0, 0x1a4, 0x1a8, 0x1ac */
319	/*       0x1b0, 0x1b4, 0x1b8, 0x1bc */
320	/*       0x1c0, 0x1c4, 0x1c8, 0x1cc */
321	/*       0x1d0, 0x1d4, 0x1d8, 0x1dc */
322	/*       0x1e0, 0x1e4, 0x1e8, 0x1ec */
323	/*       0x1f0, 0x1f4, 0x1f8, 0x1fc */
324	struct ohci_dma dma_ch[0x4];
325
326	/*       0x200, 0x204, 0x208, 0x20c */
327	/*       0x210, 0x204, 0x208, 0x20c */
328	struct ohci_itdma dma_itch[0x20];
329
330	/*       0x400, 0x404, 0x408, 0x40c */
331	/*       0x410, 0x404, 0x408, 0x40c */
332	struct ohci_dma dma_irch[0x20];
333};
334
335struct fwohcidb_tr{
336	STAILQ_ENTRY(fwohcidb_tr) link;
337	struct fw_xfer *xfer;
338	struct fwohcidb *db;
339//	bus_dmamap_t dma_map;
340	caddr_t buf;
341	bus_addr_t bus_addr;
342	int dbcnt;
343};
344
345/*
346 * OHCI info structure.
347 */
348struct fwohci_txpkthdr{
349	union{
350		uint32_t ld[4];
351		struct {
352#if BYTE_ORDER == BIG_ENDIAN
353			uint32_t spd:16, /* XXX include reserved field */
354				 :8,
355				 tcode:4,
356				 :4;
357#else
358			uint32_t :4,
359				 tcode:4,
360				 :8,
361				 spd:16; /* XXX include reserved fields */
362#endif
363		}common;
364		struct {
365#if BYTE_ORDER == BIG_ENDIAN
366			uint32_t :8,
367				 srcbus:1,
368				 :4,
369				 spd:3,
370				 tlrt:8,
371				 tcode:4,
372				 :4;
373#else
374			uint32_t :4,
375				 tcode:4,
376				 tlrt:8,
377				 spd:3,
378				 :4,
379				 srcbus:1,
380				 :8;
381#endif
382			BIT16x2(dst, );
383		}asycomm;
384		struct {
385#if BYTE_ORDER == BIG_ENDIAN
386			uint32_t :13,
387			         spd:3,
388				 chtag:8,
389				 tcode:4,
390				 sy:4;
391#else
392			uint32_t sy:4,
393				 tcode:4,
394				 chtag:8,
395			         spd:3,
396				 :13;
397#endif
398			BIT16x2(len, );
399		}stream;
400	}mode;
401};
402struct fwohci_trailer{
403#if BYTE_ORDER == BIG_ENDIAN
404	uint32_t stat:16,
405		  time:16;
406#else
407	uint32_t time:16,
408		  stat:16;
409#endif
410};
411
412#define	OHCI_CNTL_CYCSRC	(0x1 << 22)
413#define	OHCI_CNTL_CYCMTR	(0x1 << 21)
414#define	OHCI_CNTL_CYCTIMER	(0x1 << 20)
415#define	OHCI_CNTL_PHYPKT	(0x1 << 10)
416#define	OHCI_CNTL_SID		(0x1 << 9)
417
418/*
419 * defined in OHCI 1.1
420 * chapter 6.1
421 */
422#define OHCI_INT_DMA_ATRQ	(0x1 << 0)
423#define OHCI_INT_DMA_ATRS	(0x1 << 1)
424#define OHCI_INT_DMA_ARRQ	(0x1 << 2)
425#define OHCI_INT_DMA_ARRS	(0x1 << 3)
426#define OHCI_INT_DMA_PRRQ	(0x1 << 4)
427#define OHCI_INT_DMA_PRRS	(0x1 << 5)
428#define OHCI_INT_DMA_IT		(0x1 << 6)
429#define OHCI_INT_DMA_IR		(0x1 << 7)
430#define OHCI_INT_PW_ERR		(0x1 << 8)
431#define OHCI_INT_LR_ERR		(0x1 << 9)
432#define OHCI_INT_PHY_SID	(0x1 << 16)
433#define OHCI_INT_PHY_BUS_R	(0x1 << 17)
434#define OHCI_INT_REG_FAIL	(0x1 << 18)
435#define OHCI_INT_PHY_INT	(0x1 << 19)
436#define OHCI_INT_CYC_START	(0x1 << 20)
437#define OHCI_INT_CYC_64SECOND	(0x1 << 21)
438#define OHCI_INT_CYC_LOST	(0x1 << 22)
439#define OHCI_INT_CYC_ERR	(0x1 << 23)
440#define OHCI_INT_ERR		(0x1 << 24)
441#define OHCI_INT_CYC_LONG	(0x1 << 25)
442#define OHCI_INT_PHY_REG	(0x1 << 26)
443#define OHCI_INT_EN		(0x1 << 31)
444
445#define IP_CHANNELS             0x0234
446#define FWOHCI_MAXREC		2048
447
448#define	OHCI_ISORA		0x02
449#define	OHCI_ISORB		0x04
450
451#define FWOHCITCODE_PHY		0xe
452