arch_cpu.h revision 9dd4d2dd
1/*
2 * Copyright 2018, J��r��me Duval, jerome.duval@gmail.com.
3 * Copyright 2002-2009, Axel D��rfler, axeld@pinc-software.de.
4 * Copyright 2012, Alex Smith, alex@alex-smith.me.uk.
5 * Distributed under the terms of the MIT License.
6 *
7 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved.
8 * Distributed under the terms of the NewOS License.
9 */
10#ifndef _KERNEL_ARCH_x86_CPU_H
11#define _KERNEL_ARCH_x86_CPU_H
12
13
14#ifndef _ASSEMBLER
15
16#include <module.h>
17
18#include <arch_thread_types.h>
19
20#include <arch/x86/arch_altcodepatch.h>
21#include <arch/x86/descriptors.h>
22
23#ifdef __x86_64__
24#	include <arch/x86/64/cpu.h>
25#endif
26
27#endif	// !_ASSEMBLER
28
29
30#define CPU_MAX_CACHE_LEVEL	8
31
32#define CACHE_LINE_SIZE		64
33
34
35// MSR registers (possibly Intel specific)
36#define IA32_MSR_TSC					0x10
37#define IA32_MSR_APIC_BASE				0x1b
38
39#define IA32_MSR_PLATFORM_INFO			0xce
40#define IA32_MSR_MPERF					0xe7
41#define IA32_MSR_APERF					0xe8
42#define IA32_MSR_MTRR_CAPABILITIES		0xfe
43#define IA32_MSR_SYSENTER_CS			0x174
44#define IA32_MSR_SYSENTER_ESP			0x175
45#define IA32_MSR_SYSENTER_EIP			0x176
46#define IA32_MSR_PERF_STATUS			0x198
47#define IA32_MSR_PERF_CTL				0x199
48#define IA32_MSR_TURBO_RATIO_LIMIT		0x1ad
49#define IA32_MSR_ENERGY_PERF_BIAS		0x1b0
50#define IA32_MSR_MTRR_DEFAULT_TYPE		0x2ff
51#define IA32_MSR_MTRR_PHYSICAL_BASE_0	0x200
52#define IA32_MSR_MTRR_PHYSICAL_MASK_0	0x201
53
54
55// MSR APIC BASE bits
56#define IA32_MSR_APIC_BASE_BSP			0x00000100
57#define IA32_MSR_APIC_BASE_X2APIC		0x00000400
58#define IA32_MSR_APIC_BASE_ENABLED		0x00000800
59#define IA32_MSR_APIC_BASE_ADDRESS		0xfffff000
60
61// MSR EFER bits
62// reference
63#define IA32_MSR_EFER_SYSCALL			(1 << 0)
64#define IA32_MSR_EFER_NX				(1 << 11)
65
66// X2APIC MSRs.
67#define IA32_MSR_APIC_ID					0x00000802
68#define IA32_MSR_APIC_VERSION				0x00000803
69#define IA32_MSR_APIC_TASK_PRIORITY			0x00000808
70#define IA32_MSR_APIC_PROCESSOR_PRIORITY	0x0000080a
71#define IA32_MSR_APIC_EOI					0x0000080b
72#define IA32_MSR_APIC_LOGICAL_DEST			0x0000080d
73#define IA32_MSR_APIC_SPURIOUS_INTR_VECTOR	0x0000080f
74#define IA32_MSR_APIC_ERROR_STATUS			0x00000828
75#define IA32_MSR_APIC_INTR_COMMAND			0x00000830
76#define IA32_MSR_APIC_LVT_TIMER				0x00000832
77#define IA32_MSR_APIC_LVT_THERMAL_SENSOR	0x00000833
78#define IA32_MSR_APIC_LVT_PERFMON_COUNTERS	0x00000834
79#define IA32_MSR_APIC_LVT_LINT0				0x00000835
80#define IA32_MSR_APIC_LVT_LINT1				0x00000836
81#define IA32_MSR_APIC_LVT_ERROR				0x00000837
82#define IA32_MSR_APIC_INITIAL_TIMER_COUNT	0x00000838
83#define IA32_MSR_APIC_CURRENT_TIMER_COUNT	0x00000839
84#define IA32_MSR_APIC_TIMER_DIVIDE_CONFIG	0x0000083e
85#define IA32_MSR_APIC_SELF_IPI				0x0000083f
86#define IA32_MSR_XSS						0x00000da0
87
88// x86_64 MSRs.
89#define IA32_MSR_EFER					0xc0000080
90#define IA32_MSR_STAR					0xc0000081
91#define IA32_MSR_LSTAR					0xc0000082
92#define IA32_MSR_CSTAR					0xc0000083
93#define IA32_MSR_FMASK					0xc0000084
94#define IA32_MSR_FS_BASE				0xc0000100
95#define IA32_MSR_GS_BASE				0xc0000101
96#define IA32_MSR_KERNEL_GS_BASE			0xc0000102
97
98// K8 MSR registers
99#define K8_MSR_IPM						0xc0010055
100
101// x86 features from cpuid eax 1, edx register
102// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-5)
103#define IA32_FEATURE_FPU	(1 << 0) // x87 fpu
104#define IA32_FEATURE_VME	(1 << 1) // virtual 8086
105#define IA32_FEATURE_DE		(1 << 2) // debugging extensions
106#define IA32_FEATURE_PSE	(1 << 3) // page size extensions
107#define IA32_FEATURE_TSC	(1 << 4) // rdtsc instruction
108#define IA32_FEATURE_MSR	(1 << 5) // rdmsr/wrmsr instruction
109#define IA32_FEATURE_PAE	(1 << 6) // extended 3 level page table addressing
110#define IA32_FEATURE_MCE	(1 << 7) // machine check exception
111#define IA32_FEATURE_CX8	(1 << 8) // cmpxchg8b instruction
112#define IA32_FEATURE_APIC	(1 << 9) // local apic on chip
113//							(1 << 10) // Reserved
114#define IA32_FEATURE_SEP	(1 << 11) // SYSENTER/SYSEXIT
115#define IA32_FEATURE_MTRR	(1 << 12) // MTRR
116#define IA32_FEATURE_PGE	(1 << 13) // paging global bit
117#define IA32_FEATURE_MCA	(1 << 14) // machine check architecture
118#define IA32_FEATURE_CMOV	(1 << 15) // cmov instruction
119#define IA32_FEATURE_PAT	(1 << 16) // page attribute table
120#define IA32_FEATURE_PSE36	(1 << 17) // page size extensions with 4MB pages
121#define IA32_FEATURE_PSN	(1 << 18) // processor serial number
122#define IA32_FEATURE_CLFSH	(1 << 19) // cflush instruction
123//							(1 << 20) // Reserved
124#define IA32_FEATURE_DS		(1 << 21) // debug store
125#define IA32_FEATURE_ACPI	(1 << 22) // thermal monitor and clock ctrl
126#define IA32_FEATURE_MMX	(1 << 23) // mmx instructions
127#define IA32_FEATURE_FXSR	(1 << 24) // FXSAVE/FXRSTOR instruction
128#define IA32_FEATURE_SSE	(1 << 25) // SSE
129#define IA32_FEATURE_SSE2	(1 << 26) // SSE2
130#define IA32_FEATURE_SS		(1 << 27) // self snoop
131#define IA32_FEATURE_HTT	(1 << 28) // hyperthreading
132#define IA32_FEATURE_TM		(1 << 29) // thermal monitor
133#define IA32_FEATURE_IA64	(1 << 30) // IA64 processor emulating x86
134#define IA32_FEATURE_PBE	(1 << 31) // pending break enable
135
136// x86 features from cpuid eax 1, ecx register
137// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-4)
138#define IA32_FEATURE_EXT_SSE3		(1 << 0) // SSE3
139#define IA32_FEATURE_EXT_PCLMULQDQ	(1 << 1) // PCLMULQDQ Instruction
140#define IA32_FEATURE_EXT_DTES64		(1 << 2) // 64-Bit Debug Store
141#define IA32_FEATURE_EXT_MONITOR	(1 << 3) // MONITOR/MWAIT
142#define IA32_FEATURE_EXT_DSCPL		(1 << 4) // CPL qualified debug store
143#define IA32_FEATURE_EXT_VMX		(1 << 5) // Virtual Machine Extensions
144#define IA32_FEATURE_EXT_SMX		(1 << 6) // Safer Mode Extensions
145#define IA32_FEATURE_EXT_EST		(1 << 7) // Enhanced SpeedStep
146#define IA32_FEATURE_EXT_TM2		(1 << 8) // Thermal Monitor 2
147#define IA32_FEATURE_EXT_SSSE3		(1 << 9) // Supplemental SSE-3
148#define IA32_FEATURE_EXT_CNXTID		(1 << 10) // L1 Context ID
149//									(1 << 11) // Reserved
150#define IA32_FEATURE_EXT_FMA		(1 << 12) // Fused Multiply Add
151#define IA32_FEATURE_EXT_CX16		(1 << 13) // CMPXCHG16B
152#define IA32_FEATURE_EXT_XTPR		(1 << 14) // xTPR Update Control
153#define IA32_FEATURE_EXT_PDCM		(1 << 15) // Perfmon and Debug Capability
154//									(1 << 16) // Reserved
155#define IA32_FEATURE_EXT_PCID		(1 << 17) // Process Context Identifiers
156#define IA32_FEATURE_EXT_DCA		(1 << 18) // Direct Cache Access
157#define IA32_FEATURE_EXT_SSE4_1		(1 << 19) // SSE4.1
158#define IA32_FEATURE_EXT_SSE4_2		(1 << 20) // SSE4.2
159#define IA32_FEATURE_EXT_X2APIC		(1 << 21) // Extended xAPIC Support
160#define IA32_FEATURE_EXT_MOVBE 		(1 << 22) // MOVBE Instruction
161#define IA32_FEATURE_EXT_POPCNT		(1 << 23) // POPCNT Instruction
162#define IA32_FEATURE_EXT_TSCDEADLINE (1 << 24) // Time Stamp Counter Deadline
163#define IA32_FEATURE_EXT_AES		(1 << 25) // AES Instruction Extensions
164#define IA32_FEATURE_EXT_XSAVE		(1 << 26) // XSAVE/XSTOR States
165#define IA32_FEATURE_EXT_OSXSAVE	(1 << 27) // OS-Enabled XSAVE
166#define IA32_FEATURE_EXT_AVX		(1 << 28) // Advanced Vector Extensions
167#define IA32_FEATURE_EXT_F16C		(1 << 29) // 16-bit FP conversion
168#define IA32_FEATURE_EXT_RDRND		(1 << 30) // RDRAND instruction
169#define IA32_FEATURE_EXT_HYPERVISOR	(1 << 31) // Running on a hypervisor
170
171// x86 features from cpuid eax 0x80000001, ecx register (AMD)
172#define IA32_FEATURE_AMD_EXT_CMPLEGACY	(1 << 1) // Core MP legacy mode
173#define IA32_FEATURE_AMD_EXT_TOPOLOGY	(1 << 22) // Topology extensions
174
175// x86 features from cpuid eax 0x80000001, edx register (AMD)
176// only care about the ones that are unique to this register
177#define IA32_FEATURE_AMD_EXT_SYSCALL	(1 << 11) // SYSCALL/SYSRET
178#define IA32_FEATURE_AMD_EXT_NX			(1 << 20) // no execute bit
179#define IA32_FEATURE_AMD_EXT_MMXEXT		(1 << 22) // mmx extensions
180#define IA32_FEATURE_AMD_EXT_FFXSR		(1 << 25) // fast FXSAVE/FXRSTOR
181#define IA32_FEATURE_AMD_EXT_RDTSCP		(1 << 27) // rdtscp instruction
182#define IA32_FEATURE_AMD_EXT_LONG		(1 << 29) // long mode
183#define IA32_FEATURE_AMD_EXT_3DNOWEXT	(1 << 30) // 3DNow! extensions
184#define IA32_FEATURE_AMD_EXT_3DNOW		(1 << 31) // 3DNow!
185
186// some of the features from cpuid eax 0x80000001, edx register (AMD) are also
187// available on Intel processors
188#define IA32_FEATURES_INTEL_EXT			(IA32_FEATURE_AMD_EXT_SYSCALL		\
189											| IA32_FEATURE_AMD_EXT_NX		\
190											| IA32_FEATURE_AMD_EXT_RDTSCP	\
191											| IA32_FEATURE_AMD_EXT_LONG)
192
193// x86 defined features from cpuid eax 5, ecx register
194#define IA32_FEATURE_POWER_MWAIT		(1 << 0)
195#define IA32_FEATURE_INTERRUPT_MWAIT	(1 << 1)
196
197// x86 defined features from cpuid eax 6, eax register
198// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11)
199#define IA32_FEATURE_DTS	(1 << 0) //Digital Thermal Sensor
200#define IA32_FEATURE_ITB	(1 << 1) //Intel Turbo Boost Technology
201#define IA32_FEATURE_ARAT	(1 << 2) //Always running APIC Timer
202#define IA32_FEATURE_PLN	(1 << 4) //Power Limit Notification
203#define IA32_FEATURE_ECMD	(1 << 5) //Extended Clock Modulation Duty
204#define IA32_FEATURE_PTM	(1 << 6) //Package Thermal Management
205
206// x86 defined features from cpuid eax 6, ecx register
207// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11)
208#define IA32_FEATURE_APERFMPERF	(1 << 0) //IA32_APERF, IA32_MPERF
209#define IA32_FEATURE_EPB	(1 << 3) //IA32_ENERGY_PERF_BIAS
210
211// x86 features from cpuid eax 7, ebx register
212// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8)
213#define IA32_FEATURE_TSC_ADJUST	(1 << 1) // IA32_TSC_ADJUST MSR supported
214#define IA32_FEATURE_SGX		(1 << 2) // Software Guard Extensions
215#define IA32_FEATURE_BMI1		(1 << 3) // Bit Manipulation Instruction Set 1
216#define IA32_FEATURE_HLE		(1 << 4) // Hardware Lock Elision
217#define IA32_FEATURE_AVX2		(1 << 5) // Advanced Vector Extensions 2
218#define IA32_FEATURE_SMEP		(1 << 7) // Supervisor-Mode Execution Prevention
219#define IA32_FEATURE_BMI2		(1 << 8) // Bit Manipulation Instruction Set 2
220#define IA32_FEATURE_ERMS		(1 << 9) // Enhanced REP MOVSB/STOSB
221#define IA32_FEATURE_INVPCID	(1 << 10) // INVPCID instruction
222#define IA32_FEATURE_RTM		(1 << 11) // Transactional Synchronization Extensions
223#define IA32_FEATURE_CQM		(1 << 12) // Platform Quality of Service Monitoring
224#define IA32_FEATURE_MPX		(1 << 14) // Memory Protection Extensions
225#define IA32_FEATURE_RDT_A		(1 << 15) // Resource Director Technology Allocation
226#define IA32_FEATURE_AVX512F	(1 << 16) // AVX-512 Foundation
227#define IA32_FEATURE_AVX512DQ	(1 << 17) // AVX-512 Doubleword and Quadword Instructions
228#define IA32_FEATURE_RDSEED		(1 << 18) // RDSEED instruction
229#define IA32_FEATURE_ADX		(1 << 19) // ADX (Multi-Precision Add-Carry Instruction Extensions)
230#define IA32_FEATURE_SMAP		(1 << 20) // Supervisor Mode Access Prevention
231#define IA32_FEATURE_AVX512IFMA	(1 << 21) // AVX-512 Integer Fused Multiply-Add Instructions
232#define IA32_FEATURE_PCOMMIT	(1 << 22) // PCOMMIT instruction
233#define IA32_FEATURE_CLFLUSHOPT	(1 << 23) // CLFLUSHOPT instruction
234#define IA32_FEATURE_CLWB		(1 << 24) // CLWB instruction
235#define IA32_FEATURE_INTEL_PT	(1 << 25) // Intel Processor Trace
236#define IA32_FEATURE_AVX512PF	(1 << 26) // AVX-512 Prefetch Instructions
237#define IA32_FEATURE_AVX512ER	(1 << 27) // AVX-512 Exponential and Reciprocal Instructions
238#define IA32_FEATURE_AVX512CD	(1 << 28) // AVX-512 Conflict Detection Instructions
239#define IA32_FEATURE_SHA_NI		(1 << 29) // SHA extensions
240#define IA32_FEATURE_AVX512BW	(1 << 30) // AVX-512 Byte and Word Instructions
241#define IA32_FEATURE_AVX512VI	(1 << 31) // AVX-512 Vector Length Extensions
242
243// x86 features from cpuid eax 7, ecx register
244// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8)
245// https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features
246#define IA32_FEATURE_AVX512VMBI		(1 << 1) // AVX-512 Vector Bit Manipulation Instructions
247#define IA32_FEATURE_UMIP			(1 << 2) // User-mode Instruction Prevention
248#define IA32_FEATURE_PKU			(1 << 3) // Memory Protection Keys for User-mode pages
249#define IA32_FEATURE_OSPKE			(1 << 4) // PKU enabled by OS
250#define IA32_FEATURE_AVX512VMBI2	(1 << 6) // AVX-512 Vector Bit Manipulation Instructions 2
251#define IA32_FEATURE_GFNI			(1 << 8) // Galois Field instructions
252#define IA32_FEATURE_VAES			(1 << 9) // AES instruction set (VEX-256/EVEX)
253#define IA32_FEATURE_VPCLMULQDQ		(1 << 10) // CLMUL instruction set (VEX-256/EVEX)
254#define IA32_FEATURE_AVX512_VNNI	(1 << 11) // AVX-512 Vector Neural Network Instructions
255#define IA32_FEATURE_AVX512_BITALG	(1 << 12) // AVX-512 BITALG instructions
256#define IA32_FEATURE_AVX512_VPOPCNTDQ (1 << 14) // AVX-512 Vector Population Count D/Q
257#define IA32_FEATURE_LA57			(1 << 16) // 5-level page tables
258#define IA32_FEATURE_RDPID			(1 << 22) // RDPID Instruction
259#define IA32_FEATURE_SGX_LC			(1 << 30) // SGX Launch Configuration
260
261// x86 features from cpuid eax 7, edx register
262// https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features
263#define IA32_FEATURE_AVX512_4VNNIW	(1 << 2) // AVX-512 4-register Neural Network Instructions
264#define IA32_FEATURE_AVX512_4FMAPS	(1 << 3) // AVX-512 4-register Multiply Accumulation Single precision
265#define IA32_FEATURE_IBRS			(1 << 26)	// IBRS / IBPB Speculation Control
266#define IA32_FEATURE_STIBP			(1 << 27)	// STIBP Speculation Control
267
268
269// x86 defined features from cpuid eax 0x80000007, edx register
270#define IA32_FEATURE_INVARIANT_TSC		(1 << 8)
271
272// x86 defined features from cpuid eax 0x80000008, ebx register
273#define IA32_FEATURE_AMD_EXT_IBPB	(1 << 12)	/* IBPB Support only (no IBRS) */
274
275
276// Memory type ranges
277#define IA32_MTR_UNCACHED				0
278#define IA32_MTR_WRITE_COMBINING		1
279#define IA32_MTR_WRITE_THROUGH			4
280#define IA32_MTR_WRITE_PROTECTED		5
281#define IA32_MTR_WRITE_BACK				6
282
283// EFLAGS register
284#define X86_EFLAGS_CARRY						0x00000001
285#define X86_EFLAGS_RESERVED1					0x00000002
286#define X86_EFLAGS_PARITY						0x00000004
287#define X86_EFLAGS_AUXILIARY_CARRY				0x00000010
288#define X86_EFLAGS_ZERO							0x00000040
289#define X86_EFLAGS_SIGN							0x00000080
290#define X86_EFLAGS_TRAP							0x00000100
291#define X86_EFLAGS_INTERRUPT					0x00000200
292#define X86_EFLAGS_DIRECTION					0x00000400
293#define X86_EFLAGS_OVERFLOW						0x00000800
294#define X86_EFLAGS_IO_PRIVILEG_LEVEL			0x00003000
295#define X86_EFLAGS_IO_PRIVILEG_LEVEL_SHIFT		12
296#define X86_EFLAGS_NESTED_TASK					0x00004000
297#define X86_EFLAGS_RESUME						0x00010000
298#define X86_EFLAGS_V86_MODE						0x00020000
299#define X86_EFLAGS_ALIGNMENT_CHECK				0x00040000	// also SMAP status
300#define X86_EFLAGS_VIRTUAL_INTERRUPT			0x00080000
301#define X86_EFLAGS_VIRTUAL_INTERRUPT_PENDING	0x00100000
302#define X86_EFLAGS_ID							0x00200000
303
304#define X86_EFLAGS_USER_FLAGS	(X86_EFLAGS_CARRY | X86_EFLAGS_PARITY \
305	| X86_EFLAGS_AUXILIARY_CARRY | X86_EFLAGS_ZERO | X86_EFLAGS_SIGN \
306	| X86_EFLAGS_DIRECTION | X86_EFLAGS_OVERFLOW)
307
308#define CR0_CACHE_DISABLE		(1UL << 30)
309#define CR0_NOT_WRITE_THROUGH	(1UL << 29)
310#define CR0_FPU_EMULATION		(1UL << 2)
311#define CR0_MONITOR_FPU			(1UL << 1)
312
313// cr4 flags
314#define IA32_CR4_PAE			(1UL << 5)
315#define IA32_CR4_GLOBAL_PAGES	(1UL << 7)
316#define CR4_OS_FXSR				(1UL << 9)
317#define CR4_OS_XMM_EXCEPTION	(1UL << 10)
318#define IA32_CR4_SMEP			(1UL << 20)
319#define IA32_CR4_SMAP			(1UL << 21)
320
321// page fault error codes (http://wiki.osdev.org/Page_Fault)
322#define PGFAULT_P						0x01	// Protection violation
323#define PGFAULT_W						0x02	// Write
324#define PGFAULT_U						0x04	// Usermode
325#define PGFAULT_RSVD					0x08	// Reserved bits
326#define PGFAULT_I						0x10	// Instruction fetch
327
328// iframe types
329#define IFRAME_TYPE_SYSCALL				0x1
330#define IFRAME_TYPE_OTHER				0x2
331#define IFRAME_TYPE_MASK				0xf
332
333
334#ifndef _ASSEMBLER
335
336
337struct X86PagingStructures;
338
339
340typedef struct x86_mtrr_info {
341	uint64	base;
342	uint64	size;
343	uint8	type;
344} x86_mtrr_info;
345
346typedef struct x86_cpu_module_info {
347	module_info	info;
348	uint32		(*count_mtrrs)(void);
349	void		(*init_mtrrs)(void);
350
351	void		(*set_mtrr)(uint32 index, uint64 base, uint64 length,
352					uint8 type);
353	status_t	(*get_mtrr)(uint32 index, uint64* _base, uint64* _length,
354					uint8* _type);
355	void		(*set_mtrrs)(uint8 defaultType, const x86_mtrr_info* infos,
356					uint32 count);
357} x86_cpu_module_info;
358
359// features
360enum x86_feature_type {
361	FEATURE_COMMON = 0,     // cpuid eax=1, ecx register
362	FEATURE_EXT,            // cpuid eax=1, edx register
363	FEATURE_EXT_AMD_ECX,	// cpuid eax=0x80000001, ecx register (AMD)
364	FEATURE_EXT_AMD,        // cpuid eax=0x80000001, edx register (AMD)
365	FEATURE_5_ECX,			// cpuid eax=5, ecx register
366	FEATURE_6_EAX,          // cpuid eax=6, eax registers
367	FEATURE_6_ECX,          // cpuid eax=6, ecx registers
368	FEATURE_7_EBX,          // cpuid eax=7, ebx registers
369	FEATURE_7_ECX,          // cpuid eax=7, ecx registers
370	FEATURE_7_EDX,          // cpuid eax=7, edx registers
371	FEATURE_EXT_7_EDX,		// cpuid eax=0x80000007, edx register
372	FEATURE_EXT_8_EBX,		// cpuid eax=0x80000008, ebx register
373
374	FEATURE_NUM
375};
376
377enum x86_vendors {
378	VENDOR_INTEL = 0,
379	VENDOR_AMD,
380	VENDOR_CYRIX,
381	VENDOR_UMC,
382	VENDOR_NEXGEN,
383	VENDOR_CENTAUR,
384	VENDOR_RISE,
385	VENDOR_TRANSMETA,
386	VENDOR_NSC,
387
388	VENDOR_NUM,
389	VENDOR_UNKNOWN,
390};
391
392
393typedef struct arch_cpu_info {
394	// saved cpu info
395	enum x86_vendors	vendor;
396	uint32				feature[FEATURE_NUM];
397	char				model_name[49];
398	const char*			vendor_name;
399	int					type;
400	int					family;
401	int					extended_family;
402	int					stepping;
403	int					model;
404	int					extended_model;
405
406	uint32				logical_apic_id;
407
408	struct X86PagingStructures* active_paging_structures;
409
410	size_t				dr6;	// temporary storage for debug registers (cf.
411	size_t				dr7;	// x86_exit_user_debug_at_kernel_entry())
412
413	// local TSS for this cpu
414	struct tss			tss;
415#ifndef __x86_64__
416	struct tss			double_fault_tss;
417	void*				kernel_tls;
418#endif
419} arch_cpu_info;
420
421
422#define nop() __asm__ ("nop"::)
423
424#define x86_read_cr0() ({ \
425	size_t _v; \
426	__asm__("mov	%%cr0,%0" : "=r" (_v)); \
427	_v; \
428})
429
430#define x86_write_cr0(value) \
431	__asm__("mov	%0,%%cr0" : : "r" (value))
432
433#define x86_read_cr2() ({ \
434	size_t _v; \
435	__asm__("mov	%%cr2,%0" : "=r" (_v)); \
436	_v; \
437})
438
439#define x86_read_cr3() ({ \
440	size_t _v; \
441	__asm__("mov	%%cr3,%0" : "=r" (_v)); \
442	_v; \
443})
444
445#define x86_write_cr3(value) \
446	__asm__("mov	%0,%%cr3" : : "r" (value))
447
448#define x86_read_cr4() ({ \
449	size_t _v; \
450	__asm__("mov	%%cr4,%0" : "=r" (_v)); \
451	_v; \
452})
453
454#define x86_write_cr4(value) \
455	__asm__("mov	%0,%%cr4" : : "r" (value))
456
457#define x86_read_dr3() ({ \
458	size_t _v; \
459	__asm__("mov	%%dr3,%0" : "=r" (_v)); \
460	_v; \
461})
462
463#define x86_write_dr3(value) \
464	__asm__("mov	%0,%%dr3" : : "r" (value))
465
466#define invalidate_TLB(va) \
467	__asm__("invlpg (%0)" : : "r" (va))
468
469#define wbinvd() \
470	__asm__("wbinvd")
471
472#define set_ac() \
473	__asm__ volatile (ASM_STAC : : : "memory")
474
475#define clear_ac() \
476	__asm__ volatile (ASM_CLAC : : : "memory")
477
478#define out8(value,port) \
479	__asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port))
480
481#define out16(value,port) \
482	__asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port))
483
484#define out32(value,port) \
485	__asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port))
486
487#define in8(port) ({ \
488	uint8 _v; \
489	__asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \
490	_v; \
491})
492
493#define in16(port) ({ \
494	uint16 _v; \
495	__asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \
496	_v; \
497})
498
499#define in32(port) ({ \
500	uint32 _v; \
501	__asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \
502	_v; \
503})
504
505#define out8_p(value,port) \
506	__asm__ ("outb %%al,%%dx\n" \
507		"\tjmp 1f\n" \
508		"1:\tjmp 1f\n" \
509		"1:" : : "a" (value), "d" (port))
510
511#define in8_p(port) ({ \
512	uint8 _v; \
513	__asm__ volatile ("inb %%dx,%%al\n" \
514		"\tjmp 1f\n" \
515		"1:\tjmp 1f\n" \
516		"1:" : "=a" (_v) : "d" (port)); \
517	_v; \
518})
519
520
521extern void (*gCpuIdleFunc)(void);
522
523
524#ifdef __cplusplus
525extern "C" {
526#endif
527
528struct arch_thread;
529
530#ifdef __x86_64__
531void __x86_setup_system_time(uint64 conversionFactor,
532	uint64 conversionFactorNsecs);
533#else
534void __x86_setup_system_time(uint32 conversionFactor,
535	uint32 conversionFactorNsecs, bool conversionFactorNsecsShift);
536#endif
537
538void x86_userspace_thread_exit(void);
539void x86_end_userspace_thread_exit(void);
540
541addr_t x86_get_stack_frame();
542uint32 x86_count_mtrrs(void);
543void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type);
544status_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length,
545	uint8* _type);
546void x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos,
547	uint32 count);
548void x86_init_fpu();
549bool x86_check_feature(uint32 feature, enum x86_feature_type type);
550void* x86_get_double_fault_stack(int32 cpu, size_t* _size);
551int32 x86_double_fault_get_cpu(void);
552
553void x86_invalid_exception(iframe* frame);
554void x86_fatal_exception(iframe* frame);
555void x86_unexpected_exception(iframe* frame);
556void x86_hardware_interrupt(iframe* frame);
557void x86_page_fault_exception(iframe* iframe);
558
559#ifndef __x86_64__
560
561void x86_swap_pgdir(addr_t newPageDir);
562
563uint64 x86_read_msr(uint32 registerNumber);
564void x86_write_msr(uint32 registerNumber, uint64 value);
565
566void x86_context_switch(struct arch_thread* oldState,
567	struct arch_thread* newState);
568
569void x86_fnsave(void* fpuState);
570void x86_frstor(const void* fpuState);
571
572void x86_fxsave(void* fpuState);
573void x86_fxrstor(const void* fpuState);
574
575void x86_noop_swap(void* oldFpuState, const void* newFpuState);
576void x86_fnsave_swap(void* oldFpuState, const void* newFpuState);
577void x86_fxsave_swap(void* oldFpuState, const void* newFpuState);
578
579#endif
580
581
582static inline void
583arch_cpu_idle(void)
584{
585	gCpuIdleFunc();
586}
587
588
589static inline void
590arch_cpu_pause(void)
591{
592	asm volatile("pause" : : : "memory");
593}
594
595
596#ifdef __cplusplus
597}	// extern "C" {
598#endif
599
600#endif	// !_ASSEMBLER
601
602#endif	/* _KERNEL_ARCH_x86_CPU_H */
603