152a38012Sejakowatz/*
294090214SJérôme Duval * Copyright 2018, J��r��me Duval, jerome.duval@gmail.com.
3d337132bSAxel Dörfler * Copyright 2002-2009, Axel D��rfler, axeld@pinc-software.de.
40897e314SAlex Smith * Copyright 2012, Alex Smith, alex@alex-smith.me.uk.
590ce9e83SAxel Dörfler * Distributed under the terms of the MIT License.
690ce9e83SAxel Dörfler *
790ce9e83SAxel Dörfler * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved.
890ce9e83SAxel Dörfler * Distributed under the terms of the NewOS License.
990ce9e83SAxel Dörfler */
1052a38012Sejakowatz#ifndef _KERNEL_ARCH_x86_CPU_H
1152a38012Sejakowatz#define _KERNEL_ARCH_x86_CPU_H
1252a38012Sejakowatz
136a689590SAxel Dörfler
143403f23eSAlex Smith#ifndef _ASSEMBLER
150897e314SAlex Smith
160897e314SAlex Smith#include <module.h>
1788e8e24cSPawel Dziepak
1888e8e24cSPawel Dziepak#include <arch_thread_types.h>
1988e8e24cSPawel Dziepak
209dd4d2ddSJérôme Duval#include <arch/x86/arch_altcodepatch.h>
210897e314SAlex Smith#include <arch/x86/descriptors.h>
220897e314SAlex Smith
230897e314SAlex Smith#ifdef __x86_64__
2488e8e24cSPawel Dziepak#	include <arch/x86/64/cpu.h>
253403f23eSAlex Smith#endif
2624df6592SIngo Weinhold
270897e314SAlex Smith#endif	// !_ASSEMBLER
280897e314SAlex Smith
290897e314SAlex Smith
3036cc64a9SPawel Dziepak#define CPU_MAX_CACHE_LEVEL	8
3136cc64a9SPawel Dziepak
320e94a12fSPawel Dziepak#define CACHE_LINE_SIZE		64
330e94a12fSPawel Dziepak
3436cc64a9SPawel Dziepak
350897e314SAlex Smith// MSR registers (possibly Intel specific)
360897e314SAlex Smith#define IA32_MSR_TSC					0x10
370897e314SAlex Smith#define IA32_MSR_APIC_BASE				0x1b
383a764d6aSJérôme Duval#define IA32_MSR_SPEC_CTRL				0x48
393a764d6aSJérôme Duval#define IA32_MSR_PRED_CMD				0x49
409c0ff0eeSPawel Dziepak#define IA32_MSR_PLATFORM_INFO			0xce
419c0ff0eeSPawel Dziepak#define IA32_MSR_MPERF					0xe7
429c0ff0eeSPawel Dziepak#define IA32_MSR_APERF					0xe8
430897e314SAlex Smith#define IA32_MSR_MTRR_CAPABILITIES		0xfe
443a764d6aSJérôme Duval#define IA32_MSR_ARCH_CAPABILITIES		0x10a
456086986dSRob Gill#define IA32_MSR_FLUSH_CMD				0x10b
460897e314SAlex Smith#define IA32_MSR_SYSENTER_CS			0x174
470897e314SAlex Smith#define IA32_MSR_SYSENTER_ESP			0x175
480897e314SAlex Smith#define IA32_MSR_SYSENTER_EIP			0x176
499c0ff0eeSPawel Dziepak#define IA32_MSR_PERF_STATUS			0x198
509c0ff0eeSPawel Dziepak#define IA32_MSR_PERF_CTL				0x199
519c0ff0eeSPawel Dziepak#define IA32_MSR_TURBO_RATIO_LIMIT		0x1ad
5219187c46SYongcong Du#define IA32_MSR_ENERGY_PERF_BIAS		0x1b0
530897e314SAlex Smith#define IA32_MSR_MTRR_DEFAULT_TYPE		0x2ff
540897e314SAlex Smith#define IA32_MSR_MTRR_PHYSICAL_BASE_0	0x200
550897e314SAlex Smith#define IA32_MSR_MTRR_PHYSICAL_MASK_0	0x201
560897e314SAlex Smith
573a764d6aSJérôme Duval// MSR SPEC CTRL bits
583a764d6aSJérôme Duval#define IA32_MSR_SPEC_CTRL_IBRS			(1 << 0)
593a764d6aSJérôme Duval#define IA32_MSR_SPEC_CTRL_STIBP		(1 << 1)
606086986dSRob Gill#define IA32_MSR_SPEC_CTRL_SSBD			(1 << 2)
613a764d6aSJérôme Duval
623a764d6aSJérôme Duval// MSR PRED CMD bits
633a764d6aSJérôme Duval#define IA32_MSR_PRED_CMD_IBPB			(1 << 0)
6478777340SJérôme Duval
6578777340SJérôme Duval// MSR APIC BASE bits
6678777340SJérôme Duval#define IA32_MSR_APIC_BASE_BSP			0x00000100
6778777340SJérôme Duval#define IA32_MSR_APIC_BASE_X2APIC		0x00000400
6878777340SJérôme Duval#define IA32_MSR_APIC_BASE_ENABLED		0x00000800
6978777340SJérôme Duval#define IA32_MSR_APIC_BASE_ADDRESS		0xfffff000
7078777340SJérôme Duval
71966f2076SPawel Dziepak// MSR EFER bits
72966f2076SPawel Dziepak// reference
73966f2076SPawel Dziepak#define IA32_MSR_EFER_SYSCALL			(1 << 0)
74966f2076SPawel Dziepak#define IA32_MSR_EFER_NX				(1 << 11)
75966f2076SPawel Dziepak
763a764d6aSJérôme Duval// MSR ARCH CAPABILITIES bits
776086986dSRob Gill#define IA32_MSR_ARCH_CAP_RDCL_NO			(1 << 0)
786086986dSRob Gill#define IA32_MSR_ARCH_CAP_IBRS_ALL			(1 << 1)
796086986dSRob Gill#define IA32_MSR_ARCH_CAP_RSBA				(1 << 2)
806086986dSRob Gill#define IA32_MSR_ARCH_CAP_SKIP_L1D_VMENTRY	(1 << 3)
816086986dSRob Gill#define IA32_MSR_ARCH_CAP_SSB_NO			(1 << 4)
826086986dSRob Gill
836086986dSRob Gill// MSR FLUSH CMD bits
846086986dSRob Gill#define IA32_MSR_L1D_FLUSH			(1 << 1)
853a764d6aSJérôme Duval
8678777340SJérôme Duval// X2APIC MSRs.
8778777340SJérôme Duval#define IA32_MSR_APIC_ID					0x00000802
8878777340SJérôme Duval#define IA32_MSR_APIC_VERSION				0x00000803
8978777340SJérôme Duval#define IA32_MSR_APIC_TASK_PRIORITY			0x00000808
9078777340SJérôme Duval#define IA32_MSR_APIC_PROCESSOR_PRIORITY	0x0000080a
9178777340SJérôme Duval#define IA32_MSR_APIC_EOI					0x0000080b
9278777340SJérôme Duval#define IA32_MSR_APIC_LOGICAL_DEST			0x0000080d
9378777340SJérôme Duval#define IA32_MSR_APIC_SPURIOUS_INTR_VECTOR	0x0000080f
9478777340SJérôme Duval#define IA32_MSR_APIC_ERROR_STATUS			0x00000828
9578777340SJérôme Duval#define IA32_MSR_APIC_INTR_COMMAND			0x00000830
9678777340SJérôme Duval#define IA32_MSR_APIC_LVT_TIMER				0x00000832
9778777340SJérôme Duval#define IA32_MSR_APIC_LVT_THERMAL_SENSOR	0x00000833
9878777340SJérôme Duval#define IA32_MSR_APIC_LVT_PERFMON_COUNTERS	0x00000834
9978777340SJérôme Duval#define IA32_MSR_APIC_LVT_LINT0				0x00000835
10078777340SJérôme Duval#define IA32_MSR_APIC_LVT_LINT1				0x00000836
10178777340SJérôme Duval#define IA32_MSR_APIC_LVT_ERROR				0x00000837
10278777340SJérôme Duval#define IA32_MSR_APIC_INITIAL_TIMER_COUNT	0x00000838
10378777340SJérôme Duval#define IA32_MSR_APIC_CURRENT_TIMER_COUNT	0x00000839
10478777340SJérôme Duval#define IA32_MSR_APIC_TIMER_DIVIDE_CONFIG	0x0000083e
105d6aaebc7SJérôme Duval#define IA32_MSR_APIC_SELF_IPI				0x0000083f
106d6aaebc7SJérôme Duval#define IA32_MSR_XSS						0x00000da0
10778777340SJérôme Duval
108b5c9d24aSAlex Smith// x86_64 MSRs.
109d0a92cb6SJérôme Duval#define IA32_MSR_EFER					0xc0000080
110b5c9d24aSAlex Smith#define IA32_MSR_STAR					0xc0000081
111b5c9d24aSAlex Smith#define IA32_MSR_LSTAR					0xc0000082
112d0a92cb6SJérôme Duval#define IA32_MSR_CSTAR					0xc0000083
113b5c9d24aSAlex Smith#define IA32_MSR_FMASK					0xc0000084
114b5c9d24aSAlex Smith#define IA32_MSR_FS_BASE				0xc0000100
115b5c9d24aSAlex Smith#define IA32_MSR_GS_BASE				0xc0000101
116b5c9d24aSAlex Smith#define IA32_MSR_KERNEL_GS_BASE			0xc0000102
117b5c9d24aSAlex Smith
1180897e314SAlex Smith// K8 MSR registers
1190897e314SAlex Smith#define K8_MSR_IPM						0xc0010055
1200897e314SAlex Smith
1210897e314SAlex Smith// x86 features from cpuid eax 1, edx register
1220897e314SAlex Smith// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-5)
1230897e314SAlex Smith#define IA32_FEATURE_FPU	(1 << 0) // x87 fpu
1240897e314SAlex Smith#define IA32_FEATURE_VME	(1 << 1) // virtual 8086
1250897e314SAlex Smith#define IA32_FEATURE_DE		(1 << 2) // debugging extensions
1260897e314SAlex Smith#define IA32_FEATURE_PSE	(1 << 3) // page size extensions
1270897e314SAlex Smith#define IA32_FEATURE_TSC	(1 << 4) // rdtsc instruction
1280897e314SAlex Smith#define IA32_FEATURE_MSR	(1 << 5) // rdmsr/wrmsr instruction
1290897e314SAlex Smith#define IA32_FEATURE_PAE	(1 << 6) // extended 3 level page table addressing
1300897e314SAlex Smith#define IA32_FEATURE_MCE	(1 << 7) // machine check exception
1310897e314SAlex Smith#define IA32_FEATURE_CX8	(1 << 8) // cmpxchg8b instruction
1320897e314SAlex Smith#define IA32_FEATURE_APIC	(1 << 9) // local apic on chip
1330897e314SAlex Smith//							(1 << 10) // Reserved
1340897e314SAlex Smith#define IA32_FEATURE_SEP	(1 << 11) // SYSENTER/SYSEXIT
1350897e314SAlex Smith#define IA32_FEATURE_MTRR	(1 << 12) // MTRR
1360897e314SAlex Smith#define IA32_FEATURE_PGE	(1 << 13) // paging global bit
1370897e314SAlex Smith#define IA32_FEATURE_MCA	(1 << 14) // machine check architecture
1380897e314SAlex Smith#define IA32_FEATURE_CMOV	(1 << 15) // cmov instruction
1390897e314SAlex Smith#define IA32_FEATURE_PAT	(1 << 16) // page attribute table
1400897e314SAlex Smith#define IA32_FEATURE_PSE36	(1 << 17) // page size extensions with 4MB pages
1410897e314SAlex Smith#define IA32_FEATURE_PSN	(1 << 18) // processor serial number
1420897e314SAlex Smith#define IA32_FEATURE_CLFSH	(1 << 19) // cflush instruction
1430897e314SAlex Smith//							(1 << 20) // Reserved
1440897e314SAlex Smith#define IA32_FEATURE_DS		(1 << 21) // debug store
1450897e314SAlex Smith#define IA32_FEATURE_ACPI	(1 << 22) // thermal monitor and clock ctrl
1460897e314SAlex Smith#define IA32_FEATURE_MMX	(1 << 23) // mmx instructions
1470897e314SAlex Smith#define IA32_FEATURE_FXSR	(1 << 24) // FXSAVE/FXRSTOR instruction
1480897e314SAlex Smith#define IA32_FEATURE_SSE	(1 << 25) // SSE
1490897e314SAlex Smith#define IA32_FEATURE_SSE2	(1 << 26) // SSE2
1500897e314SAlex Smith#define IA32_FEATURE_SS		(1 << 27) // self snoop
1510897e314SAlex Smith#define IA32_FEATURE_HTT	(1 << 28) // hyperthreading
1520897e314SAlex Smith#define IA32_FEATURE_TM		(1 << 29) // thermal monitor
1530897e314SAlex Smith#define IA32_FEATURE_IA64	(1 << 30) // IA64 processor emulating x86
1540897e314SAlex Smith#define IA32_FEATURE_PBE	(1 << 31) // pending break enable
1550897e314SAlex Smith
1560897e314SAlex Smith// x86 features from cpuid eax 1, ecx register
1570897e314SAlex Smith// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-4)
1580897e314SAlex Smith#define IA32_FEATURE_EXT_SSE3		(1 << 0) // SSE3
1590897e314SAlex Smith#define IA32_FEATURE_EXT_PCLMULQDQ	(1 << 1) // PCLMULQDQ Instruction
1600897e314SAlex Smith#define IA32_FEATURE_EXT_DTES64		(1 << 2) // 64-Bit Debug Store
1610897e314SAlex Smith#define IA32_FEATURE_EXT_MONITOR	(1 << 3) // MONITOR/MWAIT
1620897e314SAlex Smith#define IA32_FEATURE_EXT_DSCPL		(1 << 4) // CPL qualified debug store
1630897e314SAlex Smith#define IA32_FEATURE_EXT_VMX		(1 << 5) // Virtual Machine Extensions
1640897e314SAlex Smith#define IA32_FEATURE_EXT_SMX		(1 << 6) // Safer Mode Extensions
1650897e314SAlex Smith#define IA32_FEATURE_EXT_EST		(1 << 7) // Enhanced SpeedStep
1660897e314SAlex Smith#define IA32_FEATURE_EXT_TM2		(1 << 8) // Thermal Monitor 2
1670897e314SAlex Smith#define IA32_FEATURE_EXT_SSSE3		(1 << 9) // Supplemental SSE-3
1680897e314SAlex Smith#define IA32_FEATURE_EXT_CNXTID		(1 << 10) // L1 Context ID
1690897e314SAlex Smith//									(1 << 11) // Reserved
1700897e314SAlex Smith#define IA32_FEATURE_EXT_FMA		(1 << 12) // Fused Multiply Add
1710897e314SAlex Smith#define IA32_FEATURE_EXT_CX16		(1 << 13) // CMPXCHG16B
1720897e314SAlex Smith#define IA32_FEATURE_EXT_XTPR		(1 << 14) // xTPR Update Control
1730897e314SAlex Smith#define IA32_FEATURE_EXT_PDCM		(1 << 15) // Perfmon and Debug Capability
1740897e314SAlex Smith//									(1 << 16) // Reserved
1750897e314SAlex Smith#define IA32_FEATURE_EXT_PCID		(1 << 17) // Process Context Identifiers
1760897e314SAlex Smith#define IA32_FEATURE_EXT_DCA		(1 << 18) // Direct Cache Access
1770897e314SAlex Smith#define IA32_FEATURE_EXT_SSE4_1		(1 << 19) // SSE4.1
1780897e314SAlex Smith#define IA32_FEATURE_EXT_SSE4_2		(1 << 20) // SSE4.2
1790897e314SAlex Smith#define IA32_FEATURE_EXT_X2APIC		(1 << 21) // Extended xAPIC Support
1800897e314SAlex Smith#define IA32_FEATURE_EXT_MOVBE 		(1 << 22) // MOVBE Instruction
1810897e314SAlex Smith#define IA32_FEATURE_EXT_POPCNT		(1 << 23) // POPCNT Instruction
1820897e314SAlex Smith#define IA32_FEATURE_EXT_TSCDEADLINE (1 << 24) // Time Stamp Counter Deadline
1830897e314SAlex Smith#define IA32_FEATURE_EXT_AES		(1 << 25) // AES Instruction Extensions
1840897e314SAlex Smith#define IA32_FEATURE_EXT_XSAVE		(1 << 26) // XSAVE/XSTOR States
1850897e314SAlex Smith#define IA32_FEATURE_EXT_OSXSAVE	(1 << 27) // OS-Enabled XSAVE
1860897e314SAlex Smith#define IA32_FEATURE_EXT_AVX		(1 << 28) // Advanced Vector Extensions
1870897e314SAlex Smith#define IA32_FEATURE_EXT_F16C		(1 << 29) // 16-bit FP conversion
1880897e314SAlex Smith#define IA32_FEATURE_EXT_RDRND		(1 << 30) // RDRAND instruction
1890897e314SAlex Smith#define IA32_FEATURE_EXT_HYPERVISOR	(1 << 31) // Running on a hypervisor
1900897e314SAlex Smith
19136cc64a9SPawel Dziepak// x86 features from cpuid eax 0x80000001, ecx register (AMD)
19236cc64a9SPawel Dziepak#define IA32_FEATURE_AMD_EXT_CMPLEGACY	(1 << 1) // Core MP legacy mode
19336cc64a9SPawel Dziepak#define IA32_FEATURE_AMD_EXT_TOPOLOGY	(1 << 22) // Topology extensions
19436cc64a9SPawel Dziepak
1950897e314SAlex Smith// x86 features from cpuid eax 0x80000001, edx register (AMD)
1960897e314SAlex Smith// only care about the ones that are unique to this register
1970897e314SAlex Smith#define IA32_FEATURE_AMD_EXT_SYSCALL	(1 << 11) // SYSCALL/SYSRET
1980897e314SAlex Smith#define IA32_FEATURE_AMD_EXT_NX			(1 << 20) // no execute bit
1990897e314SAlex Smith#define IA32_FEATURE_AMD_EXT_MMXEXT		(1 << 22) // mmx extensions
2000897e314SAlex Smith#define IA32_FEATURE_AMD_EXT_FFXSR		(1 << 25) // fast FXSAVE/FXRSTOR
2010897e314SAlex Smith#define IA32_FEATURE_AMD_EXT_RDTSCP		(1 << 27) // rdtscp instruction
2020897e314SAlex Smith#define IA32_FEATURE_AMD_EXT_LONG		(1 << 29) // long mode
2030897e314SAlex Smith#define IA32_FEATURE_AMD_EXT_3DNOWEXT	(1 << 30) // 3DNow! extensions
2040897e314SAlex Smith#define IA32_FEATURE_AMD_EXT_3DNOW		(1 << 31) // 3DNow!
2050897e314SAlex Smith
206966f2076SPawel Dziepak// some of the features from cpuid eax 0x80000001, edx register (AMD) are also
207966f2076SPawel Dziepak// available on Intel processors
208966f2076SPawel Dziepak#define IA32_FEATURES_INTEL_EXT			(IA32_FEATURE_AMD_EXT_SYSCALL		\
209966f2076SPawel Dziepak											| IA32_FEATURE_AMD_EXT_NX		\
210966f2076SPawel Dziepak											| IA32_FEATURE_AMD_EXT_RDTSCP	\
211966f2076SPawel Dziepak											| IA32_FEATURE_AMD_EXT_LONG)
212966f2076SPawel Dziepak
2137db89e8dSPawel Dziepak// x86 defined features from cpuid eax 5, ecx register
2147db89e8dSPawel Dziepak#define IA32_FEATURE_POWER_MWAIT		(1 << 0)
2157db89e8dSPawel Dziepak#define IA32_FEATURE_INTERRUPT_MWAIT	(1 << 1)
2167db89e8dSPawel Dziepak
2170897e314SAlex Smith// x86 defined features from cpuid eax 6, eax register
2180897e314SAlex Smith// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11)
2193a764d6aSJérôme Duval#define IA32_FEATURE_DTS	(1 << 0) // Digital Thermal Sensor
2203a764d6aSJérôme Duval#define IA32_FEATURE_ITB	(1 << 1) // Intel Turbo Boost Technology
2213a764d6aSJérôme Duval#define IA32_FEATURE_ARAT	(1 << 2) // Always running APIC Timer
2223a764d6aSJérôme Duval#define IA32_FEATURE_PLN	(1 << 4) // Power Limit Notification
2233a764d6aSJérôme Duval#define IA32_FEATURE_ECMD	(1 << 5) // Extended Clock Modulation Duty
2243a764d6aSJérôme Duval#define IA32_FEATURE_PTM	(1 << 6) // Package Thermal Management
2250897e314SAlex Smith
2260897e314SAlex Smith// x86 defined features from cpuid eax 6, ecx register
2270897e314SAlex Smith// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11)
2283a764d6aSJérôme Duval#define IA32_FEATURE_APERFMPERF	(1 << 0) // IA32_APERF, IA32_MPERF
2293a764d6aSJérôme Duval#define IA32_FEATURE_EPB	(1 << 3) // IA32_ENERGY_PERF_BIAS
2300897e314SAlex Smith
23194090214SJérôme Duval// x86 features from cpuid eax 7, ebx register
23294090214SJérôme Duval// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8)
23394090214SJérôme Duval#define IA32_FEATURE_TSC_ADJUST	(1 << 1) // IA32_TSC_ADJUST MSR supported
23494090214SJérôme Duval#define IA32_FEATURE_SGX		(1 << 2) // Software Guard Extensions
23594090214SJérôme Duval#define IA32_FEATURE_BMI1		(1 << 3) // Bit Manipulation Instruction Set 1
23694090214SJérôme Duval#define IA32_FEATURE_HLE		(1 << 4) // Hardware Lock Elision
23794090214SJérôme Duval#define IA32_FEATURE_AVX2		(1 << 5) // Advanced Vector Extensions 2
23894090214SJérôme Duval#define IA32_FEATURE_SMEP		(1 << 7) // Supervisor-Mode Execution Prevention
23994090214SJérôme Duval#define IA32_FEATURE_BMI2		(1 << 8) // Bit Manipulation Instruction Set 2
24094090214SJérôme Duval#define IA32_FEATURE_ERMS		(1 << 9) // Enhanced REP MOVSB/STOSB
24194090214SJérôme Duval#define IA32_FEATURE_INVPCID	(1 << 10) // INVPCID instruction
24294090214SJérôme Duval#define IA32_FEATURE_RTM		(1 << 11) // Transactional Synchronization Extensions
24394090214SJérôme Duval#define IA32_FEATURE_CQM		(1 << 12) // Platform Quality of Service Monitoring
24494090214SJérôme Duval#define IA32_FEATURE_MPX		(1 << 14) // Memory Protection Extensions
24594090214SJérôme Duval#define IA32_FEATURE_RDT_A		(1 << 15) // Resource Director Technology Allocation
24694090214SJérôme Duval#define IA32_FEATURE_AVX512F	(1 << 16) // AVX-512 Foundation
24794090214SJérôme Duval#define IA32_FEATURE_AVX512DQ	(1 << 17) // AVX-512 Doubleword and Quadword Instructions
24894090214SJérôme Duval#define IA32_FEATURE_RDSEED		(1 << 18) // RDSEED instruction
24994090214SJérôme Duval#define IA32_FEATURE_ADX		(1 << 19) // ADX (Multi-Precision Add-Carry Instruction Extensions)
25094090214SJérôme Duval#define IA32_FEATURE_SMAP		(1 << 20) // Supervisor Mode Access Prevention
25194090214SJérôme Duval#define IA32_FEATURE_AVX512IFMA	(1 << 21) // AVX-512 Integer Fused Multiply-Add Instructions
25294090214SJérôme Duval#define IA32_FEATURE_PCOMMIT	(1 << 22) // PCOMMIT instruction
25394090214SJérôme Duval#define IA32_FEATURE_CLFLUSHOPT	(1 << 23) // CLFLUSHOPT instruction
25494090214SJérôme Duval#define IA32_FEATURE_CLWB		(1 << 24) // CLWB instruction
25594090214SJérôme Duval#define IA32_FEATURE_INTEL_PT	(1 << 25) // Intel Processor Trace
25694090214SJérôme Duval#define IA32_FEATURE_AVX512PF	(1 << 26) // AVX-512 Prefetch Instructions
25794090214SJérôme Duval#define IA32_FEATURE_AVX512ER	(1 << 27) // AVX-512 Exponential and Reciprocal Instructions
25894090214SJérôme Duval#define IA32_FEATURE_AVX512CD	(1 << 28) // AVX-512 Conflict Detection Instructions
25994090214SJérôme Duval#define IA32_FEATURE_SHA_NI		(1 << 29) // SHA extensions
26094090214SJérôme Duval#define IA32_FEATURE_AVX512BW	(1 << 30) // AVX-512 Byte and Word Instructions
26194090214SJérôme Duval#define IA32_FEATURE_AVX512VI	(1 << 31) // AVX-512 Vector Length Extensions
26294090214SJérôme Duval
26394090214SJérôme Duval// x86 features from cpuid eax 7, ecx register
26494090214SJérôme Duval// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8)
26594090214SJérôme Duval// https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features
26694090214SJérôme Duval#define IA32_FEATURE_AVX512VMBI		(1 << 1) // AVX-512 Vector Bit Manipulation Instructions
26794090214SJérôme Duval#define IA32_FEATURE_UMIP			(1 << 2) // User-mode Instruction Prevention
26894090214SJérôme Duval#define IA32_FEATURE_PKU			(1 << 3) // Memory Protection Keys for User-mode pages
26994090214SJérôme Duval#define IA32_FEATURE_OSPKE			(1 << 4) // PKU enabled by OS
27094090214SJérôme Duval#define IA32_FEATURE_AVX512VMBI2	(1 << 6) // AVX-512 Vector Bit Manipulation Instructions 2
27194090214SJérôme Duval#define IA32_FEATURE_GFNI			(1 << 8) // Galois Field instructions
27294090214SJérôme Duval#define IA32_FEATURE_VAES			(1 << 9) // AES instruction set (VEX-256/EVEX)
27394090214SJérôme Duval#define IA32_FEATURE_VPCLMULQDQ		(1 << 10) // CLMUL instruction set (VEX-256/EVEX)
27494090214SJérôme Duval#define IA32_FEATURE_AVX512_VNNI	(1 << 11) // AVX-512 Vector Neural Network Instructions
27594090214SJérôme Duval#define IA32_FEATURE_AVX512_BITALG	(1 << 12) // AVX-512 BITALG instructions
27694090214SJérôme Duval#define IA32_FEATURE_AVX512_VPOPCNTDQ (1 << 14) // AVX-512 Vector Population Count D/Q
27794090214SJérôme Duval#define IA32_FEATURE_LA57			(1 << 16) // 5-level page tables
27894090214SJérôme Duval#define IA32_FEATURE_RDPID			(1 << 22) // RDPID Instruction
27994090214SJérôme Duval#define IA32_FEATURE_SGX_LC			(1 << 30) // SGX Launch Configuration
28094090214SJérôme Duval
28194090214SJérôme Duval// x86 features from cpuid eax 7, edx register
28294090214SJérôme Duval// https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features
28394090214SJérôme Duval#define IA32_FEATURE_AVX512_4VNNIW	(1 << 2) // AVX-512 4-register Neural Network Instructions
28494090214SJérôme Duval#define IA32_FEATURE_AVX512_4FMAPS	(1 << 3) // AVX-512 4-register Multiply Accumulation Single precision
285483c4584SJérôme Duval#define IA32_FEATURE_IBRS			(1 << 26)	// IBRS / IBPB Speculation Control
286483c4584SJérôme Duval#define IA32_FEATURE_STIBP			(1 << 27)	// STIBP Speculation Control
2876086986dSRob Gill#define IA32_FEATURE_L1D_FLUSH		(1 << 28)	// L1D_FLUSH supported
2883a764d6aSJérôme Duval#define IA32_FEATURE_ARCH_CAPABILITIES	(1 << 29)	// IA32_ARCH_CAPABILITIES MSR
2896086986dSRob Gill#define IA32_FEATURE_SSBD			(1 << 30)	// Speculative Store Bypass Disable
29094090214SJérôme Duval
2917db89e8dSPawel Dziepak// x86 defined features from cpuid eax 0x80000007, edx register
2927db89e8dSPawel Dziepak#define IA32_FEATURE_INVARIANT_TSC		(1 << 8)
2937db89e8dSPawel Dziepak
294483c4584SJérôme Duval// x86 defined features from cpuid eax 0x80000008, ebx register
295483c4584SJérôme Duval#define IA32_FEATURE_AMD_EXT_IBPB	(1 << 12)	/* IBPB Support only (no IBRS) */
296483c4584SJérôme Duval
297483c4584SJérôme Duval
2980897e314SAlex Smith// Memory type ranges
2990897e314SAlex Smith#define IA32_MTR_UNCACHED				0
3000897e314SAlex Smith#define IA32_MTR_WRITE_COMBINING		1
3010897e314SAlex Smith#define IA32_MTR_WRITE_THROUGH			4
3020897e314SAlex Smith#define IA32_MTR_WRITE_PROTECTED		5
3030897e314SAlex Smith#define IA32_MTR_WRITE_BACK				6
3040897e314SAlex Smith
3050897e314SAlex Smith// EFLAGS register
3060897e314SAlex Smith#define X86_EFLAGS_CARRY						0x00000001
3070897e314SAlex Smith#define X86_EFLAGS_RESERVED1					0x00000002
3080897e314SAlex Smith#define X86_EFLAGS_PARITY						0x00000004
3090897e314SAlex Smith#define X86_EFLAGS_AUXILIARY_CARRY				0x00000010
3100897e314SAlex Smith#define X86_EFLAGS_ZERO							0x00000040
3110897e314SAlex Smith#define X86_EFLAGS_SIGN							0x00000080
3120897e314SAlex Smith#define X86_EFLAGS_TRAP							0x00000100
3130897e314SAlex Smith#define X86_EFLAGS_INTERRUPT					0x00000200
3140897e314SAlex Smith#define X86_EFLAGS_DIRECTION					0x00000400
3150897e314SAlex Smith#define X86_EFLAGS_OVERFLOW						0x00000800
3160897e314SAlex Smith#define X86_EFLAGS_IO_PRIVILEG_LEVEL			0x00003000
3170897e314SAlex Smith#define X86_EFLAGS_IO_PRIVILEG_LEVEL_SHIFT		12
3180897e314SAlex Smith#define X86_EFLAGS_NESTED_TASK					0x00004000
3190897e314SAlex Smith#define X86_EFLAGS_RESUME						0x00010000
3200897e314SAlex Smith#define X86_EFLAGS_V86_MODE						0x00020000
3219dd4d2ddSJérôme Duval#define X86_EFLAGS_ALIGNMENT_CHECK				0x00040000	// also SMAP status
3220897e314SAlex Smith#define X86_EFLAGS_VIRTUAL_INTERRUPT			0x00080000
3230897e314SAlex Smith#define X86_EFLAGS_VIRTUAL_INTERRUPT_PENDING	0x00100000
3240897e314SAlex Smith#define X86_EFLAGS_ID							0x00200000
3250897e314SAlex Smith
3260897e314SAlex Smith#define X86_EFLAGS_USER_FLAGS	(X86_EFLAGS_CARRY | X86_EFLAGS_PARITY \
3270897e314SAlex Smith	| X86_EFLAGS_AUXILIARY_CARRY | X86_EFLAGS_ZERO | X86_EFLAGS_SIGN \
3280897e314SAlex Smith	| X86_EFLAGS_DIRECTION | X86_EFLAGS_OVERFLOW)
3290897e314SAlex Smith
330b41f2810SPaweł Dziepak#define CR0_CACHE_DISABLE		(1UL << 30)
331b41f2810SPaweł Dziepak#define CR0_NOT_WRITE_THROUGH	(1UL << 29)
332b41f2810SPaweł Dziepak#define CR0_FPU_EMULATION		(1UL << 2)
333b41f2810SPaweł Dziepak#define CR0_MONITOR_FPU			(1UL << 1)
334b41f2810SPaweł Dziepak
3359dd4d2ddSJérôme Duval// cr4 flags
3369dd4d2ddSJérôme Duval#define IA32_CR4_PAE			(1UL << 5)
3379dd4d2ddSJérôme Duval#define IA32_CR4_GLOBAL_PAGES	(1UL << 7)
338b41f2810SPaweł Dziepak#define CR4_OS_FXSR				(1UL << 9)
339b41f2810SPaweł Dziepak#define CR4_OS_XMM_EXCEPTION	(1UL << 10)
3409dd4d2ddSJérôme Duval#define IA32_CR4_SMEP			(1UL << 20)
3419dd4d2ddSJérôme Duval#define IA32_CR4_SMAP			(1UL << 21)
342b41f2810SPaweł Dziepak
3439dd4d2ddSJérôme Duval// page fault error codes (http://wiki.osdev.org/Page_Fault)
3449dd4d2ddSJérôme Duval#define PGFAULT_P						0x01	// Protection violation
3459dd4d2ddSJérôme Duval#define PGFAULT_W						0x02	// Write
3469dd4d2ddSJérôme Duval#define PGFAULT_U						0x04	// Usermode
3479dd4d2ddSJérôme Duval#define PGFAULT_RSVD					0x08	// Reserved bits
3489dd4d2ddSJérôme Duval#define PGFAULT_I						0x10	// Instruction fetch
34924df6592SIngo Weinhold
35034b3b26bSIngo Weinhold// iframe types
351d337132bSAxel Dörfler#define IFRAME_TYPE_SYSCALL				0x1
352d337132bSAxel Dörfler#define IFRAME_TYPE_OTHER				0x2
353d337132bSAxel Dörfler#define IFRAME_TYPE_MASK				0xf
35434b3b26bSIngo Weinhold
35534b3b26bSIngo Weinhold
35634b3b26bSIngo Weinhold#ifndef _ASSEMBLER
35734b3b26bSIngo Weinhold
3580897e314SAlex Smith
35984217140SIngo Weinholdstruct X86PagingStructures;
36084217140SIngo Weinhold
36152a38012Sejakowatz
3620897e314SAlex Smithtypedef struct x86_mtrr_info {
3630897e314SAlex Smith	uint64	base;
3640897e314SAlex Smith	uint64	size;
3650897e314SAlex Smith	uint8	type;
3660897e314SAlex Smith} x86_mtrr_info;
3670897e314SAlex Smith
3680897e314SAlex Smithtypedef struct x86_cpu_module_info {
3690897e314SAlex Smith	module_info	info;
3700897e314SAlex Smith	uint32		(*count_mtrrs)(void);
3710897e314SAlex Smith	void		(*init_mtrrs)(void);
3720897e314SAlex Smith
3730897e314SAlex Smith	void		(*set_mtrr)(uint32 index, uint64 base, uint64 length,
3740897e314SAlex Smith					uint8 type);
3750897e314SAlex Smith	status_t	(*get_mtrr)(uint32 index, uint64* _base, uint64* _length,
3760897e314SAlex Smith					uint8* _type);
3770897e314SAlex Smith	void		(*set_mtrrs)(uint8 defaultType, const x86_mtrr_info* infos,
3780897e314SAlex Smith					uint32 count);
3790897e314SAlex Smith} x86_cpu_module_info;
3800897e314SAlex Smith
3810897e314SAlex Smith// features
3820897e314SAlex Smithenum x86_feature_type {
3830897e314SAlex Smith	FEATURE_COMMON = 0,     // cpuid eax=1, ecx register
3840897e314SAlex Smith	FEATURE_EXT,            // cpuid eax=1, edx register
38536cc64a9SPawel Dziepak	FEATURE_EXT_AMD_ECX,	// cpuid eax=0x80000001, ecx register (AMD)
3860897e314SAlex Smith	FEATURE_EXT_AMD,        // cpuid eax=0x80000001, edx register (AMD)
3877db89e8dSPawel Dziepak	FEATURE_5_ECX,			// cpuid eax=5, ecx register
3880897e314SAlex Smith	FEATURE_6_EAX,          // cpuid eax=6, eax registers
3890897e314SAlex Smith	FEATURE_6_ECX,          // cpuid eax=6, ecx registers
39094090214SJérôme Duval	FEATURE_7_EBX,          // cpuid eax=7, ebx registers
39194090214SJérôme Duval	FEATURE_7_ECX,          // cpuid eax=7, ecx registers
39294090214SJérôme Duval	FEATURE_7_EDX,          // cpuid eax=7, edx registers
3937db89e8dSPawel Dziepak	FEATURE_EXT_7_EDX,		// cpuid eax=0x80000007, edx register
394483c4584SJérôme Duval	FEATURE_EXT_8_EBX,		// cpuid eax=0x80000008, ebx register
3950897e314SAlex Smith
3960897e314SAlex Smith	FEATURE_NUM
3975ca8da7aSAxel Dörfler};
3985ca8da7aSAxel Dörfler
3990897e314SAlex Smithenum x86_vendors {
4000897e314SAlex Smith	VENDOR_INTEL = 0,
4010897e314SAlex Smith	VENDOR_AMD,
4020897e314SAlex Smith	VENDOR_CYRIX,
4030897e314SAlex Smith	VENDOR_UMC,
4040897e314SAlex Smith	VENDOR_NEXGEN,
4050897e314SAlex Smith	VENDOR_CENTAUR,
4060897e314SAlex Smith	VENDOR_RISE,
4070897e314SAlex Smith	VENDOR_TRANSMETA,
4080897e314SAlex Smith	VENDOR_NSC,
4090897e314SAlex Smith
4100897e314SAlex Smith	VENDOR_NUM,
4110897e314SAlex Smith	VENDOR_UNKNOWN,
41215173df4SAxel Dörfler};
41315173df4SAxel Dörfler
414bb107c4eSAxel Dörfler
415dcdc4f4bSTravis Geiselbrechttypedef struct arch_cpu_info {
416dfb5375dSTravis Geiselbrecht	// saved cpu info
417d337132bSAxel Dörfler	enum x86_vendors	vendor;
418d337132bSAxel Dörfler	uint32				feature[FEATURE_NUM];
419d337132bSAxel Dörfler	char				model_name[49];
420d337132bSAxel Dörfler	const char*			vendor_name;
421d337132bSAxel Dörfler	int					type;
422d337132bSAxel Dörfler	int					family;
423d337132bSAxel Dörfler	int					extended_family;
424d337132bSAxel Dörfler	int					stepping;
425d337132bSAxel Dörfler	int					model;
426d337132bSAxel Dörfler	int					extended_model;
427dfb5375dSTravis Geiselbrecht
428e3d001ffSPawel Dziepak	uint32				logical_apic_id;
429e3d001ffSPawel Dziepak
43084217140SIngo Weinhold	struct X86PagingStructures* active_paging_structures;
4319a42ad7aSIngo Weinhold
4328a190335SAlex Smith	size_t				dr6;	// temporary storage for debug registers (cf.
4338a190335SAlex Smith	size_t				dr7;	// x86_exit_user_debug_at_kernel_entry())
434feddedabSIngo Weinhold
435dfb5375dSTravis Geiselbrecht	// local TSS for this cpu
436d337132bSAxel Dörfler	struct tss			tss;
4370897e314SAlex Smith#ifndef __x86_64__
438d337132bSAxel Dörfler	struct tss			double_fault_tss;
439611376feSPawel Dziepak	void*				kernel_tls;
4400897e314SAlex Smith#endif
441dcdc4f4bSTravis Geiselbrecht} arch_cpu_info;
44290ce9e83SAxel Dörfler
4433403f23eSAlex Smith
4440897e314SAlex Smith#define nop() __asm__ ("nop"::)
4450897e314SAlex Smith
4464e8fbfb2SAlex Smith#define x86_read_cr0() ({ \
4474e8fbfb2SAlex Smith	size_t _v; \
4484e8fbfb2SAlex Smith	__asm__("mov	%%cr0,%0" : "=r" (_v)); \
4494e8fbfb2SAlex Smith	_v; \
4504e8fbfb2SAlex Smith})
4510897e314SAlex Smith
4524e8fbfb2SAlex Smith#define x86_write_cr0(value) \
4534e8fbfb2SAlex Smith	__asm__("mov	%0,%%cr0" : : "r" (value))
4544e8fbfb2SAlex Smith
4554e8fbfb2SAlex Smith#define x86_read_cr2() ({ \
4564e8fbfb2SAlex Smith	size_t _v; \
4574e8fbfb2SAlex Smith	__asm__("mov	%%cr2,%0" : "=r" (_v)); \
4584e8fbfb2SAlex Smith	_v; \
4594e8fbfb2SAlex Smith})
4604e8fbfb2SAlex Smith
4614e8fbfb2SAlex Smith#define x86_read_cr3() ({ \
4624e8fbfb2SAlex Smith	size_t _v; \
4634e8fbfb2SAlex Smith	__asm__("mov	%%cr3,%0" : "=r" (_v)); \
4644e8fbfb2SAlex Smith	_v; \
4654e8fbfb2SAlex Smith})
4660897e314SAlex Smith
4674e8fbfb2SAlex Smith#define x86_write_cr3(value) \
4680897e314SAlex Smith	__asm__("mov	%0,%%cr3" : : "r" (value))
4690897e314SAlex Smith
4704e8fbfb2SAlex Smith#define x86_read_cr4() ({ \
4714e8fbfb2SAlex Smith	size_t _v; \
4724e8fbfb2SAlex Smith	__asm__("mov	%%cr4,%0" : "=r" (_v)); \
4734e8fbfb2SAlex Smith	_v; \
4744e8fbfb2SAlex Smith})
4754e8fbfb2SAlex Smith
4764e8fbfb2SAlex Smith#define x86_write_cr4(value) \
4774e8fbfb2SAlex Smith	__asm__("mov	%0,%%cr4" : : "r" (value))
4784e8fbfb2SAlex Smith
4794e8fbfb2SAlex Smith#define x86_read_dr3() ({ \
4804e8fbfb2SAlex Smith	size_t _v; \
4814e8fbfb2SAlex Smith	__asm__("mov	%%dr3,%0" : "=r" (_v)); \
4824e8fbfb2SAlex Smith	_v; \
4834e8fbfb2SAlex Smith})
4840897e314SAlex Smith
4854e8fbfb2SAlex Smith#define x86_write_dr3(value) \
4860897e314SAlex Smith	__asm__("mov	%0,%%dr3" : : "r" (value))
4870897e314SAlex Smith
4880897e314SAlex Smith#define invalidate_TLB(va) \
4890897e314SAlex Smith	__asm__("invlpg (%0)" : : "r" (va))
4900897e314SAlex Smith
4910897e314SAlex Smith#define wbinvd() \
4920897e314SAlex Smith	__asm__("wbinvd")
4930897e314SAlex Smith
4949dd4d2ddSJérôme Duval#define set_ac() \
4959dd4d2ddSJérôme Duval	__asm__ volatile (ASM_STAC : : : "memory")
4969dd4d2ddSJérôme Duval
4979dd4d2ddSJérôme Duval#define clear_ac() \
4989dd4d2ddSJérôme Duval	__asm__ volatile (ASM_CLAC : : : "memory")
4999dd4d2ddSJérôme Duval
5000897e314SAlex Smith#define out8(value,port) \
5010897e314SAlex Smith	__asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port))
5020897e314SAlex Smith
5030897e314SAlex Smith#define out16(value,port) \
5040897e314SAlex Smith	__asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port))
5050897e314SAlex Smith
5060897e314SAlex Smith#define out32(value,port) \
5070897e314SAlex Smith	__asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port))
5080897e314SAlex Smith
5090897e314SAlex Smith#define in8(port) ({ \
5100897e314SAlex Smith	uint8 _v; \
5110897e314SAlex Smith	__asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \
5120897e314SAlex Smith	_v; \
5130897e314SAlex Smith})
5140897e314SAlex Smith
5150897e314SAlex Smith#define in16(port) ({ \
5160897e314SAlex Smith	uint16 _v; \
5170897e314SAlex Smith	__asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \
5180897e314SAlex Smith	_v; \
5190897e314SAlex Smith})
5200897e314SAlex Smith
5210897e314SAlex Smith#define in32(port) ({ \
5220897e314SAlex Smith	uint32 _v; \
5230897e314SAlex Smith	__asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \
5240897e314SAlex Smith	_v; \
5250897e314SAlex Smith})
5260897e314SAlex Smith
5270897e314SAlex Smith#define out8_p(value,port) \
5280897e314SAlex Smith	__asm__ ("outb %%al,%%dx\n" \
5290897e314SAlex Smith		"\tjmp 1f\n" \
5300897e314SAlex Smith		"1:\tjmp 1f\n" \
5310897e314SAlex Smith		"1:" : : "a" (value), "d" (port))
5320897e314SAlex Smith
5330897e314SAlex Smith#define in8_p(port) ({ \
5340897e314SAlex Smith	uint8 _v; \
5350897e314SAlex Smith	__asm__ volatile ("inb %%dx,%%al\n" \
5360897e314SAlex Smith		"\tjmp 1f\n" \
5370897e314SAlex Smith		"1:\tjmp 1f\n" \
5380897e314SAlex Smith		"1:" : "=a" (_v) : "d" (port)); \
5390897e314SAlex Smith	_v; \
5400897e314SAlex Smith})
5410897e314SAlex Smith
5420897e314SAlex Smith
5437db89e8dSPawel Dziepakextern void (*gCpuIdleFunc)(void);
5447db89e8dSPawel Dziepak
5457db89e8dSPawel Dziepak
54690ce9e83SAxel Dörfler#ifdef __cplusplus
54790ce9e83SAxel Dörflerextern "C" {
54890ce9e83SAxel Dörfler#endif
54990ce9e83SAxel Dörfler
5503490a4beSAxel Dörflerstruct arch_thread;
5513490a4beSAxel Dörfler
5525c7d5218SAlex Smith#ifdef __x86_64__
5535c7d5218SAlex Smithvoid __x86_setup_system_time(uint64 conversionFactor,
5545c7d5218SAlex Smith	uint64 conversionFactorNsecs);
5555c7d5218SAlex Smith#else
55634a48c70SIngo Weinholdvoid __x86_setup_system_time(uint32 conversionFactor,
55734a48c70SIngo Weinhold	uint32 conversionFactorNsecs, bool conversionFactorNsecsShift);
5585c7d5218SAlex Smith#endif
5595c7d5218SAlex Smith
56026e0b0c8SAugustin Cavalierstatus_t __x86_patch_errata_percpu(int cpu);
56126e0b0c8SAugustin Cavalier
5628fc075acSAxel Dörflervoid x86_userspace_thread_exit(void);
5638fc075acSAxel Dörflervoid x86_end_userspace_thread_exit(void);
564396b7422SPaweł Dziepak
565b5c9d24aSAlex Smithaddr_t x86_get_stack_frame();
5667c0a9357SAxel Dörfleruint32 x86_count_mtrrs(void);
56751a3c450SAxel Dörflervoid x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type);
568d337132bSAxel Dörflerstatus_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length,
569d337132bSAxel Dörfler	uint8* _type);
570dac21d8bSIngo Weinholdvoid x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos,
571dac21d8bSIngo Weinhold	uint32 count);
5723f1eed70SAlexander von Gluck IVvoid x86_init_fpu();
573dcdc4f4bSTravis Geiselbrechtbool x86_check_feature(uint32 feature, enum x86_feature_type type);
574bca3215fSIngo Weinholdvoid* x86_get_double_fault_stack(int32 cpu, size_t* _size);
5755670b0a8SAlex Smithint32 x86_double_fault_get_cpu(void);
5765670b0a8SAlex Smith
5776497f6b1SAlex Smithvoid x86_invalid_exception(iframe* frame);
5786497f6b1SAlex Smithvoid x86_fatal_exception(iframe* frame);
5796497f6b1SAlex Smithvoid x86_unexpected_exception(iframe* frame);
5806497f6b1SAlex Smithvoid x86_hardware_interrupt(iframe* frame);
5816497f6b1SAlex Smithvoid x86_page_fault_exception(iframe* iframe);
5828e26b085SIngo Weinhold
5834304bb98SAlex Smith#ifndef __x86_64__
58476636769SPawel Dziepak
5854b75a1e2SPaweł Dziepakvoid x86_swap_pgdir(addr_t newPageDir);
5864b75a1e2SPaweł Dziepak
58776636769SPawel Dziepakuint64 x86_read_msr(uint32 registerNumber);
58876636769SPawel Dziepakvoid x86_write_msr(uint32 registerNumber, uint64 value);
58976636769SPawel Dziepak
59088e8e24cSPawel Dziepakvoid x86_context_switch(struct arch_thread* oldState,
59188e8e24cSPawel Dziepak	struct arch_thread* newState);
5920897e314SAlex Smith
593513403d4SAugustin Cavaliervoid x86_fnsave(void* fpuState);
594513403d4SAugustin Cavaliervoid x86_frstor(const void* fpuState);
595513403d4SAugustin Cavalier
596396b7422SPaweł Dziepakvoid x86_fxsave(void* fpuState);
597396b7422SPaweł Dziepakvoid x86_fxrstor(const void* fpuState);
598396b7422SPaweł Dziepak
599396b7422SPaweł Dziepakvoid x86_noop_swap(void* oldFpuState, const void* newFpuState);
6004304bb98SAlex Smithvoid x86_fnsave_swap(void* oldFpuState, const void* newFpuState);
601396b7422SPaweł Dziepakvoid x86_fxsave_swap(void* oldFpuState, const void* newFpuState);
602dcdc4f4bSTravis Geiselbrecht
6034304bb98SAlex Smith#endif
60452a38012Sejakowatz
605c8d7534eSIngo Weinhold
6067db89e8dSPawel Dziepakstatic inline void
6077db89e8dSPawel Dziepakarch_cpu_idle(void)
6087db89e8dSPawel Dziepak{
6097db89e8dSPawel Dziepak	gCpuIdleFunc();
6107db89e8dSPawel Dziepak}
6117db89e8dSPawel Dziepak
6127db89e8dSPawel Dziepak
6137db89e8dSPawel Dziepakstatic inline void
6147db89e8dSPawel Dziepakarch_cpu_pause(void)
6157db89e8dSPawel Dziepak{
6163514fd77SPawel Dziepak	asm volatile("pause" : : : "memory");
6177db89e8dSPawel Dziepak}
6187db89e8dSPawel Dziepak
6197db89e8dSPawel Dziepak
620c8d7534eSIngo Weinhold#ifdef __cplusplus
621c8d7534eSIngo Weinhold}	// extern "C" {
622c8d7534eSIngo Weinhold#endif
623c8d7534eSIngo Weinhold
62434b3b26bSIngo Weinhold#endif	// !_ASSEMBLER
625c8d7534eSIngo Weinhold
6267208e95fSAxel Dörfler#endif	/* _KERNEL_ARCH_x86_CPU_H */
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