1/*
2 * Copyright 2018, J��r��me Duval, jerome.duval@gmail.com.
3 * Copyright 2002-2009, Axel D��rfler, axeld@pinc-software.de.
4 * Copyright 2012, Alex Smith, alex@alex-smith.me.uk.
5 * Distributed under the terms of the MIT License.
6 *
7 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved.
8 * Distributed under the terms of the NewOS License.
9 */
10#ifndef _KERNEL_ARCH_x86_CPU_H
11#define _KERNEL_ARCH_x86_CPU_H
12
13
14#ifndef _ASSEMBLER
15
16#include <module.h>
17
18#include <arch_thread_types.h>
19
20#include <arch/x86/arch_altcodepatch.h>
21#include <arch/x86/descriptors.h>
22
23#ifdef __x86_64__
24#	include <arch/x86/64/cpu.h>
25#endif
26
27#endif	// !_ASSEMBLER
28
29
30#define CPU_MAX_CACHE_LEVEL	8
31
32#define CACHE_LINE_SIZE		64
33
34
35// MSR registers (possibly Intel specific)
36#define IA32_MSR_TSC					0x10
37#define IA32_MSR_APIC_BASE				0x1b
38#define IA32_MSR_SPEC_CTRL				0x48
39#define IA32_MSR_PRED_CMD				0x49
40#define IA32_MSR_PLATFORM_INFO			0xce
41#define IA32_MSR_MPERF					0xe7
42#define IA32_MSR_APERF					0xe8
43#define IA32_MSR_MTRR_CAPABILITIES		0xfe
44#define IA32_MSR_ARCH_CAPABILITIES		0x10a
45#define IA32_MSR_FLUSH_CMD				0x10b
46#define IA32_MSR_SYSENTER_CS			0x174
47#define IA32_MSR_SYSENTER_ESP			0x175
48#define IA32_MSR_SYSENTER_EIP			0x176
49#define IA32_MSR_PERF_STATUS			0x198
50#define IA32_MSR_PERF_CTL				0x199
51#define IA32_MSR_TURBO_RATIO_LIMIT		0x1ad
52#define IA32_MSR_ENERGY_PERF_BIAS		0x1b0
53#define IA32_MSR_MTRR_DEFAULT_TYPE		0x2ff
54#define IA32_MSR_MTRR_PHYSICAL_BASE_0	0x200
55#define IA32_MSR_MTRR_PHYSICAL_MASK_0	0x201
56
57// MSR SPEC CTRL bits
58#define IA32_MSR_SPEC_CTRL_IBRS			(1 << 0)
59#define IA32_MSR_SPEC_CTRL_STIBP		(1 << 1)
60#define IA32_MSR_SPEC_CTRL_SSBD			(1 << 2)
61
62// MSR PRED CMD bits
63#define IA32_MSR_PRED_CMD_IBPB			(1 << 0)
64
65// MSR APIC BASE bits
66#define IA32_MSR_APIC_BASE_BSP			0x00000100
67#define IA32_MSR_APIC_BASE_X2APIC		0x00000400
68#define IA32_MSR_APIC_BASE_ENABLED		0x00000800
69#define IA32_MSR_APIC_BASE_ADDRESS		0xfffff000
70
71// MSR EFER bits
72// reference
73#define IA32_MSR_EFER_SYSCALL			(1 << 0)
74#define IA32_MSR_EFER_NX				(1 << 11)
75
76// MSR ARCH CAPABILITIES bits
77#define IA32_MSR_ARCH_CAP_RDCL_NO			(1 << 0)
78#define IA32_MSR_ARCH_CAP_IBRS_ALL			(1 << 1)
79#define IA32_MSR_ARCH_CAP_RSBA				(1 << 2)
80#define IA32_MSR_ARCH_CAP_SKIP_L1D_VMENTRY	(1 << 3)
81#define IA32_MSR_ARCH_CAP_SSB_NO			(1 << 4)
82
83// MSR FLUSH CMD bits
84#define IA32_MSR_L1D_FLUSH			(1 << 1)
85
86// X2APIC MSRs.
87#define IA32_MSR_APIC_ID					0x00000802
88#define IA32_MSR_APIC_VERSION				0x00000803
89#define IA32_MSR_APIC_TASK_PRIORITY			0x00000808
90#define IA32_MSR_APIC_PROCESSOR_PRIORITY	0x0000080a
91#define IA32_MSR_APIC_EOI					0x0000080b
92#define IA32_MSR_APIC_LOGICAL_DEST			0x0000080d
93#define IA32_MSR_APIC_SPURIOUS_INTR_VECTOR	0x0000080f
94#define IA32_MSR_APIC_ERROR_STATUS			0x00000828
95#define IA32_MSR_APIC_INTR_COMMAND			0x00000830
96#define IA32_MSR_APIC_LVT_TIMER				0x00000832
97#define IA32_MSR_APIC_LVT_THERMAL_SENSOR	0x00000833
98#define IA32_MSR_APIC_LVT_PERFMON_COUNTERS	0x00000834
99#define IA32_MSR_APIC_LVT_LINT0				0x00000835
100#define IA32_MSR_APIC_LVT_LINT1				0x00000836
101#define IA32_MSR_APIC_LVT_ERROR				0x00000837
102#define IA32_MSR_APIC_INITIAL_TIMER_COUNT	0x00000838
103#define IA32_MSR_APIC_CURRENT_TIMER_COUNT	0x00000839
104#define IA32_MSR_APIC_TIMER_DIVIDE_CONFIG	0x0000083e
105#define IA32_MSR_APIC_SELF_IPI				0x0000083f
106#define IA32_MSR_XSS						0x00000da0
107
108// x86_64 MSRs.
109#define IA32_MSR_EFER					0xc0000080
110#define IA32_MSR_STAR					0xc0000081
111#define IA32_MSR_LSTAR					0xc0000082
112#define IA32_MSR_CSTAR					0xc0000083
113#define IA32_MSR_FMASK					0xc0000084
114#define IA32_MSR_FS_BASE				0xc0000100
115#define IA32_MSR_GS_BASE				0xc0000101
116#define IA32_MSR_KERNEL_GS_BASE			0xc0000102
117
118// K8 MSR registers
119#define K8_MSR_IPM						0xc0010055
120
121// x86 features from cpuid eax 1, edx register
122// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-5)
123#define IA32_FEATURE_FPU	(1 << 0) // x87 fpu
124#define IA32_FEATURE_VME	(1 << 1) // virtual 8086
125#define IA32_FEATURE_DE		(1 << 2) // debugging extensions
126#define IA32_FEATURE_PSE	(1 << 3) // page size extensions
127#define IA32_FEATURE_TSC	(1 << 4) // rdtsc instruction
128#define IA32_FEATURE_MSR	(1 << 5) // rdmsr/wrmsr instruction
129#define IA32_FEATURE_PAE	(1 << 6) // extended 3 level page table addressing
130#define IA32_FEATURE_MCE	(1 << 7) // machine check exception
131#define IA32_FEATURE_CX8	(1 << 8) // cmpxchg8b instruction
132#define IA32_FEATURE_APIC	(1 << 9) // local apic on chip
133//							(1 << 10) // Reserved
134#define IA32_FEATURE_SEP	(1 << 11) // SYSENTER/SYSEXIT
135#define IA32_FEATURE_MTRR	(1 << 12) // MTRR
136#define IA32_FEATURE_PGE	(1 << 13) // paging global bit
137#define IA32_FEATURE_MCA	(1 << 14) // machine check architecture
138#define IA32_FEATURE_CMOV	(1 << 15) // cmov instruction
139#define IA32_FEATURE_PAT	(1 << 16) // page attribute table
140#define IA32_FEATURE_PSE36	(1 << 17) // page size extensions with 4MB pages
141#define IA32_FEATURE_PSN	(1 << 18) // processor serial number
142#define IA32_FEATURE_CLFSH	(1 << 19) // cflush instruction
143//							(1 << 20) // Reserved
144#define IA32_FEATURE_DS		(1 << 21) // debug store
145#define IA32_FEATURE_ACPI	(1 << 22) // thermal monitor and clock ctrl
146#define IA32_FEATURE_MMX	(1 << 23) // mmx instructions
147#define IA32_FEATURE_FXSR	(1 << 24) // FXSAVE/FXRSTOR instruction
148#define IA32_FEATURE_SSE	(1 << 25) // SSE
149#define IA32_FEATURE_SSE2	(1 << 26) // SSE2
150#define IA32_FEATURE_SS		(1 << 27) // self snoop
151#define IA32_FEATURE_HTT	(1 << 28) // hyperthreading
152#define IA32_FEATURE_TM		(1 << 29) // thermal monitor
153#define IA32_FEATURE_IA64	(1 << 30) // IA64 processor emulating x86
154#define IA32_FEATURE_PBE	(1 << 31) // pending break enable
155
156// x86 features from cpuid eax 1, ecx register
157// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-4)
158#define IA32_FEATURE_EXT_SSE3		(1 << 0) // SSE3
159#define IA32_FEATURE_EXT_PCLMULQDQ	(1 << 1) // PCLMULQDQ Instruction
160#define IA32_FEATURE_EXT_DTES64		(1 << 2) // 64-Bit Debug Store
161#define IA32_FEATURE_EXT_MONITOR	(1 << 3) // MONITOR/MWAIT
162#define IA32_FEATURE_EXT_DSCPL		(1 << 4) // CPL qualified debug store
163#define IA32_FEATURE_EXT_VMX		(1 << 5) // Virtual Machine Extensions
164#define IA32_FEATURE_EXT_SMX		(1 << 6) // Safer Mode Extensions
165#define IA32_FEATURE_EXT_EST		(1 << 7) // Enhanced SpeedStep
166#define IA32_FEATURE_EXT_TM2		(1 << 8) // Thermal Monitor 2
167#define IA32_FEATURE_EXT_SSSE3		(1 << 9) // Supplemental SSE-3
168#define IA32_FEATURE_EXT_CNXTID		(1 << 10) // L1 Context ID
169//									(1 << 11) // Reserved
170#define IA32_FEATURE_EXT_FMA		(1 << 12) // Fused Multiply Add
171#define IA32_FEATURE_EXT_CX16		(1 << 13) // CMPXCHG16B
172#define IA32_FEATURE_EXT_XTPR		(1 << 14) // xTPR Update Control
173#define IA32_FEATURE_EXT_PDCM		(1 << 15) // Perfmon and Debug Capability
174//									(1 << 16) // Reserved
175#define IA32_FEATURE_EXT_PCID		(1 << 17) // Process Context Identifiers
176#define IA32_FEATURE_EXT_DCA		(1 << 18) // Direct Cache Access
177#define IA32_FEATURE_EXT_SSE4_1		(1 << 19) // SSE4.1
178#define IA32_FEATURE_EXT_SSE4_2		(1 << 20) // SSE4.2
179#define IA32_FEATURE_EXT_X2APIC		(1 << 21) // Extended xAPIC Support
180#define IA32_FEATURE_EXT_MOVBE 		(1 << 22) // MOVBE Instruction
181#define IA32_FEATURE_EXT_POPCNT		(1 << 23) // POPCNT Instruction
182#define IA32_FEATURE_EXT_TSCDEADLINE (1 << 24) // Time Stamp Counter Deadline
183#define IA32_FEATURE_EXT_AES		(1 << 25) // AES Instruction Extensions
184#define IA32_FEATURE_EXT_XSAVE		(1 << 26) // XSAVE/XSTOR States
185#define IA32_FEATURE_EXT_OSXSAVE	(1 << 27) // OS-Enabled XSAVE
186#define IA32_FEATURE_EXT_AVX		(1 << 28) // Advanced Vector Extensions
187#define IA32_FEATURE_EXT_F16C		(1 << 29) // 16-bit FP conversion
188#define IA32_FEATURE_EXT_RDRND		(1 << 30) // RDRAND instruction
189#define IA32_FEATURE_EXT_HYPERVISOR	(1 << 31) // Running on a hypervisor
190
191// x86 features from cpuid eax 0x80000001, ecx register (AMD)
192#define IA32_FEATURE_AMD_EXT_CMPLEGACY	(1 << 1) // Core MP legacy mode
193#define IA32_FEATURE_AMD_EXT_TOPOLOGY	(1 << 22) // Topology extensions
194
195// x86 features from cpuid eax 0x80000001, edx register (AMD)
196// only care about the ones that are unique to this register
197#define IA32_FEATURE_AMD_EXT_SYSCALL	(1 << 11) // SYSCALL/SYSRET
198#define IA32_FEATURE_AMD_EXT_NX			(1 << 20) // no execute bit
199#define IA32_FEATURE_AMD_EXT_MMXEXT		(1 << 22) // mmx extensions
200#define IA32_FEATURE_AMD_EXT_FFXSR		(1 << 25) // fast FXSAVE/FXRSTOR
201#define IA32_FEATURE_AMD_EXT_RDTSCP		(1 << 27) // rdtscp instruction
202#define IA32_FEATURE_AMD_EXT_LONG		(1 << 29) // long mode
203#define IA32_FEATURE_AMD_EXT_3DNOWEXT	(1 << 30) // 3DNow! extensions
204#define IA32_FEATURE_AMD_EXT_3DNOW		(1 << 31) // 3DNow!
205
206// some of the features from cpuid eax 0x80000001, edx register (AMD) are also
207// available on Intel processors
208#define IA32_FEATURES_INTEL_EXT			(IA32_FEATURE_AMD_EXT_SYSCALL		\
209											| IA32_FEATURE_AMD_EXT_NX		\
210											| IA32_FEATURE_AMD_EXT_RDTSCP	\
211											| IA32_FEATURE_AMD_EXT_LONG)
212
213// x86 defined features from cpuid eax 5, ecx register
214#define IA32_FEATURE_POWER_MWAIT		(1 << 0)
215#define IA32_FEATURE_INTERRUPT_MWAIT	(1 << 1)
216
217// x86 defined features from cpuid eax 6, eax register
218// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11)
219#define IA32_FEATURE_DTS	(1 << 0) // Digital Thermal Sensor
220#define IA32_FEATURE_ITB	(1 << 1) // Intel Turbo Boost Technology
221#define IA32_FEATURE_ARAT	(1 << 2) // Always running APIC Timer
222#define IA32_FEATURE_PLN	(1 << 4) // Power Limit Notification
223#define IA32_FEATURE_ECMD	(1 << 5) // Extended Clock Modulation Duty
224#define IA32_FEATURE_PTM	(1 << 6) // Package Thermal Management
225
226// x86 defined features from cpuid eax 6, ecx register
227// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11)
228#define IA32_FEATURE_APERFMPERF	(1 << 0) // IA32_APERF, IA32_MPERF
229#define IA32_FEATURE_EPB	(1 << 3) // IA32_ENERGY_PERF_BIAS
230
231// x86 features from cpuid eax 7, ebx register
232// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8)
233#define IA32_FEATURE_TSC_ADJUST	(1 << 1) // IA32_TSC_ADJUST MSR supported
234#define IA32_FEATURE_SGX		(1 << 2) // Software Guard Extensions
235#define IA32_FEATURE_BMI1		(1 << 3) // Bit Manipulation Instruction Set 1
236#define IA32_FEATURE_HLE		(1 << 4) // Hardware Lock Elision
237#define IA32_FEATURE_AVX2		(1 << 5) // Advanced Vector Extensions 2
238#define IA32_FEATURE_SMEP		(1 << 7) // Supervisor-Mode Execution Prevention
239#define IA32_FEATURE_BMI2		(1 << 8) // Bit Manipulation Instruction Set 2
240#define IA32_FEATURE_ERMS		(1 << 9) // Enhanced REP MOVSB/STOSB
241#define IA32_FEATURE_INVPCID	(1 << 10) // INVPCID instruction
242#define IA32_FEATURE_RTM		(1 << 11) // Transactional Synchronization Extensions
243#define IA32_FEATURE_CQM		(1 << 12) // Platform Quality of Service Monitoring
244#define IA32_FEATURE_MPX		(1 << 14) // Memory Protection Extensions
245#define IA32_FEATURE_RDT_A		(1 << 15) // Resource Director Technology Allocation
246#define IA32_FEATURE_AVX512F	(1 << 16) // AVX-512 Foundation
247#define IA32_FEATURE_AVX512DQ	(1 << 17) // AVX-512 Doubleword and Quadword Instructions
248#define IA32_FEATURE_RDSEED		(1 << 18) // RDSEED instruction
249#define IA32_FEATURE_ADX		(1 << 19) // ADX (Multi-Precision Add-Carry Instruction Extensions)
250#define IA32_FEATURE_SMAP		(1 << 20) // Supervisor Mode Access Prevention
251#define IA32_FEATURE_AVX512IFMA	(1 << 21) // AVX-512 Integer Fused Multiply-Add Instructions
252#define IA32_FEATURE_PCOMMIT	(1 << 22) // PCOMMIT instruction
253#define IA32_FEATURE_CLFLUSHOPT	(1 << 23) // CLFLUSHOPT instruction
254#define IA32_FEATURE_CLWB		(1 << 24) // CLWB instruction
255#define IA32_FEATURE_INTEL_PT	(1 << 25) // Intel Processor Trace
256#define IA32_FEATURE_AVX512PF	(1 << 26) // AVX-512 Prefetch Instructions
257#define IA32_FEATURE_AVX512ER	(1 << 27) // AVX-512 Exponential and Reciprocal Instructions
258#define IA32_FEATURE_AVX512CD	(1 << 28) // AVX-512 Conflict Detection Instructions
259#define IA32_FEATURE_SHA_NI		(1 << 29) // SHA extensions
260#define IA32_FEATURE_AVX512BW	(1 << 30) // AVX-512 Byte and Word Instructions
261#define IA32_FEATURE_AVX512VI	(1 << 31) // AVX-512 Vector Length Extensions
262
263// x86 features from cpuid eax 7, ecx register
264// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8)
265// https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features
266#define IA32_FEATURE_AVX512VMBI		(1 << 1) // AVX-512 Vector Bit Manipulation Instructions
267#define IA32_FEATURE_UMIP			(1 << 2) // User-mode Instruction Prevention
268#define IA32_FEATURE_PKU			(1 << 3) // Memory Protection Keys for User-mode pages
269#define IA32_FEATURE_OSPKE			(1 << 4) // PKU enabled by OS
270#define IA32_FEATURE_AVX512VMBI2	(1 << 6) // AVX-512 Vector Bit Manipulation Instructions 2
271#define IA32_FEATURE_GFNI			(1 << 8) // Galois Field instructions
272#define IA32_FEATURE_VAES			(1 << 9) // AES instruction set (VEX-256/EVEX)
273#define IA32_FEATURE_VPCLMULQDQ		(1 << 10) // CLMUL instruction set (VEX-256/EVEX)
274#define IA32_FEATURE_AVX512_VNNI	(1 << 11) // AVX-512 Vector Neural Network Instructions
275#define IA32_FEATURE_AVX512_BITALG	(1 << 12) // AVX-512 BITALG instructions
276#define IA32_FEATURE_AVX512_VPOPCNTDQ (1 << 14) // AVX-512 Vector Population Count D/Q
277#define IA32_FEATURE_LA57			(1 << 16) // 5-level page tables
278#define IA32_FEATURE_RDPID			(1 << 22) // RDPID Instruction
279#define IA32_FEATURE_SGX_LC			(1 << 30) // SGX Launch Configuration
280
281// x86 features from cpuid eax 7, edx register
282// https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features
283#define IA32_FEATURE_AVX512_4VNNIW	(1 << 2) // AVX-512 4-register Neural Network Instructions
284#define IA32_FEATURE_AVX512_4FMAPS	(1 << 3) // AVX-512 4-register Multiply Accumulation Single precision
285#define IA32_FEATURE_IBRS			(1 << 26)	// IBRS / IBPB Speculation Control
286#define IA32_FEATURE_STIBP			(1 << 27)	// STIBP Speculation Control
287#define IA32_FEATURE_L1D_FLUSH		(1 << 28)	// L1D_FLUSH supported
288#define IA32_FEATURE_ARCH_CAPABILITIES	(1 << 29)	// IA32_ARCH_CAPABILITIES MSR
289#define IA32_FEATURE_SSBD			(1 << 30)	// Speculative Store Bypass Disable
290
291// x86 defined features from cpuid eax 0x80000007, edx register
292#define IA32_FEATURE_INVARIANT_TSC		(1 << 8)
293
294// x86 defined features from cpuid eax 0x80000008, ebx register
295#define IA32_FEATURE_AMD_EXT_IBPB	(1 << 12)	/* IBPB Support only (no IBRS) */
296
297
298// Memory type ranges
299#define IA32_MTR_UNCACHED				0
300#define IA32_MTR_WRITE_COMBINING		1
301#define IA32_MTR_WRITE_THROUGH			4
302#define IA32_MTR_WRITE_PROTECTED		5
303#define IA32_MTR_WRITE_BACK				6
304
305// EFLAGS register
306#define X86_EFLAGS_CARRY						0x00000001
307#define X86_EFLAGS_RESERVED1					0x00000002
308#define X86_EFLAGS_PARITY						0x00000004
309#define X86_EFLAGS_AUXILIARY_CARRY				0x00000010
310#define X86_EFLAGS_ZERO							0x00000040
311#define X86_EFLAGS_SIGN							0x00000080
312#define X86_EFLAGS_TRAP							0x00000100
313#define X86_EFLAGS_INTERRUPT					0x00000200
314#define X86_EFLAGS_DIRECTION					0x00000400
315#define X86_EFLAGS_OVERFLOW						0x00000800
316#define X86_EFLAGS_IO_PRIVILEG_LEVEL			0x00003000
317#define X86_EFLAGS_IO_PRIVILEG_LEVEL_SHIFT		12
318#define X86_EFLAGS_NESTED_TASK					0x00004000
319#define X86_EFLAGS_RESUME						0x00010000
320#define X86_EFLAGS_V86_MODE						0x00020000
321#define X86_EFLAGS_ALIGNMENT_CHECK				0x00040000	// also SMAP status
322#define X86_EFLAGS_VIRTUAL_INTERRUPT			0x00080000
323#define X86_EFLAGS_VIRTUAL_INTERRUPT_PENDING	0x00100000
324#define X86_EFLAGS_ID							0x00200000
325
326#define X86_EFLAGS_USER_FLAGS	(X86_EFLAGS_CARRY | X86_EFLAGS_PARITY \
327	| X86_EFLAGS_AUXILIARY_CARRY | X86_EFLAGS_ZERO | X86_EFLAGS_SIGN \
328	| X86_EFLAGS_DIRECTION | X86_EFLAGS_OVERFLOW)
329
330#define CR0_CACHE_DISABLE		(1UL << 30)
331#define CR0_NOT_WRITE_THROUGH	(1UL << 29)
332#define CR0_FPU_EMULATION		(1UL << 2)
333#define CR0_MONITOR_FPU			(1UL << 1)
334
335// cr4 flags
336#define IA32_CR4_PAE			(1UL << 5)
337#define IA32_CR4_GLOBAL_PAGES	(1UL << 7)
338#define CR4_OS_FXSR				(1UL << 9)
339#define CR4_OS_XMM_EXCEPTION	(1UL << 10)
340#define IA32_CR4_SMEP			(1UL << 20)
341#define IA32_CR4_SMAP			(1UL << 21)
342
343// page fault error codes (http://wiki.osdev.org/Page_Fault)
344#define PGFAULT_P						0x01	// Protection violation
345#define PGFAULT_W						0x02	// Write
346#define PGFAULT_U						0x04	// Usermode
347#define PGFAULT_RSVD					0x08	// Reserved bits
348#define PGFAULT_I						0x10	// Instruction fetch
349
350// iframe types
351#define IFRAME_TYPE_SYSCALL				0x1
352#define IFRAME_TYPE_OTHER				0x2
353#define IFRAME_TYPE_MASK				0xf
354
355
356#ifndef _ASSEMBLER
357
358
359struct X86PagingStructures;
360
361
362typedef struct x86_mtrr_info {
363	uint64	base;
364	uint64	size;
365	uint8	type;
366} x86_mtrr_info;
367
368typedef struct x86_cpu_module_info {
369	module_info	info;
370	uint32		(*count_mtrrs)(void);
371	void		(*init_mtrrs)(void);
372
373	void		(*set_mtrr)(uint32 index, uint64 base, uint64 length,
374					uint8 type);
375	status_t	(*get_mtrr)(uint32 index, uint64* _base, uint64* _length,
376					uint8* _type);
377	void		(*set_mtrrs)(uint8 defaultType, const x86_mtrr_info* infos,
378					uint32 count);
379} x86_cpu_module_info;
380
381// features
382enum x86_feature_type {
383	FEATURE_COMMON = 0,     // cpuid eax=1, ecx register
384	FEATURE_EXT,            // cpuid eax=1, edx register
385	FEATURE_EXT_AMD_ECX,	// cpuid eax=0x80000001, ecx register (AMD)
386	FEATURE_EXT_AMD,        // cpuid eax=0x80000001, edx register (AMD)
387	FEATURE_5_ECX,			// cpuid eax=5, ecx register
388	FEATURE_6_EAX,          // cpuid eax=6, eax registers
389	FEATURE_6_ECX,          // cpuid eax=6, ecx registers
390	FEATURE_7_EBX,          // cpuid eax=7, ebx registers
391	FEATURE_7_ECX,          // cpuid eax=7, ecx registers
392	FEATURE_7_EDX,          // cpuid eax=7, edx registers
393	FEATURE_EXT_7_EDX,		// cpuid eax=0x80000007, edx register
394	FEATURE_EXT_8_EBX,		// cpuid eax=0x80000008, ebx register
395
396	FEATURE_NUM
397};
398
399enum x86_vendors {
400	VENDOR_INTEL = 0,
401	VENDOR_AMD,
402	VENDOR_CYRIX,
403	VENDOR_UMC,
404	VENDOR_NEXGEN,
405	VENDOR_CENTAUR,
406	VENDOR_RISE,
407	VENDOR_TRANSMETA,
408	VENDOR_NSC,
409
410	VENDOR_NUM,
411	VENDOR_UNKNOWN,
412};
413
414
415typedef struct arch_cpu_info {
416	// saved cpu info
417	enum x86_vendors	vendor;
418	uint32				feature[FEATURE_NUM];
419	char				model_name[49];
420	const char*			vendor_name;
421	int					type;
422	int					family;
423	int					extended_family;
424	int					stepping;
425	int					model;
426	int					extended_model;
427
428	uint32				logical_apic_id;
429
430	struct X86PagingStructures* active_paging_structures;
431
432	size_t				dr6;	// temporary storage for debug registers (cf.
433	size_t				dr7;	// x86_exit_user_debug_at_kernel_entry())
434
435	// local TSS for this cpu
436	struct tss			tss;
437#ifndef __x86_64__
438	struct tss			double_fault_tss;
439	void*				kernel_tls;
440#endif
441} arch_cpu_info;
442
443
444#define nop() __asm__ ("nop"::)
445
446#define x86_read_cr0() ({ \
447	size_t _v; \
448	__asm__("mov	%%cr0,%0" : "=r" (_v)); \
449	_v; \
450})
451
452#define x86_write_cr0(value) \
453	__asm__("mov	%0,%%cr0" : : "r" (value))
454
455#define x86_read_cr2() ({ \
456	size_t _v; \
457	__asm__("mov	%%cr2,%0" : "=r" (_v)); \
458	_v; \
459})
460
461#define x86_read_cr3() ({ \
462	size_t _v; \
463	__asm__("mov	%%cr3,%0" : "=r" (_v)); \
464	_v; \
465})
466
467#define x86_write_cr3(value) \
468	__asm__("mov	%0,%%cr3" : : "r" (value))
469
470#define x86_read_cr4() ({ \
471	size_t _v; \
472	__asm__("mov	%%cr4,%0" : "=r" (_v)); \
473	_v; \
474})
475
476#define x86_write_cr4(value) \
477	__asm__("mov	%0,%%cr4" : : "r" (value))
478
479#define x86_read_dr3() ({ \
480	size_t _v; \
481	__asm__("mov	%%dr3,%0" : "=r" (_v)); \
482	_v; \
483})
484
485#define x86_write_dr3(value) \
486	__asm__("mov	%0,%%dr3" : : "r" (value))
487
488#define invalidate_TLB(va) \
489	__asm__("invlpg (%0)" : : "r" (va))
490
491#define wbinvd() \
492	__asm__("wbinvd")
493
494#define set_ac() \
495	__asm__ volatile (ASM_STAC : : : "memory")
496
497#define clear_ac() \
498	__asm__ volatile (ASM_CLAC : : : "memory")
499
500#define out8(value,port) \
501	__asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port))
502
503#define out16(value,port) \
504	__asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port))
505
506#define out32(value,port) \
507	__asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port))
508
509#define in8(port) ({ \
510	uint8 _v; \
511	__asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \
512	_v; \
513})
514
515#define in16(port) ({ \
516	uint16 _v; \
517	__asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \
518	_v; \
519})
520
521#define in32(port) ({ \
522	uint32 _v; \
523	__asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \
524	_v; \
525})
526
527#define out8_p(value,port) \
528	__asm__ ("outb %%al,%%dx\n" \
529		"\tjmp 1f\n" \
530		"1:\tjmp 1f\n" \
531		"1:" : : "a" (value), "d" (port))
532
533#define in8_p(port) ({ \
534	uint8 _v; \
535	__asm__ volatile ("inb %%dx,%%al\n" \
536		"\tjmp 1f\n" \
537		"1:\tjmp 1f\n" \
538		"1:" : "=a" (_v) : "d" (port)); \
539	_v; \
540})
541
542
543extern void (*gCpuIdleFunc)(void);
544
545
546#ifdef __cplusplus
547extern "C" {
548#endif
549
550struct arch_thread;
551
552#ifdef __x86_64__
553void __x86_setup_system_time(uint64 conversionFactor,
554	uint64 conversionFactorNsecs);
555#else
556void __x86_setup_system_time(uint32 conversionFactor,
557	uint32 conversionFactorNsecs, bool conversionFactorNsecsShift);
558#endif
559
560void x86_userspace_thread_exit(void);
561void x86_end_userspace_thread_exit(void);
562
563addr_t x86_get_stack_frame();
564uint32 x86_count_mtrrs(void);
565void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type);
566status_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length,
567	uint8* _type);
568void x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos,
569	uint32 count);
570void x86_init_fpu();
571bool x86_check_feature(uint32 feature, enum x86_feature_type type);
572void* x86_get_double_fault_stack(int32 cpu, size_t* _size);
573int32 x86_double_fault_get_cpu(void);
574
575void x86_invalid_exception(iframe* frame);
576void x86_fatal_exception(iframe* frame);
577void x86_unexpected_exception(iframe* frame);
578void x86_hardware_interrupt(iframe* frame);
579void x86_page_fault_exception(iframe* iframe);
580
581#ifndef __x86_64__
582
583void x86_swap_pgdir(addr_t newPageDir);
584
585uint64 x86_read_msr(uint32 registerNumber);
586void x86_write_msr(uint32 registerNumber, uint64 value);
587
588void x86_context_switch(struct arch_thread* oldState,
589	struct arch_thread* newState);
590
591void x86_fnsave(void* fpuState);
592void x86_frstor(const void* fpuState);
593
594void x86_fxsave(void* fpuState);
595void x86_fxrstor(const void* fpuState);
596
597void x86_noop_swap(void* oldFpuState, const void* newFpuState);
598void x86_fnsave_swap(void* oldFpuState, const void* newFpuState);
599void x86_fxsave_swap(void* oldFpuState, const void* newFpuState);
600
601#endif
602
603
604static inline void
605arch_cpu_idle(void)
606{
607	gCpuIdleFunc();
608}
609
610
611static inline void
612arch_cpu_pause(void)
613{
614	asm volatile("pause" : : : "memory");
615}
616
617
618#ifdef __cplusplus
619}	// extern "C" {
620#endif
621
622#endif	// !_ASSEMBLER
623
624#endif	/* _KERNEL_ARCH_x86_CPU_H */
625