omap3.h revision 83f5e2a2
1/*
2 * Copyright (c) 2008 Travis Geiselbrecht
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#ifndef __PLATFORM_OMAP3_H
24#define __PLATFORM_OMAP3_H
25
26#define SDRAM_BASE 0x80000000
27// Offset of stack top defined with respect to SDRAM_BASE
28#define KSTACK_TOP 0x2800000
29
30#define VECT_BASE 0x00000000
31#define VECT_SIZE 0x1000
32
33#define DEVICE_BASE 0x48000000
34#define DEVICE_SIZE 0x2000000
35
36/* framebuffer */
37#define FB_BASE 0x88000000
38#define FB_SIZE 0x200000
39
40#define L4_BASE     0x48000000
41#define L4_WKUP_BASE    0x48300000
42#define L4_PER_BASE 0x49000000
43#define L4_EMU_BASE 0x54000000
44#define GFX_BASE    0x50000000
45#define L3_BASE     0x68000000
46#define SMS_BASE    0x6C000000
47#define SDRC_BASE   0x6D000000
48#define GPMC_BASE   0x6E000000
49#define SCM_BASE    0x48002000
50
51/* clocks */
52#define CM_CLKSEL_PER		(L4_BASE + 0x5040)
53
54/* PRCM */
55#define CM_FCLKEN_IVA2      (L4_BASE + 0x4000)
56#define CM_CLKEN_PLL_IVA2   (L4_BASE + 0x4004)
57#define CM_IDLEST_PLL_IVA2  (L4_BASE + 0x4024)
58#define CM_CLKSEL1_PLL_IVA2 (L4_BASE + 0x4040)
59#define CM_CLKSEL2_PLL_IVA2 (L4_BASE + 0x4044)
60#define CM_CLKEN_PLL_MPU    (L4_BASE + 0x4904)
61#define CM_IDLEST_PLL_MPU   (L4_BASE + 0x4924)
62#define CM_CLKSEL1_PLL_MPU  (L4_BASE + 0x4940)
63#define CM_CLKSEL2_PLL_MPU  (L4_BASE + 0x4944)
64#define CM_FCLKEN1_CORE     (L4_BASE + 0x4a00)
65#define CM_ICLKEN1_CORE     (L4_BASE + 0x4a10)
66#define CM_ICLKEN2_CORE     (L4_BASE + 0x4a14)
67#define CM_CLKSEL_CORE      (L4_BASE + 0x4a40)
68#define CM_FCLKEN_GFX       (L4_BASE + 0x4b00)
69#define CM_ICLKEN_GFX       (L4_BASE + 0x4b10)
70#define CM_CLKSEL_GFX       (L4_BASE + 0x4b40)
71#define CM_FCLKEN_WKUP      (L4_BASE + 0x4c00)
72#define CM_ICLKEN_WKUP      (L4_BASE + 0x4c10)
73#define CM_CLKSEL_WKUP      (L4_BASE + 0x4c40)
74#define CM_IDLEST_WKUP      (L4_BASE + 0x4c20)
75#define CM_CLKEN_PLL        (L4_BASE + 0x4d00)
76#define CM_IDLEST_CKGEN     (L4_BASE + 0x4d20)
77#define CM_CLKSEL1_PLL      (L4_BASE + 0x4d40)
78#define CM_CLKSEL2_PLL      (L4_BASE + 0x4d44)
79#define CM_CLKSEL3_PLL      (L4_BASE + 0x4d48)
80#define CM_FCLKEN_DSS       (L4_BASE + 0x4e00)
81#define CM_ICLKEN_DSS       (L4_BASE + 0x4e10)
82#define CM_CLKSEL_DSS       (L4_BASE + 0x4e40)
83#define CM_FCLKEN_CAM       (L4_BASE + 0x4f00)
84#define CM_ICLKEN_CAM       (L4_BASE + 0x4f10)
85#define CM_CLKSEL_CAM       (L4_BASE + 0x4F40)
86#define CM_FCLKEN_PER       (L4_BASE + 0x5000)
87#define CM_ICLKEN_PER       (L4_BASE + 0x5010)
88#define CM_CLKSEL_PER       (L4_BASE + 0x5040)
89#define CM_CLKSEL1_EMU      (L4_BASE + 0x5140)
90
91#define PRM_CLKSEL			(L4_BASE + 0x306d40)
92#define PRM_RSTCTRL			(L4_BASE + 0x307250)
93#define PRM_CLKSRC_CTRL		(L4_BASE + 0x307270)
94
95/* General Purpose Timers */
96#define OMAP34XX_GPT1           (L4_BASE + 0x318000)
97#define OMAP34XX_GPT2           (L4_BASE + 0x1032000)
98#define OMAP34XX_GPT3           (L4_BASE + 0x1034000)
99#define OMAP34XX_GPT4           (L4_BASE + 0x1036000)
100#define OMAP34XX_GPT5           (L4_BASE + 0x1038000)
101#define OMAP34XX_GPT6           (L4_BASE + 0x103A000)
102#define OMAP34XX_GPT7           (L4_BASE + 0x103C000)
103#define OMAP34XX_GPT8           (L4_BASE + 0x103E000)
104#define OMAP34XX_GPT9           (L4_BASE + 0x1040000)
105#define OMAP34XX_GPT10          (L4_BASE + 0x86000)
106#define OMAP34XX_GPT11          (L4_BASE + 0x88000)
107#define OMAP34XX_GPT12          (L4_BASE + 0x304000)
108
109#define TIDR				0x00
110#define TIOCP_CFG			0x10
111#define TISTAT				0x14
112#define TISR				0x18
113#define TIER				0x1C
114#define TWER				0x20
115#define TCLR				0x24
116#define TCRR				0x28
117#define TLDR				0x2C
118#define TTGR				0x30
119#define TWPS				0x34
120#define TMAR				0x38
121#define TCAR1				0x3C
122#define TSICR				0x40
123#define TCAR2				0x44
124#define TPIR				0x48
125#define TNIR				0x4C
126#define TCVR				0x50
127#define TOCR				0x54
128#define TOWR				0x58
129
130/* WatchDog Timers (1 secure, 3 GP) */
131#define WD1_BASE            (0x4830C000)
132#define WD2_BASE            (0x48314000)
133#define WD3_BASE            (0x49030000)
134
135#define WIDR		0x00
136#define WD_SYSCONFIG	0x10
137#define WD_SYSSTATUS	0x14
138#define WISR		0x18
139#define WIER		0x1C
140#define WCLR		0x24
141#define WCRR		0x28
142#define WLDR		0x2C
143#define WTGR		0x30
144#define WWPS		0x34
145#define WSPR		0x48
146
147#define W_PEND_WCLR	(1<<0)
148#define W_PEND_WCRR	(1<<1)
149#define W_PEND_WLDR	(1<<2)
150#define W_PEND_WTGR	(1<<3)
151#define W_PEND_WSPR	(1<<4)
152
153#define WD_UNLOCK1      0xAAAA
154#define WD_UNLOCK2      0x5555
155
156/* 32KTIMER */
157#define TIMER32K_BASE		(L4_BASE + 0x320000)
158#define TIMER32K_REV		(TIMER32K_BASE + 0x00)
159#define TIMER32K_CR			(TIMER32K_BASE + 0x10)
160
161/* UART */
162#define OMAP_UART1_BASE     (L4_BASE + 0x6a000)
163#define OMAP_UART2_BASE     (L4_BASE + 0x6c000)
164#define OMAP_UART3_BASE     (L4_BASE + 0x01020000)
165
166#define UART_RHR    0
167#define UART_THR    0
168#define UART_DLL    0
169#define UART_IER    1
170#define UART_DLH    1
171#define UART_IIR    2
172#define UART_FCR    2
173#define UART_EFR    2
174#define UART_LCR    3
175#define UART_MCR    4
176#define UART_LSR    5
177#define UART_MSR    6
178#define UART_TCR    6
179#define UART_SPR    7
180#define UART_TLR    7
181#define UART_MDR1   8
182#define UART_MDR2   9
183#define UART_SFLSR  10
184#define UART_RESUME 11
185#define UART_TXFLL  10
186#define UART_TXFLH  11
187#define UART_SFREGL 12
188#define UART_SFREGH 13
189#define UART_RXFLL  12
190#define UART_RXFLH  13
191#define UART_BLR    14
192#define UART_UASR   14
193#define UART_ACREG  15
194#define UART_SCR    16
195#define UART_SSR    17
196#define UART_EBLR   18
197#define UART_MVR    19
198#define UART_SYSC   20
199
200/* MPU INTC */
201#define INTC_BASE			(L4_BASE + 0x200000)
202#define INTC_REVISION		(INTC_BASE + 0x000)
203#define INTC_SYSCONFIG		(INTC_BASE + 0x010)
204#define INTC_SYSSTATUS		(INTC_BASE + 0x014)
205#define INTC_SIR_IRQ		(INTC_BASE + 0x040)
206#define INTC_SIR_FIQ		(INTC_BASE + 0x044)
207#define INTC_CONTROL		(INTC_BASE + 0x048)
208#define INTC_PROTECTION		(INTC_BASE + 0x04C)
209#define INTC_IDLE			(INTC_BASE + 0x050)
210#define INTC_IRQ_PRIORITY	(INTC_BASE + 0x060)
211#define INTC_FIQ_PRIORITY	(INTC_BASE + 0x064)
212#define INTC_THRESHOLD		(INTC_BASE + 0x068)
213#define INTC_ITR(n)			(INTC_BASE + 0x080 + (n) * 0x20)
214#define INTC_MIR(n)			(INTC_BASE + 0x084 + (n) * 0x20)
215#define INTC_MIR_CLEAR(n)	(INTC_BASE + 0x088 + (n) * 0x20)
216#define INTC_MIR_SET(n)		(INTC_BASE + 0x08C + (n) * 0x20)
217#define INTC_ISR_SET(n)		(INTC_BASE + 0x090 + (n) * 0x20)
218#define INTC_ISR_CLEAR(n)	(INTC_BASE + 0x094 + (n) * 0x20)
219#define INTC_PENDING_IRQ(n)	(INTC_BASE + 0x098 + (n) * 0x20)
220#define INTC_PENDING_FIQ(n)	(INTC_BASE + 0x09C + (n) * 0x20)
221#define INTC_ILR(n)			(INTC_BASE + 0x100 + (n) * 4)
222
223/* interrupts */
224#define INT_VECTORS 		96
225#define GPT2_IRQ			38
226
227/* HS USB */
228#define USB_HS_BASE			(L4_BASE + 0xab000)
229
230/* USB OTG */
231#define OTG_BASE			(L4_BASE + 0xab400)
232
233#define OTG_REVISION		(OTG_BASE + 0x00)
234#define OTG_SYSCONFIG		(OTG_BASE + 0x04)
235#define OTG_SYSSTATUS		(OTG_BASE + 0x08)
236#define OTG_INTERFSEL		(OTG_BASE + 0x0C)
237#define OTG_SIMENABLE		(OTG_BASE + 0x10)
238#define OTG_FORCESTDBY		(OTG_BASE + 0x14)
239
240/* I2C */
241#define I2C1_BASE		(L4_BASE + 0x70000)
242#define I2C2_BASE		(L4_BASE + 0x72000)
243#define I2C3_BASE		(L4_BASE + 0x60000)
244
245#define I2C_REV				(0x00)
246#define I2C_IE				(0x04)
247#define I2C_STAT			(0x08)
248#define I2C_WE				(0x0C)
249#define I2C_SYSS			(0x10)
250#define I2C_BUF				(0x14)
251#define I2C_CNT				(0x18)
252#define I2C_DATA			(0x1C)
253#define I2C_SYSC			(0x20)
254#define I2C_CON				(0x24)
255#define I2C_OA0				(0x28)
256#define I2C_SA				(0x2C)
257#define I2C_PSC				(0x30)
258#define I2C_SCLL			(0x34)
259#define I2C_SCLH			(0x38)
260#define I2C_SYSTEST			(0x3C)
261#define I2C_BUFSTAT			(0x40)
262#define I2C_OA1				(0x44)
263#define I2C_OA2				(0x48)
264#define I2C_OA3				(0x4C)
265#define I2C_ACTOA			(0x50)
266#define I2C_SBLOCK			(0x54)
267
268/* GPIO */
269#define GPIO1_BASE 0x48310000
270#define GPIO2_BASE 0x49050000
271#define GPIO3_BASE 0x49052000
272#define GPIO4_BASE 0x49054000
273#define GPIO5_BASE 0x49056000
274#define GPIO6_BASE 0x49058000
275
276/* (incomplete) */
277#define GPIO_OE 0x034
278#define GPIO_DATAIN 0x038
279#define GPIO_DATAOUT 0x03C
280#define GPIO_SETDATAOUT 0x094
281
282#endif
283
284