bcm283X.h revision 523c77e0
1/*
2 * Copyright (c) 2012 Haiku Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 *		Alexander von Gluck, kallisti5@unixzen.com
25 */
26#ifndef __PLATFORM_BCM283X_H
27#define __PLATFORM_BCM283X_H
28
29
30#define SIZE_4K 0x00001000
31
32
33/*
34 * Found in:
35 * Broadcom BCM2835 ARM Peripherals
36 *  - BCM2835-ARM-Peripherals.pdf
37 */
38
39// Section 1.2.2
40#define BCM283X_SDRAM_BASE		0x00000000
41#define BCM283X_PERIPHERAL_BASE	0x20000000
42
43// Added to physical addresses to select the different cache behaviours
44#define BCM283X_VIDEO_CORE_L1_L2_CACHED		(0 << 30)
45#define BCM283X_VIDEO_CORE_L2_COHERENT		(1 << 30)
46#define BCM283X_VIDEO_CORE_L2_CACHED		(2 << 30)
47#define BCM283X_VIDEO_CORE_UNCACHED			(3 << 30)
48
49// The highest two bits are used to select aliases to the physical memory
50// with different cache semantic. Clearing them converts the address to
51// physical memory as seen by ARM.
52#define BCM283X_BUS_TO_PHYSICAL(x)			(x & ~BCM283X_VIDEO_CORE_UNCACHED)
53
54
55#define ST_BASE			0x3000
56	// System Timer, sec 12.0, page 172
57#define DMA_BASE		0x7000
58	// DMA Controller, sec 4.2, page 39
59#define ARM_BASE		0xB000
60	// BCM283X ARM Control Block, sec 7.5, page 112
61#define PM_BASE			0x100000
62	// Power Management, Reset controller and Watchdog registers
63#define GPIO_BASE		0x200000
64	// GPIO, sec 6.1, page 90
65#define UART0_BASE		0x201000
66	// UART 0, sec 13.4, page 177
67#define MMCI0_BASE		0x202000
68	// MMC
69#define UART1_BASE		0x215000
70	// UART 1, sec 2.1, page 65
71#define EMMC_BASE		0x300000
72	// eMMC interface, sec 5, page 66
73#define SMI_BASE		0x600000
74	// SMI Base
75#define USB_BASE		0x980000
76	// USB Controller, 15.2, page 202
77// FB_BASE will depend on memory split
78
79
80// 7.5, page 112
81#define ARM_CTRL_BASE			(ARM_BASE + 0x000)
82#define ARM_CTRL_IC_BASa		(ARM_BASE + 0x200)
83	// Interrupt controller
84#define ARM_CTRL_TIMER0_1_BASE	(ARM_BASE + 0x400)
85	// Timer 0 and 1
86#define ARM_CTRL_0_SBM_BASE		(ARM_BASE + 0x800)
87	// ARM Semaphores, Doorbells, and Mailboxes
88
89#define VECT_BASE 0xFFFF0000
90#define VECT_SIZE SIZE_4K
91
92#define DEVICE_BASE	BCM283X_PERIPHERAL_BASE
93#define DEVICE_SIZE	0xFFFFFF
94
95#define SDRAM_BASE		BCM283X_SDRAM_BASE
96#define SDRAM_SIZE		0x4000000
97	// 64Mb
98
99
100/* UART */
101// TODO: Check these UART defines!
102#define UART_RHR    0
103#define UART_THR    0
104#define UART_DLL    0
105#define UART_IER    1
106#define UART_DLH    1
107#define UART_IIR    2
108#define UART_FCR    2
109#define UART_EFR    2
110#define UART_LCR    3
111#define UART_MCR    4
112#define UART_LSR    5
113#define UART_MSR    6
114#define UART_TCR    6
115#define UART_SPR    7
116#define UART_TLR    7
117#define UART_MDR1   8
118#define UART_MDR2   9
119#define UART_SFLSR  10
120#define UART_RESUME 11
121#define UART_TXFLL  10
122#define UART_TXFLH  11
123#define UART_SFREGL 12
124#define UART_SFREGH 13
125#define UART_RXFLL  12
126#define UART_RXFLH  13
127#define UART_BLR    14
128#define UART_UASR   14
129#define UART_ACREG  15
130#define UART_SCR    16
131#define UART_SSR    17
132#define UART_EBLR   18
133#define UART_MVR    19
134#define UART_SYSC   20
135
136
137/* Mailbox */
138#define ARM_CTRL_0_MAILBOX_BASE				(ARM_CTRL_0_SBM_BASE + 0x80)
139
140#define ARM_MAILBOX_READ					0x00
141#define ARM_MAILBOX_STATUS					0x18
142#define ARM_MAILBOX_WRITE					0x20
143
144#define ARM_MAILBOX_FULL					(1 << 31)
145#define ARM_MAILBOX_EMPTY					(1 << 30)
146
147#define ARM_MAILBOX_DATA_MASK				0xfffffff0
148#define ARM_MAILBOX_CHANNEL_MASK			0x0000000f
149
150#define ARM_MAILBOX_CHANNEL_FRAMEBUFFER		1
151
152#endif /* __PLATFORM_BCM283X_H */
153