bcm283X.h revision 196479ae
1/*
2 * Copyright (c) 2012-2015 Haiku, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 *		Alexander von Gluck, kallisti5@unixzen.com
25 */
26#ifndef __PLATFORM_BCM283X_H
27#define __PLATFORM_BCM283X_H
28
29
30#include <board_config.h>
31
32
33#define SIZE_4K 0x00001000
34
35/*
36 * Found in:
37 * Broadcom BCM2835 ARM Peripherals
38 *  - BCM2835-ARM-Peripherals.pdf
39 */
40
41// Section 1.2.2
42#define BCM283X_SDRAM_BASE		0x00000000
43#if defined(BOARD_CPU_BCM2835)
44#define BCM283X_PERIPHERAL_BASE	0x20000000
45#elif defined(BOARD_CPU_BCM2836)
46#define BCM283X_PERIPHERAL_BASE	0x3f000000
47#else
48#error Unknown BCM283X!
49#endif
50
51
52// Added to physical addresses to select the different cache behaviours
53#define BCM283X_VIDEO_CORE_L1_L2_CACHED		(0 << 30)
54#define BCM283X_VIDEO_CORE_L2_COHERENT		(1 << 30)
55#define BCM283X_VIDEO_CORE_L2_CACHED		(2 << 30)
56#define BCM283X_VIDEO_CORE_UNCACHED			(3 << 30)
57
58// The highest two bits are used to select aliases to the physical memory
59// with different cache semantic. Clearing them converts the address to
60// physical memory as seen by ARM.
61#define BCM283X_BUS_TO_PHYSICAL(x)			(x & ~BCM283X_VIDEO_CORE_UNCACHED)
62
63
64#define ST_BASE			0x3000
65	// System Timer, sec 12.0, page 172
66#define DMA_BASE		0x7000
67	// DMA Controller, sec 4.2, page 39
68#define ARM_BASE		0xB000
69	// BCM283X ARM Control Block, sec 7.5, page 112
70#define PM_BASE			0x100000
71	// Power Management, Reset controller and Watchdog registers
72#define GPIO_BASE		0x200000
73	// GPIO, sec 6.1, page 90
74#define UART0_BASE		0x201000
75	// UART 0, sec 13.4, page 177
76#define MMCI0_BASE		0x202000
77	// MMC
78#define UART1_BASE		0x215000
79	// UART 1, sec 2.1, page 65
80#define EMMC_BASE		0x300000
81	// eMMC interface, sec 5, page 66
82#define SMI_BASE		0x600000
83	// SMI Base
84#define USB_BASE		0x980000
85	// USB Controller, 15.2, page 202
86// FB_BASE will depend on memory split
87
88
89// 7.5, page 112
90#define ARM_CTRL_BASE			(ARM_BASE + 0x000)
91#define ARM_CTRL_IC_BASa		(ARM_BASE + 0x200)
92	// Interrupt controller
93#define ARM_CTRL_TIMER0_1_BASE	(ARM_BASE + 0x400)
94	// Timer 0 and 1
95#define ARM_CTRL_0_SBM_BASE		(ARM_BASE + 0x800)
96	// ARM Semaphores, Doorbells, and Mailboxes
97
98#define VECT_BASE 0xFFFF0000
99#define VECT_SIZE SIZE_4K
100
101#define DEVICE_BASE	BCM283X_PERIPHERAL_BASE
102#define DEVICE_SIZE	0xFFFFFF
103
104#define SDRAM_BASE		BCM283X_SDRAM_BASE
105#define SDRAM_SIZE		0x4000000
106	// 64Mb
107
108
109/* UART */
110// TODO: Check these UART defines!
111#define UART_RHR    0
112#define UART_THR    0
113#define UART_DLL    0
114#define UART_IER    1
115#define UART_DLH    1
116#define UART_IIR    2
117#define UART_FCR    2
118#define UART_EFR    2
119#define UART_LCR    3
120#define UART_MCR    4
121#define UART_LSR    5
122#define UART_MSR    6
123#define UART_TCR    6
124#define UART_SPR    7
125#define UART_TLR    7
126#define UART_MDR1   8
127#define UART_MDR2   9
128#define UART_SFLSR  10
129#define UART_RESUME 11
130#define UART_TXFLL  10
131#define UART_TXFLH  11
132#define UART_SFREGL 12
133#define UART_SFREGH 13
134#define UART_RXFLL  12
135#define UART_RXFLH  13
136#define UART_BLR    14
137#define UART_UASR   14
138#define UART_ACREG  15
139#define UART_SCR    16
140#define UART_SSR    17
141#define UART_EBLR   18
142#define UART_MVR    19
143#define UART_SYSC   20
144
145
146/* Mailbox */
147#define ARM_CTRL_0_MAILBOX_BASE				(ARM_CTRL_0_SBM_BASE + 0x80)
148
149#define ARM_MAILBOX_READ					0x00
150#define ARM_MAILBOX_STATUS					0x18
151#define ARM_MAILBOX_WRITE					0x20
152
153#define ARM_MAILBOX_FULL					(1 << 31)
154#define ARM_MAILBOX_EMPTY					(1 << 30)
155
156#define ARM_MAILBOX_DATA_MASK				0xfffffff0
157#define ARM_MAILBOX_CHANNEL_MASK			0x0000000f
158
159#define ARM_MAILBOX_CHANNEL_FRAMEBUFFER		1
160
161#endif /* __PLATFORM_BCM283X_H */
162