167f767c0SRudolf Cornelissen/*
267f767c0SRudolf Cornelissen	Copyright 1999, Be Incorporated.   All Rights Reserved.
367f767c0SRudolf Cornelissen	This file may be used under the terms of the Be Sample Code License.
467f767c0SRudolf Cornelissen
567f767c0SRudolf Cornelissen	Other authors:
667f767c0SRudolf Cornelissen	Mark Watson;
767f767c0SRudolf Cornelissen	Apsed;
814de50baSRudolf Cornelissen	Rudolf Cornelissen 10/2002-1/2016.
967f767c0SRudolf Cornelissen*/
1067f767c0SRudolf Cornelissen
1167f767c0SRudolf Cornelissen#ifndef DRIVERINTERFACE_H
1267f767c0SRudolf Cornelissen#define DRIVERINTERFACE_H
1367f767c0SRudolf Cornelissen
1467f767c0SRudolf Cornelissen#include <Accelerant.h>
1567f767c0SRudolf Cornelissen#include "video_overlay.h"
1667f767c0SRudolf Cornelissen#include <Drivers.h>
1767f767c0SRudolf Cornelissen#include <PCI.h>
1867f767c0SRudolf Cornelissen#include <OS.h>
1967f767c0SRudolf Cornelissen#include "AGP.h"
2067f767c0SRudolf Cornelissen
219784ce8dSRudolf Cornelissen#define DRIVER_PREFIX "via"
2267f767c0SRudolf Cornelissen
2367f767c0SRudolf Cornelissen/*
2467f767c0SRudolf Cornelissen	Internal driver state (also for sharing info between driver and accelerant)
2567f767c0SRudolf Cornelissen*/
2667f767c0SRudolf Cornelissen#if defined(__cplusplus)
2767f767c0SRudolf Cornelissenextern "C" {
2867f767c0SRudolf Cornelissen#endif
2967f767c0SRudolf Cornelissen
3067f767c0SRudolf Cornelissentypedef struct {
3167f767c0SRudolf Cornelissen	sem_id	sem;
3267f767c0SRudolf Cornelissen	int32	ben;
3367f767c0SRudolf Cornelissen} benaphore;
3467f767c0SRudolf Cornelissen
3567f767c0SRudolf Cornelissen#define INIT_BEN(x)		x.sem = create_sem(0, "NV "#x" benaphore");  x.ben = 0;
3667f767c0SRudolf Cornelissen#define AQUIRE_BEN(x)	if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
3767f767c0SRudolf Cornelissen#define RELEASE_BEN(x)	if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
3867f767c0SRudolf Cornelissen#define	DELETE_BEN(x)	delete_sem(x.sem);
3967f767c0SRudolf Cornelissen
4067f767c0SRudolf Cornelissen
417d971e51SRudolf Cornelissen#define VIA_PRIVATE_DATA_MAGIC	0x0009 /* a private driver rev, of sorts */
4267f767c0SRudolf Cornelissen
4367f767c0SRudolf Cornelissen/*dualhead extensions to flags*/
4467f767c0SRudolf Cornelissen#define DUALHEAD_OFF (0<<6)
4567f767c0SRudolf Cornelissen#define DUALHEAD_CLONE (1<<6)
4667f767c0SRudolf Cornelissen#define DUALHEAD_ON (2<<6)
4767f767c0SRudolf Cornelissen#define DUALHEAD_SWITCH (3<<6)
4867f767c0SRudolf Cornelissen#define DUALHEAD_BITS (3<<6)
4967f767c0SRudolf Cornelissen#define DUALHEAD_CAPABLE (1<<8)
5067f767c0SRudolf Cornelissen#define TV_BITS (3<<9)
5167f767c0SRudolf Cornelissen#define TV_MON (0<<9
5267f767c0SRudolf Cornelissen#define TV_PAL (1<<9)
5367f767c0SRudolf Cornelissen#define TV_NTSC (2<<9)
5467f767c0SRudolf Cornelissen#define TV_CAPABLE (1<<11)
5567f767c0SRudolf Cornelissen#define TV_VIDEO (1<<12)
5667f767c0SRudolf Cornelissen
5767f767c0SRudolf Cornelissen#define SKD_MOVE_CURSOR    0x00000001
5867f767c0SRudolf Cornelissen#define SKD_PROGRAM_CLUT   0x00000002
5967f767c0SRudolf Cornelissen#define SKD_SET_START_ADDR 0x00000004
6067f767c0SRudolf Cornelissen#define SKD_SET_CURSOR     0x00000008
6167f767c0SRudolf Cornelissen#define SKD_HANDLER_INSTALLED 0x80000000
6267f767c0SRudolf Cornelissen
6367f767c0SRudolf Cornelissenenum {
6467f767c0SRudolf Cornelissen	ENG_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
6567f767c0SRudolf Cornelissen	ENG_GET_PCI,
6667f767c0SRudolf Cornelissen	ENG_SET_PCI,
6767f767c0SRudolf Cornelissen	ENG_DEVICE_NAME,
6867f767c0SRudolf Cornelissen	ENG_RUN_INTERRUPTS,
6967f767c0SRudolf Cornelissen	ENG_GET_NTH_AGP_INFO,
7067f767c0SRudolf Cornelissen	ENG_ENABLE_AGP,
7167f767c0SRudolf Cornelissen	ENG_ISA_OUT,
7267f767c0SRudolf Cornelissen	ENG_ISA_IN
7367f767c0SRudolf Cornelissen};
7467f767c0SRudolf Cornelissen
7567f767c0SRudolf Cornelissen/* max. number of overlay buffers */
7667f767c0SRudolf Cornelissen#define MAXBUFFERS 3
7767f767c0SRudolf Cornelissen
7867f767c0SRudolf Cornelissen/* internal used info on overlay buffers */
7967f767c0SRudolf Cornelissentypedef	struct
8067f767c0SRudolf Cornelissen{
8167f767c0SRudolf Cornelissen	uint16 slopspace;
8267f767c0SRudolf Cornelissen	uint32 size;
8367f767c0SRudolf Cornelissen} int_buf_info;
8467f767c0SRudolf Cornelissen
8567f767c0SRudolf Cornelissentypedef struct settings {  // apsed, see comments in skel.settings
8667f767c0SRudolf Cornelissen	// for driver
8767f767c0SRudolf Cornelissen	char   accelerant[B_FILE_NAME_LENGTH];
8867f767c0SRudolf Cornelissen	bool   dumprom;
8967f767c0SRudolf Cornelissen	// for accelerant
9067f767c0SRudolf Cornelissen	uint32 logmask;
9167f767c0SRudolf Cornelissen	uint32 memory;
9267f767c0SRudolf Cornelissen	bool   usebios;
9367f767c0SRudolf Cornelissen	bool   hardcursor;
9467f767c0SRudolf Cornelissen	bool   switchhead;
9567f767c0SRudolf Cornelissen	bool   force_pci;
9667f767c0SRudolf Cornelissen	bool   unhide_fw;
9767f767c0SRudolf Cornelissen	bool   pgm_panel;
9867f767c0SRudolf Cornelissen} settings;
9967f767c0SRudolf Cornelissen
100f369957dSJérôme Duval/* card info - information gathered from PINS (and other sources) */
101f369957dSJérôme Duvalenum
102f369957dSJérôme Duval{	// card_type in order of date of VIA chip design (fixme: check order)
103f369957dSJérôme Duval	VT3122 = 0,
104f369957dSJérôme Duval	VT3022,
105f369957dSJérôme Duval	VT7205,
106f369957dSJérôme Duval	VT3205,
107f369957dSJérôme Duval	VT3108,
108f369957dSJérôme Duval	VT3204NC,
109f369957dSJérôme Duval	NV04,
110f369957dSJérôme Duval	NV05,
111f369957dSJérôme Duval	NV05M64,
112f369957dSJérôme Duval	NV06,
113f369957dSJérôme Duval	NV10,
114f369957dSJérôme Duval	NV11,
115f369957dSJérôme Duval	NV11M,
116f369957dSJérôme Duval	NV15,
117f369957dSJérôme Duval	NV17,
118f369957dSJérôme Duval	NV17M,
119f369957dSJérôme Duval	NV18,
120f369957dSJérôme Duval	NV18M,
121f369957dSJérôme Duval	NV20,
122f369957dSJérôme Duval	NV25,
123f369957dSJérôme Duval	NV28,
124f369957dSJérôme Duval	NV30,
125f369957dSJérôme Duval	NV31,
126f369957dSJérôme Duval	NV34,
127f369957dSJérôme Duval	NV35,
128f369957dSJérôme Duval	NV36,
129f369957dSJérôme Duval	NV38,
130f369957dSJérôme Duval	NV40,
131f369957dSJérôme Duval	NV41,
132f369957dSJérôme Duval	NV43,
133f369957dSJérôme Duval	NV45
134f369957dSJérôme Duval};
135f369957dSJérôme Duvalenum
136f369957dSJérôme Duval{	// card_arch in order of date of VIA chip design
137f369957dSJérôme Duval	CLE266 = 0,
138f369957dSJérôme Duval	KM400,
139f369957dSJérôme Duval	K8M800,
140f369957dSJérôme Duval	NV04A,
141f369957dSJérôme Duval	NV10A,
142f369957dSJérôme Duval	NV20A,
143f369957dSJérôme Duval	NV30A,
144f369957dSJérôme Duval	NV40A
145f369957dSJérôme Duval};
146f369957dSJérôme Duvalenum
147f369957dSJérôme Duval{	// tvout_chip_type in order of capability (more or less)
148f369957dSJérôme Duval	NONE = 0,
149f369957dSJérôme Duval	CH7003,
150f369957dSJérôme Duval	CH7004,
151f369957dSJérôme Duval	CH7005,
152f369957dSJérôme Duval	CH7006,
153f369957dSJérôme Duval	CH7007,
154f369957dSJérôme Duval	CH7008,
155f369957dSJérôme Duval	SAA7102,
156f369957dSJérôme Duval	SAA7103,
157f369957dSJérôme Duval	SAA7104,
158f369957dSJérôme Duval	SAA7105,
159f369957dSJérôme Duval	BT868,
160f369957dSJérôme Duval	BT869,
161f369957dSJérôme Duval	CX25870,
162f369957dSJérôme Duval	CX25871,
163f369957dSJérôme Duval	NVIDIA
164f369957dSJérôme Duval};
165f369957dSJérôme Duval
166f369957dSJérôme Duval
16767f767c0SRudolf Cornelissen/*shared info*/
16867f767c0SRudolf Cornelissentypedef struct {
16967f767c0SRudolf Cornelissen  /*a few ID things*/
17067f767c0SRudolf Cornelissen	uint16	vendor_id;	/* PCI vendor ID, from pci_info */
17167f767c0SRudolf Cornelissen	uint16	device_id;	/* PCI device ID, from pci_info */
17267f767c0SRudolf Cornelissen	uint8	revision;	/* PCI device revsion, from pci_info */
17367f767c0SRudolf Cornelissen	uint8	bus;		/* PCI bus number, from pci_info */
17467f767c0SRudolf Cornelissen	uint8	device;		/* PCI device number on bus, from pci_info */
17567f767c0SRudolf Cornelissen	uint8	function;	/* PCI function number in device, from pci_info */
17667f767c0SRudolf Cornelissen
17767f767c0SRudolf Cornelissen  /* bug workaround for 4.5.0 */
17867f767c0SRudolf Cornelissen	uint32 use_clone_bugfix;	/*for 4.5.0, cloning of physical memory does not work*/
17967f767c0SRudolf Cornelissen	uint32 * clone_bugfix_regs;
18067f767c0SRudolf Cornelissen
18167f767c0SRudolf Cornelissen  /*memory mappings*/
18267f767c0SRudolf Cornelissen	area_id	regs_area;	/* Kernel's area_id for the memory mapped registers.
18367f767c0SRudolf Cornelissen							It will be cloned into the accelerant's	address
18467f767c0SRudolf Cornelissen							space. */
18567f767c0SRudolf Cornelissen
18667f767c0SRudolf Cornelissen	area_id	fb_area;	/* Frame buffer's area_id.  The addresses are shared with all teams. */
18767f767c0SRudolf Cornelissen	area_id pseudo_dma_area;	/* Pseudo dma area_id. Shared by all teams. */
18867f767c0SRudolf Cornelissen	area_id	dma_buffer_area;	/* Area assigned for dma*/
18967f767c0SRudolf Cornelissen
19067f767c0SRudolf Cornelissen	void	*framebuffer;		/* As viewed from virtual memory */
19167f767c0SRudolf Cornelissen	void	*framebuffer_pci;	/* As viewed from the PCI bus (for DMA) */
19267f767c0SRudolf Cornelissen
19367f767c0SRudolf Cornelissen	void	*pseudo_dma;		/* As viewed from virtual memory */
19467f767c0SRudolf Cornelissen
19567f767c0SRudolf Cornelissen	void	*dma_buffer;		/* buffer for dma*/
19667f767c0SRudolf Cornelissen	void	*dma_buffer_pci;	/* buffer for dma - from PCI bus*/
19767f767c0SRudolf Cornelissen
19867f767c0SRudolf Cornelissen  /*screenmode list*/
19967f767c0SRudolf Cornelissen	area_id	mode_area;              /* Contains the list of display modes the driver supports */
20067f767c0SRudolf Cornelissen	uint32	mode_count;             /* Number of display modes in the list */
20167f767c0SRudolf Cornelissen
20267f767c0SRudolf Cornelissen  /*flags - used by driver*/
20367f767c0SRudolf Cornelissen	uint32 flags;
20467f767c0SRudolf Cornelissen
20567f767c0SRudolf Cornelissen  /*vblank semaphore*/
20667f767c0SRudolf Cornelissen	sem_id	vblank;	                /* The vertical blank semaphore. Ownership will be
20767f767c0SRudolf Cornelissen						transfered to the team opening the device first */
20867f767c0SRudolf Cornelissen  /*cursor information*/
20967f767c0SRudolf Cornelissen	struct {
21067f767c0SRudolf Cornelissen		uint16	hot_x;		/* Cursor hot spot. The top left corner of the cursor */
21167f767c0SRudolf Cornelissen		uint16	hot_y;		/* is 0,0 */
21267f767c0SRudolf Cornelissen		uint16	x;		/* The location of the cursor hot spot on the */
21367f767c0SRudolf Cornelissen		uint16	y;		/* desktop */
21467f767c0SRudolf Cornelissen		uint16	width;		/* Width and height of the cursor shape (always 16!) */
21567f767c0SRudolf Cornelissen		uint16	height;
21667f767c0SRudolf Cornelissen		bool	is_visible;	/* Is the cursor currently displayed? */
21767f767c0SRudolf Cornelissen		bool	dh_right;	/* Is cursor on right side of stretched screen? */
21867f767c0SRudolf Cornelissen	} cursor;
21967f767c0SRudolf Cornelissen
22067f767c0SRudolf Cornelissen  /*colour lookup table*/
22167f767c0SRudolf Cornelissen	uint8	color_data[3 * 256];	/* Colour lookup table - as used by DAC */
22267f767c0SRudolf Cornelissen
22367f767c0SRudolf Cornelissen  /*more display mode stuff*/
22467f767c0SRudolf Cornelissen	display_mode dm;		/* current display mode configuration: head1 */
22567f767c0SRudolf Cornelissen	display_mode dm2;		/* current display mode configuration: head2 */
22667f767c0SRudolf Cornelissen	bool acc_mode;			/* signals (non)accelerated mode */
22767f767c0SRudolf Cornelissen	bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */
22867f767c0SRudolf Cornelissen	bool crtc_switch_mode;	/* signals dualhead switch mode if panels are used */
22967f767c0SRudolf Cornelissen
23067f767c0SRudolf Cornelissen  /*frame buffer config - for BDirectScreen*/
23167f767c0SRudolf Cornelissen	frame_buffer_config fbc;	/* bytes_per_row and start of frame buffer: head1 */
23267f767c0SRudolf Cornelissen	frame_buffer_config fbc2;	/* bytes_per_row and start of frame buffer: head2 */
23367f767c0SRudolf Cornelissen
23467f767c0SRudolf Cornelissen  /*acceleration engine*/
23567f767c0SRudolf Cornelissen	struct {
23667f767c0SRudolf Cornelissen		uint32		count;		/* last dwgsync slot used */
23767f767c0SRudolf Cornelissen		uint32		last_idle;	/* last dwgsync slot we *know* the engine was idle after */
23867f767c0SRudolf Cornelissen		benaphore	lock;		/* for serializing access to the acceleration engine */
23967f767c0SRudolf Cornelissen	} engine;
24067f767c0SRudolf Cornelissen
24167f767c0SRudolf Cornelissen	struct
24267f767c0SRudolf Cornelissen	{
24367f767c0SRudolf Cornelissen		/* specialised registers for card initialisation read from NV BIOS (pins) */
24467f767c0SRudolf Cornelissen
24567f767c0SRudolf Cornelissen		/* general card information */
24667f767c0SRudolf Cornelissen		uint32 card_type;           /* see card_type enum above */
24767f767c0SRudolf Cornelissen		uint32 card_arch;           /* see card_arch enum above */
2489794c563SRudolf Cornelissen		uint8 chip_rev;				/* chip revision number */
24967f767c0SRudolf Cornelissen		bool laptop;	            /* mobile chipset or not ('internal' flatpanel!) */
25067f767c0SRudolf Cornelissen		bool slaved_tmds1;			/* external TMDS encoder active on CRTC1 */
25167f767c0SRudolf Cornelissen		bool slaved_tmds2;			/* external TMDS encoder active on CRTC2 */
25267f767c0SRudolf Cornelissen		bool master_tmds1;			/* on die TMDS encoder active on CRTC1 */
25367f767c0SRudolf Cornelissen		bool master_tmds2;			/* on die TMDS encoder active on CRTC2 */
25467f767c0SRudolf Cornelissen		bool tmds1_active;			/* found panel on CRTC1 that is active */
25567f767c0SRudolf Cornelissen		bool tmds2_active;			/* found panel on CRTC2 that is active */
25667f767c0SRudolf Cornelissen		display_timing p1_timing;	/* 'modeline' fetched for panel 1 */
25767f767c0SRudolf Cornelissen		display_timing p2_timing;	/* 'modeline' fetched for panel 2 */
25867f767c0SRudolf Cornelissen		float panel1_aspect;		/* panel's aspect ratio */
25967f767c0SRudolf Cornelissen		float panel2_aspect;		/* panel's aspect ratio */
26067f767c0SRudolf Cornelissen		bool crtc2_prim;			/* using CRTC2 as primary CRTC */
26167f767c0SRudolf Cornelissen		uint32 tvout_chip_type;     /* see tvchip_type enum above */
26267f767c0SRudolf Cornelissen		uint8 monitors;				/* output devices connection matrix */
26367f767c0SRudolf Cornelissen		status_t pins_status;		/* B_OK if read correctly, B_ERROR if faked */
26467f767c0SRudolf Cornelissen
26567f767c0SRudolf Cornelissen		/* PINS */
26667f767c0SRudolf Cornelissen		float f_ref;				/* PLL reference-oscillator frequency (Mhz) */
26767f767c0SRudolf Cornelissen		bool ext_pll;				/* the extended PLL contains more dividers */
26867f767c0SRudolf Cornelissen		uint32 max_system_vco;		/* graphics engine PLL VCO limits (Mhz) */
26967f767c0SRudolf Cornelissen		uint32 min_system_vco;
27067f767c0SRudolf Cornelissen		uint32 max_pixel_vco;		/* dac1 PLL VCO limits (Mhz) */
27167f767c0SRudolf Cornelissen		uint32 min_pixel_vco;
27267f767c0SRudolf Cornelissen		uint32 max_video_vco;		/* dac2 PLL VCO limits (Mhz) */
27367f767c0SRudolf Cornelissen		uint32 min_video_vco;
27467f767c0SRudolf Cornelissen		uint32 std_engine_clock;	/* graphics engine clock speed needed (Mhz) */
27567f767c0SRudolf Cornelissen		uint32 std_memory_clock;	/* card memory clock speed needed (Mhz) */
27667f767c0SRudolf Cornelissen		uint32 max_dac1_clock;		/* dac1 limits (Mhz) */
27767f767c0SRudolf Cornelissen		uint32 max_dac1_clock_8;	/* dac1 limits correlated to RAMspeed limits (Mhz) */
27867f767c0SRudolf Cornelissen		uint32 max_dac1_clock_16;
27967f767c0SRudolf Cornelissen		uint32 max_dac1_clock_24;
28067f767c0SRudolf Cornelissen		uint32 max_dac1_clock_32;
28167f767c0SRudolf Cornelissen		uint32 max_dac1_clock_32dh;
28267f767c0SRudolf Cornelissen		uint32 max_dac2_clock;		/* dac2 limits (Mhz) */
28367f767c0SRudolf Cornelissen		uint32 max_dac2_clock_8;	/* dac2, maven limits correlated to RAMspeed limits (Mhz) */
28467f767c0SRudolf Cornelissen		uint32 max_dac2_clock_16;
28567f767c0SRudolf Cornelissen		uint32 max_dac2_clock_24;
28667f767c0SRudolf Cornelissen		uint32 max_dac2_clock_32;
28767f767c0SRudolf Cornelissen		uint32 max_dac2_clock_32dh;
28867f767c0SRudolf Cornelissen		bool secondary_head;		/* presence of functions */
28967f767c0SRudolf Cornelissen		bool tvout;
29067f767c0SRudolf Cornelissen		bool primary_dvi;
29167f767c0SRudolf Cornelissen		bool secondary_dvi;
29267f767c0SRudolf Cornelissen		uint32 memory_size;			/* memory (in bytes) */
29367f767c0SRudolf Cornelissen	} ps;
29467f767c0SRudolf Cornelissen
29567f767c0SRudolf Cornelissen	/* mirror of the ROM (copied in driver, because may not be mapped permanently) */
29667f767c0SRudolf Cornelissen	uint8 rom_mirror[65536];
29767f767c0SRudolf Cornelissen
29867f767c0SRudolf Cornelissen	/* some configuration settings from ~/config/settings/kernel/drivers/skel.settings if exists */
29967f767c0SRudolf Cornelissen	settings settings;
30067f767c0SRudolf Cornelissen
30167f767c0SRudolf Cornelissen	struct
30267f767c0SRudolf Cornelissen	{
30367f767c0SRudolf Cornelissen		overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */
30467f767c0SRudolf Cornelissen		int_buf_info myBufInfo[MAXBUFFERS];	/* extra info on scaler input buffers */
30567f767c0SRudolf Cornelissen		overlay_token myToken;				/* scaler is free/in use */
30667f767c0SRudolf Cornelissen		benaphore lock;						/* for creating buffers and aquiring overlay unit routines */
30767f767c0SRudolf Cornelissen		bool crtc;							/* location of overlay unit */
30867f767c0SRudolf Cornelissen		/* variables needed for virtualscreens (move_overlay()): */
30967f767c0SRudolf Cornelissen		bool active;						/* true is overlay currently in use */
31067f767c0SRudolf Cornelissen		overlay_window ow;					/* current position of overlay output window */
31167f767c0SRudolf Cornelissen		overlay_buffer ob;					/* current inputbuffer in use */
31267f767c0SRudolf Cornelissen		overlay_view my_ov;					/* current corrected view in inputbuffer */
31367f767c0SRudolf Cornelissen		uint32 h_ifactor;					/* current 'unclipped' horizontal inverse scaling factor */
31467f767c0SRudolf Cornelissen		uint32 v_ifactor;					/* current 'unclipped' vertical inverse scaling factor */
31567f767c0SRudolf Cornelissen	} overlay;
31667f767c0SRudolf Cornelissen
31767f767c0SRudolf Cornelissen} shared_info;
31867f767c0SRudolf Cornelissen
31967f767c0SRudolf Cornelissen/* Read or write a value in PCI configuration space */
32067f767c0SRudolf Cornelissentypedef struct {
32167f767c0SRudolf Cornelissen	uint32	magic;		/* magic number to make sure the caller groks us */
32267f767c0SRudolf Cornelissen	uint32	offset;		/* Offset to read/write */
32367f767c0SRudolf Cornelissen	uint32	size;		/* Number of bytes to transfer */
32467f767c0SRudolf Cornelissen	uint32	value;		/* The value read or written */
32567f767c0SRudolf Cornelissen} eng_get_set_pci;
32667f767c0SRudolf Cornelissen
32767f767c0SRudolf Cornelissen/* Set some boolean condition (like enabling or disabling interrupts) */
32867f767c0SRudolf Cornelissentypedef struct {
32967f767c0SRudolf Cornelissen	uint32	magic;		/* magic number to make sure the caller groks us */
33067f767c0SRudolf Cornelissen	bool	do_it;		/* state to set */
33167f767c0SRudolf Cornelissen} eng_set_bool_state;
33267f767c0SRudolf Cornelissen
33367f767c0SRudolf Cornelissen/* Retrieve the area_id of the kernel/accelerant shared info */
33467f767c0SRudolf Cornelissentypedef struct {
33567f767c0SRudolf Cornelissen	uint32	magic;		/* magic number to make sure the caller groks us */
33667f767c0SRudolf Cornelissen	area_id	shared_info_area;	/* area_id containing the shared information */
33767f767c0SRudolf Cornelissen} eng_get_private_data;
33867f767c0SRudolf Cornelissen
33967f767c0SRudolf Cornelissen/* Retrieve the device name.  Usefull for when we have a file handle, but want
34067f767c0SRudolf Cornelissento know the device name (like when we are cloning the accelerant) */
34167f767c0SRudolf Cornelissentypedef struct {
34267f767c0SRudolf Cornelissen	uint32	magic;		/* magic number to make sure the caller groks us */
34367f767c0SRudolf Cornelissen	char	*name;		/* The name of the device, less the /dev root */
34467f767c0SRudolf Cornelissen} eng_device_name;
34567f767c0SRudolf Cornelissen
34667f767c0SRudolf Cornelissen/* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme
34767f767c0SRudolf Cornelissenused (pre 3.x or 3.x) */
34867f767c0SRudolf Cornelissentypedef struct {
34967f767c0SRudolf Cornelissen	uint32		magic;	/* magic number to make sure the caller groks us */
35067f767c0SRudolf Cornelissen	bool		agp_bus;/* indicates if we have access to the AGP busmanager */
35167f767c0SRudolf Cornelissen	uint8		index;	/* device index in list of devices found */
35267f767c0SRudolf Cornelissen	bool		exist;	/* we got AGP device info */
35367f767c0SRudolf Cornelissen	agp_info	agpi;	/* AGP interface info of a device */
35467f767c0SRudolf Cornelissen} eng_nth_agp_info;
35567f767c0SRudolf Cornelissen
35667f767c0SRudolf Cornelissen/* Execute an AGP command */
35767f767c0SRudolf Cornelissentypedef struct {
35867f767c0SRudolf Cornelissen	uint32		magic;	/* magic number to make sure the caller groks us */
35967f767c0SRudolf Cornelissen	bool		agp_bus;/* indicates if we have access to the AGP busmanager */
36067f767c0SRudolf Cornelissen	uint32		cmd;	/* actual command to execute */
36167f767c0SRudolf Cornelissen} eng_cmd_agp;
36267f767c0SRudolf Cornelissen
36367f767c0SRudolf Cornelissen/* Read or write a value in ISA I/O space */
36467f767c0SRudolf Cornelissentypedef struct {
36567f767c0SRudolf Cornelissen	uint32	magic;		/* magic number to make sure the caller groks us */
36667f767c0SRudolf Cornelissen	uint16	adress;		/* Offset to read/write */
36767f767c0SRudolf Cornelissen	uint8	size;		/* Number of bytes to transfer */
36867f767c0SRudolf Cornelissen	uint16	data;		/* The value read or written */
36967f767c0SRudolf Cornelissen} eng_in_out_isa;
37067f767c0SRudolf Cornelissen
37167f767c0SRudolf Cornelissenenum {
37267f767c0SRudolf Cornelissen
37367f767c0SRudolf Cornelissen	_WAIT_FOR_VBLANK = (1 << 0)
37467f767c0SRudolf Cornelissen};
37567f767c0SRudolf Cornelissen
37667f767c0SRudolf Cornelissen#if defined(__cplusplus)
37767f767c0SRudolf Cornelissen}
37867f767c0SRudolf Cornelissen#endif
37967f767c0SRudolf Cornelissen
38067f767c0SRudolf Cornelissen
38167f767c0SRudolf Cornelissen#endif