sea_reg.h revision 1b69f339
1/*
2 * DCE_8_0 Register documentation
3 *
4 * Copyright (C) 2014  Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef DCE_8_0_D_H
25#define DCE_8_0_D_H
26
27#define SEA_mmPIPE0_PG_CONFIG                                                       0x1760
28#define SEA_mmPIPE0_PG_ENABLE                                                       0x1761
29#define SEA_mmPIPE0_PG_STATUS                                                       0x1762
30#define SEA_mmPIPE1_PG_CONFIG                                                       0x1764
31#define SEA_mmPIPE1_PG_ENABLE                                                       0x1765
32#define SEA_mmPIPE1_PG_STATUS                                                       0x1766
33#define SEA_mmPIPE2_PG_CONFIG                                                       0x1768
34#define SEA_mmPIPE2_PG_ENABLE                                                       0x1769
35#define SEA_mmPIPE2_PG_STATUS                                                       0x176a
36#define SEA_mmPIPE3_PG_CONFIG                                                       0x176c
37#define SEA_mmPIPE3_PG_ENABLE                                                       0x176d
38#define SEA_mmPIPE3_PG_STATUS                                                       0x176e
39#define SEA_mmPIPE4_PG_CONFIG                                                       0x1770
40#define SEA_mmPIPE4_PG_ENABLE                                                       0x1771
41#define SEA_mmPIPE4_PG_STATUS                                                       0x1772
42#define SEA_mmPIPE5_PG_CONFIG                                                       0x1774
43#define SEA_mmPIPE5_PG_ENABLE                                                       0x1775
44#define SEA_mmPIPE5_PG_STATUS                                                       0x1776
45#define SEA_mmDC_IP_REQUEST_CNTL                                                    0x1778
46#define SEA_mmDC_PGFSM_CONFIG_REG                                                   0x177c
47#define SEA_mmDC_PGFSM_WRITE_REG                                                    0x177d
48#define SEA_mmDC_PGCNTL_STATUS_REG                                                  0x177e
49#define SEA_mmDCPG_TEST_DEBUG_INDEX                                                 0x1779
50#define SEA_mmDCPG_TEST_DEBUG_DATA                                                  0x177b
51#define SEA_mmBL1_PWM_AMBIENT_LIGHT_LEVEL                                           0x1628
52#define SEA_mmBL1_PWM_USER_LEVEL                                                    0x1629
53#define SEA_mmBL1_PWM_TARGET_ABM_LEVEL                                              0x162a
54#define SEA_mmBL1_PWM_CURRENT_ABM_LEVEL                                             0x162b
55#define SEA_mmBL1_PWM_FINAL_DUTY_CYCLE                                              0x162c
56#define SEA_mmBL1_PWM_MINIMUM_DUTY_CYCLE                                            0x162d
57#define SEA_mmBL1_PWM_ABM_CNTL                                                      0x162e
58#define SEA_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                         0x162f
59#define SEA_mmBL1_PWM_GRP2_REG_LOCK                                                 0x1630
60#define SEA_mmDC_ABM1_CNTL                                                          0x1638
61#define SEA_mmDC_ABM1_IPCSC_COEFF_SEL                                               0x1639
62#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_0                                            0x163a
63#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_1                                            0x163b
64#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_2                                            0x163c
65#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_3                                            0x163d
66#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_4                                            0x163e
67#define SEA_mmDC_ABM1_ACE_THRES_12                                                  0x163f
68#define SEA_mmDC_ABM1_ACE_THRES_34                                                  0x1640
69#define SEA_mmDC_ABM1_ACE_CNTL_MISC                                                 0x1641
70#define SEA_mmDC_ABM1_DEBUG_MISC                                                    0x1649
71#define SEA_mmDC_ABM1_HGLS_REG_READ_PROGRESS                                        0x164a
72#define SEA_mmDC_ABM1_HG_MISC_CTRL                                                  0x164b
73#define SEA_mmDC_ABM1_LS_SUM_OF_LUMA                                                0x164c
74#define SEA_mmDC_ABM1_LS_MIN_MAX_LUMA                                               0x164d
75#define SEA_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                      0x164e
76#define SEA_mmDC_ABM1_LS_PIXEL_COUNT                                                0x164f
77#define SEA_mmDC_ABM1_LS_OVR_SCAN_BIN                                               0x1650
78#define SEA_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                  0x1651
79#define SEA_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                      0x1652
80#define SEA_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                      0x1653
81#define SEA_mmDC_ABM1_HG_SAMPLE_RATE                                                0x1654
82#define SEA_mmDC_ABM1_LS_SAMPLE_RATE                                                0x1655
83#define SEA_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                        0x1656
84#define SEA_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                        0x1657
85#define SEA_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                       0x1658
86#define SEA_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                      0x1659
87#define SEA_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                      0x165a
88#define SEA_mmDC_ABM1_HG_RESULT_1                                                   0x165b
89#define SEA_mmDC_ABM1_HG_RESULT_2                                                   0x165c
90#define SEA_mmDC_ABM1_HG_RESULT_3                                                   0x165d
91#define SEA_mmDC_ABM1_HG_RESULT_4                                                   0x165e
92#define SEA_mmDC_ABM1_HG_RESULT_5                                                   0x165f
93#define SEA_mmDC_ABM1_HG_RESULT_6                                                   0x1660
94#define SEA_mmDC_ABM1_HG_RESULT_7                                                   0x1661
95#define SEA_mmDC_ABM1_HG_RESULT_8                                                   0x1662
96#define SEA_mmDC_ABM1_HG_RESULT_9                                                   0x1663
97#define SEA_mmDC_ABM1_HG_RESULT_10                                                  0x1664
98#define SEA_mmDC_ABM1_HG_RESULT_11                                                  0x1665
99#define SEA_mmDC_ABM1_HG_RESULT_12                                                  0x1666
100#define SEA_mmDC_ABM1_HG_RESULT_13                                                  0x1667
101#define SEA_mmDC_ABM1_HG_RESULT_14                                                  0x1668
102#define SEA_mmDC_ABM1_HG_RESULT_15                                                  0x1669
103#define SEA_mmDC_ABM1_HG_RESULT_16                                                  0x166a
104#define SEA_mmDC_ABM1_HG_RESULT_17                                                  0x166b
105#define SEA_mmDC_ABM1_HG_RESULT_18                                                  0x166c
106#define SEA_mmDC_ABM1_HG_RESULT_19                                                  0x166d
107#define SEA_mmDC_ABM1_HG_RESULT_20                                                  0x166e
108#define SEA_mmDC_ABM1_HG_RESULT_21                                                  0x166f
109#define SEA_mmDC_ABM1_HG_RESULT_22                                                  0x1670
110#define SEA_mmDC_ABM1_HG_RESULT_23                                                  0x1671
111#define SEA_mmDC_ABM1_HG_RESULT_24                                                  0x1672
112#define SEA_mmDC_ABM1_OVERSCAN_PIXEL_VALUE                                          0x169b
113#define SEA_mmDC_ABM1_BL_MASTER_LOCK                                                0x169c
114#define SEA_mmABM_TEST_DEBUG_INDEX                                                  0x169e
115#define SEA_mmABM_TEST_DEBUG_DATA                                                   0x169f
116#define SEA_mmCRTC_DCFE_CLOCK_CONTROL                                               0x1b7c
117#define SEA_mmCRTC0_CRTC_DCFE_CLOCK_CONTROL                                         0x1b7c
118#define SEA_mmCRTC1_CRTC_DCFE_CLOCK_CONTROL                                         0x1e7c
119#define SEA_mmCRTC2_CRTC_DCFE_CLOCK_CONTROL                                         0x417c
120#define SEA_mmCRTC3_CRTC_DCFE_CLOCK_CONTROL                                         0x447c
121#define SEA_mmCRTC4_CRTC_DCFE_CLOCK_CONTROL                                         0x477c
122#define SEA_mmCRTC5_CRTC_DCFE_CLOCK_CONTROL                                         0x4a7c
123#define SEA_mmCRTC_H_BLANK_EARLY_NUM                                                0x1b7d
124#define SEA_mmCRTC0_CRTC_H_BLANK_EARLY_NUM                                          0x1b7d
125#define SEA_mmCRTC1_CRTC_H_BLANK_EARLY_NUM                                          0x1e7d
126#define SEA_mmCRTC2_CRTC_H_BLANK_EARLY_NUM                                          0x417d
127#define SEA_mmCRTC3_CRTC_H_BLANK_EARLY_NUM                                          0x447d
128#define SEA_mmCRTC4_CRTC_H_BLANK_EARLY_NUM                                          0x477d
129#define SEA_mmCRTC5_CRTC_H_BLANK_EARLY_NUM                                          0x4a7d
130#define SEA_mmDCFE_DBG_SEL                                                          0x1b7e
131#define SEA_mmCRTC0_DCFE_DBG_SEL                                                    0x1b7e
132#define SEA_mmCRTC1_DCFE_DBG_SEL                                                    0x1e7e
133#define SEA_mmCRTC2_DCFE_DBG_SEL                                                    0x417e
134#define SEA_mmCRTC3_DCFE_DBG_SEL                                                    0x447e
135#define SEA_mmCRTC4_DCFE_DBG_SEL                                                    0x477e
136#define SEA_mmCRTC5_DCFE_DBG_SEL                                                    0x4a7e
137#define SEA_mmDCFE_MEM_LIGHT_SLEEP_CNTL                                             0x1b7f
138#define SEA_mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x1b7f
139#define SEA_mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x1e7f
140#define SEA_mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x417f
141#define SEA_mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x447f
142#define SEA_mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x477f
143#define SEA_mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x4a7f
144#define SEA_mmCRTC_H_TOTAL                                                          0x1b80
145#define SEA_mmCRTC0_CRTC_H_TOTAL                                                    0x1b80
146#define SEA_mmCRTC1_CRTC_H_TOTAL                                                    0x1e80
147#define SEA_mmCRTC2_CRTC_H_TOTAL                                                    0x4180
148#define SEA_mmCRTC3_CRTC_H_TOTAL                                                    0x4480
149#define SEA_mmCRTC4_CRTC_H_TOTAL                                                    0x4780
150#define SEA_mmCRTC5_CRTC_H_TOTAL                                                    0x4a80
151#define SEA_mmCRTC_H_BLANK_START_END                                                0x1b81
152#define SEA_mmCRTC0_CRTC_H_BLANK_START_END                                          0x1b81
153#define SEA_mmCRTC1_CRTC_H_BLANK_START_END                                          0x1e81
154#define SEA_mmCRTC2_CRTC_H_BLANK_START_END                                          0x4181
155#define SEA_mmCRTC3_CRTC_H_BLANK_START_END                                          0x4481
156#define SEA_mmCRTC4_CRTC_H_BLANK_START_END                                          0x4781
157#define SEA_mmCRTC5_CRTC_H_BLANK_START_END                                          0x4a81
158#define SEA_mmCRTC_H_SYNC_A                                                         0x1b82
159#define SEA_mmCRTC0_CRTC_H_SYNC_A                                                   0x1b82
160#define SEA_mmCRTC1_CRTC_H_SYNC_A                                                   0x1e82
161#define SEA_mmCRTC2_CRTC_H_SYNC_A                                                   0x4182
162#define SEA_mmCRTC3_CRTC_H_SYNC_A                                                   0x4482
163#define SEA_mmCRTC4_CRTC_H_SYNC_A                                                   0x4782
164#define SEA_mmCRTC5_CRTC_H_SYNC_A                                                   0x4a82
165#define SEA_mmCRTC_H_SYNC_A_CNTL                                                    0x1b83
166#define SEA_mmCRTC0_CRTC_H_SYNC_A_CNTL                                              0x1b83
167#define SEA_mmCRTC1_CRTC_H_SYNC_A_CNTL                                              0x1e83
168#define SEA_mmCRTC2_CRTC_H_SYNC_A_CNTL                                              0x4183
169#define SEA_mmCRTC3_CRTC_H_SYNC_A_CNTL                                              0x4483
170#define SEA_mmCRTC4_CRTC_H_SYNC_A_CNTL                                              0x4783
171#define SEA_mmCRTC5_CRTC_H_SYNC_A_CNTL                                              0x4a83
172#define SEA_mmCRTC_H_SYNC_B                                                         0x1b84
173#define SEA_mmCRTC0_CRTC_H_SYNC_B                                                   0x1b84
174#define SEA_mmCRTC1_CRTC_H_SYNC_B                                                   0x1e84
175#define SEA_mmCRTC2_CRTC_H_SYNC_B                                                   0x4184
176#define SEA_mmCRTC3_CRTC_H_SYNC_B                                                   0x4484
177#define SEA_mmCRTC4_CRTC_H_SYNC_B                                                   0x4784
178#define SEA_mmCRTC5_CRTC_H_SYNC_B                                                   0x4a84
179#define SEA_mmCRTC_H_SYNC_B_CNTL                                                    0x1b85
180#define SEA_mmCRTC0_CRTC_H_SYNC_B_CNTL                                              0x1b85
181#define SEA_mmCRTC1_CRTC_H_SYNC_B_CNTL                                              0x1e85
182#define SEA_mmCRTC2_CRTC_H_SYNC_B_CNTL                                              0x4185
183#define SEA_mmCRTC3_CRTC_H_SYNC_B_CNTL                                              0x4485
184#define SEA_mmCRTC4_CRTC_H_SYNC_B_CNTL                                              0x4785
185#define SEA_mmCRTC5_CRTC_H_SYNC_B_CNTL                                              0x4a85
186#define SEA_mmCRTC_VBI_END                                                          0x1b86
187#define SEA_mmCRTC0_CRTC_VBI_END                                                    0x1b86
188#define SEA_mmCRTC1_CRTC_VBI_END                                                    0x1e86
189#define SEA_mmCRTC2_CRTC_VBI_END                                                    0x4186
190#define SEA_mmCRTC3_CRTC_VBI_END                                                    0x4486
191#define SEA_mmCRTC4_CRTC_VBI_END                                                    0x4786
192#define SEA_mmCRTC5_CRTC_VBI_END                                                    0x4a86
193#define SEA_mmCRTC_V_TOTAL                                                          0x1b87
194#define SEA_mmCRTC0_CRTC_V_TOTAL                                                    0x1b87
195#define SEA_mmCRTC1_CRTC_V_TOTAL                                                    0x1e87
196#define SEA_mmCRTC2_CRTC_V_TOTAL                                                    0x4187
197#define SEA_mmCRTC3_CRTC_V_TOTAL                                                    0x4487
198#define SEA_mmCRTC4_CRTC_V_TOTAL                                                    0x4787
199#define SEA_mmCRTC5_CRTC_V_TOTAL                                                    0x4a87
200#define SEA_mmCRTC_V_TOTAL_MIN                                                      0x1b88
201#define SEA_mmCRTC0_CRTC_V_TOTAL_MIN                                                0x1b88
202#define SEA_mmCRTC1_CRTC_V_TOTAL_MIN                                                0x1e88
203#define SEA_mmCRTC2_CRTC_V_TOTAL_MIN                                                0x4188
204#define SEA_mmCRTC3_CRTC_V_TOTAL_MIN                                                0x4488
205#define SEA_mmCRTC4_CRTC_V_TOTAL_MIN                                                0x4788
206#define SEA_mmCRTC5_CRTC_V_TOTAL_MIN                                                0x4a88
207#define SEA_mmCRTC_V_TOTAL_MAX                                                      0x1b89
208#define SEA_mmCRTC0_CRTC_V_TOTAL_MAX                                                0x1b89
209#define SEA_mmCRTC1_CRTC_V_TOTAL_MAX                                                0x1e89
210#define SEA_mmCRTC2_CRTC_V_TOTAL_MAX                                                0x4189
211#define SEA_mmCRTC3_CRTC_V_TOTAL_MAX                                                0x4489
212#define SEA_mmCRTC4_CRTC_V_TOTAL_MAX                                                0x4789
213#define SEA_mmCRTC5_CRTC_V_TOTAL_MAX                                                0x4a89
214#define SEA_mmCRTC_V_TOTAL_CONTROL                                                  0x1b8a
215#define SEA_mmCRTC0_CRTC_V_TOTAL_CONTROL                                            0x1b8a
216#define SEA_mmCRTC1_CRTC_V_TOTAL_CONTROL                                            0x1e8a
217#define SEA_mmCRTC2_CRTC_V_TOTAL_CONTROL                                            0x418a
218#define SEA_mmCRTC3_CRTC_V_TOTAL_CONTROL                                            0x448a
219#define SEA_mmCRTC4_CRTC_V_TOTAL_CONTROL                                            0x478a
220#define SEA_mmCRTC5_CRTC_V_TOTAL_CONTROL                                            0x4a8a
221#define SEA_mmCRTC_V_TOTAL_INT_STATUS                                               0x1b8b
222#define SEA_mmCRTC0_CRTC_V_TOTAL_INT_STATUS                                         0x1b8b
223#define SEA_mmCRTC1_CRTC_V_TOTAL_INT_STATUS                                         0x1e8b
224#define SEA_mmCRTC2_CRTC_V_TOTAL_INT_STATUS                                         0x418b
225#define SEA_mmCRTC3_CRTC_V_TOTAL_INT_STATUS                                         0x448b
226#define SEA_mmCRTC4_CRTC_V_TOTAL_INT_STATUS                                         0x478b
227#define SEA_mmCRTC5_CRTC_V_TOTAL_INT_STATUS                                         0x4a8b
228#define SEA_mmCRTC_VSYNC_NOM_INT_STATUS                                             0x1b8c
229#define SEA_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS                                       0x1b8c
230#define SEA_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS                                       0x1e8c
231#define SEA_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS                                       0x418c
232#define SEA_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS                                       0x448c
233#define SEA_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS                                       0x478c
234#define SEA_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS                                       0x4a8c
235#define SEA_mmCRTC_V_BLANK_START_END                                                0x1b8d
236#define SEA_mmCRTC0_CRTC_V_BLANK_START_END                                          0x1b8d
237#define SEA_mmCRTC1_CRTC_V_BLANK_START_END                                          0x1e8d
238#define SEA_mmCRTC2_CRTC_V_BLANK_START_END                                          0x418d
239#define SEA_mmCRTC3_CRTC_V_BLANK_START_END                                          0x448d
240#define SEA_mmCRTC4_CRTC_V_BLANK_START_END                                          0x478d
241#define SEA_mmCRTC5_CRTC_V_BLANK_START_END                                          0x4a8d
242#define SEA_mmCRTC_V_SYNC_A                                                         0x1b8e
243#define SEA_mmCRTC0_CRTC_V_SYNC_A                                                   0x1b8e
244#define SEA_mmCRTC1_CRTC_V_SYNC_A                                                   0x1e8e
245#define SEA_mmCRTC2_CRTC_V_SYNC_A                                                   0x418e
246#define SEA_mmCRTC3_CRTC_V_SYNC_A                                                   0x448e
247#define SEA_mmCRTC4_CRTC_V_SYNC_A                                                   0x478e
248#define SEA_mmCRTC5_CRTC_V_SYNC_A                                                   0x4a8e
249#define SEA_mmCRTC_V_SYNC_A_CNTL                                                    0x1b8f
250#define SEA_mmCRTC0_CRTC_V_SYNC_A_CNTL                                              0x1b8f
251#define SEA_mmCRTC1_CRTC_V_SYNC_A_CNTL                                              0x1e8f
252#define SEA_mmCRTC2_CRTC_V_SYNC_A_CNTL                                              0x418f
253#define SEA_mmCRTC3_CRTC_V_SYNC_A_CNTL                                              0x448f
254#define SEA_mmCRTC4_CRTC_V_SYNC_A_CNTL                                              0x478f
255#define SEA_mmCRTC5_CRTC_V_SYNC_A_CNTL                                              0x4a8f
256#define SEA_mmCRTC_V_SYNC_B                                                         0x1b90
257#define SEA_mmCRTC0_CRTC_V_SYNC_B                                                   0x1b90
258#define SEA_mmCRTC1_CRTC_V_SYNC_B                                                   0x1e90
259#define SEA_mmCRTC2_CRTC_V_SYNC_B                                                   0x4190
260#define SEA_mmCRTC3_CRTC_V_SYNC_B                                                   0x4490
261#define SEA_mmCRTC4_CRTC_V_SYNC_B                                                   0x4790
262#define SEA_mmCRTC5_CRTC_V_SYNC_B                                                   0x4a90
263#define SEA_mmCRTC_V_SYNC_B_CNTL                                                    0x1b91
264#define SEA_mmCRTC0_CRTC_V_SYNC_B_CNTL                                              0x1b91
265#define SEA_mmCRTC1_CRTC_V_SYNC_B_CNTL                                              0x1e91
266#define SEA_mmCRTC2_CRTC_V_SYNC_B_CNTL                                              0x4191
267#define SEA_mmCRTC3_CRTC_V_SYNC_B_CNTL                                              0x4491
268#define SEA_mmCRTC4_CRTC_V_SYNC_B_CNTL                                              0x4791
269#define SEA_mmCRTC5_CRTC_V_SYNC_B_CNTL                                              0x4a91
270#define SEA_mmCRTC_DTMTEST_CNTL                                                     0x1b92
271#define SEA_mmCRTC0_CRTC_DTMTEST_CNTL                                               0x1b92
272#define SEA_mmCRTC1_CRTC_DTMTEST_CNTL                                               0x1e92
273#define SEA_mmCRTC2_CRTC_DTMTEST_CNTL                                               0x4192
274#define SEA_mmCRTC3_CRTC_DTMTEST_CNTL                                               0x4492
275#define SEA_mmCRTC4_CRTC_DTMTEST_CNTL                                               0x4792
276#define SEA_mmCRTC5_CRTC_DTMTEST_CNTL                                               0x4a92
277#define SEA_mmCRTC_DTMTEST_STATUS_POSITION                                          0x1b93
278#define SEA_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION                                    0x1b93
279#define SEA_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION                                    0x1e93
280#define SEA_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION                                    0x4193
281#define SEA_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION                                    0x4493
282#define SEA_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION                                    0x4793
283#define SEA_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION                                    0x4a93
284#define SEA_mmCRTC_TRIGA_CNTL                                                       0x1b94
285#define SEA_mmCRTC0_CRTC_TRIGA_CNTL                                                 0x1b94
286#define SEA_mmCRTC1_CRTC_TRIGA_CNTL                                                 0x1e94
287#define SEA_mmCRTC2_CRTC_TRIGA_CNTL                                                 0x4194
288#define SEA_mmCRTC3_CRTC_TRIGA_CNTL                                                 0x4494
289#define SEA_mmCRTC4_CRTC_TRIGA_CNTL                                                 0x4794
290#define SEA_mmCRTC5_CRTC_TRIGA_CNTL                                                 0x4a94
291#define SEA_mmCRTC_TRIGA_MANUAL_TRIG                                                0x1b95
292#define SEA_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG                                          0x1b95
293#define SEA_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG                                          0x1e95
294#define SEA_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG                                          0x4195
295#define SEA_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG                                          0x4495
296#define SEA_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG                                          0x4795
297#define SEA_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG                                          0x4a95
298#define SEA_mmCRTC_TRIGB_CNTL                                                       0x1b96
299#define SEA_mmCRTC0_CRTC_TRIGB_CNTL                                                 0x1b96
300#define SEA_mmCRTC1_CRTC_TRIGB_CNTL                                                 0x1e96
301#define SEA_mmCRTC2_CRTC_TRIGB_CNTL                                                 0x4196
302#define SEA_mmCRTC3_CRTC_TRIGB_CNTL                                                 0x4496
303#define SEA_mmCRTC4_CRTC_TRIGB_CNTL                                                 0x4796
304#define SEA_mmCRTC5_CRTC_TRIGB_CNTL                                                 0x4a96
305#define SEA_mmCRTC_TRIGB_MANUAL_TRIG                                                0x1b97
306#define SEA_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG                                          0x1b97
307#define SEA_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG                                          0x1e97
308#define SEA_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG                                          0x4197
309#define SEA_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG                                          0x4497
310#define SEA_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG                                          0x4797
311#define SEA_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG                                          0x4a97
312#define SEA_mmCRTC_FORCE_COUNT_NOW_CNTL                                             0x1b98
313#define SEA_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1b98
314#define SEA_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1e98
315#define SEA_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4198
316#define SEA_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4498
317#define SEA_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4798
318#define SEA_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4a98
319#define SEA_mmCRTC_FLOW_CONTROL                                                     0x1b99
320#define SEA_mmCRTC0_CRTC_FLOW_CONTROL                                               0x1b99
321#define SEA_mmCRTC1_CRTC_FLOW_CONTROL                                               0x1e99
322#define SEA_mmCRTC2_CRTC_FLOW_CONTROL                                               0x4199
323#define SEA_mmCRTC3_CRTC_FLOW_CONTROL                                               0x4499
324#define SEA_mmCRTC4_CRTC_FLOW_CONTROL                                               0x4799
325#define SEA_mmCRTC5_CRTC_FLOW_CONTROL                                               0x4a99
326#define SEA_mmCRTC_STEREO_FORCE_NEXT_EYE                                            0x1b9b
327#define SEA_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1b9b
328#define SEA_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1e9b
329#define SEA_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE                                      0x419b
330#define SEA_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE                                      0x449b
331#define SEA_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE                                      0x479b
332#define SEA_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE                                      0x4a9b
333#define SEA_mmCRTC_CONTROL                                                          0x1b9c
334#define SEA_mmCRTC0_CRTC_CONTROL                                                    0x1b9c
335#define SEA_mmCRTC1_CRTC_CONTROL                                                    0x1e9c
336#define SEA_mmCRTC2_CRTC_CONTROL                                                    0x419c
337#define SEA_mmCRTC3_CRTC_CONTROL                                                    0x449c
338#define SEA_mmCRTC4_CRTC_CONTROL                                                    0x479c
339#define SEA_mmCRTC5_CRTC_CONTROL                                                    0x4a9c
340#define SEA_mmCRTC_BLANK_CONTROL                                                    0x1b9d
341#define SEA_mmCRTC0_CRTC_BLANK_CONTROL                                              0x1b9d
342#define SEA_mmCRTC1_CRTC_BLANK_CONTROL                                              0x1e9d
343#define SEA_mmCRTC2_CRTC_BLANK_CONTROL                                              0x419d
344#define SEA_mmCRTC3_CRTC_BLANK_CONTROL                                              0x449d
345#define SEA_mmCRTC4_CRTC_BLANK_CONTROL                                              0x479d
346#define SEA_mmCRTC5_CRTC_BLANK_CONTROL                                              0x4a9d
347#define SEA_mmCRTC_INTERLACE_CONTROL                                                0x1b9e
348#define SEA_mmCRTC0_CRTC_INTERLACE_CONTROL                                          0x1b9e
349#define SEA_mmCRTC1_CRTC_INTERLACE_CONTROL                                          0x1e9e
350#define SEA_mmCRTC2_CRTC_INTERLACE_CONTROL                                          0x419e
351#define SEA_mmCRTC3_CRTC_INTERLACE_CONTROL                                          0x449e
352#define SEA_mmCRTC4_CRTC_INTERLACE_CONTROL                                          0x479e
353#define SEA_mmCRTC5_CRTC_INTERLACE_CONTROL                                          0x4a9e
354#define SEA_mmCRTC_INTERLACE_STATUS                                                 0x1b9f
355#define SEA_mmCRTC0_CRTC_INTERLACE_STATUS                                           0x1b9f
356#define SEA_mmCRTC1_CRTC_INTERLACE_STATUS                                           0x1e9f
357#define SEA_mmCRTC2_CRTC_INTERLACE_STATUS                                           0x419f
358#define SEA_mmCRTC3_CRTC_INTERLACE_STATUS                                           0x449f
359#define SEA_mmCRTC4_CRTC_INTERLACE_STATUS                                           0x479f
360#define SEA_mmCRTC5_CRTC_INTERLACE_STATUS                                           0x4a9f
361#define SEA_mmCRTC_FIELD_INDICATION_CONTROL                                         0x1ba0
362#define SEA_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL                                   0x1ba0
363#define SEA_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL                                   0x1ea0
364#define SEA_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL                                   0x41a0
365#define SEA_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL                                   0x44a0
366#define SEA_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL                                   0x47a0
367#define SEA_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL                                   0x4aa0
368#define SEA_mmCRTC_PIXEL_DATA_READBACK0                                             0x1ba1
369#define SEA_mmCRTC0_CRTC_PIXEL_DATA_READBACK0                                       0x1ba1
370#define SEA_mmCRTC1_CRTC_PIXEL_DATA_READBACK0                                       0x1ea1
371#define SEA_mmCRTC2_CRTC_PIXEL_DATA_READBACK0                                       0x41a1
372#define SEA_mmCRTC3_CRTC_PIXEL_DATA_READBACK0                                       0x44a1
373#define SEA_mmCRTC4_CRTC_PIXEL_DATA_READBACK0                                       0x47a1
374#define SEA_mmCRTC5_CRTC_PIXEL_DATA_READBACK0                                       0x4aa1
375#define SEA_mmCRTC_PIXEL_DATA_READBACK1                                             0x1ba2
376#define SEA_mmCRTC0_CRTC_PIXEL_DATA_READBACK1                                       0x1ba2
377#define SEA_mmCRTC1_CRTC_PIXEL_DATA_READBACK1                                       0x1ea2
378#define SEA_mmCRTC2_CRTC_PIXEL_DATA_READBACK1                                       0x41a2
379#define SEA_mmCRTC3_CRTC_PIXEL_DATA_READBACK1                                       0x44a2
380#define SEA_mmCRTC4_CRTC_PIXEL_DATA_READBACK1                                       0x47a2
381#define SEA_mmCRTC5_CRTC_PIXEL_DATA_READBACK1                                       0x4aa2
382#define SEA_mmCRTC_STATUS                                                           0x1ba3
383#define SEA_mmCRTC0_CRTC_STATUS                                                     0x1ba3
384#define SEA_mmCRTC1_CRTC_STATUS                                                     0x1ea3
385#define SEA_mmCRTC2_CRTC_STATUS                                                     0x41a3
386#define SEA_mmCRTC3_CRTC_STATUS                                                     0x44a3
387#define SEA_mmCRTC4_CRTC_STATUS                                                     0x47a3
388#define SEA_mmCRTC5_CRTC_STATUS                                                     0x4aa3
389#define SEA_mmCRTC_STATUS_POSITION                                                  0x1ba4
390#define SEA_mmCRTC0_CRTC_STATUS_POSITION                                            0x1ba4
391#define SEA_mmCRTC1_CRTC_STATUS_POSITION                                            0x1ea4
392#define SEA_mmCRTC2_CRTC_STATUS_POSITION                                            0x41a4
393#define SEA_mmCRTC3_CRTC_STATUS_POSITION                                            0x44a4
394#define SEA_mmCRTC4_CRTC_STATUS_POSITION                                            0x47a4
395#define SEA_mmCRTC5_CRTC_STATUS_POSITION                                            0x4aa4
396#define SEA_mmCRTC_NOM_VERT_POSITION                                                0x1ba5
397#define SEA_mmCRTC0_CRTC_NOM_VERT_POSITION                                          0x1ba5
398#define SEA_mmCRTC1_CRTC_NOM_VERT_POSITION                                          0x1ea5
399#define SEA_mmCRTC2_CRTC_NOM_VERT_POSITION                                          0x41a5
400#define SEA_mmCRTC3_CRTC_NOM_VERT_POSITION                                          0x44a5
401#define SEA_mmCRTC4_CRTC_NOM_VERT_POSITION                                          0x47a5
402#define SEA_mmCRTC5_CRTC_NOM_VERT_POSITION                                          0x4aa5
403#define SEA_mmCRTC_STATUS_FRAME_COUNT                                               0x1ba6
404#define SEA_mmCRTC0_CRTC_STATUS_FRAME_COUNT                                         0x1ba6
405#define SEA_mmCRTC1_CRTC_STATUS_FRAME_COUNT                                         0x1ea6
406#define SEA_mmCRTC2_CRTC_STATUS_FRAME_COUNT                                         0x41a6
407#define SEA_mmCRTC3_CRTC_STATUS_FRAME_COUNT                                         0x44a6
408#define SEA_mmCRTC4_CRTC_STATUS_FRAME_COUNT                                         0x47a6
409#define SEA_mmCRTC5_CRTC_STATUS_FRAME_COUNT                                         0x4aa6
410#define SEA_mmCRTC_STATUS_VF_COUNT                                                  0x1ba7
411#define SEA_mmCRTC0_CRTC_STATUS_VF_COUNT                                            0x1ba7
412#define SEA_mmCRTC1_CRTC_STATUS_VF_COUNT                                            0x1ea7
413#define SEA_mmCRTC2_CRTC_STATUS_VF_COUNT                                            0x41a7
414#define SEA_mmCRTC3_CRTC_STATUS_VF_COUNT                                            0x44a7
415#define SEA_mmCRTC4_CRTC_STATUS_VF_COUNT                                            0x47a7
416#define SEA_mmCRTC5_CRTC_STATUS_VF_COUNT                                            0x4aa7
417#define SEA_mmCRTC_STATUS_HV_COUNT                                                  0x1ba8
418#define SEA_mmCRTC0_CRTC_STATUS_HV_COUNT                                            0x1ba8
419#define SEA_mmCRTC1_CRTC_STATUS_HV_COUNT                                            0x1ea8
420#define SEA_mmCRTC2_CRTC_STATUS_HV_COUNT                                            0x41a8
421#define SEA_mmCRTC3_CRTC_STATUS_HV_COUNT                                            0x44a8
422#define SEA_mmCRTC4_CRTC_STATUS_HV_COUNT                                            0x47a8
423#define SEA_mmCRTC5_CRTC_STATUS_HV_COUNT                                            0x4aa8
424#define SEA_mmCRTC_COUNT_CONTROL                                                    0x1ba9
425#define SEA_mmCRTC0_CRTC_COUNT_CONTROL                                              0x1ba9
426#define SEA_mmCRTC1_CRTC_COUNT_CONTROL                                              0x1ea9
427#define SEA_mmCRTC2_CRTC_COUNT_CONTROL                                              0x41a9
428#define SEA_mmCRTC3_CRTC_COUNT_CONTROL                                              0x44a9
429#define SEA_mmCRTC4_CRTC_COUNT_CONTROL                                              0x47a9
430#define SEA_mmCRTC5_CRTC_COUNT_CONTROL                                              0x4aa9
431#define SEA_mmCRTC_COUNT_RESET                                                      0x1baa
432#define SEA_mmCRTC0_CRTC_COUNT_RESET                                                0x1baa
433#define SEA_mmCRTC1_CRTC_COUNT_RESET                                                0x1eaa
434#define SEA_mmCRTC2_CRTC_COUNT_RESET                                                0x41aa
435#define SEA_mmCRTC3_CRTC_COUNT_RESET                                                0x44aa
436#define SEA_mmCRTC4_CRTC_COUNT_RESET                                                0x47aa
437#define SEA_mmCRTC5_CRTC_COUNT_RESET                                                0x4aaa
438#define SEA_mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                     0x1bab
439#define SEA_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1bab
440#define SEA_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1eab
441#define SEA_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x41ab
442#define SEA_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x44ab
443#define SEA_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x47ab
444#define SEA_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x4aab
445#define SEA_mmCRTC_VERT_SYNC_CONTROL                                                0x1bac
446#define SEA_mmCRTC0_CRTC_VERT_SYNC_CONTROL                                          0x1bac
447#define SEA_mmCRTC1_CRTC_VERT_SYNC_CONTROL                                          0x1eac
448#define SEA_mmCRTC2_CRTC_VERT_SYNC_CONTROL                                          0x41ac
449#define SEA_mmCRTC3_CRTC_VERT_SYNC_CONTROL                                          0x44ac
450#define SEA_mmCRTC4_CRTC_VERT_SYNC_CONTROL                                          0x47ac
451#define SEA_mmCRTC5_CRTC_VERT_SYNC_CONTROL                                          0x4aac
452#define SEA_mmCRTC_STEREO_STATUS                                                    0x1bad
453#define SEA_mmCRTC0_CRTC_STEREO_STATUS                                              0x1bad
454#define SEA_mmCRTC1_CRTC_STEREO_STATUS                                              0x1ead
455#define SEA_mmCRTC2_CRTC_STEREO_STATUS                                              0x41ad
456#define SEA_mmCRTC3_CRTC_STEREO_STATUS                                              0x44ad
457#define SEA_mmCRTC4_CRTC_STEREO_STATUS                                              0x47ad
458#define SEA_mmCRTC5_CRTC_STEREO_STATUS                                              0x4aad
459#define SEA_mmCRTC_STEREO_CONTROL                                                   0x1bae
460#define SEA_mmCRTC0_CRTC_STEREO_CONTROL                                             0x1bae
461#define SEA_mmCRTC1_CRTC_STEREO_CONTROL                                             0x1eae
462#define SEA_mmCRTC2_CRTC_STEREO_CONTROL                                             0x41ae
463#define SEA_mmCRTC3_CRTC_STEREO_CONTROL                                             0x44ae
464#define SEA_mmCRTC4_CRTC_STEREO_CONTROL                                             0x47ae
465#define SEA_mmCRTC5_CRTC_STEREO_CONTROL                                             0x4aae
466#define SEA_mmCRTC_SNAPSHOT_STATUS                                                  0x1baf
467#define SEA_mmCRTC0_CRTC_SNAPSHOT_STATUS                                            0x1baf
468#define SEA_mmCRTC1_CRTC_SNAPSHOT_STATUS                                            0x1eaf
469#define SEA_mmCRTC2_CRTC_SNAPSHOT_STATUS                                            0x41af
470#define SEA_mmCRTC3_CRTC_SNAPSHOT_STATUS                                            0x44af
471#define SEA_mmCRTC4_CRTC_SNAPSHOT_STATUS                                            0x47af
472#define SEA_mmCRTC5_CRTC_SNAPSHOT_STATUS                                            0x4aaf
473#define SEA_mmCRTC_SNAPSHOT_CONTROL                                                 0x1bb0
474#define SEA_mmCRTC0_CRTC_SNAPSHOT_CONTROL                                           0x1bb0
475#define SEA_mmCRTC1_CRTC_SNAPSHOT_CONTROL                                           0x1eb0
476#define SEA_mmCRTC2_CRTC_SNAPSHOT_CONTROL                                           0x41b0
477#define SEA_mmCRTC3_CRTC_SNAPSHOT_CONTROL                                           0x44b0
478#define SEA_mmCRTC4_CRTC_SNAPSHOT_CONTROL                                           0x47b0
479#define SEA_mmCRTC5_CRTC_SNAPSHOT_CONTROL                                           0x4ab0
480#define SEA_mmCRTC_SNAPSHOT_POSITION                                                0x1bb1
481#define SEA_mmCRTC0_CRTC_SNAPSHOT_POSITION                                          0x1bb1
482#define SEA_mmCRTC1_CRTC_SNAPSHOT_POSITION                                          0x1eb1
483#define SEA_mmCRTC2_CRTC_SNAPSHOT_POSITION                                          0x41b1
484#define SEA_mmCRTC3_CRTC_SNAPSHOT_POSITION                                          0x44b1
485#define SEA_mmCRTC4_CRTC_SNAPSHOT_POSITION                                          0x47b1
486#define SEA_mmCRTC5_CRTC_SNAPSHOT_POSITION                                          0x4ab1
487#define SEA_mmCRTC_SNAPSHOT_FRAME                                                   0x1bb2
488#define SEA_mmCRTC0_CRTC_SNAPSHOT_FRAME                                             0x1bb2
489#define SEA_mmCRTC1_CRTC_SNAPSHOT_FRAME                                             0x1eb2
490#define SEA_mmCRTC2_CRTC_SNAPSHOT_FRAME                                             0x41b2
491#define SEA_mmCRTC3_CRTC_SNAPSHOT_FRAME                                             0x44b2
492#define SEA_mmCRTC4_CRTC_SNAPSHOT_FRAME                                             0x47b2
493#define SEA_mmCRTC5_CRTC_SNAPSHOT_FRAME                                             0x4ab2
494#define SEA_mmCRTC_START_LINE_CONTROL                                               0x1bb3
495#define SEA_mmCRTC0_CRTC_START_LINE_CONTROL                                         0x1bb3
496#define SEA_mmCRTC1_CRTC_START_LINE_CONTROL                                         0x1eb3
497#define SEA_mmCRTC2_CRTC_START_LINE_CONTROL                                         0x41b3
498#define SEA_mmCRTC3_CRTC_START_LINE_CONTROL                                         0x44b3
499#define SEA_mmCRTC4_CRTC_START_LINE_CONTROL                                         0x47b3
500#define SEA_mmCRTC5_CRTC_START_LINE_CONTROL                                         0x4ab3
501#define SEA_mmCRTC_INTERRUPT_CONTROL                                                0x1bb4
502#define SEA_mmCRTC0_CRTC_INTERRUPT_CONTROL                                          0x1bb4
503#define SEA_mmCRTC1_CRTC_INTERRUPT_CONTROL                                          0x1eb4
504#define SEA_mmCRTC2_CRTC_INTERRUPT_CONTROL                                          0x41b4
505#define SEA_mmCRTC3_CRTC_INTERRUPT_CONTROL                                          0x44b4
506#define SEA_mmCRTC4_CRTC_INTERRUPT_CONTROL                                          0x47b4
507#define SEA_mmCRTC5_CRTC_INTERRUPT_CONTROL                                          0x4ab4
508#define SEA_mmCRTC_UPDATE_LOCK                                                      0x1bb5
509#define SEA_mmCRTC0_CRTC_UPDATE_LOCK                                                0x1bb5
510#define SEA_mmCRTC1_CRTC_UPDATE_LOCK                                                0x1eb5
511#define SEA_mmCRTC2_CRTC_UPDATE_LOCK                                                0x41b5
512#define SEA_mmCRTC3_CRTC_UPDATE_LOCK                                                0x44b5
513#define SEA_mmCRTC4_CRTC_UPDATE_LOCK                                                0x47b5
514#define SEA_mmCRTC5_CRTC_UPDATE_LOCK                                                0x4ab5
515#define SEA_mmCRTC_DOUBLE_BUFFER_CONTROL                                            0x1bb6
516#define SEA_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1bb6
517#define SEA_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1eb6
518#define SEA_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL                                      0x41b6
519#define SEA_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL                                      0x44b6
520#define SEA_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL                                      0x47b6
521#define SEA_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL                                      0x4ab6
522#define SEA_mmCRTC_VGA_PARAMETER_CAPTURE_MODE                                       0x1bb7
523#define SEA_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1bb7
524#define SEA_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1eb7
525#define SEA_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x41b7
526#define SEA_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x44b7
527#define SEA_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x47b7
528#define SEA_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x4ab7
529#define SEA_mmCRTC_TEST_PATTERN_CONTROL                                             0x1bba
530#define SEA_mmCRTC0_CRTC_TEST_PATTERN_CONTROL                                       0x1bba
531#define SEA_mmCRTC1_CRTC_TEST_PATTERN_CONTROL                                       0x1eba
532#define SEA_mmCRTC2_CRTC_TEST_PATTERN_CONTROL                                       0x41ba
533#define SEA_mmCRTC3_CRTC_TEST_PATTERN_CONTROL                                       0x44ba
534#define SEA_mmCRTC4_CRTC_TEST_PATTERN_CONTROL                                       0x47ba
535#define SEA_mmCRTC5_CRTC_TEST_PATTERN_CONTROL                                       0x4aba
536#define SEA_mmCRTC_TEST_PATTERN_PARAMETERS                                          0x1bbb
537#define SEA_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS                                    0x1bbb
538#define SEA_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS                                    0x1ebb
539#define SEA_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS                                    0x41bb
540#define SEA_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS                                    0x44bb
541#define SEA_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS                                    0x47bb
542#define SEA_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS                                    0x4abb
543#define SEA_mmCRTC_TEST_PATTERN_COLOR                                               0x1bbc
544#define SEA_mmCRTC0_CRTC_TEST_PATTERN_COLOR                                         0x1bbc
545#define SEA_mmCRTC1_CRTC_TEST_PATTERN_COLOR                                         0x1ebc
546#define SEA_mmCRTC2_CRTC_TEST_PATTERN_COLOR                                         0x41bc
547#define SEA_mmCRTC3_CRTC_TEST_PATTERN_COLOR                                         0x44bc
548#define SEA_mmCRTC4_CRTC_TEST_PATTERN_COLOR                                         0x47bc
549#define SEA_mmCRTC5_CRTC_TEST_PATTERN_COLOR                                         0x4abc
550#define SEA_mmMASTER_UPDATE_LOCK                                                    0x1bbd
551#define SEA_mmCRTC0_MASTER_UPDATE_LOCK                                              0x1bbd
552#define SEA_mmCRTC1_MASTER_UPDATE_LOCK                                              0x1ebd
553#define SEA_mmCRTC2_MASTER_UPDATE_LOCK                                              0x41bd
554#define SEA_mmCRTC3_MASTER_UPDATE_LOCK                                              0x44bd
555#define SEA_mmCRTC4_MASTER_UPDATE_LOCK                                              0x47bd
556#define SEA_mmCRTC5_MASTER_UPDATE_LOCK                                              0x4abd
557#define SEA_mmMASTER_UPDATE_MODE                                                    0x1bbe
558#define SEA_mmCRTC0_MASTER_UPDATE_MODE                                              0x1bbe
559#define SEA_mmCRTC1_MASTER_UPDATE_MODE                                              0x1ebe
560#define SEA_mmCRTC2_MASTER_UPDATE_MODE                                              0x41be
561#define SEA_mmCRTC3_MASTER_UPDATE_MODE                                              0x44be
562#define SEA_mmCRTC4_MASTER_UPDATE_MODE                                              0x47be
563#define SEA_mmCRTC5_MASTER_UPDATE_MODE                                              0x4abe
564#define SEA_mmCRTC_MVP_INBAND_CNTL_INSERT                                           0x1bbf
565#define SEA_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1bbf
566#define SEA_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1ebf
567#define SEA_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT                                     0x41bf
568#define SEA_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT                                     0x44bf
569#define SEA_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT                                     0x47bf
570#define SEA_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT                                     0x4abf
571#define SEA_mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER                                     0x1bc0
572#define SEA_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1bc0
573#define SEA_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1ec0
574#define SEA_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x41c0
575#define SEA_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x44c0
576#define SEA_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x47c0
577#define SEA_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x4ac0
578#define SEA_mmCRTC_MVP_STATUS                                                       0x1bc1
579#define SEA_mmCRTC0_CRTC_MVP_STATUS                                                 0x1bc1
580#define SEA_mmCRTC1_CRTC_MVP_STATUS                                                 0x1ec1
581#define SEA_mmCRTC2_CRTC_MVP_STATUS                                                 0x41c1
582#define SEA_mmCRTC3_CRTC_MVP_STATUS                                                 0x44c1
583#define SEA_mmCRTC4_CRTC_MVP_STATUS                                                 0x47c1
584#define SEA_mmCRTC5_CRTC_MVP_STATUS                                                 0x4ac1
585#define SEA_mmCRTC_MASTER_EN                                                        0x1bc2
586#define SEA_mmCRTC0_CRTC_MASTER_EN                                                  0x1bc2
587#define SEA_mmCRTC1_CRTC_MASTER_EN                                                  0x1ec2
588#define SEA_mmCRTC2_CRTC_MASTER_EN                                                  0x41c2
589#define SEA_mmCRTC3_CRTC_MASTER_EN                                                  0x44c2
590#define SEA_mmCRTC4_CRTC_MASTER_EN                                                  0x47c2
591#define SEA_mmCRTC5_CRTC_MASTER_EN                                                  0x4ac2
592#define SEA_mmCRTC_ALLOW_STOP_OFF_V_CNT                                             0x1bc3
593#define SEA_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1bc3
594#define SEA_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1ec3
595#define SEA_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x41c3
596#define SEA_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x44c3
597#define SEA_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x47c3
598#define SEA_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x4ac3
599#define SEA_mmCRTC_V_UPDATE_INT_STATUS                                              0x1bc4
600#define SEA_mmCRTC0_CRTC_V_UPDATE_INT_STATUS                                        0x1bc4
601#define SEA_mmCRTC1_CRTC_V_UPDATE_INT_STATUS                                        0x1ec4
602#define SEA_mmCRTC2_CRTC_V_UPDATE_INT_STATUS                                        0x41c4
603#define SEA_mmCRTC3_CRTC_V_UPDATE_INT_STATUS                                        0x44c4
604#define SEA_mmCRTC4_CRTC_V_UPDATE_INT_STATUS                                        0x47c4
605#define SEA_mmCRTC5_CRTC_V_UPDATE_INT_STATUS                                        0x4ac4
606#define SEA_mmCRTC_OVERSCAN_COLOR                                                   0x1bc8
607#define SEA_mmCRTC0_CRTC_OVERSCAN_COLOR                                             0x1bc8
608#define SEA_mmCRTC1_CRTC_OVERSCAN_COLOR                                             0x1ec8
609#define SEA_mmCRTC2_CRTC_OVERSCAN_COLOR                                             0x41c8
610#define SEA_mmCRTC3_CRTC_OVERSCAN_COLOR                                             0x44c8
611#define SEA_mmCRTC4_CRTC_OVERSCAN_COLOR                                             0x47c8
612#define SEA_mmCRTC5_CRTC_OVERSCAN_COLOR                                             0x4ac8
613#define SEA_mmCRTC_OVERSCAN_COLOR_EXT                                               0x1bc9
614#define SEA_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT                                         0x1bc9
615#define SEA_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT                                         0x1ec9
616#define SEA_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT                                         0x41c9
617#define SEA_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT                                         0x44c9
618#define SEA_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT                                         0x47c9
619#define SEA_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT                                         0x4ac9
620#define SEA_mmCRTC_BLANK_DATA_COLOR                                                 0x1bca
621#define SEA_mmCRTC0_CRTC_BLANK_DATA_COLOR                                           0x1bca
622#define SEA_mmCRTC1_CRTC_BLANK_DATA_COLOR                                           0x1eca
623#define SEA_mmCRTC2_CRTC_BLANK_DATA_COLOR                                           0x41ca
624#define SEA_mmCRTC3_CRTC_BLANK_DATA_COLOR                                           0x44ca
625#define SEA_mmCRTC4_CRTC_BLANK_DATA_COLOR                                           0x47ca
626#define SEA_mmCRTC5_CRTC_BLANK_DATA_COLOR                                           0x4aca
627#define SEA_mmCRTC_BLANK_DATA_COLOR_EXT                                             0x1bcb
628#define SEA_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT                                       0x1bcb
629#define SEA_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT                                       0x1ecb
630#define SEA_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT                                       0x41cb
631#define SEA_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT                                       0x44cb
632#define SEA_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT                                       0x47cb
633#define SEA_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT                                       0x4acb
634#define SEA_mmCRTC_BLACK_COLOR                                                      0x1bcc
635#define SEA_mmCRTC0_CRTC_BLACK_COLOR                                                0x1bcc
636#define SEA_mmCRTC1_CRTC_BLACK_COLOR                                                0x1ecc
637#define SEA_mmCRTC2_CRTC_BLACK_COLOR                                                0x41cc
638#define SEA_mmCRTC3_CRTC_BLACK_COLOR                                                0x44cc
639#define SEA_mmCRTC4_CRTC_BLACK_COLOR                                                0x47cc
640#define SEA_mmCRTC5_CRTC_BLACK_COLOR                                                0x4acc
641#define SEA_mmCRTC_BLACK_COLOR_EXT                                                  0x1bcd
642#define SEA_mmCRTC0_CRTC_BLACK_COLOR_EXT                                            0x1bcd
643#define SEA_mmCRTC1_CRTC_BLACK_COLOR_EXT                                            0x1ecd
644#define SEA_mmCRTC2_CRTC_BLACK_COLOR_EXT                                            0x41cd
645#define SEA_mmCRTC3_CRTC_BLACK_COLOR_EXT                                            0x44cd
646#define SEA_mmCRTC4_CRTC_BLACK_COLOR_EXT                                            0x47cd
647#define SEA_mmCRTC5_CRTC_BLACK_COLOR_EXT                                            0x4acd
648#define SEA_mmCRTC_VERTICAL_INTERRUPT0_POSITION                                     0x1bce
649#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1bce
650#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1ece
651#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x41ce
652#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x44ce
653#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x47ce
654#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x4ace
655#define SEA_mmCRTC_VERTICAL_INTERRUPT0_CONTROL                                      0x1bcf
656#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1bcf
657#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1ecf
658#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x41cf
659#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x44cf
660#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x47cf
661#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x4acf
662#define SEA_mmCRTC_VERTICAL_INTERRUPT1_POSITION                                     0x1bd0
663#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1bd0
664#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1ed0
665#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x41d0
666#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x44d0
667#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x47d0
668#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x4ad0
669#define SEA_mmCRTC_VERTICAL_INTERRUPT1_CONTROL                                      0x1bd1
670#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1bd1
671#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1ed1
672#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x41d1
673#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x44d1
674#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x47d1
675#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x4ad1
676#define SEA_mmCRTC_VERTICAL_INTERRUPT2_POSITION                                     0x1bd2
677#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1bd2
678#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1ed2
679#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x41d2
680#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x44d2
681#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x47d2
682#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x4ad2
683#define SEA_mmCRTC_VERTICAL_INTERRUPT2_CONTROL                                      0x1bd3
684#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1bd3
685#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1ed3
686#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x41d3
687#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x44d3
688#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x47d3
689#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x4ad3
690#define SEA_mmCRTC_CRC_CNTL                                                         0x1bd4
691#define SEA_mmCRTC0_CRTC_CRC_CNTL                                                   0x1bd4
692#define SEA_mmCRTC1_CRTC_CRC_CNTL                                                   0x1ed4
693#define SEA_mmCRTC2_CRTC_CRC_CNTL                                                   0x41d4
694#define SEA_mmCRTC3_CRTC_CRC_CNTL                                                   0x44d4
695#define SEA_mmCRTC4_CRTC_CRC_CNTL                                                   0x47d4
696#define SEA_mmCRTC5_CRTC_CRC_CNTL                                                   0x4ad4
697#define SEA_mmCRTC_CRC0_WINDOWA_X_CONTROL                                           0x1bd5
698#define SEA_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1bd5
699#define SEA_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1ed5
700#define SEA_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x41d5
701#define SEA_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x44d5
702#define SEA_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x47d5
703#define SEA_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x4ad5
704#define SEA_mmCRTC_CRC0_WINDOWA_Y_CONTROL                                           0x1bd6
705#define SEA_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1bd6
706#define SEA_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1ed6
707#define SEA_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x41d6
708#define SEA_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x44d6
709#define SEA_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x47d6
710#define SEA_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x4ad6
711#define SEA_mmCRTC_CRC0_WINDOWB_X_CONTROL                                           0x1bd7
712#define SEA_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1bd7
713#define SEA_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1ed7
714#define SEA_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x41d7
715#define SEA_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x44d7
716#define SEA_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x47d7
717#define SEA_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x4ad7
718#define SEA_mmCRTC_CRC0_WINDOWB_Y_CONTROL                                           0x1bd8
719#define SEA_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1bd8
720#define SEA_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1ed8
721#define SEA_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x41d8
722#define SEA_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x44d8
723#define SEA_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x47d8
724#define SEA_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x4ad8
725#define SEA_mmCRTC_CRC0_DATA_RG                                                     0x1bd9
726#define SEA_mmCRTC0_CRTC_CRC0_DATA_RG                                               0x1bd9
727#define SEA_mmCRTC1_CRTC_CRC0_DATA_RG                                               0x1ed9
728#define SEA_mmCRTC2_CRTC_CRC0_DATA_RG                                               0x41d9
729#define SEA_mmCRTC3_CRTC_CRC0_DATA_RG                                               0x44d9
730#define SEA_mmCRTC4_CRTC_CRC0_DATA_RG                                               0x47d9
731#define SEA_mmCRTC5_CRTC_CRC0_DATA_RG                                               0x4ad9
732#define SEA_mmCRTC_CRC0_DATA_B                                                      0x1bda
733#define SEA_mmCRTC0_CRTC_CRC0_DATA_B                                                0x1bda
734#define SEA_mmCRTC1_CRTC_CRC0_DATA_B                                                0x1eda
735#define SEA_mmCRTC2_CRTC_CRC0_DATA_B                                                0x41da
736#define SEA_mmCRTC3_CRTC_CRC0_DATA_B                                                0x44da
737#define SEA_mmCRTC4_CRTC_CRC0_DATA_B                                                0x47da
738#define SEA_mmCRTC5_CRTC_CRC0_DATA_B                                                0x4ada
739#define SEA_mmCRTC_CRC1_WINDOWA_X_CONTROL                                           0x1bdb
740#define SEA_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1bdb
741#define SEA_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1edb
742#define SEA_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x41db
743#define SEA_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x44db
744#define SEA_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x47db
745#define SEA_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x4adb
746#define SEA_mmCRTC_CRC1_WINDOWA_Y_CONTROL                                           0x1bdc
747#define SEA_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1bdc
748#define SEA_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1edc
749#define SEA_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x41dc
750#define SEA_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x44dc
751#define SEA_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x47dc
752#define SEA_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x4adc
753#define SEA_mmCRTC_CRC1_WINDOWB_X_CONTROL                                           0x1bdd
754#define SEA_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1bdd
755#define SEA_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1edd
756#define SEA_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x41dd
757#define SEA_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x44dd
758#define SEA_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x47dd
759#define SEA_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x4add
760#define SEA_mmCRTC_CRC1_WINDOWB_Y_CONTROL                                           0x1bde
761#define SEA_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1bde
762#define SEA_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1ede
763#define SEA_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x41de
764#define SEA_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x44de
765#define SEA_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x47de
766#define SEA_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x4ade
767#define SEA_mmCRTC_CRC1_DATA_RG                                                     0x1bdf
768#define SEA_mmCRTC0_CRTC_CRC1_DATA_RG                                               0x1bdf
769#define SEA_mmCRTC1_CRTC_CRC1_DATA_RG                                               0x1edf
770#define SEA_mmCRTC2_CRTC_CRC1_DATA_RG                                               0x41df
771#define SEA_mmCRTC3_CRTC_CRC1_DATA_RG                                               0x44df
772#define SEA_mmCRTC4_CRTC_CRC1_DATA_RG                                               0x47df
773#define SEA_mmCRTC5_CRTC_CRC1_DATA_RG                                               0x4adf
774#define SEA_mmCRTC_CRC1_DATA_B                                                      0x1be0
775#define SEA_mmCRTC0_CRTC_CRC1_DATA_B                                                0x1be0
776#define SEA_mmCRTC1_CRTC_CRC1_DATA_B                                                0x1ee0
777#define SEA_mmCRTC2_CRTC_CRC1_DATA_B                                                0x41e0
778#define SEA_mmCRTC3_CRTC_CRC1_DATA_B                                                0x44e0
779#define SEA_mmCRTC4_CRTC_CRC1_DATA_B                                                0x47e0
780#define SEA_mmCRTC5_CRTC_CRC1_DATA_B                                                0x4ae0
781#define SEA_mmCRTC_EXT_TIMING_SYNC_CONTROL                                          0x1be1
782#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1be1
783#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1ee1
784#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x41e1
785#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x44e1
786#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x47e1
787#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x4ae1
788#define SEA_mmCRTC_EXT_TIMING_SYNC_WINDOW_START                                     0x1be2
789#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1be2
790#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1ee2
791#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x41e2
792#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x44e2
793#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x47e2
794#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x4ae2
795#define SEA_mmCRTC_EXT_TIMING_SYNC_WINDOW_END                                       0x1be3
796#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1be3
797#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1ee3
798#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x41e3
799#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x44e3
800#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x47e3
801#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x4ae3
802#define SEA_mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                           0x1be4
803#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1be4
804#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1ee4
805#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x41e4
806#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x44e4
807#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x47e4
808#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x4ae4
809#define SEA_mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                0x1be5
810#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1be5
811#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1ee5
812#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x41e5
813#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x44e5
814#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x47e5
815#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x4ae5
816#define SEA_mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                         0x1be6
817#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1be6
818#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1ee6
819#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x41e6
820#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x44e6
821#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x47e6
822#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x4ae6
823#define SEA_mmCRTC_STATIC_SCREEN_CONTROL                                            0x1be7
824#define SEA_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL                                      0x1be7
825#define SEA_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL                                      0x1ee7
826#define SEA_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL                                      0x41e7
827#define SEA_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL                                      0x44e7
828#define SEA_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL                                      0x47e7
829#define SEA_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL                                      0x4ae7
830#define SEA_mmCRTC_3D_STRUCTURE_CONTROL                                             0x1b78
831#define SEA_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL                                       0x1b78
832#define SEA_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL                                       0x1e78
833#define SEA_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL                                       0x4178
834#define SEA_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL                                       0x4478
835#define SEA_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL                                       0x4778
836#define SEA_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL                                       0x4a78
837#define SEA_mmCRTC_GSL_VSYNC_GAP                                                    0x1b79
838#define SEA_mmCRTC0_CRTC_GSL_VSYNC_GAP                                              0x1b79
839#define SEA_mmCRTC1_CRTC_GSL_VSYNC_GAP                                              0x1e79
840#define SEA_mmCRTC2_CRTC_GSL_VSYNC_GAP                                              0x4179
841#define SEA_mmCRTC3_CRTC_GSL_VSYNC_GAP                                              0x4479
842#define SEA_mmCRTC4_CRTC_GSL_VSYNC_GAP                                              0x4779
843#define SEA_mmCRTC5_CRTC_GSL_VSYNC_GAP                                              0x4a79
844#define SEA_mmCRTC_GSL_WINDOW                                                       0x1b7a
845#define SEA_mmCRTC0_CRTC_GSL_WINDOW                                                 0x1b7a
846#define SEA_mmCRTC1_CRTC_GSL_WINDOW                                                 0x1e7a
847#define SEA_mmCRTC2_CRTC_GSL_WINDOW                                                 0x417a
848#define SEA_mmCRTC3_CRTC_GSL_WINDOW                                                 0x447a
849#define SEA_mmCRTC4_CRTC_GSL_WINDOW                                                 0x477a
850#define SEA_mmCRTC5_CRTC_GSL_WINDOW                                                 0x4a7a
851#define SEA_mmCRTC_GSL_CONTROL                                                      0x1b7b
852#define SEA_mmCRTC0_CRTC_GSL_CONTROL                                                0x1b7b
853#define SEA_mmCRTC1_CRTC_GSL_CONTROL                                                0x1e7b
854#define SEA_mmCRTC2_CRTC_GSL_CONTROL                                                0x417b
855#define SEA_mmCRTC3_CRTC_GSL_CONTROL                                                0x447b
856#define SEA_mmCRTC4_CRTC_GSL_CONTROL                                                0x477b
857#define SEA_mmCRTC5_CRTC_GSL_CONTROL                                                0x4a7b
858#define SEA_mmCRTC_TEST_DEBUG_INDEX                                                 0x1bc6
859#define SEA_mmCRTC0_CRTC_TEST_DEBUG_INDEX                                           0x1bc6
860#define SEA_mmCRTC1_CRTC_TEST_DEBUG_INDEX                                           0x1ec6
861#define SEA_mmCRTC2_CRTC_TEST_DEBUG_INDEX                                           0x41c6
862#define SEA_mmCRTC3_CRTC_TEST_DEBUG_INDEX                                           0x44c6
863#define SEA_mmCRTC4_CRTC_TEST_DEBUG_INDEX                                           0x47c6
864#define SEA_mmCRTC5_CRTC_TEST_DEBUG_INDEX                                           0x4ac6
865#define SEA_mmCRTC_TEST_DEBUG_DATA                                                  0x1bc7
866#define SEA_mmCRTC0_CRTC_TEST_DEBUG_DATA                                            0x1bc7
867#define SEA_mmCRTC1_CRTC_TEST_DEBUG_DATA                                            0x1ec7
868#define SEA_mmCRTC2_CRTC_TEST_DEBUG_DATA                                            0x41c7
869#define SEA_mmCRTC3_CRTC_TEST_DEBUG_DATA                                            0x44c7
870#define SEA_mmCRTC4_CRTC_TEST_DEBUG_DATA                                            0x47c7
871#define SEA_mmCRTC5_CRTC_TEST_DEBUG_DATA                                            0x4ac7
872#define SEA_mmDAC_ENABLE                                                            0x19e4
873#define SEA_mmDAC_SOURCE_SELECT                                                     0x19e5
874#define SEA_mmDAC_CRC_EN                                                            0x19e6
875#define SEA_mmDAC_CRC_CONTROL                                                       0x19e7
876#define SEA_mmDAC_CRC_SIG_RGB_MASK                                                  0x19e8
877#define SEA_mmDAC_CRC_SIG_CONTROL_MASK                                              0x19e9
878#define SEA_mmDAC_CRC_SIG_RGB                                                       0x19ea
879#define SEA_mmDAC_CRC_SIG_CONTROL                                                   0x19eb
880#define SEA_mmDAC_SYNC_TRISTATE_CONTROL                                             0x19ec
881#define SEA_mmDAC_STEREOSYNC_SELECT                                                 0x19ed
882#define SEA_mmDAC_AUTODETECT_CONTROL                                                0x19ee
883#define SEA_mmDAC_AUTODETECT_CONTROL2                                               0x19ef
884#define SEA_mmDAC_AUTODETECT_CONTROL3                                               0x19f0
885#define SEA_mmDAC_AUTODETECT_STATUS                                                 0x19f1
886#define SEA_mmDAC_AUTODETECT_INT_CONTROL                                            0x19f2
887#define SEA_mmDAC_FORCE_OUTPUT_CNTL                                                 0x19f3
888#define SEA_mmDAC_FORCE_DATA                                                        0x19f4
889#define SEA_mmDAC_POWERDOWN                                                         0x19f5
890#define SEA_mmDAC_CONTROL                                                           0x19f6
891#define SEA_mmDAC_COMPARATOR_ENABLE                                                 0x19f7
892#define SEA_mmDAC_COMPARATOR_OUTPUT                                                 0x19f8
893#define SEA_mmDAC_PWR_CNTL                                                          0x19f9
894#define SEA_mmDAC_DFT_CONFIG                                                        0x19fa
895#define SEA_mmDAC_FIFO_STATUS                                                       0x19fb
896#define SEA_mmPERFCOUNTER_CNTL                                                      0x170
897#define SEA_mmDC_PERFMON0_PERFCOUNTER_CNTL                                          0x170
898#define SEA_mmDC_PERFMON1_PERFCOUNTER_CNTL                                          0x1870
899#define SEA_mmDC_PERFMON2_PERFCOUNTER_CNTL                                          0x1b24
900#define SEA_mmDC_PERFMON3_PERFCOUNTER_CNTL                                          0x1e24
901#define SEA_mmDC_PERFMON4_PERFCOUNTER_CNTL                                          0x4124
902#define SEA_mmDC_PERFMON5_PERFCOUNTER_CNTL                                          0x4424
903#define SEA_mmDC_PERFMON6_PERFCOUNTER_CNTL                                          0x4724
904#define SEA_mmDC_PERFMON7_PERFCOUNTER_CNTL                                          0x4a24
905#define SEA_mmDC_PERFMON8_PERFCOUNTER_CNTL                                          0x4c40
906#define SEA_mmDC_PERFMON9_PERFCOUNTER_CNTL                                          0x4d14
907#define SEA_mmPERFCOUNTER_STATE                                                     0x171
908#define SEA_mmDC_PERFMON0_PERFCOUNTER_STATE                                         0x171
909#define SEA_mmDC_PERFMON1_PERFCOUNTER_STATE                                         0x1871
910#define SEA_mmDC_PERFMON2_PERFCOUNTER_STATE                                         0x1b25
911#define SEA_mmDC_PERFMON3_PERFCOUNTER_STATE                                         0x1e25
912#define SEA_mmDC_PERFMON4_PERFCOUNTER_STATE                                         0x4125
913#define SEA_mmDC_PERFMON5_PERFCOUNTER_STATE                                         0x4425
914#define SEA_mmDC_PERFMON6_PERFCOUNTER_STATE                                         0x4725
915#define SEA_mmDC_PERFMON7_PERFCOUNTER_STATE                                         0x4a25
916#define SEA_mmDC_PERFMON8_PERFCOUNTER_STATE                                         0x4c41
917#define SEA_mmDC_PERFMON9_PERFCOUNTER_STATE                                         0x4d15
918#define SEA_mmPERFMON_CNTL                                                          0x173
919#define SEA_mmDC_PERFMON0_PERFMON_CNTL                                              0x173
920#define SEA_mmDC_PERFMON1_PERFMON_CNTL                                              0x1873
921#define SEA_mmDC_PERFMON2_PERFMON_CNTL                                              0x1b27
922#define SEA_mmDC_PERFMON3_PERFMON_CNTL                                              0x1e27
923#define SEA_mmDC_PERFMON4_PERFMON_CNTL                                              0x4127
924#define SEA_mmDC_PERFMON5_PERFMON_CNTL                                              0x4427
925#define SEA_mmDC_PERFMON6_PERFMON_CNTL                                              0x4727
926#define SEA_mmDC_PERFMON7_PERFMON_CNTL                                              0x4a27
927#define SEA_mmDC_PERFMON8_PERFMON_CNTL                                              0x4c43
928#define SEA_mmDC_PERFMON9_PERFMON_CNTL                                              0x4d17
929#define SEA_mmPERFMON_CVALUE_INT_MISC                                               0x172
930#define SEA_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                   0x172
931#define SEA_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                   0x1872
932#define SEA_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                   0x1b26
933#define SEA_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                   0x1e26
934#define SEA_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                   0x4126
935#define SEA_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                   0x4426
936#define SEA_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                   0x4726
937#define SEA_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                   0x4a26
938#define SEA_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                   0x4c42
939#define SEA_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                   0x4d16
940#define SEA_mmPERFMON_CVALUE_LOW                                                    0x174
941#define SEA_mmDC_PERFMON0_PERFMON_CVALUE_LOW                                        0x174
942#define SEA_mmDC_PERFMON1_PERFMON_CVALUE_LOW                                        0x1874
943#define SEA_mmDC_PERFMON2_PERFMON_CVALUE_LOW                                        0x1b28
944#define SEA_mmDC_PERFMON3_PERFMON_CVALUE_LOW                                        0x1e28
945#define SEA_mmDC_PERFMON4_PERFMON_CVALUE_LOW                                        0x4128
946#define SEA_mmDC_PERFMON5_PERFMON_CVALUE_LOW                                        0x4428
947#define SEA_mmDC_PERFMON6_PERFMON_CVALUE_LOW                                        0x4728
948#define SEA_mmDC_PERFMON7_PERFMON_CVALUE_LOW                                        0x4a28
949#define SEA_mmDC_PERFMON8_PERFMON_CVALUE_LOW                                        0x4c44
950#define SEA_mmDC_PERFMON9_PERFMON_CVALUE_LOW                                        0x4d18
951#define SEA_mmPERFMON_HI                                                            0x175
952#define SEA_mmDC_PERFMON0_PERFMON_HI                                                0x175
953#define SEA_mmDC_PERFMON1_PERFMON_HI                                                0x1875
954#define SEA_mmDC_PERFMON2_PERFMON_HI                                                0x1b29
955#define SEA_mmDC_PERFMON3_PERFMON_HI                                                0x1e29
956#define SEA_mmDC_PERFMON4_PERFMON_HI                                                0x4129
957#define SEA_mmDC_PERFMON5_PERFMON_HI                                                0x4429
958#define SEA_mmDC_PERFMON6_PERFMON_HI                                                0x4729
959#define SEA_mmDC_PERFMON7_PERFMON_HI                                                0x4a29
960#define SEA_mmDC_PERFMON8_PERFMON_HI                                                0x4c45
961#define SEA_mmDC_PERFMON9_PERFMON_HI                                                0x4d19
962#define SEA_mmPERFMON_LOW                                                           0x176
963#define SEA_mmDC_PERFMON0_PERFMON_LOW                                               0x176
964#define SEA_mmDC_PERFMON1_PERFMON_LOW                                               0x1876
965#define SEA_mmDC_PERFMON2_PERFMON_LOW                                               0x1b2a
966#define SEA_mmDC_PERFMON3_PERFMON_LOW                                               0x1e2a
967#define SEA_mmDC_PERFMON4_PERFMON_LOW                                               0x412a
968#define SEA_mmDC_PERFMON5_PERFMON_LOW                                               0x442a
969#define SEA_mmDC_PERFMON6_PERFMON_LOW                                               0x472a
970#define SEA_mmDC_PERFMON7_PERFMON_LOW                                               0x4a2a
971#define SEA_mmDC_PERFMON8_PERFMON_LOW                                               0x4c46
972#define SEA_mmDC_PERFMON9_PERFMON_LOW                                               0x4d1a
973#define SEA_mmPERFMON_TEST_DEBUG_INDEX                                              0x177
974#define SEA_mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX                                  0x177
975#define SEA_mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX                                  0x1877
976#define SEA_mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX                                  0x1b2b
977#define SEA_mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX                                  0x1e2b
978#define SEA_mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX                                  0x412b
979#define SEA_mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX                                  0x442b
980#define SEA_mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX                                  0x472b
981#define SEA_mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX                                  0x4a2b
982#define SEA_mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX                                  0x4c47
983#define SEA_mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX                                  0x4d1b
984#define SEA_mmPERFMON_TEST_DEBUG_DATA                                               0x178
985#define SEA_mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA                                   0x178
986#define SEA_mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA                                   0x1878
987#define SEA_mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA                                   0x1b2c
988#define SEA_mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA                                   0x1e2c
989#define SEA_mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA                                   0x412c
990#define SEA_mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA                                   0x442c
991#define SEA_mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA                                   0x472c
992#define SEA_mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA                                   0x4a2c
993#define SEA_mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA                                   0x4c48
994#define SEA_mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA                                   0x4d1c
995#define SEA_mmVGA25_PPLL_REF_DIV                                                    0xd8
996#define SEA_mmVGA28_PPLL_REF_DIV                                                    0xd9
997#define SEA_mmVGA41_PPLL_REF_DIV                                                    0xda
998#define SEA_mmVGA25_PPLL_FB_DIV                                                     0xdc
999#define SEA_mmVGA28_PPLL_FB_DIV                                                     0xdd
1000#define SEA_mmVGA41_PPLL_FB_DIV                                                     0xde
1001#define SEA_mmVGA25_PPLL_POST_DIV                                                   0xe0
1002#define SEA_mmVGA28_PPLL_POST_DIV                                                   0xe1
1003#define SEA_mmVGA41_PPLL_POST_DIV                                                   0xe2
1004#define SEA_mmVGA25_PPLL_ANALOG                                                     0xe4
1005#define SEA_mmVGA28_PPLL_ANALOG                                                     0xe5
1006#define SEA_mmVGA41_PPLL_ANALOG                                                     0xe6
1007#define SEA_mmDPREFCLK_CNTL                                                         0x118
1008#define SEA_mmSCANIN_SOFT_RESET                                                     0x11e
1009#define SEA_mmDCCG_GTC_CNTL                                                         0x120
1010#define SEA_mmDCCG_GTC_DTO_INCR                                                     0x121
1011#define SEA_mmDCCG_GTC_DTO_MODULO                                                   0x122
1012#define SEA_mmDCCG_GTC_CURRENT                                                      0x123
1013#define SEA_mmDCCG_DS_DTO_INCR                                                      0x113
1014#define SEA_mmDCCG_DS_DTO_MODULO                                                    0x114
1015#define SEA_mmDCCG_DS_CNTL                                                          0x115
1016#define SEA_mmDCCG_DS_HW_CAL_INTERVAL                                               0x116
1017#define SEA_mmDCCG_DS_DEBUG_CNTL                                                    0x112
1018#define SEA_mmDMCU_SMU_INTERRUPT_CNTL                                               0x12c
1019#define SEA_mmSMU_CONTROL                                                           0x12d
1020#define SEA_mmSMU_INTERRUPT_CONTROL                                                 0x12e
1021#define SEA_mmDAC_CLK_ENABLE                                                        0x128
1022#define SEA_mmDVO_CLK_ENABLE                                                        0x129
1023#define SEA_mmDCCG_GATE_DISABLE_CNTL                                                0x134
1024#define SEA_mmDISPCLK_CGTT_BLK_CTRL_REG                                             0x135
1025#define SEA_mmSCLK_CGTT_BLK_CTRL_REG                                                0x136
1026#define SEA_mmDCCG_CAC_STATUS                                                       0x137
1027#define SEA_mmPIXCLK1_RESYNC_CNTL                                                   0x138
1028#define SEA_mmPIXCLK2_RESYNC_CNTL                                                   0x139
1029#define SEA_mmPIXCLK0_RESYNC_CNTL                                                   0x13a
1030#define SEA_mmMICROSECOND_TIME_BASE_DIV                                             0x13b
1031#define SEA_mmDCCG_DISP_CNTL_REG                                                    0x13f
1032#define SEA_mmDISPPLL_BG_CNTL                                                       0x13c
1033#define SEA_mmDIG_SOFT_RESET                                                        0x13d
1034#define SEA_mmMILLISECOND_TIME_BASE_DIV                                             0x130
1035#define SEA_mmDISPCLK_FREQ_CHANGE_CNTL                                              0x131
1036#define SEA_mmLIGHT_SLEEP_CNTL                                                      0x132
1037#define SEA_mmDCCG_PERFMON_CNTL                                                     0x133
1038#define SEA_mmCRTC0_PIXEL_RATE_CNTL                                                 0x140
1039#define SEA_mmDP_DTO0_PHASE                                                         0x141
1040#define SEA_mmDP_DTO0_MODULO                                                        0x142
1041#define SEA_mmCRTC1_PIXEL_RATE_CNTL                                                 0x144
1042#define SEA_mmDP_DTO1_PHASE                                                         0x145
1043#define SEA_mmDP_DTO1_MODULO                                                        0x146
1044#define SEA_mmCRTC2_PIXEL_RATE_CNTL                                                 0x148
1045#define SEA_mmDP_DTO2_PHASE                                                         0x149
1046#define SEA_mmDP_DTO2_MODULO                                                        0x14a
1047#define SEA_mmCRTC3_PIXEL_RATE_CNTL                                                 0x14c
1048#define SEA_mmDP_DTO3_PHASE                                                         0x14d
1049#define SEA_mmDP_DTO3_MODULO                                                        0x14e
1050#define SEA_mmCRTC4_PIXEL_RATE_CNTL                                                 0x150
1051#define SEA_mmDP_DTO4_PHASE                                                         0x151
1052#define SEA_mmDP_DTO4_MODULO                                                        0x152
1053#define SEA_mmCRTC5_PIXEL_RATE_CNTL                                                 0x154
1054#define SEA_mmDP_DTO5_PHASE                                                         0x155
1055#define SEA_mmDP_DTO5_MODULO                                                        0x156
1056#define SEA_mmDCFE0_SOFT_RESET                                                      0x158
1057#define SEA_mmDCFE1_SOFT_RESET                                                      0x159
1058#define SEA_mmDCFE2_SOFT_RESET                                                      0x15a
1059#define SEA_mmDCFE3_SOFT_RESET                                                      0x15b
1060#define SEA_mmDCFE4_SOFT_RESET                                                      0x15c
1061#define SEA_mmDCFE5_SOFT_RESET                                                      0x15d
1062#define SEA_mmDCI_SOFT_RESET                                                        0x15e
1063#define SEA_mmDCCG_SOFT_RESET                                                       0x15f
1064#define SEA_mmSYMCLKA_CLOCK_ENABLE                                                  0x160
1065#define SEA_mmSYMCLKB_CLOCK_ENABLE                                                  0x161
1066#define SEA_mmSYMCLKC_CLOCK_ENABLE                                                  0x162
1067#define SEA_mmSYMCLKD_CLOCK_ENABLE                                                  0x163
1068#define SEA_mmSYMCLKE_CLOCK_ENABLE                                                  0x164
1069#define SEA_mmSYMCLKF_CLOCK_ENABLE                                                  0x165
1070#define SEA_mmSYMCLKG_CLOCK_ENABLE                                                  0x117
1071#define SEA_mmUNIPHY_SOFT_RESET                                                     0x166
1072#define SEA_mmDCO_SOFT_RESET                                                        0x167
1073#define SEA_mmDVOACLKD_CNTL                                                         0x168
1074#define SEA_mmDVOACLKC_MVP_CNTL                                                     0x169
1075#define SEA_mmDVOACLKC_CNTL                                                         0x16a
1076#define SEA_mmDCCG_AUDIO_DTO_SOURCE                                                 0x16b
1077#define SEA_mmDCCG_AUDIO_DTO0_PHASE                                                 0x16c
1078#define SEA_mmDCCG_AUDIO_DTO0_MODULE                                                0x16d
1079#define SEA_mmDCCG_AUDIO_DTO1_PHASE                                                 0x16e
1080#define SEA_mmDCCG_AUDIO_DTO1_MODULE                                                0x16f
1081#define SEA_mmDCCG_TEST_DEBUG_INDEX                                                 0x17c
1082#define SEA_mmDCCG_TEST_DEBUG_DATA                                                  0x17d
1083#define SEA_mmDCCG_TEST_CLK_SEL                                                     0x17e
1084#define SEA_mmPLL_REF_DIV                                                           0x1700
1085#define SEA_mmDCCG_PLL0_PLL_REF_DIV                                                 0x1700
1086#define SEA_mmDCCG_PLL1_PLL_REF_DIV                                                 0x1714
1087#define SEA_mmDCCG_PLL2_PLL_REF_DIV                                                 0x1728
1088#define SEA_mmDCCG_PLL3_PLL_REF_DIV                                                 0x173c
1089#define SEA_mmPLL_FB_DIV                                                            0x1701
1090#define SEA_mmDCCG_PLL0_PLL_FB_DIV                                                  0x1701
1091#define SEA_mmDCCG_PLL1_PLL_FB_DIV                                                  0x1715
1092#define SEA_mmDCCG_PLL2_PLL_FB_DIV                                                  0x1729
1093#define SEA_mmDCCG_PLL3_PLL_FB_DIV                                                  0x173d
1094#define SEA_mmPLL_POST_DIV                                                          0x1702
1095#define SEA_mmDCCG_PLL0_PLL_POST_DIV                                                0x1702
1096#define SEA_mmDCCG_PLL1_PLL_POST_DIV                                                0x1716
1097#define SEA_mmDCCG_PLL2_PLL_POST_DIV                                                0x172a
1098#define SEA_mmDCCG_PLL3_PLL_POST_DIV                                                0x173e
1099#define SEA_mmPLL_SS_AMOUNT_DSFRAC                                                  0x1703
1100#define SEA_mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC                                        0x1703
1101#define SEA_mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC                                        0x1717
1102#define SEA_mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC                                        0x172b
1103#define SEA_mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC                                        0x173f
1104#define SEA_mmPLL_SS_CNTL                                                           0x1704
1105#define SEA_mmDCCG_PLL0_PLL_SS_CNTL                                                 0x1704
1106#define SEA_mmDCCG_PLL1_PLL_SS_CNTL                                                 0x1718
1107#define SEA_mmDCCG_PLL2_PLL_SS_CNTL                                                 0x172c
1108#define SEA_mmDCCG_PLL3_PLL_SS_CNTL                                                 0x1740
1109#define SEA_mmPLL_DS_CNTL                                                           0x1705
1110#define SEA_mmDCCG_PLL0_PLL_DS_CNTL                                                 0x1705
1111#define SEA_mmDCCG_PLL1_PLL_DS_CNTL                                                 0x1719
1112#define SEA_mmDCCG_PLL2_PLL_DS_CNTL                                                 0x172d
1113#define SEA_mmDCCG_PLL3_PLL_DS_CNTL                                                 0x1741
1114#define SEA_mmPLL_IDCLK_CNTL                                                        0x1706
1115#define SEA_mmDCCG_PLL0_PLL_IDCLK_CNTL                                              0x1706
1116#define SEA_mmDCCG_PLL1_PLL_IDCLK_CNTL                                              0x171a
1117#define SEA_mmDCCG_PLL2_PLL_IDCLK_CNTL                                              0x172e
1118#define SEA_mmDCCG_PLL3_PLL_IDCLK_CNTL                                              0x1742
1119#define SEA_mmPLL_CNTL                                                              0x1707
1120#define SEA_mmDCCG_PLL0_PLL_CNTL                                                    0x1707
1121#define SEA_mmDCCG_PLL1_PLL_CNTL                                                    0x171b
1122#define SEA_mmDCCG_PLL2_PLL_CNTL                                                    0x172f
1123#define SEA_mmDCCG_PLL3_PLL_CNTL                                                    0x1743
1124#define SEA_mmPLL_ANALOG                                                            0x1708
1125#define SEA_mmDCCG_PLL0_PLL_ANALOG                                                  0x1708
1126#define SEA_mmDCCG_PLL1_PLL_ANALOG                                                  0x171c
1127#define SEA_mmDCCG_PLL2_PLL_ANALOG                                                  0x1730
1128#define SEA_mmDCCG_PLL3_PLL_ANALOG                                                  0x1744
1129#define SEA_mmPLL_ANALOG_CNTL                                                       0x1711
1130#define SEA_mmDCCG_PLL0_PLL_ANALOG_CNTL                                             0x1711
1131#define SEA_mmDCCG_PLL1_PLL_ANALOG_CNTL                                             0x1725
1132#define SEA_mmDCCG_PLL2_PLL_ANALOG_CNTL                                             0x1739
1133#define SEA_mmDCCG_PLL3_PLL_ANALOG_CNTL                                             0x174d
1134#define SEA_mmPLL_VREG_CNTL                                                         0x1709
1135#define SEA_mmDCCG_PLL0_PLL_VREG_CNTL                                               0x1709
1136#define SEA_mmDCCG_PLL1_PLL_VREG_CNTL                                               0x171d
1137#define SEA_mmDCCG_PLL2_PLL_VREG_CNTL                                               0x1731
1138#define SEA_mmDCCG_PLL3_PLL_VREG_CNTL                                               0x1745
1139#define SEA_mmPLL_XOR_LOCK                                                          0x1710
1140#define SEA_mmDCCG_PLL0_PLL_XOR_LOCK                                                0x1710
1141#define SEA_mmDCCG_PLL1_PLL_XOR_LOCK                                                0x1724
1142#define SEA_mmDCCG_PLL2_PLL_XOR_LOCK                                                0x1738
1143#define SEA_mmDCCG_PLL3_PLL_XOR_LOCK                                                0x174c
1144#define SEA_mmPLL_UNLOCK_DETECT_CNTL                                                0x170a
1145#define SEA_mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL                                      0x170a
1146#define SEA_mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL                                      0x171e
1147#define SEA_mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL                                      0x1732
1148#define SEA_mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL                                      0x1746
1149#define SEA_mmPLL_DEBUG_CNTL                                                        0x170b
1150#define SEA_mmDCCG_PLL0_PLL_DEBUG_CNTL                                              0x170b
1151#define SEA_mmDCCG_PLL1_PLL_DEBUG_CNTL                                              0x171f
1152#define SEA_mmDCCG_PLL2_PLL_DEBUG_CNTL                                              0x1733
1153#define SEA_mmDCCG_PLL3_PLL_DEBUG_CNTL                                              0x1747
1154#define SEA_mmPLL_UPDATE_LOCK                                                       0x170c
1155#define SEA_mmDCCG_PLL0_PLL_UPDATE_LOCK                                             0x170c
1156#define SEA_mmDCCG_PLL1_PLL_UPDATE_LOCK                                             0x1720
1157#define SEA_mmDCCG_PLL2_PLL_UPDATE_LOCK                                             0x1734
1158#define SEA_mmDCCG_PLL3_PLL_UPDATE_LOCK                                             0x1748
1159#define SEA_mmPLL_UPDATE_CNTL                                                       0x170d
1160#define SEA_mmDCCG_PLL0_PLL_UPDATE_CNTL                                             0x170d
1161#define SEA_mmDCCG_PLL1_PLL_UPDATE_CNTL                                             0x1721
1162#define SEA_mmDCCG_PLL2_PLL_UPDATE_CNTL                                             0x1735
1163#define SEA_mmDCCG_PLL3_PLL_UPDATE_CNTL                                             0x1749
1164#define SEA_mmPLL_DISPCLK_DTO_CNTL                                                  0x170e
1165#define SEA_mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL                                        0x170e
1166#define SEA_mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL                                        0x1722
1167#define SEA_mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL                                        0x1736
1168#define SEA_mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL                                        0x174a
1169#define SEA_mmPLL_DISPCLK_CURRENT_DTO_PHASE                                         0x170f
1170#define SEA_mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE                               0x170f
1171#define SEA_mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE                               0x1723
1172#define SEA_mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE                               0x1737
1173#define SEA_mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE                               0x174b
1174#define SEA_mmDENTIST_DISPCLK_CNTL                                                  0x124
1175#define SEA_mmDCDEBUG_BUS_CLK1_SEL                                                  0x1860
1176#define SEA_mmDCDEBUG_BUS_CLK2_SEL                                                  0x1861
1177#define SEA_mmDCDEBUG_BUS_CLK3_SEL                                                  0x1862
1178#define SEA_mmDCDEBUG_BUS_CLK4_SEL                                                  0x1863
1179#define SEA_mmDCDEBUG_OUT_PIN_OVERRIDE                                              0x186a
1180#define SEA_mmDCDEBUG_OUT_CNTL                                                      0x186b
1181#define SEA_mmDCDEBUG_OUT_DATA                                                      0x186e
1182#define SEA_mmDMIF_ADDR_CONFIG                                                      0x2f5
1183#define SEA_mmDMIF_CONTROL                                                          0x2f6
1184#define SEA_mmDMIF_STATUS                                                           0x2f7
1185#define SEA_mmDMIF_HW_DEBUG                                                         0x2f8
1186#define SEA_mmDMIF_ARBITRATION_CONTROL                                              0x2f9
1187#define SEA_mmPIPE0_ARBITRATION_CONTROL3                                            0x2fa
1188#define SEA_mmPIPE1_ARBITRATION_CONTROL3                                            0x2fb
1189#define SEA_mmPIPE2_ARBITRATION_CONTROL3                                            0x2fc
1190#define SEA_mmPIPE3_ARBITRATION_CONTROL3                                            0x2fd
1191#define SEA_mmPIPE4_ARBITRATION_CONTROL3                                            0x2fe
1192#define SEA_mmPIPE5_ARBITRATION_CONTROL3                                            0x2ff
1193#define SEA_mmDMIF_TEST_DEBUG_INDEX                                                 0x312
1194#define SEA_mmDMIF_TEST_DEBUG_DATA                                                  0x313
1195#define SEA_ixDMIF_DEBUG02_CORE0                                                    0x2
1196#define SEA_ixDMIF_DEBUG02_CORE1                                                    0xa
1197#define SEA_mmDMIF_ADDR_CALC                                                        0x300
1198#define SEA_mmDMIF_STATUS2                                                          0x301
1199#define SEA_mmPIPE0_MAX_REQUESTS                                                    0x302
1200#define SEA_mmPIPE1_MAX_REQUESTS                                                    0x303
1201#define SEA_mmPIPE2_MAX_REQUESTS                                                    0x304
1202#define SEA_mmPIPE3_MAX_REQUESTS                                                    0x305
1203#define SEA_mmPIPE4_MAX_REQUESTS                                                    0x306
1204#define SEA_mmPIPE5_MAX_REQUESTS                                                    0x307
1205#define SEA_mmLOW_POWER_TILING_CONTROL                                              0x325
1206#define SEA_mmMCIF_CONTROL                                                          0x314
1207#define SEA_mmMCIF_WRITE_COMBINE_CONTROL                                            0x315
1208#define SEA_mmMCIF_TEST_DEBUG_INDEX                                                 0x316
1209#define SEA_mmMCIF_TEST_DEBUG_DATA                                                  0x317
1210#define SEA_ixIDDCCIF02_DBG_DCCIF_C                                                 0x9
1211#define SEA_ixIDDCCIF04_DBG_DCCIF_E                                                 0xb
1212#define SEA_ixIDDCCIF05_DBG_DCCIF_F                                                 0xc
1213#define SEA_mmMCIF_VMID                                                             0x318
1214#define SEA_mmMCIF_MEM_CONTROL                                                      0x319
1215#define SEA_mmCC_DC_PIPE_DIS                                                        0x177f
1216#define SEA_mmMC_DC_INTERFACE_NACK_STATUS                                           0x31c
1217#define SEA_mmDC_RBBMIF_RDWR_CNTL1                                                  0x31a
1218#define SEA_mmDC_RBBMIF_RDWR_CNTL2                                                  0x31d
1219#define SEA_mmDC_RBBMIF_RDWR_CNTL3                                                  0x311
1220#define SEA_mmDCI_MEM_PWR_STATE                                                     0x31b
1221#define SEA_mmDCI_MEM_PWR_STATE2                                                    0x322
1222#define SEA_mmDCI_CLK_CNTL                                                          0x31e
1223#define SEA_mmDCCG_VPCLK_CNTL                                                       0x31f
1224#define SEA_mmDCI_MEM_PWR_CNTL                                                      0x326
1225#define SEA_mmDC_XDMA_INTERFACE_CNTL                                                0x327
1226#define SEA_mmDCI_TEST_DEBUG_INDEX                                                  0x320
1227#define SEA_mmDCI_TEST_DEBUG_DATA                                                   0x321
1228#define SEA_mmDCI_DEBUG_CONFIG                                                      0x323
1229#define SEA_mmPIPE0_DMIF_BUFFER_CONTROL                                             0x328
1230#define SEA_mmPIPE1_DMIF_BUFFER_CONTROL                                             0x330
1231#define SEA_mmPIPE2_DMIF_BUFFER_CONTROL                                             0x338
1232#define SEA_mmPIPE3_DMIF_BUFFER_CONTROL                                             0x340
1233#define SEA_mmPIPE4_DMIF_BUFFER_CONTROL                                             0x348
1234#define SEA_mmPIPE5_DMIF_BUFFER_CONTROL                                             0x350
1235#define SEA_mmMCIF_BUFMGR_SW_CONTROL                                                0x358
1236#define SEA_mmMCIF_BUFMGR_STATUS                                                    0x35a
1237#define SEA_mmMCIF_BUF_PITCH                                                        0x35b
1238#define SEA_mmMCIF_BUF_1_ADDR_Y_LOW                                                 0x35c
1239#define SEA_mmMCIF_BUF_2_ADDR_Y_LOW                                                 0x360
1240#define SEA_mmMCIF_BUF_3_ADDR_Y_LOW                                                 0x364
1241#define SEA_mmMCIF_BUF_4_ADDR_Y_LOW                                                 0x368
1242#define SEA_mmMCIF_BUF_1_ADDR_UP                                                    0x35d
1243#define SEA_mmMCIF_BUF_2_ADDR_UP                                                    0x361
1244#define SEA_mmMCIF_BUF_3_ADDR_UP                                                    0x365
1245#define SEA_mmMCIF_BUF_4_ADDR_UP                                                    0x369
1246#define SEA_mmMCIF_BUF_1_ADDR_C_LOW                                                 0x35e
1247#define SEA_mmMCIF_BUF_2_ADDR_C_LOW                                                 0x362
1248#define SEA_mmMCIF_BUF_3_ADDR_C_LOW                                                 0x366
1249#define SEA_mmMCIF_BUF_4_ADDR_C_LOW                                                 0x36a
1250#define SEA_mmMCIF_BUF_1_STATUS                                                     0x35f
1251#define SEA_mmMCIF_BUF_2_STATUS                                                     0x363
1252#define SEA_mmMCIF_BUF_3_STATUS                                                     0x367
1253#define SEA_mmMCIF_BUF_4_STATUS                                                     0x36b
1254#define SEA_mmMCIF_SI_ARBITRATION_CONTROL                                           0x36c
1255#define SEA_mmMCIF_URGENCY_WATERMARK                                                0x36d
1256#define SEA_mmDC_GENERICA                                                           0x1900
1257#define SEA_mmDC_GENERICB                                                           0x1901
1258#define SEA_mmDC_PAD_EXTERN_SIG                                                     0x1902
1259#define SEA_mmDC_REF_CLK_CNTL                                                       0x1903
1260#define SEA_mmDC_GPIO_DEBUG                                                         0x1904
1261#define SEA_mmDCO_MEM_POWER_STATE                                                   0x1906
1262#define SEA_mmDCO_MEM_POWER_STATE_2                                                 0x193a
1263#define SEA_mmDCO_LIGHT_SLEEP_DIS                                                   0x1907
1264#define SEA_mmUNIPHY_IMPCAL_LINKA                                                   0x1908
1265#define SEA_mmUNIPHY_IMPCAL_LINKB                                                   0x1909
1266#define SEA_mmUNIPHY_IMPCAL_PERIOD                                                  0x190a
1267#define SEA_mmAUXP_IMPCAL                                                           0x190b
1268#define SEA_mmAUXN_IMPCAL                                                           0x190c
1269#define SEA_mmDCIO_IMPCAL_CNTL_AB                                                   0x190d
1270#define SEA_mmUNIPHY_IMPCAL_PSW_AB                                                  0x190e
1271#define SEA_mmUNIPHY_IMPCAL_LINKC                                                   0x190f
1272#define SEA_mmUNIPHY_IMPCAL_LINKD                                                   0x1910
1273#define SEA_mmDCIO_IMPCAL_CNTL_CD                                                   0x1911
1274#define SEA_mmUNIPHY_IMPCAL_PSW_CD                                                  0x1912
1275#define SEA_mmUNIPHY_IMPCAL_LINKE                                                   0x1913
1276#define SEA_mmUNIPHY_IMPCAL_LINKF                                                   0x1914
1277#define SEA_mmDCIO_IMPCAL_CNTL_EF                                                   0x1915
1278#define SEA_mmUNIPHY_IMPCAL_PSW_EF                                                  0x1916
1279#define SEA_mmDC_PINSTRAPS                                                          0x1917
1280#define SEA_mmDC_DVODATA_CONFIG                                                     0x1905
1281#define SEA_mmLVTMA_PWRSEQ_CNTL                                                     0x1919
1282#define SEA_mmLVTMA_PWRSEQ_STATE                                                    0x191a
1283#define SEA_mmLVTMA_PWRSEQ_REF_DIV                                                  0x191b
1284#define SEA_mmLVTMA_PWRSEQ_DELAY1                                                   0x191c
1285#define SEA_mmLVTMA_PWRSEQ_DELAY2                                                   0x191d
1286#define SEA_mmBL_PWM_CNTL                                                           0x191e
1287#define SEA_mmBL_PWM_CNTL2                                                          0x191f
1288#define SEA_mmBL_PWM_PERIOD_CNTL                                                    0x1920
1289#define SEA_mmBL_PWM_GRP1_REG_LOCK                                                  0x1921
1290#define SEA_mmDCIO_GSL_GENLK_PAD_CNTL                                               0x1922
1291#define SEA_mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                            0x1923
1292#define SEA_mmDCIO_GSL0_CNTL                                                        0x1924
1293#define SEA_mmDCIO_GSL1_CNTL                                                        0x1925
1294#define SEA_mmDCIO_GSL2_CNTL                                                        0x1926
1295#define SEA_mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                  0x1927
1296#define SEA_mmDC_GPU_TIMER_START_POSITION_P_FLIP                                    0x1928
1297#define SEA_mmDC_GPU_TIMER_READ                                                     0x1929
1298#define SEA_mmDC_GPU_TIMER_READ_CNTL                                                0x192a
1299#define SEA_mmDCO_CLK_CNTL                                                          0x192b
1300#define SEA_mmDCO_CLK_RAMP_CNTL                                                     0x192c
1301#define SEA_mmDCIO_DEBUG                                                            0x192e
1302#define SEA_mmDCO_DCFE_EXT_VSYNC_CNTL                                               0x1937
1303#define SEA_mmDCIO_TEST_DEBUG_INDEX                                                 0x192f
1304#define SEA_mmDCIO_TEST_DEBUG_DATA                                                  0x1930
1305#define SEA_ixDCIO_DEBUG1                                                           0x1
1306#define SEA_ixDCIO_DEBUG2                                                           0x2
1307#define SEA_ixDCIO_DEBUG3                                                           0x3
1308#define SEA_ixDCIO_DEBUG4                                                           0x4
1309#define SEA_ixDCIO_DEBUG5                                                           0x5
1310#define SEA_ixDCIO_DEBUG6                                                           0x6
1311#define SEA_ixDCIO_DEBUG7                                                           0x7
1312#define SEA_ixDCIO_DEBUG8                                                           0x8
1313#define SEA_ixDCIO_DEBUG9                                                           0x9
1314#define SEA_ixDCIO_DEBUGA                                                           0xa
1315#define SEA_ixDCIO_DEBUGB                                                           0xb
1316#define SEA_ixDCIO_DEBUGC                                                           0xc
1317#define SEA_ixDCIO_DEBUGD                                                           0xd
1318#define SEA_ixDCIO_DEBUGE                                                           0xe
1319#define SEA_ixDCIO_DEBUGF                                                           0xf
1320#define SEA_ixDCIO_DEBUG10                                                          0x10
1321#define SEA_ixDCIO_DEBUG11                                                          0x11
1322#define SEA_ixDCIO_DEBUG12                                                          0x12
1323#define SEA_ixDCIO_DEBUG13                                                          0x13
1324#define SEA_ixDCIO_DEBUG14                                                          0x14
1325#define SEA_ixDCIO_DEBUG15                                                          0x15
1326#define SEA_ixDCIO_DEBUG_ID                                                         0x0
1327#define SEA_mmDC_GPIO_GENERIC_MASK                                                  0x1944
1328#define SEA_mmDC_GPIO_GENERIC_A                                                     0x1945
1329#define SEA_mmDC_GPIO_GENERIC_EN                                                    0x1946
1330#define SEA_mmDC_GPIO_GENERIC_Y                                                     0x1947
1331#define SEA_mmDC_GPIO_DVODATA_MASK                                                  0x1948
1332#define SEA_mmDC_GPIO_DVODATA_A                                                     0x1949
1333#define SEA_mmDC_GPIO_DVODATA_EN                                                    0x194a
1334#define SEA_mmDC_GPIO_DVODATA_Y                                                     0x194b
1335#define SEA_mmDC_GPIO_DDC1_MASK                                                     0x194c
1336#define SEA_mmDC_GPIO_DDC1_A                                                        0x194d
1337#define SEA_mmDC_GPIO_DDC1_EN                                                       0x194e
1338#define SEA_mmDC_GPIO_DDC1_Y                                                        0x194f
1339#define SEA_mmDC_GPIO_DDC2_MASK                                                     0x1950
1340#define SEA_mmDC_GPIO_DDC2_A                                                        0x1951
1341#define SEA_mmDC_GPIO_DDC2_EN                                                       0x1952
1342#define SEA_mmDC_GPIO_DDC2_Y                                                        0x1953
1343#define SEA_mmDC_GPIO_DDC3_MASK                                                     0x1954
1344#define SEA_mmDC_GPIO_DDC3_A                                                        0x1955
1345#define SEA_mmDC_GPIO_DDC3_EN                                                       0x1956
1346#define SEA_mmDC_GPIO_DDC3_Y                                                        0x1957
1347#define SEA_mmDC_GPIO_DDC4_MASK                                                     0x1958
1348#define SEA_mmDC_GPIO_DDC4_A                                                        0x1959
1349#define SEA_mmDC_GPIO_DDC4_EN                                                       0x195a
1350#define SEA_mmDC_GPIO_DDC4_Y                                                        0x195b
1351#define SEA_mmDC_GPIO_DDC5_MASK                                                     0x195c
1352#define SEA_mmDC_GPIO_DDC5_A                                                        0x195d
1353#define SEA_mmDC_GPIO_DDC5_EN                                                       0x195e
1354#define SEA_mmDC_GPIO_DDC5_Y                                                        0x195f
1355#define SEA_mmDC_GPIO_DDC6_MASK                                                     0x1960
1356#define SEA_mmDC_GPIO_DDC6_A                                                        0x1961
1357#define SEA_mmDC_GPIO_DDC6_EN                                                       0x1962
1358#define SEA_mmDC_GPIO_DDC6_Y                                                        0x1963
1359#define SEA_mmDC_GPIO_DDCVGA_MASK                                                   0x1970
1360#define SEA_mmDC_GPIO_DDCVGA_A                                                      0x1971
1361#define SEA_mmDC_GPIO_DDCVGA_EN                                                     0x1972
1362#define SEA_mmDC_GPIO_DDCVGA_Y                                                      0x1973
1363#define SEA_mmDC_GPIO_SYNCA_MASK                                                    0x1964
1364#define SEA_mmDC_GPIO_SYNCA_A                                                       0x1965
1365#define SEA_mmDC_GPIO_SYNCA_EN                                                      0x1966
1366#define SEA_mmDC_GPIO_SYNCA_Y                                                       0x1967
1367#define SEA_mmDC_GPIO_GENLK_MASK                                                    0x1968
1368#define SEA_mmDC_GPIO_GENLK_A                                                       0x1969
1369#define SEA_mmDC_GPIO_GENLK_EN                                                      0x196a
1370#define SEA_mmDC_GPIO_GENLK_Y                                                       0x196b
1371#define SEA_mmDC_GPIO_HPD_MASK                                                      0x196c
1372#define SEA_mmDC_GPIO_HPD_A                                                         0x196d
1373#define SEA_mmDC_GPIO_HPD_EN                                                        0x196e
1374#define SEA_mmDC_GPIO_HPD_Y                                                         0x196f
1375#define SEA_mmDC_GPIO_PWRSEQ_MASK                                                   0x1940
1376#define SEA_mmDC_GPIO_PWRSEQ_A                                                      0x1941
1377#define SEA_mmDC_GPIO_PWRSEQ_EN                                                     0x1942
1378#define SEA_mmDC_GPIO_PWRSEQ_Y                                                      0x1943
1379#define SEA_mmDC_GPIO_PAD_STRENGTH_1                                                0x1978
1380#define SEA_mmDC_GPIO_PAD_STRENGTH_2                                                0x1979
1381#define SEA_mmPHY_AUX_CNTL                                                          0x197f
1382#define SEA_mmDC_GPIO_I2CPAD_A                                                      0x1975
1383#define SEA_mmDC_GPIO_I2CPAD_EN                                                     0x1976
1384#define SEA_mmDC_GPIO_I2CPAD_Y                                                      0x1977
1385#define SEA_mmDC_GPIO_I2CPAD_STRENGTH                                               0x197a
1386#define SEA_mmDVO_STRENGTH_CONTROL                                                  0x197b
1387#define SEA_mmDVO_VREF_CONTROL                                                      0x197c
1388#define SEA_mmDVO_SKEW_ADJUST                                                       0x197d
1389#define SEA_mmUNIPHYAB_TPG_CONTROL                                                  0x1931
1390#define SEA_mmUNIPHYAB_TPG_SEED                                                     0x1932
1391#define SEA_mmUNIPHYCD_TPG_CONTROL                                                  0x1933
1392#define SEA_mmUNIPHYCD_TPG_SEED                                                     0x1934
1393#define SEA_mmUNIPHYEF_TPG_CONTROL                                                  0x1935
1394#define SEA_mmUNIPHYEF_TPG_SEED                                                     0x1936
1395#define SEA_mmUNIPHYGH_TPG_CONTROL                                                  0x1938
1396#define SEA_mmUNIPHYGH_TPG_SEED                                                     0x1939
1397#define SEA_mmDC_GPIO_I2S_SPDIF_MASK                                                0x193c
1398#define SEA_mmDC_GPIO_I2S_SPDIF_A                                                   0x193d
1399#define SEA_mmDC_GPIO_I2S_SPDIF_EN                                                  0x193e
1400#define SEA_mmDC_GPIO_I2S_SPDIF_Y                                                   0x193f
1401#define SEA_mmDC_GPIO_I2S_SPDIF_STRENGTH                                            0x193b
1402#define SEA_mmDAC_MACRO_CNTL_RESERVED0                                              0x19fc
1403#define SEA_mmDAC_MACRO_CNTL_RESERVED1                                              0x19fd
1404#define SEA_mmDAC_MACRO_CNTL_RESERVED2                                              0x19fe
1405#define SEA_mmDAC_MACRO_CNTL_RESERVED3                                              0x19ff
1406#define SEA_mmUNIPHY_TX_CONTROL1                                                    0x1980
1407#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1                                       0x1980
1408#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1                                       0x1990
1409#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1                                       0x19a0
1410#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1                                       0x19b0
1411#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1                                       0x19c0
1412#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1                                       0x19d0
1413#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1                                       0x4df0
1414#define SEA_mmUNIPHY_TX_CONTROL2                                                    0x1981
1415#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2                                       0x1981
1416#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2                                       0x1991
1417#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2                                       0x19a1
1418#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2                                       0x19b1
1419#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2                                       0x19c1
1420#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2                                       0x19d1
1421#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2                                       0x4df1
1422#define SEA_mmUNIPHY_TX_CONTROL3                                                    0x1982
1423#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3                                       0x1982
1424#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3                                       0x1992
1425#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3                                       0x19a2
1426#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3                                       0x19b2
1427#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3                                       0x19c2
1428#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3                                       0x19d2
1429#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3                                       0x4df2
1430#define SEA_mmUNIPHY_TX_CONTROL4                                                    0x1983
1431#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4                                       0x1983
1432#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4                                       0x1993
1433#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4                                       0x19a3
1434#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4                                       0x19b3
1435#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4                                       0x19c3
1436#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4                                       0x19d3
1437#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4                                       0x4df3
1438#define SEA_mmUNIPHY_POWER_CONTROL                                                  0x1984
1439#define SEA_mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL                                     0x1984
1440#define SEA_mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL                                     0x1994
1441#define SEA_mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL                                     0x19a4
1442#define SEA_mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL                                     0x19b4
1443#define SEA_mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL                                     0x19c4
1444#define SEA_mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL                                     0x19d4
1445#define SEA_mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL                                     0x4df4
1446#define SEA_mmUNIPHY_PLL_FBDIV                                                      0x1985
1447#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV                                         0x1985
1448#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV                                         0x1995
1449#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV                                         0x19a5
1450#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV                                         0x19b5
1451#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV                                         0x19c5
1452#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV                                         0x19d5
1453#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV                                         0x4df5
1454#define SEA_mmUNIPHY_PLL_CONTROL1                                                   0x1986
1455#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1                                      0x1986
1456#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1                                      0x1996
1457#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1                                      0x19a6
1458#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1                                      0x19b6
1459#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1                                      0x19c6
1460#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1                                      0x19d6
1461#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1                                      0x4df6
1462#define SEA_mmUNIPHY_PLL_CONTROL2                                                   0x1987
1463#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2                                      0x1987
1464#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2                                      0x1997
1465#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2                                      0x19a7
1466#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2                                      0x19b7
1467#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2                                      0x19c7
1468#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2                                      0x19d7
1469#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2                                      0x4df7
1470#define SEA_mmUNIPHY_PLL_SS_STEP_SIZE                                               0x1988
1471#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE                                  0x1988
1472#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE                                  0x1998
1473#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE                                  0x19a8
1474#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE                                  0x19b8
1475#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE                                  0x19c8
1476#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE                                  0x19d8
1477#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE                                  0x4df8
1478#define SEA_mmUNIPHY_PLL_SS_CNTL                                                    0x1989
1479#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL                                       0x1989
1480#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL                                       0x1999
1481#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL                                       0x19a9
1482#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL                                       0x19b9
1483#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL                                       0x19c9
1484#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL                                       0x19d9
1485#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL                                       0x4df9
1486#define SEA_mmUNIPHY_DATA_SYNCHRONIZATION                                           0x198a
1487#define SEA_mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION                              0x198a
1488#define SEA_mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION                              0x199a
1489#define SEA_mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION                              0x19aa
1490#define SEA_mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION                              0x19ba
1491#define SEA_mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION                              0x19ca
1492#define SEA_mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION                              0x19da
1493#define SEA_mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION                              0x4dfa
1494#define SEA_mmUNIPHY_REG_TEST_OUTPUT                                                0x198b
1495#define SEA_mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT                                   0x198b
1496#define SEA_mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT                                   0x199b
1497#define SEA_mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT                                   0x19ab
1498#define SEA_mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT                                   0x19bb
1499#define SEA_mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT                                   0x19cb
1500#define SEA_mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT                                   0x19db
1501#define SEA_mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT                                   0x4dfb
1502#define SEA_mmUNIPHY_ANG_BIST_CNTL                                                  0x198c
1503#define SEA_mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL                                     0x198c
1504#define SEA_mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL                                     0x199c
1505#define SEA_mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL                                     0x19ac
1506#define SEA_mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL                                     0x19bc
1507#define SEA_mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL                                     0x19cc
1508#define SEA_mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL                                     0x19dc
1509#define SEA_mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL                                     0x4dfc
1510#define SEA_mmUNIPHY_LINK_CNTL                                                      0x198d
1511#define SEA_mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL                                         0x198d
1512#define SEA_mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL                                         0x199d
1513#define SEA_mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL                                         0x19ad
1514#define SEA_mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL                                         0x19bd
1515#define SEA_mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL                                         0x19cd
1516#define SEA_mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL                                         0x19dd
1517#define SEA_mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL                                         0x4dfd
1518#define SEA_mmUNIPHY_CHANNEL_XBAR_CNTL                                              0x198e
1519#define SEA_mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL                                 0x198e
1520#define SEA_mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL                                 0x199e
1521#define SEA_mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL                                 0x19ae
1522#define SEA_mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL                                 0x19be
1523#define SEA_mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL                                 0x19ce
1524#define SEA_mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL                                 0x19de
1525#define SEA_mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL                                 0x4dfe
1526#define SEA_mmUNIPHY_REG_TEST_OUTPUT2                                               0x198f
1527#define SEA_mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2                                  0x198f
1528#define SEA_mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2                                  0x199f
1529#define SEA_mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2                                  0x19af
1530#define SEA_mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2                                  0x19bf
1531#define SEA_mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2                                  0x19cf
1532#define SEA_mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2                                  0x19df
1533#define SEA_mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2                                  0x4dff
1534#define SEA_mmGRPH_ENABLE                                                           0x1a00
1535#define SEA_mmDCP0_GRPH_ENABLE                                                      0x1a00
1536#define SEA_mmDCP1_GRPH_ENABLE                                                      0x1d00
1537#define SEA_mmDCP2_GRPH_ENABLE                                                      0x4000
1538#define SEA_mmDCP3_GRPH_ENABLE                                                      0x4300
1539#define SEA_mmDCP4_GRPH_ENABLE                                                      0x4600
1540#define SEA_mmDCP5_GRPH_ENABLE                                                      0x4900
1541#define SEA_mmGRPH_CONTROL                                                          0x1a01
1542#define SEA_mmDCP0_GRPH_CONTROL                                                     0x1a01
1543#define SEA_mmDCP1_GRPH_CONTROL                                                     0x1d01
1544#define SEA_mmDCP2_GRPH_CONTROL                                                     0x4001
1545#define SEA_mmDCP3_GRPH_CONTROL                                                     0x4301
1546#define SEA_mmDCP4_GRPH_CONTROL                                                     0x4601
1547#define SEA_mmDCP5_GRPH_CONTROL                                                     0x4901
1548#define SEA_mmGRPH_LUT_10BIT_BYPASS                                                 0x1a02
1549#define SEA_mmDCP0_GRPH_LUT_10BIT_BYPASS                                            0x1a02
1550#define SEA_mmDCP1_GRPH_LUT_10BIT_BYPASS                                            0x1d02
1551#define SEA_mmDCP2_GRPH_LUT_10BIT_BYPASS                                            0x4002
1552#define SEA_mmDCP3_GRPH_LUT_10BIT_BYPASS                                            0x4302
1553#define SEA_mmDCP4_GRPH_LUT_10BIT_BYPASS                                            0x4602
1554#define SEA_mmDCP5_GRPH_LUT_10BIT_BYPASS                                            0x4902
1555#define SEA_mmGRPH_SWAP_CNTL                                                        0x1a03
1556#define SEA_mmDCP0_GRPH_SWAP_CNTL                                                   0x1a03
1557#define SEA_mmDCP1_GRPH_SWAP_CNTL                                                   0x1d03
1558#define SEA_mmDCP2_GRPH_SWAP_CNTL                                                   0x4003
1559#define SEA_mmDCP3_GRPH_SWAP_CNTL                                                   0x4303
1560#define SEA_mmDCP4_GRPH_SWAP_CNTL                                                   0x4603
1561#define SEA_mmDCP5_GRPH_SWAP_CNTL                                                   0x4903
1562#define SEA_mmGRPH_PRIMARY_SURFACE_ADDRESS                                          0x1a04
1563#define SEA_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1a04
1564#define SEA_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1d04
1565#define SEA_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4004
1566#define SEA_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4304
1567#define SEA_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4604
1568#define SEA_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4904
1569#define SEA_mmGRPH_SECONDARY_SURFACE_ADDRESS                                        0x1a05
1570#define SEA_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1a05
1571#define SEA_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1d05
1572#define SEA_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4005
1573#define SEA_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4305
1574#define SEA_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4605
1575#define SEA_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4905
1576#define SEA_mmGRPH_PITCH                                                            0x1a06
1577#define SEA_mmDCP0_GRPH_PITCH                                                       0x1a06
1578#define SEA_mmDCP1_GRPH_PITCH                                                       0x1d06
1579#define SEA_mmDCP2_GRPH_PITCH                                                       0x4006
1580#define SEA_mmDCP3_GRPH_PITCH                                                       0x4306
1581#define SEA_mmDCP4_GRPH_PITCH                                                       0x4606
1582#define SEA_mmDCP5_GRPH_PITCH                                                       0x4906
1583#define SEA_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                     0x1a07
1584#define SEA_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1a07
1585#define SEA_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1d07
1586#define SEA_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4007
1587#define SEA_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4307
1588#define SEA_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4607
1589#define SEA_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4907
1590#define SEA_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                   0x1a08
1591#define SEA_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1a08
1592#define SEA_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1d08
1593#define SEA_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4008
1594#define SEA_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4308
1595#define SEA_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4608
1596#define SEA_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4908
1597#define SEA_mmGRPH_SURFACE_OFFSET_X                                                 0x1a09
1598#define SEA_mmDCP0_GRPH_SURFACE_OFFSET_X                                            0x1a09
1599#define SEA_mmDCP1_GRPH_SURFACE_OFFSET_X                                            0x1d09
1600#define SEA_mmDCP2_GRPH_SURFACE_OFFSET_X                                            0x4009
1601#define SEA_mmDCP3_GRPH_SURFACE_OFFSET_X                                            0x4309
1602#define SEA_mmDCP4_GRPH_SURFACE_OFFSET_X                                            0x4609
1603#define SEA_mmDCP5_GRPH_SURFACE_OFFSET_X                                            0x4909
1604#define SEA_mmGRPH_SURFACE_OFFSET_Y                                                 0x1a0a
1605#define SEA_mmDCP0_GRPH_SURFACE_OFFSET_Y                                            0x1a0a
1606#define SEA_mmDCP1_GRPH_SURFACE_OFFSET_Y                                            0x1d0a
1607#define SEA_mmDCP2_GRPH_SURFACE_OFFSET_Y                                            0x400a
1608#define SEA_mmDCP3_GRPH_SURFACE_OFFSET_Y                                            0x430a
1609#define SEA_mmDCP4_GRPH_SURFACE_OFFSET_Y                                            0x460a
1610#define SEA_mmDCP5_GRPH_SURFACE_OFFSET_Y                                            0x490a
1611#define SEA_mmGRPH_X_START                                                          0x1a0b
1612#define SEA_mmDCP0_GRPH_X_START                                                     0x1a0b
1613#define SEA_mmDCP1_GRPH_X_START                                                     0x1d0b
1614#define SEA_mmDCP2_GRPH_X_START                                                     0x400b
1615#define SEA_mmDCP3_GRPH_X_START                                                     0x430b
1616#define SEA_mmDCP4_GRPH_X_START                                                     0x460b
1617#define SEA_mmDCP5_GRPH_X_START                                                     0x490b
1618#define SEA_mmGRPH_Y_START                                                          0x1a0c
1619#define SEA_mmDCP0_GRPH_Y_START                                                     0x1a0c
1620#define SEA_mmDCP1_GRPH_Y_START                                                     0x1d0c
1621#define SEA_mmDCP2_GRPH_Y_START                                                     0x400c
1622#define SEA_mmDCP3_GRPH_Y_START                                                     0x430c
1623#define SEA_mmDCP4_GRPH_Y_START                                                     0x460c
1624#define SEA_mmDCP5_GRPH_Y_START                                                     0x490c
1625#define SEA_mmGRPH_X_END                                                            0x1a0d
1626#define SEA_mmDCP0_GRPH_X_END                                                       0x1a0d
1627#define SEA_mmDCP1_GRPH_X_END                                                       0x1d0d
1628#define SEA_mmDCP2_GRPH_X_END                                                       0x400d
1629#define SEA_mmDCP3_GRPH_X_END                                                       0x430d
1630#define SEA_mmDCP4_GRPH_X_END                                                       0x460d
1631#define SEA_mmDCP5_GRPH_X_END                                                       0x490d
1632#define SEA_mmGRPH_Y_END                                                            0x1a0e
1633#define SEA_mmDCP0_GRPH_Y_END                                                       0x1a0e
1634#define SEA_mmDCP1_GRPH_Y_END                                                       0x1d0e
1635#define SEA_mmDCP2_GRPH_Y_END                                                       0x400e
1636#define SEA_mmDCP3_GRPH_Y_END                                                       0x430e
1637#define SEA_mmDCP4_GRPH_Y_END                                                       0x460e
1638#define SEA_mmDCP5_GRPH_Y_END                                                       0x490e
1639#define SEA_mmINPUT_GAMMA_CONTROL                                                   0x1a10
1640#define SEA_mmDCP0_INPUT_GAMMA_CONTROL                                              0x1a10
1641#define SEA_mmDCP1_INPUT_GAMMA_CONTROL                                              0x1d10
1642#define SEA_mmDCP2_INPUT_GAMMA_CONTROL                                              0x4010
1643#define SEA_mmDCP3_INPUT_GAMMA_CONTROL                                              0x4310
1644#define SEA_mmDCP4_INPUT_GAMMA_CONTROL                                              0x4610
1645#define SEA_mmDCP5_INPUT_GAMMA_CONTROL                                              0x4910
1646#define SEA_mmGRPH_UPDATE                                                           0x1a11
1647#define SEA_mmDCP0_GRPH_UPDATE                                                      0x1a11
1648#define SEA_mmDCP1_GRPH_UPDATE                                                      0x1d11
1649#define SEA_mmDCP2_GRPH_UPDATE                                                      0x4011
1650#define SEA_mmDCP3_GRPH_UPDATE                                                      0x4311
1651#define SEA_mmDCP4_GRPH_UPDATE                                                      0x4611
1652#define SEA_mmDCP5_GRPH_UPDATE                                                      0x4911
1653#define SEA_mmGRPH_FLIP_CONTROL                                                     0x1a12
1654#define SEA_mmDCP0_GRPH_FLIP_CONTROL                                                0x1a12
1655#define SEA_mmDCP1_GRPH_FLIP_CONTROL                                                0x1d12
1656#define SEA_mmDCP2_GRPH_FLIP_CONTROL                                                0x4012
1657#define SEA_mmDCP3_GRPH_FLIP_CONTROL                                                0x4312
1658#define SEA_mmDCP4_GRPH_FLIP_CONTROL                                                0x4612
1659#define SEA_mmDCP5_GRPH_FLIP_CONTROL                                                0x4912
1660#define SEA_mmGRPH_SURFACE_ADDRESS_INUSE                                            0x1a13
1661#define SEA_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE                                       0x1a13
1662#define SEA_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE                                       0x1d13
1663#define SEA_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE                                       0x4013
1664#define SEA_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE                                       0x4313
1665#define SEA_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE                                       0x4613
1666#define SEA_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE                                       0x4913
1667#define SEA_mmGRPH_DFQ_CONTROL                                                      0x1a14
1668#define SEA_mmDCP0_GRPH_DFQ_CONTROL                                                 0x1a14
1669#define SEA_mmDCP1_GRPH_DFQ_CONTROL                                                 0x1d14
1670#define SEA_mmDCP2_GRPH_DFQ_CONTROL                                                 0x4014
1671#define SEA_mmDCP3_GRPH_DFQ_CONTROL                                                 0x4314
1672#define SEA_mmDCP4_GRPH_DFQ_CONTROL                                                 0x4614
1673#define SEA_mmDCP5_GRPH_DFQ_CONTROL                                                 0x4914
1674#define SEA_mmGRPH_DFQ_STATUS                                                       0x1a15
1675#define SEA_mmDCP0_GRPH_DFQ_STATUS                                                  0x1a15
1676#define SEA_mmDCP1_GRPH_DFQ_STATUS                                                  0x1d15
1677#define SEA_mmDCP2_GRPH_DFQ_STATUS                                                  0x4015
1678#define SEA_mmDCP3_GRPH_DFQ_STATUS                                                  0x4315
1679#define SEA_mmDCP4_GRPH_DFQ_STATUS                                                  0x4615
1680#define SEA_mmDCP5_GRPH_DFQ_STATUS                                                  0x4915
1681#define SEA_mmGRPH_INTERRUPT_STATUS                                                 0x1a16
1682#define SEA_mmDCP0_GRPH_INTERRUPT_STATUS                                            0x1a16
1683#define SEA_mmDCP1_GRPH_INTERRUPT_STATUS                                            0x1d16
1684#define SEA_mmDCP2_GRPH_INTERRUPT_STATUS                                            0x4016
1685#define SEA_mmDCP3_GRPH_INTERRUPT_STATUS                                            0x4316
1686#define SEA_mmDCP4_GRPH_INTERRUPT_STATUS                                            0x4616
1687#define SEA_mmDCP5_GRPH_INTERRUPT_STATUS                                            0x4916
1688#define SEA_mmGRPH_INTERRUPT_CONTROL                                                0x1a17
1689#define SEA_mmDCP0_GRPH_INTERRUPT_CONTROL                                           0x1a17
1690#define SEA_mmDCP1_GRPH_INTERRUPT_CONTROL                                           0x1d17
1691#define SEA_mmDCP2_GRPH_INTERRUPT_CONTROL                                           0x4017
1692#define SEA_mmDCP3_GRPH_INTERRUPT_CONTROL                                           0x4317
1693#define SEA_mmDCP4_GRPH_INTERRUPT_CONTROL                                           0x4617
1694#define SEA_mmDCP5_GRPH_INTERRUPT_CONTROL                                           0x4917
1695#define SEA_mmGRPH_SURFACE_ADDRESS_HIGH_INUSE                                       0x1a18
1696#define SEA_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1a18
1697#define SEA_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1d18
1698#define SEA_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4018
1699#define SEA_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4318
1700#define SEA_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4618
1701#define SEA_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4918
1702#define SEA_mmGRPH_COMPRESS_SURFACE_ADDRESS                                         0x1a19
1703#define SEA_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1a19
1704#define SEA_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1d19
1705#define SEA_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4019
1706#define SEA_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4319
1707#define SEA_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4619
1708#define SEA_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4919
1709#define SEA_mmGRPH_COMPRESS_PITCH                                                   0x1a1a
1710#define SEA_mmDCP0_GRPH_COMPRESS_PITCH                                              0x1a1a
1711#define SEA_mmDCP1_GRPH_COMPRESS_PITCH                                              0x1d1a
1712#define SEA_mmDCP2_GRPH_COMPRESS_PITCH                                              0x401a
1713#define SEA_mmDCP3_GRPH_COMPRESS_PITCH                                              0x431a
1714#define SEA_mmDCP4_GRPH_COMPRESS_PITCH                                              0x461a
1715#define SEA_mmDCP5_GRPH_COMPRESS_PITCH                                              0x491a
1716#define SEA_mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                    0x1a1b
1717#define SEA_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1a1b
1718#define SEA_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1d1b
1719#define SEA_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x401b
1720#define SEA_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x431b
1721#define SEA_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x461b
1722#define SEA_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x491b
1723#define SEA_mmOVL_ENABLE                                                            0x1a1c
1724#define SEA_mmDCP0_OVL_ENABLE                                                       0x1a1c
1725#define SEA_mmDCP1_OVL_ENABLE                                                       0x1d1c
1726#define SEA_mmDCP2_OVL_ENABLE                                                       0x401c
1727#define SEA_mmDCP3_OVL_ENABLE                                                       0x431c
1728#define SEA_mmDCP4_OVL_ENABLE                                                       0x461c
1729#define SEA_mmDCP5_OVL_ENABLE                                                       0x491c
1730#define SEA_mmOVL_CONTROL1                                                          0x1a1d
1731#define SEA_mmDCP0_OVL_CONTROL1                                                     0x1a1d
1732#define SEA_mmDCP1_OVL_CONTROL1                                                     0x1d1d
1733#define SEA_mmDCP2_OVL_CONTROL1                                                     0x401d
1734#define SEA_mmDCP3_OVL_CONTROL1                                                     0x431d
1735#define SEA_mmDCP4_OVL_CONTROL1                                                     0x461d
1736#define SEA_mmDCP5_OVL_CONTROL1                                                     0x491d
1737#define SEA_mmOVL_CONTROL2                                                          0x1a1e
1738#define SEA_mmDCP0_OVL_CONTROL2                                                     0x1a1e
1739#define SEA_mmDCP1_OVL_CONTROL2                                                     0x1d1e
1740#define SEA_mmDCP2_OVL_CONTROL2                                                     0x401e
1741#define SEA_mmDCP3_OVL_CONTROL2                                                     0x431e
1742#define SEA_mmDCP4_OVL_CONTROL2                                                     0x461e
1743#define SEA_mmDCP5_OVL_CONTROL2                                                     0x491e
1744#define SEA_mmOVL_SWAP_CNTL                                                         0x1a1f
1745#define SEA_mmDCP0_OVL_SWAP_CNTL                                                    0x1a1f
1746#define SEA_mmDCP1_OVL_SWAP_CNTL                                                    0x1d1f
1747#define SEA_mmDCP2_OVL_SWAP_CNTL                                                    0x401f
1748#define SEA_mmDCP3_OVL_SWAP_CNTL                                                    0x431f
1749#define SEA_mmDCP4_OVL_SWAP_CNTL                                                    0x461f
1750#define SEA_mmDCP5_OVL_SWAP_CNTL                                                    0x491f
1751#define SEA_mmOVL_SURFACE_ADDRESS                                                   0x1a20
1752#define SEA_mmDCP0_OVL_SURFACE_ADDRESS                                              0x1a20
1753#define SEA_mmDCP1_OVL_SURFACE_ADDRESS                                              0x1d20
1754#define SEA_mmDCP2_OVL_SURFACE_ADDRESS                                              0x4020
1755#define SEA_mmDCP3_OVL_SURFACE_ADDRESS                                              0x4320
1756#define SEA_mmDCP4_OVL_SURFACE_ADDRESS                                              0x4620
1757#define SEA_mmDCP5_OVL_SURFACE_ADDRESS                                              0x4920
1758#define SEA_mmOVL_PITCH                                                             0x1a21
1759#define SEA_mmDCP0_OVL_PITCH                                                        0x1a21
1760#define SEA_mmDCP1_OVL_PITCH                                                        0x1d21
1761#define SEA_mmDCP2_OVL_PITCH                                                        0x4021
1762#define SEA_mmDCP3_OVL_PITCH                                                        0x4321
1763#define SEA_mmDCP4_OVL_PITCH                                                        0x4621
1764#define SEA_mmDCP5_OVL_PITCH                                                        0x4921
1765#define SEA_mmOVL_SURFACE_ADDRESS_HIGH                                              0x1a22
1766#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_HIGH                                         0x1a22
1767#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_HIGH                                         0x1d22
1768#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_HIGH                                         0x4022
1769#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_HIGH                                         0x4322
1770#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_HIGH                                         0x4622
1771#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_HIGH                                         0x4922
1772#define SEA_mmOVL_SURFACE_OFFSET_X                                                  0x1a23
1773#define SEA_mmDCP0_OVL_SURFACE_OFFSET_X                                             0x1a23
1774#define SEA_mmDCP1_OVL_SURFACE_OFFSET_X                                             0x1d23
1775#define SEA_mmDCP2_OVL_SURFACE_OFFSET_X                                             0x4023
1776#define SEA_mmDCP3_OVL_SURFACE_OFFSET_X                                             0x4323
1777#define SEA_mmDCP4_OVL_SURFACE_OFFSET_X                                             0x4623
1778#define SEA_mmDCP5_OVL_SURFACE_OFFSET_X                                             0x4923
1779#define SEA_mmOVL_SURFACE_OFFSET_Y                                                  0x1a24
1780#define SEA_mmDCP0_OVL_SURFACE_OFFSET_Y                                             0x1a24
1781#define SEA_mmDCP1_OVL_SURFACE_OFFSET_Y                                             0x1d24
1782#define SEA_mmDCP2_OVL_SURFACE_OFFSET_Y                                             0x4024
1783#define SEA_mmDCP3_OVL_SURFACE_OFFSET_Y                                             0x4324
1784#define SEA_mmDCP4_OVL_SURFACE_OFFSET_Y                                             0x4624
1785#define SEA_mmDCP5_OVL_SURFACE_OFFSET_Y                                             0x4924
1786#define SEA_mmOVL_START                                                             0x1a25
1787#define SEA_mmDCP0_OVL_START                                                        0x1a25
1788#define SEA_mmDCP1_OVL_START                                                        0x1d25
1789#define SEA_mmDCP2_OVL_START                                                        0x4025
1790#define SEA_mmDCP3_OVL_START                                                        0x4325
1791#define SEA_mmDCP4_OVL_START                                                        0x4625
1792#define SEA_mmDCP5_OVL_START                                                        0x4925
1793#define SEA_mmOVL_END                                                               0x1a26
1794#define SEA_mmDCP0_OVL_END                                                          0x1a26
1795#define SEA_mmDCP1_OVL_END                                                          0x1d26
1796#define SEA_mmDCP2_OVL_END                                                          0x4026
1797#define SEA_mmDCP3_OVL_END                                                          0x4326
1798#define SEA_mmDCP4_OVL_END                                                          0x4626
1799#define SEA_mmDCP5_OVL_END                                                          0x4926
1800#define SEA_mmOVL_UPDATE                                                            0x1a27
1801#define SEA_mmDCP0_OVL_UPDATE                                                       0x1a27
1802#define SEA_mmDCP1_OVL_UPDATE                                                       0x1d27
1803#define SEA_mmDCP2_OVL_UPDATE                                                       0x4027
1804#define SEA_mmDCP3_OVL_UPDATE                                                       0x4327
1805#define SEA_mmDCP4_OVL_UPDATE                                                       0x4627
1806#define SEA_mmDCP5_OVL_UPDATE                                                       0x4927
1807#define SEA_mmOVL_SURFACE_ADDRESS_INUSE                                             0x1a28
1808#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_INUSE                                        0x1a28
1809#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_INUSE                                        0x1d28
1810#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_INUSE                                        0x4028
1811#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_INUSE                                        0x4328
1812#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_INUSE                                        0x4628
1813#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_INUSE                                        0x4928
1814#define SEA_mmOVL_DFQ_CONTROL                                                       0x1a29
1815#define SEA_mmDCP0_OVL_DFQ_CONTROL                                                  0x1a29
1816#define SEA_mmDCP1_OVL_DFQ_CONTROL                                                  0x1d29
1817#define SEA_mmDCP2_OVL_DFQ_CONTROL                                                  0x4029
1818#define SEA_mmDCP3_OVL_DFQ_CONTROL                                                  0x4329
1819#define SEA_mmDCP4_OVL_DFQ_CONTROL                                                  0x4629
1820#define SEA_mmDCP5_OVL_DFQ_CONTROL                                                  0x4929
1821#define SEA_mmOVL_DFQ_STATUS                                                        0x1a2a
1822#define SEA_mmDCP0_OVL_DFQ_STATUS                                                   0x1a2a
1823#define SEA_mmDCP1_OVL_DFQ_STATUS                                                   0x1d2a
1824#define SEA_mmDCP2_OVL_DFQ_STATUS                                                   0x402a
1825#define SEA_mmDCP3_OVL_DFQ_STATUS                                                   0x432a
1826#define SEA_mmDCP4_OVL_DFQ_STATUS                                                   0x462a
1827#define SEA_mmDCP5_OVL_DFQ_STATUS                                                   0x492a
1828#define SEA_mmOVL_SURFACE_ADDRESS_HIGH_INUSE                                        0x1a2b
1829#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x1a2b
1830#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x1d2b
1831#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x402b
1832#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x432b
1833#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x462b
1834#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x492b
1835#define SEA_mmOVLSCL_EDGE_PIXEL_CNTL                                                0x1a2c
1836#define SEA_mmDCP0_OVLSCL_EDGE_PIXEL_CNTL                                           0x1a2c
1837#define SEA_mmDCP1_OVLSCL_EDGE_PIXEL_CNTL                                           0x1d2c
1838#define SEA_mmDCP2_OVLSCL_EDGE_PIXEL_CNTL                                           0x402c
1839#define SEA_mmDCP3_OVLSCL_EDGE_PIXEL_CNTL                                           0x432c
1840#define SEA_mmDCP4_OVLSCL_EDGE_PIXEL_CNTL                                           0x462c
1841#define SEA_mmDCP5_OVLSCL_EDGE_PIXEL_CNTL                                           0x492c
1842#define SEA_mmPRESCALE_GRPH_CONTROL                                                 0x1a2d
1843#define SEA_mmDCP0_PRESCALE_GRPH_CONTROL                                            0x1a2d
1844#define SEA_mmDCP1_PRESCALE_GRPH_CONTROL                                            0x1d2d
1845#define SEA_mmDCP2_PRESCALE_GRPH_CONTROL                                            0x402d
1846#define SEA_mmDCP3_PRESCALE_GRPH_CONTROL                                            0x432d
1847#define SEA_mmDCP4_PRESCALE_GRPH_CONTROL                                            0x462d
1848#define SEA_mmDCP5_PRESCALE_GRPH_CONTROL                                            0x492d
1849#define SEA_mmPRESCALE_VALUES_GRPH_R                                                0x1a2e
1850#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_R                                           0x1a2e
1851#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_R                                           0x1d2e
1852#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_R                                           0x402e
1853#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_R                                           0x432e
1854#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_R                                           0x462e
1855#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_R                                           0x492e
1856#define SEA_mmPRESCALE_VALUES_GRPH_G                                                0x1a2f
1857#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_G                                           0x1a2f
1858#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_G                                           0x1d2f
1859#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_G                                           0x402f
1860#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_G                                           0x432f
1861#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_G                                           0x462f
1862#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_G                                           0x492f
1863#define SEA_mmPRESCALE_VALUES_GRPH_B                                                0x1a30
1864#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_B                                           0x1a30
1865#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_B                                           0x1d30
1866#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_B                                           0x4030
1867#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_B                                           0x4330
1868#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_B                                           0x4630
1869#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_B                                           0x4930
1870#define SEA_mmPRESCALE_OVL_CONTROL                                                  0x1a31
1871#define SEA_mmDCP0_PRESCALE_OVL_CONTROL                                             0x1a31
1872#define SEA_mmDCP1_PRESCALE_OVL_CONTROL                                             0x1d31
1873#define SEA_mmDCP2_PRESCALE_OVL_CONTROL                                             0x4031
1874#define SEA_mmDCP3_PRESCALE_OVL_CONTROL                                             0x4331
1875#define SEA_mmDCP4_PRESCALE_OVL_CONTROL                                             0x4631
1876#define SEA_mmDCP5_PRESCALE_OVL_CONTROL                                             0x4931
1877#define SEA_mmPRESCALE_VALUES_OVL_CB                                                0x1a32
1878#define SEA_mmDCP0_PRESCALE_VALUES_OVL_CB                                           0x1a32
1879#define SEA_mmDCP1_PRESCALE_VALUES_OVL_CB                                           0x1d32
1880#define SEA_mmDCP2_PRESCALE_VALUES_OVL_CB                                           0x4032
1881#define SEA_mmDCP3_PRESCALE_VALUES_OVL_CB                                           0x4332
1882#define SEA_mmDCP4_PRESCALE_VALUES_OVL_CB                                           0x4632
1883#define SEA_mmDCP5_PRESCALE_VALUES_OVL_CB                                           0x4932
1884#define SEA_mmPRESCALE_VALUES_OVL_Y                                                 0x1a33
1885#define SEA_mmDCP0_PRESCALE_VALUES_OVL_Y                                            0x1a33
1886#define SEA_mmDCP1_PRESCALE_VALUES_OVL_Y                                            0x1d33
1887#define SEA_mmDCP2_PRESCALE_VALUES_OVL_Y                                            0x4033
1888#define SEA_mmDCP3_PRESCALE_VALUES_OVL_Y                                            0x4333
1889#define SEA_mmDCP4_PRESCALE_VALUES_OVL_Y                                            0x4633
1890#define SEA_mmDCP5_PRESCALE_VALUES_OVL_Y                                            0x4933
1891#define SEA_mmPRESCALE_VALUES_OVL_CR                                                0x1a34
1892#define SEA_mmDCP0_PRESCALE_VALUES_OVL_CR                                           0x1a34
1893#define SEA_mmDCP1_PRESCALE_VALUES_OVL_CR                                           0x1d34
1894#define SEA_mmDCP2_PRESCALE_VALUES_OVL_CR                                           0x4034
1895#define SEA_mmDCP3_PRESCALE_VALUES_OVL_CR                                           0x4334
1896#define SEA_mmDCP4_PRESCALE_VALUES_OVL_CR                                           0x4634
1897#define SEA_mmDCP5_PRESCALE_VALUES_OVL_CR                                           0x4934
1898#define SEA_mmINPUT_CSC_CONTROL                                                     0x1a35
1899#define SEA_mmDCP0_INPUT_CSC_CONTROL                                                0x1a35
1900#define SEA_mmDCP1_INPUT_CSC_CONTROL                                                0x1d35
1901#define SEA_mmDCP2_INPUT_CSC_CONTROL                                                0x4035
1902#define SEA_mmDCP3_INPUT_CSC_CONTROL                                                0x4335
1903#define SEA_mmDCP4_INPUT_CSC_CONTROL                                                0x4635
1904#define SEA_mmDCP5_INPUT_CSC_CONTROL                                                0x4935
1905#define SEA_mmINPUT_CSC_C11_C12                                                     0x1a36
1906#define SEA_mmDCP0_INPUT_CSC_C11_C12                                                0x1a36
1907#define SEA_mmDCP1_INPUT_CSC_C11_C12                                                0x1d36
1908#define SEA_mmDCP2_INPUT_CSC_C11_C12                                                0x4036
1909#define SEA_mmDCP3_INPUT_CSC_C11_C12                                                0x4336
1910#define SEA_mmDCP4_INPUT_CSC_C11_C12                                                0x4636
1911#define SEA_mmDCP5_INPUT_CSC_C11_C12                                                0x4936
1912#define SEA_mmINPUT_CSC_C13_C14                                                     0x1a37
1913#define SEA_mmDCP0_INPUT_CSC_C13_C14                                                0x1a37
1914#define SEA_mmDCP1_INPUT_CSC_C13_C14                                                0x1d37
1915#define SEA_mmDCP2_INPUT_CSC_C13_C14                                                0x4037
1916#define SEA_mmDCP3_INPUT_CSC_C13_C14                                                0x4337
1917#define SEA_mmDCP4_INPUT_CSC_C13_C14                                                0x4637
1918#define SEA_mmDCP5_INPUT_CSC_C13_C14                                                0x4937
1919#define SEA_mmINPUT_CSC_C21_C22                                                     0x1a38
1920#define SEA_mmDCP0_INPUT_CSC_C21_C22                                                0x1a38
1921#define SEA_mmDCP1_INPUT_CSC_C21_C22                                                0x1d38
1922#define SEA_mmDCP2_INPUT_CSC_C21_C22                                                0x4038
1923#define SEA_mmDCP3_INPUT_CSC_C21_C22                                                0x4338
1924#define SEA_mmDCP4_INPUT_CSC_C21_C22                                                0x4638
1925#define SEA_mmDCP5_INPUT_CSC_C21_C22                                                0x4938
1926#define SEA_mmINPUT_CSC_C23_C24                                                     0x1a39
1927#define SEA_mmDCP0_INPUT_CSC_C23_C24                                                0x1a39
1928#define SEA_mmDCP1_INPUT_CSC_C23_C24                                                0x1d39
1929#define SEA_mmDCP2_INPUT_CSC_C23_C24                                                0x4039
1930#define SEA_mmDCP3_INPUT_CSC_C23_C24                                                0x4339
1931#define SEA_mmDCP4_INPUT_CSC_C23_C24                                                0x4639
1932#define SEA_mmDCP5_INPUT_CSC_C23_C24                                                0x4939
1933#define SEA_mmINPUT_CSC_C31_C32                                                     0x1a3a
1934#define SEA_mmDCP0_INPUT_CSC_C31_C32                                                0x1a3a
1935#define SEA_mmDCP1_INPUT_CSC_C31_C32                                                0x1d3a
1936#define SEA_mmDCP2_INPUT_CSC_C31_C32                                                0x403a
1937#define SEA_mmDCP3_INPUT_CSC_C31_C32                                                0x433a
1938#define SEA_mmDCP4_INPUT_CSC_C31_C32                                                0x463a
1939#define SEA_mmDCP5_INPUT_CSC_C31_C32                                                0x493a
1940#define SEA_mmINPUT_CSC_C33_C34                                                     0x1a3b
1941#define SEA_mmDCP0_INPUT_CSC_C33_C34                                                0x1a3b
1942#define SEA_mmDCP1_INPUT_CSC_C33_C34                                                0x1d3b
1943#define SEA_mmDCP2_INPUT_CSC_C33_C34                                                0x403b
1944#define SEA_mmDCP3_INPUT_CSC_C33_C34                                                0x433b
1945#define SEA_mmDCP4_INPUT_CSC_C33_C34                                                0x463b
1946#define SEA_mmDCP5_INPUT_CSC_C33_C34                                                0x493b
1947#define SEA_mmOUTPUT_CSC_CONTROL                                                    0x1a3c
1948#define SEA_mmDCP0_OUTPUT_CSC_CONTROL                                               0x1a3c
1949#define SEA_mmDCP1_OUTPUT_CSC_CONTROL                                               0x1d3c
1950#define SEA_mmDCP2_OUTPUT_CSC_CONTROL                                               0x403c
1951#define SEA_mmDCP3_OUTPUT_CSC_CONTROL                                               0x433c
1952#define SEA_mmDCP4_OUTPUT_CSC_CONTROL                                               0x463c
1953#define SEA_mmDCP5_OUTPUT_CSC_CONTROL                                               0x493c
1954#define SEA_mmOUTPUT_CSC_C11_C12                                                    0x1a3d
1955#define SEA_mmDCP0_OUTPUT_CSC_C11_C12                                               0x1a3d
1956#define SEA_mmDCP1_OUTPUT_CSC_C11_C12                                               0x1d3d
1957#define SEA_mmDCP2_OUTPUT_CSC_C11_C12                                               0x403d
1958#define SEA_mmDCP3_OUTPUT_CSC_C11_C12                                               0x433d
1959#define SEA_mmDCP4_OUTPUT_CSC_C11_C12                                               0x463d
1960#define SEA_mmDCP5_OUTPUT_CSC_C11_C12                                               0x493d
1961#define SEA_mmOUTPUT_CSC_C13_C14                                                    0x1a3e
1962#define SEA_mmDCP0_OUTPUT_CSC_C13_C14                                               0x1a3e
1963#define SEA_mmDCP1_OUTPUT_CSC_C13_C14                                               0x1d3e
1964#define SEA_mmDCP2_OUTPUT_CSC_C13_C14                                               0x403e
1965#define SEA_mmDCP3_OUTPUT_CSC_C13_C14                                               0x433e
1966#define SEA_mmDCP4_OUTPUT_CSC_C13_C14                                               0x463e
1967#define SEA_mmDCP5_OUTPUT_CSC_C13_C14                                               0x493e
1968#define SEA_mmOUTPUT_CSC_C21_C22                                                    0x1a3f
1969#define SEA_mmDCP0_OUTPUT_CSC_C21_C22                                               0x1a3f
1970#define SEA_mmDCP1_OUTPUT_CSC_C21_C22                                               0x1d3f
1971#define SEA_mmDCP2_OUTPUT_CSC_C21_C22                                               0x403f
1972#define SEA_mmDCP3_OUTPUT_CSC_C21_C22                                               0x433f
1973#define SEA_mmDCP4_OUTPUT_CSC_C21_C22                                               0x463f
1974#define SEA_mmDCP5_OUTPUT_CSC_C21_C22                                               0x493f
1975#define SEA_mmOUTPUT_CSC_C23_C24                                                    0x1a40
1976#define SEA_mmDCP0_OUTPUT_CSC_C23_C24                                               0x1a40
1977#define SEA_mmDCP1_OUTPUT_CSC_C23_C24                                               0x1d40
1978#define SEA_mmDCP2_OUTPUT_CSC_C23_C24                                               0x4040
1979#define SEA_mmDCP3_OUTPUT_CSC_C23_C24                                               0x4340
1980#define SEA_mmDCP4_OUTPUT_CSC_C23_C24                                               0x4640
1981#define SEA_mmDCP5_OUTPUT_CSC_C23_C24                                               0x4940
1982#define SEA_mmOUTPUT_CSC_C31_C32                                                    0x1a41
1983#define SEA_mmDCP0_OUTPUT_CSC_C31_C32                                               0x1a41
1984#define SEA_mmDCP1_OUTPUT_CSC_C31_C32                                               0x1d41
1985#define SEA_mmDCP2_OUTPUT_CSC_C31_C32                                               0x4041
1986#define SEA_mmDCP3_OUTPUT_CSC_C31_C32                                               0x4341
1987#define SEA_mmDCP4_OUTPUT_CSC_C31_C32                                               0x4641
1988#define SEA_mmDCP5_OUTPUT_CSC_C31_C32                                               0x4941
1989#define SEA_mmOUTPUT_CSC_C33_C34                                                    0x1a42
1990#define SEA_mmDCP0_OUTPUT_CSC_C33_C34                                               0x1a42
1991#define SEA_mmDCP1_OUTPUT_CSC_C33_C34                                               0x1d42
1992#define SEA_mmDCP2_OUTPUT_CSC_C33_C34                                               0x4042
1993#define SEA_mmDCP3_OUTPUT_CSC_C33_C34                                               0x4342
1994#define SEA_mmDCP4_OUTPUT_CSC_C33_C34                                               0x4642
1995#define SEA_mmDCP5_OUTPUT_CSC_C33_C34                                               0x4942
1996#define SEA_mmCOMM_MATRIXA_TRANS_C11_C12                                            0x1a43
1997#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C11_C12                                       0x1a43
1998#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C11_C12                                       0x1d43
1999#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C11_C12                                       0x4043
2000#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C11_C12                                       0x4343
2001#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C11_C12                                       0x4643
2002#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C11_C12                                       0x4943
2003#define SEA_mmCOMM_MATRIXA_TRANS_C13_C14                                            0x1a44
2004#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C13_C14                                       0x1a44
2005#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C13_C14                                       0x1d44
2006#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C13_C14                                       0x4044
2007#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C13_C14                                       0x4344
2008#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C13_C14                                       0x4644
2009#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C13_C14                                       0x4944
2010#define SEA_mmCOMM_MATRIXA_TRANS_C21_C22                                            0x1a45
2011#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C21_C22                                       0x1a45
2012#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C21_C22                                       0x1d45
2013#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C21_C22                                       0x4045
2014#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C21_C22                                       0x4345
2015#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C21_C22                                       0x4645
2016#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C21_C22                                       0x4945
2017#define SEA_mmCOMM_MATRIXA_TRANS_C23_C24                                            0x1a46
2018#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C23_C24                                       0x1a46
2019#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C23_C24                                       0x1d46
2020#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C23_C24                                       0x4046
2021#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C23_C24                                       0x4346
2022#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C23_C24                                       0x4646
2023#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C23_C24                                       0x4946
2024#define SEA_mmCOMM_MATRIXA_TRANS_C31_C32                                            0x1a47
2025#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C31_C32                                       0x1a47
2026#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C31_C32                                       0x1d47
2027#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C31_C32                                       0x4047
2028#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C31_C32                                       0x4347
2029#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C31_C32                                       0x4647
2030#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C31_C32                                       0x4947
2031#define SEA_mmCOMM_MATRIXA_TRANS_C33_C34                                            0x1a48
2032#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C33_C34                                       0x1a48
2033#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C33_C34                                       0x1d48
2034#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C33_C34                                       0x4048
2035#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C33_C34                                       0x4348
2036#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C33_C34                                       0x4648
2037#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C33_C34                                       0x4948
2038#define SEA_mmCOMM_MATRIXB_TRANS_C11_C12                                            0x1a49
2039#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C11_C12                                       0x1a49
2040#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C11_C12                                       0x1d49
2041#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C11_C12                                       0x4049
2042#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C11_C12                                       0x4349
2043#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C11_C12                                       0x4649
2044#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C11_C12                                       0x4949
2045#define SEA_mmCOMM_MATRIXB_TRANS_C13_C14                                            0x1a4a
2046#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C13_C14                                       0x1a4a
2047#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C13_C14                                       0x1d4a
2048#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C13_C14                                       0x404a
2049#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C13_C14                                       0x434a
2050#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C13_C14                                       0x464a
2051#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C13_C14                                       0x494a
2052#define SEA_mmCOMM_MATRIXB_TRANS_C21_C22                                            0x1a4b
2053#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C21_C22                                       0x1a4b
2054#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C21_C22                                       0x1d4b
2055#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C21_C22                                       0x404b
2056#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C21_C22                                       0x434b
2057#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C21_C22                                       0x464b
2058#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C21_C22                                       0x494b
2059#define SEA_mmCOMM_MATRIXB_TRANS_C23_C24                                            0x1a4c
2060#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C23_C24                                       0x1a4c
2061#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C23_C24                                       0x1d4c
2062#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C23_C24                                       0x404c
2063#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C23_C24                                       0x434c
2064#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C23_C24                                       0x464c
2065#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C23_C24                                       0x494c
2066#define SEA_mmCOMM_MATRIXB_TRANS_C31_C32                                            0x1a4d
2067#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C31_C32                                       0x1a4d
2068#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C31_C32                                       0x1d4d
2069#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C31_C32                                       0x404d
2070#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C31_C32                                       0x434d
2071#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C31_C32                                       0x464d
2072#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C31_C32                                       0x494d
2073#define SEA_mmCOMM_MATRIXB_TRANS_C33_C34                                            0x1a4e
2074#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C33_C34                                       0x1a4e
2075#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C33_C34                                       0x1d4e
2076#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C33_C34                                       0x404e
2077#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C33_C34                                       0x434e
2078#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C33_C34                                       0x464e
2079#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C33_C34                                       0x494e
2080#define SEA_mmDENORM_CONTROL                                                        0x1a50
2081#define SEA_mmDCP0_DENORM_CONTROL                                                   0x1a50
2082#define SEA_mmDCP1_DENORM_CONTROL                                                   0x1d50
2083#define SEA_mmDCP2_DENORM_CONTROL                                                   0x4050
2084#define SEA_mmDCP3_DENORM_CONTROL                                                   0x4350
2085#define SEA_mmDCP4_DENORM_CONTROL                                                   0x4650
2086#define SEA_mmDCP5_DENORM_CONTROL                                                   0x4950
2087#define SEA_mmOUT_ROUND_CONTROL                                                     0x1a51
2088#define SEA_mmDCP0_OUT_ROUND_CONTROL                                                0x1a51
2089#define SEA_mmDCP1_OUT_ROUND_CONTROL                                                0x1d51
2090#define SEA_mmDCP2_OUT_ROUND_CONTROL                                                0x4051
2091#define SEA_mmDCP3_OUT_ROUND_CONTROL                                                0x4351
2092#define SEA_mmDCP4_OUT_ROUND_CONTROL                                                0x4651
2093#define SEA_mmDCP5_OUT_ROUND_CONTROL                                                0x4951
2094#define SEA_mmOUT_CLAMP_CONTROL_R_CR                                                0x1a52
2095#define SEA_mmDCP0_OUT_CLAMP_CONTROL_R_CR                                           0x1a52
2096#define SEA_mmDCP1_OUT_CLAMP_CONTROL_R_CR                                           0x1d52
2097#define SEA_mmDCP2_OUT_CLAMP_CONTROL_R_CR                                           0x4052
2098#define SEA_mmDCP3_OUT_CLAMP_CONTROL_R_CR                                           0x4352
2099#define SEA_mmDCP4_OUT_CLAMP_CONTROL_R_CR                                           0x4652
2100#define SEA_mmDCP5_OUT_CLAMP_CONTROL_R_CR                                           0x4952
2101#define SEA_mmOUT_CLAMP_CONTROL_G_Y                                                 0x1a9c
2102#define SEA_mmDCP0_OUT_CLAMP_CONTROL_G_Y                                            0x1a9c
2103#define SEA_mmDCP1_OUT_CLAMP_CONTROL_G_Y                                            0x1d9c
2104#define SEA_mmDCP2_OUT_CLAMP_CONTROL_G_Y                                            0x409c
2105#define SEA_mmDCP3_OUT_CLAMP_CONTROL_G_Y                                            0x439c
2106#define SEA_mmDCP4_OUT_CLAMP_CONTROL_G_Y                                            0x469c
2107#define SEA_mmDCP5_OUT_CLAMP_CONTROL_G_Y                                            0x499c
2108#define SEA_mmOUT_CLAMP_CONTROL_B_CB                                                0x1a9d
2109#define SEA_mmDCP0_OUT_CLAMP_CONTROL_B_CB                                           0x1a9d
2110#define SEA_mmDCP1_OUT_CLAMP_CONTROL_B_CB                                           0x1d9d
2111#define SEA_mmDCP2_OUT_CLAMP_CONTROL_B_CB                                           0x409d
2112#define SEA_mmDCP3_OUT_CLAMP_CONTROL_B_CB                                           0x439d
2113#define SEA_mmDCP4_OUT_CLAMP_CONTROL_B_CB                                           0x469d
2114#define SEA_mmDCP5_OUT_CLAMP_CONTROL_B_CB                                           0x499d
2115#define SEA_mmKEY_CONTROL                                                           0x1a53
2116#define SEA_mmDCP0_KEY_CONTROL                                                      0x1a53
2117#define SEA_mmDCP1_KEY_CONTROL                                                      0x1d53
2118#define SEA_mmDCP2_KEY_CONTROL                                                      0x4053
2119#define SEA_mmDCP3_KEY_CONTROL                                                      0x4353
2120#define SEA_mmDCP4_KEY_CONTROL                                                      0x4653
2121#define SEA_mmDCP5_KEY_CONTROL                                                      0x4953
2122#define SEA_mmKEY_RANGE_ALPHA                                                       0x1a54
2123#define SEA_mmDCP0_KEY_RANGE_ALPHA                                                  0x1a54
2124#define SEA_mmDCP1_KEY_RANGE_ALPHA                                                  0x1d54
2125#define SEA_mmDCP2_KEY_RANGE_ALPHA                                                  0x4054
2126#define SEA_mmDCP3_KEY_RANGE_ALPHA                                                  0x4354
2127#define SEA_mmDCP4_KEY_RANGE_ALPHA                                                  0x4654
2128#define SEA_mmDCP5_KEY_RANGE_ALPHA                                                  0x4954
2129#define SEA_mmKEY_RANGE_RED                                                         0x1a55
2130#define SEA_mmDCP0_KEY_RANGE_RED                                                    0x1a55
2131#define SEA_mmDCP1_KEY_RANGE_RED                                                    0x1d55
2132#define SEA_mmDCP2_KEY_RANGE_RED                                                    0x4055
2133#define SEA_mmDCP3_KEY_RANGE_RED                                                    0x4355
2134#define SEA_mmDCP4_KEY_RANGE_RED                                                    0x4655
2135#define SEA_mmDCP5_KEY_RANGE_RED                                                    0x4955
2136#define SEA_mmKEY_RANGE_GREEN                                                       0x1a56
2137#define SEA_mmDCP0_KEY_RANGE_GREEN                                                  0x1a56
2138#define SEA_mmDCP1_KEY_RANGE_GREEN                                                  0x1d56
2139#define SEA_mmDCP2_KEY_RANGE_GREEN                                                  0x4056
2140#define SEA_mmDCP3_KEY_RANGE_GREEN                                                  0x4356
2141#define SEA_mmDCP4_KEY_RANGE_GREEN                                                  0x4656
2142#define SEA_mmDCP5_KEY_RANGE_GREEN                                                  0x4956
2143#define SEA_mmKEY_RANGE_BLUE                                                        0x1a57
2144#define SEA_mmDCP0_KEY_RANGE_BLUE                                                   0x1a57
2145#define SEA_mmDCP1_KEY_RANGE_BLUE                                                   0x1d57
2146#define SEA_mmDCP2_KEY_RANGE_BLUE                                                   0x4057
2147#define SEA_mmDCP3_KEY_RANGE_BLUE                                                   0x4357
2148#define SEA_mmDCP4_KEY_RANGE_BLUE                                                   0x4657
2149#define SEA_mmDCP5_KEY_RANGE_BLUE                                                   0x4957
2150#define SEA_mmDEGAMMA_CONTROL                                                       0x1a58
2151#define SEA_mmDCP0_DEGAMMA_CONTROL                                                  0x1a58
2152#define SEA_mmDCP1_DEGAMMA_CONTROL                                                  0x1d58
2153#define SEA_mmDCP2_DEGAMMA_CONTROL                                                  0x4058
2154#define SEA_mmDCP3_DEGAMMA_CONTROL                                                  0x4358
2155#define SEA_mmDCP4_DEGAMMA_CONTROL                                                  0x4658
2156#define SEA_mmDCP5_DEGAMMA_CONTROL                                                  0x4958
2157#define SEA_mmGAMUT_REMAP_CONTROL                                                   0x1a59
2158#define SEA_mmDCP0_GAMUT_REMAP_CONTROL                                              0x1a59
2159#define SEA_mmDCP1_GAMUT_REMAP_CONTROL                                              0x1d59
2160#define SEA_mmDCP2_GAMUT_REMAP_CONTROL                                              0x4059
2161#define SEA_mmDCP3_GAMUT_REMAP_CONTROL                                              0x4359
2162#define SEA_mmDCP4_GAMUT_REMAP_CONTROL                                              0x4659
2163#define SEA_mmDCP5_GAMUT_REMAP_CONTROL                                              0x4959
2164#define SEA_mmGAMUT_REMAP_C11_C12                                                   0x1a5a
2165#define SEA_mmDCP0_GAMUT_REMAP_C11_C12                                              0x1a5a
2166#define SEA_mmDCP1_GAMUT_REMAP_C11_C12                                              0x1d5a
2167#define SEA_mmDCP2_GAMUT_REMAP_C11_C12                                              0x405a
2168#define SEA_mmDCP3_GAMUT_REMAP_C11_C12                                              0x435a
2169#define SEA_mmDCP4_GAMUT_REMAP_C11_C12                                              0x465a
2170#define SEA_mmDCP5_GAMUT_REMAP_C11_C12                                              0x495a
2171#define SEA_mmGAMUT_REMAP_C13_C14                                                   0x1a5b
2172#define SEA_mmDCP0_GAMUT_REMAP_C13_C14                                              0x1a5b
2173#define SEA_mmDCP1_GAMUT_REMAP_C13_C14                                              0x1d5b
2174#define SEA_mmDCP2_GAMUT_REMAP_C13_C14                                              0x405b
2175#define SEA_mmDCP3_GAMUT_REMAP_C13_C14                                              0x435b
2176#define SEA_mmDCP4_GAMUT_REMAP_C13_C14                                              0x465b
2177#define SEA_mmDCP5_GAMUT_REMAP_C13_C14                                              0x495b
2178#define SEA_mmGAMUT_REMAP_C21_C22                                                   0x1a5c
2179#define SEA_mmDCP0_GAMUT_REMAP_C21_C22                                              0x1a5c
2180#define SEA_mmDCP1_GAMUT_REMAP_C21_C22                                              0x1d5c
2181#define SEA_mmDCP2_GAMUT_REMAP_C21_C22                                              0x405c
2182#define SEA_mmDCP3_GAMUT_REMAP_C21_C22                                              0x435c
2183#define SEA_mmDCP4_GAMUT_REMAP_C21_C22                                              0x465c
2184#define SEA_mmDCP5_GAMUT_REMAP_C21_C22                                              0x495c
2185#define SEA_mmGAMUT_REMAP_C23_C24                                                   0x1a5d
2186#define SEA_mmDCP0_GAMUT_REMAP_C23_C24                                              0x1a5d
2187#define SEA_mmDCP1_GAMUT_REMAP_C23_C24                                              0x1d5d
2188#define SEA_mmDCP2_GAMUT_REMAP_C23_C24                                              0x405d
2189#define SEA_mmDCP3_GAMUT_REMAP_C23_C24                                              0x435d
2190#define SEA_mmDCP4_GAMUT_REMAP_C23_C24                                              0x465d
2191#define SEA_mmDCP5_GAMUT_REMAP_C23_C24                                              0x495d
2192#define SEA_mmGAMUT_REMAP_C31_C32                                                   0x1a5e
2193#define SEA_mmDCP0_GAMUT_REMAP_C31_C32                                              0x1a5e
2194#define SEA_mmDCP1_GAMUT_REMAP_C31_C32                                              0x1d5e
2195#define SEA_mmDCP2_GAMUT_REMAP_C31_C32                                              0x405e
2196#define SEA_mmDCP3_GAMUT_REMAP_C31_C32                                              0x435e
2197#define SEA_mmDCP4_GAMUT_REMAP_C31_C32                                              0x465e
2198#define SEA_mmDCP5_GAMUT_REMAP_C31_C32                                              0x495e
2199#define SEA_mmGAMUT_REMAP_C33_C34                                                   0x1a5f
2200#define SEA_mmDCP0_GAMUT_REMAP_C33_C34                                              0x1a5f
2201#define SEA_mmDCP1_GAMUT_REMAP_C33_C34                                              0x1d5f
2202#define SEA_mmDCP2_GAMUT_REMAP_C33_C34                                              0x405f
2203#define SEA_mmDCP3_GAMUT_REMAP_C33_C34                                              0x435f
2204#define SEA_mmDCP4_GAMUT_REMAP_C33_C34                                              0x465f
2205#define SEA_mmDCP5_GAMUT_REMAP_C33_C34                                              0x495f
2206#define SEA_mmDCP_SPATIAL_DITHER_CNTL                                               0x1a60
2207#define SEA_mmDCP0_DCP_SPATIAL_DITHER_CNTL                                          0x1a60
2208#define SEA_mmDCP1_DCP_SPATIAL_DITHER_CNTL                                          0x1d60
2209#define SEA_mmDCP2_DCP_SPATIAL_DITHER_CNTL                                          0x4060
2210#define SEA_mmDCP3_DCP_SPATIAL_DITHER_CNTL                                          0x4360
2211#define SEA_mmDCP4_DCP_SPATIAL_DITHER_CNTL                                          0x4660
2212#define SEA_mmDCP5_DCP_SPATIAL_DITHER_CNTL                                          0x4960
2213#define SEA_mmDCP_RANDOM_SEEDS                                                      0x1a61
2214#define SEA_mmDCP0_DCP_RANDOM_SEEDS                                                 0x1a61
2215#define SEA_mmDCP1_DCP_RANDOM_SEEDS                                                 0x1d61
2216#define SEA_mmDCP2_DCP_RANDOM_SEEDS                                                 0x4061
2217#define SEA_mmDCP3_DCP_RANDOM_SEEDS                                                 0x4361
2218#define SEA_mmDCP4_DCP_RANDOM_SEEDS                                                 0x4661
2219#define SEA_mmDCP5_DCP_RANDOM_SEEDS                                                 0x4961
2220#define SEA_mmDCP_FP_CONVERTED_FIELD                                                0x1a65
2221#define SEA_mmDCP0_DCP_FP_CONVERTED_FIELD                                           0x1a65
2222#define SEA_mmDCP1_DCP_FP_CONVERTED_FIELD                                           0x1d65
2223#define SEA_mmDCP2_DCP_FP_CONVERTED_FIELD                                           0x4065
2224#define SEA_mmDCP3_DCP_FP_CONVERTED_FIELD                                           0x4365
2225#define SEA_mmDCP4_DCP_FP_CONVERTED_FIELD                                           0x4665
2226#define SEA_mmDCP5_DCP_FP_CONVERTED_FIELD                                           0x4965
2227#define SEA_mmCUR_CONTROL                                                           0x1a66
2228#define SEA_mmDCP0_CUR_CONTROL                                                      0x1a66
2229#define SEA_mmDCP1_CUR_CONTROL                                                      0x1d66
2230#define SEA_mmDCP2_CUR_CONTROL                                                      0x4066
2231#define SEA_mmDCP3_CUR_CONTROL                                                      0x4366
2232#define SEA_mmDCP4_CUR_CONTROL                                                      0x4666
2233#define SEA_mmDCP5_CUR_CONTROL                                                      0x4966
2234#define SEA_mmCUR_SURFACE_ADDRESS                                                   0x1a67
2235#define SEA_mmDCP0_CUR_SURFACE_ADDRESS                                              0x1a67
2236#define SEA_mmDCP1_CUR_SURFACE_ADDRESS                                              0x1d67
2237#define SEA_mmDCP2_CUR_SURFACE_ADDRESS                                              0x4067
2238#define SEA_mmDCP3_CUR_SURFACE_ADDRESS                                              0x4367
2239#define SEA_mmDCP4_CUR_SURFACE_ADDRESS                                              0x4667
2240#define SEA_mmDCP5_CUR_SURFACE_ADDRESS                                              0x4967
2241#define SEA_mmCUR_SIZE                                                              0x1a68
2242#define SEA_mmDCP0_CUR_SIZE                                                         0x1a68
2243#define SEA_mmDCP1_CUR_SIZE                                                         0x1d68
2244#define SEA_mmDCP2_CUR_SIZE                                                         0x4068
2245#define SEA_mmDCP3_CUR_SIZE                                                         0x4368
2246#define SEA_mmDCP4_CUR_SIZE                                                         0x4668
2247#define SEA_mmDCP5_CUR_SIZE                                                         0x4968
2248#define SEA_mmCUR_SURFACE_ADDRESS_HIGH                                              0x1a69
2249#define SEA_mmDCP0_CUR_SURFACE_ADDRESS_HIGH                                         0x1a69
2250#define SEA_mmDCP1_CUR_SURFACE_ADDRESS_HIGH                                         0x1d69
2251#define SEA_mmDCP2_CUR_SURFACE_ADDRESS_HIGH                                         0x4069
2252#define SEA_mmDCP3_CUR_SURFACE_ADDRESS_HIGH                                         0x4369
2253#define SEA_mmDCP4_CUR_SURFACE_ADDRESS_HIGH                                         0x4669
2254#define SEA_mmDCP5_CUR_SURFACE_ADDRESS_HIGH                                         0x4969
2255#define SEA_mmCUR_POSITION                                                          0x1a6a
2256#define SEA_mmDCP0_CUR_POSITION                                                     0x1a6a
2257#define SEA_mmDCP1_CUR_POSITION                                                     0x1d6a
2258#define SEA_mmDCP2_CUR_POSITION                                                     0x406a
2259#define SEA_mmDCP3_CUR_POSITION                                                     0x436a
2260#define SEA_mmDCP4_CUR_POSITION                                                     0x466a
2261#define SEA_mmDCP5_CUR_POSITION                                                     0x496a
2262#define SEA_mmCUR_HOT_SPOT                                                          0x1a6b
2263#define SEA_mmDCP0_CUR_HOT_SPOT                                                     0x1a6b
2264#define SEA_mmDCP1_CUR_HOT_SPOT                                                     0x1d6b
2265#define SEA_mmDCP2_CUR_HOT_SPOT                                                     0x406b
2266#define SEA_mmDCP3_CUR_HOT_SPOT                                                     0x436b
2267#define SEA_mmDCP4_CUR_HOT_SPOT                                                     0x466b
2268#define SEA_mmDCP5_CUR_HOT_SPOT                                                     0x496b
2269#define SEA_mmCUR_COLOR1                                                            0x1a6c
2270#define SEA_mmDCP0_CUR_COLOR1                                                       0x1a6c
2271#define SEA_mmDCP1_CUR_COLOR1                                                       0x1d6c
2272#define SEA_mmDCP2_CUR_COLOR1                                                       0x406c
2273#define SEA_mmDCP3_CUR_COLOR1                                                       0x436c
2274#define SEA_mmDCP4_CUR_COLOR1                                                       0x466c
2275#define SEA_mmDCP5_CUR_COLOR1                                                       0x496c
2276#define SEA_mmCUR_COLOR2                                                            0x1a6d
2277#define SEA_mmDCP0_CUR_COLOR2                                                       0x1a6d
2278#define SEA_mmDCP1_CUR_COLOR2                                                       0x1d6d
2279#define SEA_mmDCP2_CUR_COLOR2                                                       0x406d
2280#define SEA_mmDCP3_CUR_COLOR2                                                       0x436d
2281#define SEA_mmDCP4_CUR_COLOR2                                                       0x466d
2282#define SEA_mmDCP5_CUR_COLOR2                                                       0x496d
2283#define SEA_mmCUR_UPDATE                                                            0x1a6e
2284#define SEA_mmDCP0_CUR_UPDATE                                                       0x1a6e
2285#define SEA_mmDCP1_CUR_UPDATE                                                       0x1d6e
2286#define SEA_mmDCP2_CUR_UPDATE                                                       0x406e
2287#define SEA_mmDCP3_CUR_UPDATE                                                       0x436e
2288#define SEA_mmDCP4_CUR_UPDATE                                                       0x466e
2289#define SEA_mmDCP5_CUR_UPDATE                                                       0x496e
2290#define SEA_mmCUR2_CONTROL                                                          0x1a6f
2291#define SEA_mmDCP0_CUR2_CONTROL                                                     0x1a6f
2292#define SEA_mmDCP1_CUR2_CONTROL                                                     0x1d6f
2293#define SEA_mmDCP2_CUR2_CONTROL                                                     0x406f
2294#define SEA_mmDCP3_CUR2_CONTROL                                                     0x436f
2295#define SEA_mmDCP4_CUR2_CONTROL                                                     0x466f
2296#define SEA_mmDCP5_CUR2_CONTROL                                                     0x496f
2297#define SEA_mmCUR2_SURFACE_ADDRESS                                                  0x1a70
2298#define SEA_mmDCP0_CUR2_SURFACE_ADDRESS                                             0x1a70
2299#define SEA_mmDCP1_CUR2_SURFACE_ADDRESS                                             0x1d70
2300#define SEA_mmDCP2_CUR2_SURFACE_ADDRESS                                             0x4070
2301#define SEA_mmDCP3_CUR2_SURFACE_ADDRESS                                             0x4370
2302#define SEA_mmDCP4_CUR2_SURFACE_ADDRESS                                             0x4670
2303#define SEA_mmDCP5_CUR2_SURFACE_ADDRESS                                             0x4970
2304#define SEA_mmCUR2_SIZE                                                             0x1a71
2305#define SEA_mmDCP0_CUR2_SIZE                                                        0x1a71
2306#define SEA_mmDCP1_CUR2_SIZE                                                        0x1d71
2307#define SEA_mmDCP2_CUR2_SIZE                                                        0x4071
2308#define SEA_mmDCP3_CUR2_SIZE                                                        0x4371
2309#define SEA_mmDCP4_CUR2_SIZE                                                        0x4671
2310#define SEA_mmDCP5_CUR2_SIZE                                                        0x4971
2311#define SEA_mmCUR2_SURFACE_ADDRESS_HIGH                                             0x1a72
2312#define SEA_mmDCP0_CUR2_SURFACE_ADDRESS_HIGH                                        0x1a72
2313#define SEA_mmDCP1_CUR2_SURFACE_ADDRESS_HIGH                                        0x1d72
2314#define SEA_mmDCP2_CUR2_SURFACE_ADDRESS_HIGH                                        0x4072
2315#define SEA_mmDCP3_CUR2_SURFACE_ADDRESS_HIGH                                        0x4372
2316#define SEA_mmDCP4_CUR2_SURFACE_ADDRESS_HIGH                                        0x4672
2317#define SEA_mmDCP5_CUR2_SURFACE_ADDRESS_HIGH                                        0x4972
2318#define SEA_mmCUR2_POSITION                                                         0x1a73
2319#define SEA_mmDCP0_CUR2_POSITION                                                    0x1a73
2320#define SEA_mmDCP1_CUR2_POSITION                                                    0x1d73
2321#define SEA_mmDCP2_CUR2_POSITION                                                    0x4073
2322#define SEA_mmDCP3_CUR2_POSITION                                                    0x4373
2323#define SEA_mmDCP4_CUR2_POSITION                                                    0x4673
2324#define SEA_mmDCP5_CUR2_POSITION                                                    0x4973
2325#define SEA_mmCUR2_HOT_SPOT                                                         0x1a74
2326#define SEA_mmDCP0_CUR2_HOT_SPOT                                                    0x1a74
2327#define SEA_mmDCP1_CUR2_HOT_SPOT                                                    0x1d74
2328#define SEA_mmDCP2_CUR2_HOT_SPOT                                                    0x4074
2329#define SEA_mmDCP3_CUR2_HOT_SPOT                                                    0x4374
2330#define SEA_mmDCP4_CUR2_HOT_SPOT                                                    0x4674
2331#define SEA_mmDCP5_CUR2_HOT_SPOT                                                    0x4974
2332#define SEA_mmCUR2_COLOR1                                                           0x1a75
2333#define SEA_mmDCP0_CUR2_COLOR1                                                      0x1a75
2334#define SEA_mmDCP1_CUR2_COLOR1                                                      0x1d75
2335#define SEA_mmDCP2_CUR2_COLOR1                                                      0x4075
2336#define SEA_mmDCP3_CUR2_COLOR1                                                      0x4375
2337#define SEA_mmDCP4_CUR2_COLOR1                                                      0x4675
2338#define SEA_mmDCP5_CUR2_COLOR1                                                      0x4975
2339#define SEA_mmCUR2_COLOR2                                                           0x1a76
2340#define SEA_mmDCP0_CUR2_COLOR2                                                      0x1a76
2341#define SEA_mmDCP1_CUR2_COLOR2                                                      0x1d76
2342#define SEA_mmDCP2_CUR2_COLOR2                                                      0x4076
2343#define SEA_mmDCP3_CUR2_COLOR2                                                      0x4376
2344#define SEA_mmDCP4_CUR2_COLOR2                                                      0x4676
2345#define SEA_mmDCP5_CUR2_COLOR2                                                      0x4976
2346#define SEA_mmCUR2_UPDATE                                                           0x1a77
2347#define SEA_mmDCP0_CUR2_UPDATE                                                      0x1a77
2348#define SEA_mmDCP1_CUR2_UPDATE                                                      0x1d77
2349#define SEA_mmDCP2_CUR2_UPDATE                                                      0x4077
2350#define SEA_mmDCP3_CUR2_UPDATE                                                      0x4377
2351#define SEA_mmDCP4_CUR2_UPDATE                                                      0x4677
2352#define SEA_mmDCP5_CUR2_UPDATE                                                      0x4977
2353#define SEA_mmCUR_REQUEST_FILTER_CNTL                                               0x1a99
2354#define SEA_mmDCP0_CUR_REQUEST_FILTER_CNTL                                          0x1a99
2355#define SEA_mmDCP1_CUR_REQUEST_FILTER_CNTL                                          0x1d99
2356#define SEA_mmDCP2_CUR_REQUEST_FILTER_CNTL                                          0x4099
2357#define SEA_mmDCP3_CUR_REQUEST_FILTER_CNTL                                          0x4399
2358#define SEA_mmDCP4_CUR_REQUEST_FILTER_CNTL                                          0x4699
2359#define SEA_mmDCP5_CUR_REQUEST_FILTER_CNTL                                          0x4999
2360#define SEA_mmCUR_STEREO_CONTROL                                                    0x1a9a
2361#define SEA_mmDCP0_CUR_STEREO_CONTROL                                               0x1a9a
2362#define SEA_mmDCP1_CUR_STEREO_CONTROL                                               0x1d9a
2363#define SEA_mmDCP2_CUR_STEREO_CONTROL                                               0x409a
2364#define SEA_mmDCP3_CUR_STEREO_CONTROL                                               0x439a
2365#define SEA_mmDCP4_CUR_STEREO_CONTROL                                               0x469a
2366#define SEA_mmDCP5_CUR_STEREO_CONTROL                                               0x499a
2367#define SEA_mmCUR2_STEREO_CONTROL                                                   0x1a9b
2368#define SEA_mmDCP0_CUR2_STEREO_CONTROL                                              0x1a9b
2369#define SEA_mmDCP1_CUR2_STEREO_CONTROL                                              0x1d9b
2370#define SEA_mmDCP2_CUR2_STEREO_CONTROL                                              0x409b
2371#define SEA_mmDCP3_CUR2_STEREO_CONTROL                                              0x439b
2372#define SEA_mmDCP4_CUR2_STEREO_CONTROL                                              0x469b
2373#define SEA_mmDCP5_CUR2_STEREO_CONTROL                                              0x499b
2374#define SEA_mmDC_LUT_RW_MODE                                                        0x1a78
2375#define SEA_mmDCP0_DC_LUT_RW_MODE                                                   0x1a78
2376#define SEA_mmDCP1_DC_LUT_RW_MODE                                                   0x1d78
2377#define SEA_mmDCP2_DC_LUT_RW_MODE                                                   0x4078
2378#define SEA_mmDCP3_DC_LUT_RW_MODE                                                   0x4378
2379#define SEA_mmDCP4_DC_LUT_RW_MODE                                                   0x4678
2380#define SEA_mmDCP5_DC_LUT_RW_MODE                                                   0x4978
2381#define SEA_mmDC_LUT_RW_INDEX                                                       0x1a79
2382#define SEA_mmDCP0_DC_LUT_RW_INDEX                                                  0x1a79
2383#define SEA_mmDCP1_DC_LUT_RW_INDEX                                                  0x1d79
2384#define SEA_mmDCP2_DC_LUT_RW_INDEX                                                  0x4079
2385#define SEA_mmDCP3_DC_LUT_RW_INDEX                                                  0x4379
2386#define SEA_mmDCP4_DC_LUT_RW_INDEX                                                  0x4679
2387#define SEA_mmDCP5_DC_LUT_RW_INDEX                                                  0x4979
2388#define SEA_mmDC_LUT_SEQ_COLOR                                                      0x1a7a
2389#define SEA_mmDCP0_DC_LUT_SEQ_COLOR                                                 0x1a7a
2390#define SEA_mmDCP1_DC_LUT_SEQ_COLOR                                                 0x1d7a
2391#define SEA_mmDCP2_DC_LUT_SEQ_COLOR                                                 0x407a
2392#define SEA_mmDCP3_DC_LUT_SEQ_COLOR                                                 0x437a
2393#define SEA_mmDCP4_DC_LUT_SEQ_COLOR                                                 0x467a
2394#define SEA_mmDCP5_DC_LUT_SEQ_COLOR                                                 0x497a
2395#define SEA_mmDC_LUT_PWL_DATA                                                       0x1a7b
2396#define SEA_mmDCP0_DC_LUT_PWL_DATA                                                  0x1a7b
2397#define SEA_mmDCP1_DC_LUT_PWL_DATA                                                  0x1d7b
2398#define SEA_mmDCP2_DC_LUT_PWL_DATA                                                  0x407b
2399#define SEA_mmDCP3_DC_LUT_PWL_DATA                                                  0x437b
2400#define SEA_mmDCP4_DC_LUT_PWL_DATA                                                  0x467b
2401#define SEA_mmDCP5_DC_LUT_PWL_DATA                                                  0x497b
2402#define SEA_mmDC_LUT_30_COLOR                                                       0x1a7c
2403#define SEA_mmDCP0_DC_LUT_30_COLOR                                                  0x1a7c
2404#define SEA_mmDCP1_DC_LUT_30_COLOR                                                  0x1d7c
2405#define SEA_mmDCP2_DC_LUT_30_COLOR                                                  0x407c
2406#define SEA_mmDCP3_DC_LUT_30_COLOR                                                  0x437c
2407#define SEA_mmDCP4_DC_LUT_30_COLOR                                                  0x467c
2408#define SEA_mmDCP5_DC_LUT_30_COLOR                                                  0x497c
2409#define SEA_mmDC_LUT_VGA_ACCESS_ENABLE                                              0x1a7d
2410#define SEA_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE                                         0x1a7d
2411#define SEA_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE                                         0x1d7d
2412#define SEA_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE                                         0x407d
2413#define SEA_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE                                         0x437d
2414#define SEA_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE                                         0x467d
2415#define SEA_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE                                         0x497d
2416#define SEA_mmDC_LUT_WRITE_EN_MASK                                                  0x1a7e
2417#define SEA_mmDCP0_DC_LUT_WRITE_EN_MASK                                             0x1a7e
2418#define SEA_mmDCP1_DC_LUT_WRITE_EN_MASK                                             0x1d7e
2419#define SEA_mmDCP2_DC_LUT_WRITE_EN_MASK                                             0x407e
2420#define SEA_mmDCP3_DC_LUT_WRITE_EN_MASK                                             0x437e
2421#define SEA_mmDCP4_DC_LUT_WRITE_EN_MASK                                             0x467e
2422#define SEA_mmDCP5_DC_LUT_WRITE_EN_MASK                                             0x497e
2423#define SEA_mmDC_LUT_AUTOFILL                                                       0x1a7f
2424#define SEA_mmDCP0_DC_LUT_AUTOFILL                                                  0x1a7f
2425#define SEA_mmDCP1_DC_LUT_AUTOFILL                                                  0x1d7f
2426#define SEA_mmDCP2_DC_LUT_AUTOFILL                                                  0x407f
2427#define SEA_mmDCP3_DC_LUT_AUTOFILL                                                  0x437f
2428#define SEA_mmDCP4_DC_LUT_AUTOFILL                                                  0x467f
2429#define SEA_mmDCP5_DC_LUT_AUTOFILL                                                  0x497f
2430#define SEA_mmDC_LUT_CONTROL                                                        0x1a80
2431#define SEA_mmDCP0_DC_LUT_CONTROL                                                   0x1a80
2432#define SEA_mmDCP1_DC_LUT_CONTROL                                                   0x1d80
2433#define SEA_mmDCP2_DC_LUT_CONTROL                                                   0x4080
2434#define SEA_mmDCP3_DC_LUT_CONTROL                                                   0x4380
2435#define SEA_mmDCP4_DC_LUT_CONTROL                                                   0x4680
2436#define SEA_mmDCP5_DC_LUT_CONTROL                                                   0x4980
2437#define SEA_mmDC_LUT_BLACK_OFFSET_BLUE                                              0x1a81
2438#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE                                         0x1a81
2439#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE                                         0x1d81
2440#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE                                         0x4081
2441#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE                                         0x4381
2442#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE                                         0x4681
2443#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE                                         0x4981
2444#define SEA_mmDC_LUT_BLACK_OFFSET_GREEN                                             0x1a82
2445#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN                                        0x1a82
2446#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN                                        0x1d82
2447#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN                                        0x4082
2448#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN                                        0x4382
2449#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN                                        0x4682
2450#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN                                        0x4982
2451#define SEA_mmDC_LUT_BLACK_OFFSET_RED                                               0x1a83
2452#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_RED                                          0x1a83
2453#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_RED                                          0x1d83
2454#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_RED                                          0x4083
2455#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_RED                                          0x4383
2456#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_RED                                          0x4683
2457#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_RED                                          0x4983
2458#define SEA_mmDC_LUT_WHITE_OFFSET_BLUE                                              0x1a84
2459#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE                                         0x1a84
2460#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE                                         0x1d84
2461#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE                                         0x4084
2462#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE                                         0x4384
2463#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE                                         0x4684
2464#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE                                         0x4984
2465#define SEA_mmDC_LUT_WHITE_OFFSET_GREEN                                             0x1a85
2466#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN                                        0x1a85
2467#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN                                        0x1d85
2468#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN                                        0x4085
2469#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN                                        0x4385
2470#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN                                        0x4685
2471#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN                                        0x4985
2472#define SEA_mmDC_LUT_WHITE_OFFSET_RED                                               0x1a86
2473#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_RED                                          0x1a86
2474#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_RED                                          0x1d86
2475#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_RED                                          0x4086
2476#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_RED                                          0x4386
2477#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_RED                                          0x4686
2478#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_RED                                          0x4986
2479#define SEA_mmDCP_CRC_CONTROL                                                       0x1a87
2480#define SEA_mmDCP0_DCP_CRC_CONTROL                                                  0x1a87
2481#define SEA_mmDCP1_DCP_CRC_CONTROL                                                  0x1d87
2482#define SEA_mmDCP2_DCP_CRC_CONTROL                                                  0x4087
2483#define SEA_mmDCP3_DCP_CRC_CONTROL                                                  0x4387
2484#define SEA_mmDCP4_DCP_CRC_CONTROL                                                  0x4687
2485#define SEA_mmDCP5_DCP_CRC_CONTROL                                                  0x4987
2486#define SEA_mmDCP_CRC_MASK                                                          0x1a88
2487#define SEA_mmDCP0_DCP_CRC_MASK                                                     0x1a88
2488#define SEA_mmDCP1_DCP_CRC_MASK                                                     0x1d88
2489#define SEA_mmDCP2_DCP_CRC_MASK                                                     0x4088
2490#define SEA_mmDCP3_DCP_CRC_MASK                                                     0x4388
2491#define SEA_mmDCP4_DCP_CRC_MASK                                                     0x4688
2492#define SEA_mmDCP5_DCP_CRC_MASK                                                     0x4988
2493#define SEA_mmDCP_CRC_CURRENT                                                       0x1a89
2494#define SEA_mmDCP0_DCP_CRC_CURRENT                                                  0x1a89
2495#define SEA_mmDCP1_DCP_CRC_CURRENT                                                  0x1d89
2496#define SEA_mmDCP2_DCP_CRC_CURRENT                                                  0x4089
2497#define SEA_mmDCP3_DCP_CRC_CURRENT                                                  0x4389
2498#define SEA_mmDCP4_DCP_CRC_CURRENT                                                  0x4689
2499#define SEA_mmDCP5_DCP_CRC_CURRENT                                                  0x4989
2500#define SEA_mmDCP_CRC_LAST                                                          0x1a8b
2501#define SEA_mmDCP0_DCP_CRC_LAST                                                     0x1a8b
2502#define SEA_mmDCP1_DCP_CRC_LAST                                                     0x1d8b
2503#define SEA_mmDCP2_DCP_CRC_LAST                                                     0x408b
2504#define SEA_mmDCP3_DCP_CRC_LAST                                                     0x438b
2505#define SEA_mmDCP4_DCP_CRC_LAST                                                     0x468b
2506#define SEA_mmDCP5_DCP_CRC_LAST                                                     0x498b
2507#define SEA_mmDCP_DEBUG                                                             0x1a8d
2508#define SEA_mmDCP0_DCP_DEBUG                                                        0x1a8d
2509#define SEA_mmDCP1_DCP_DEBUG                                                        0x1d8d
2510#define SEA_mmDCP2_DCP_DEBUG                                                        0x408d
2511#define SEA_mmDCP3_DCP_DEBUG                                                        0x438d
2512#define SEA_mmDCP4_DCP_DEBUG                                                        0x468d
2513#define SEA_mmDCP5_DCP_DEBUG                                                        0x498d
2514#define SEA_mmGRPH_FLIP_RATE_CNTL                                                   0x1a8e
2515#define SEA_mmDCP0_GRPH_FLIP_RATE_CNTL                                              0x1a8e
2516#define SEA_mmDCP1_GRPH_FLIP_RATE_CNTL                                              0x1d8e
2517#define SEA_mmDCP2_GRPH_FLIP_RATE_CNTL                                              0x408e
2518#define SEA_mmDCP3_GRPH_FLIP_RATE_CNTL                                              0x438e
2519#define SEA_mmDCP4_GRPH_FLIP_RATE_CNTL                                              0x468e
2520#define SEA_mmDCP5_GRPH_FLIP_RATE_CNTL                                              0x498e
2521#define SEA_mmDCP_GSL_CONTROL                                                       0x1a90
2522#define SEA_mmDCP0_DCP_GSL_CONTROL                                                  0x1a90
2523#define SEA_mmDCP1_DCP_GSL_CONTROL                                                  0x1d90
2524#define SEA_mmDCP2_DCP_GSL_CONTROL                                                  0x4090
2525#define SEA_mmDCP3_DCP_GSL_CONTROL                                                  0x4390
2526#define SEA_mmDCP4_DCP_GSL_CONTROL                                                  0x4690
2527#define SEA_mmDCP5_DCP_GSL_CONTROL                                                  0x4990
2528#define SEA_mmDCP_LB_DATA_GAP_BETWEEN_CHUNK                                         0x1a91
2529#define SEA_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1a91
2530#define SEA_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1d91
2531#define SEA_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4091
2532#define SEA_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4391
2533#define SEA_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4691
2534#define SEA_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4991
2535#define SEA_mmOVL_SECONDARY_SURFACE_ADDRESS                                         0x1a92
2536#define SEA_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS                                    0x1a92
2537#define SEA_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS                                    0x1d92
2538#define SEA_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4092
2539#define SEA_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4392
2540#define SEA_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4692
2541#define SEA_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4992
2542#define SEA_mmOVL_STEREOSYNC_FLIP                                                   0x1a93
2543#define SEA_mmDCP0_OVL_STEREOSYNC_FLIP                                              0x1a93
2544#define SEA_mmDCP1_OVL_STEREOSYNC_FLIP                                              0x1d93
2545#define SEA_mmDCP2_OVL_STEREOSYNC_FLIP                                              0x4093
2546#define SEA_mmDCP3_OVL_STEREOSYNC_FLIP                                              0x4393
2547#define SEA_mmDCP4_OVL_STEREOSYNC_FLIP                                              0x4693
2548#define SEA_mmDCP5_OVL_STEREOSYNC_FLIP                                              0x4993
2549#define SEA_mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH                                    0x1a94
2550#define SEA_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x1a94
2551#define SEA_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x1d94
2552#define SEA_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4094
2553#define SEA_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4394
2554#define SEA_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4694
2555#define SEA_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4994
2556#define SEA_mmDCP_TEST_DEBUG_INDEX                                                  0x1a95
2557#define SEA_mmDCP0_DCP_TEST_DEBUG_INDEX                                             0x1a95
2558#define SEA_mmDCP1_DCP_TEST_DEBUG_INDEX                                             0x1d95
2559#define SEA_mmDCP2_DCP_TEST_DEBUG_INDEX                                             0x4095
2560#define SEA_mmDCP3_DCP_TEST_DEBUG_INDEX                                             0x4395
2561#define SEA_mmDCP4_DCP_TEST_DEBUG_INDEX                                             0x4695
2562#define SEA_mmDCP5_DCP_TEST_DEBUG_INDEX                                             0x4995
2563#define SEA_mmDCP_TEST_DEBUG_DATA                                                   0x1a96
2564#define SEA_mmDCP0_DCP_TEST_DEBUG_DATA                                              0x1a96
2565#define SEA_mmDCP1_DCP_TEST_DEBUG_DATA                                              0x1d96
2566#define SEA_mmDCP2_DCP_TEST_DEBUG_DATA                                              0x4096
2567#define SEA_mmDCP3_DCP_TEST_DEBUG_DATA                                              0x4396
2568#define SEA_mmDCP4_DCP_TEST_DEBUG_DATA                                              0x4696
2569#define SEA_mmDCP5_DCP_TEST_DEBUG_DATA                                              0x4996
2570#define SEA_mmGRPH_STEREOSYNC_FLIP                                                  0x1a97
2571#define SEA_mmDCP0_GRPH_STEREOSYNC_FLIP                                             0x1a97
2572#define SEA_mmDCP1_GRPH_STEREOSYNC_FLIP                                             0x1d97
2573#define SEA_mmDCP2_GRPH_STEREOSYNC_FLIP                                             0x4097
2574#define SEA_mmDCP3_GRPH_STEREOSYNC_FLIP                                             0x4397
2575#define SEA_mmDCP4_GRPH_STEREOSYNC_FLIP                                             0x4697
2576#define SEA_mmDCP5_GRPH_STEREOSYNC_FLIP                                             0x4997
2577#define SEA_mmDCP_DEBUG2                                                            0x1a98
2578#define SEA_mmDCP0_DCP_DEBUG2                                                       0x1a98
2579#define SEA_mmDCP1_DCP_DEBUG2                                                       0x1d98
2580#define SEA_mmDCP2_DCP_DEBUG2                                                       0x4098
2581#define SEA_mmDCP3_DCP_DEBUG2                                                       0x4398
2582#define SEA_mmDCP4_DCP_DEBUG2                                                       0x4698
2583#define SEA_mmDCP5_DCP_DEBUG2                                                       0x4998
2584#define SEA_mmHW_ROTATION                                                           0x1a9e
2585#define SEA_mmDCP0_HW_ROTATION                                                      0x1a9e
2586#define SEA_mmDCP1_HW_ROTATION                                                      0x1d9e
2587#define SEA_mmDCP2_HW_ROTATION                                                      0x409e
2588#define SEA_mmDCP3_HW_ROTATION                                                      0x439e
2589#define SEA_mmDCP4_HW_ROTATION                                                      0x469e
2590#define SEA_mmDCP5_HW_ROTATION                                                      0x499e
2591#define SEA_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                    0x1a9f
2592#define SEA_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1a9f
2593#define SEA_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1d9f
2594#define SEA_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x409f
2595#define SEA_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x439f
2596#define SEA_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x469f
2597#define SEA_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x499f
2598#define SEA_mmREGAMMA_CONTROL                                                       0x1aa0
2599#define SEA_mmDCP0_REGAMMA_CONTROL                                                  0x1aa0
2600#define SEA_mmDCP1_REGAMMA_CONTROL                                                  0x1da0
2601#define SEA_mmDCP2_REGAMMA_CONTROL                                                  0x40a0
2602#define SEA_mmDCP3_REGAMMA_CONTROL                                                  0x43a0
2603#define SEA_mmDCP4_REGAMMA_CONTROL                                                  0x46a0
2604#define SEA_mmDCP5_REGAMMA_CONTROL                                                  0x49a0
2605#define SEA_mmREGAMMA_LUT_INDEX                                                     0x1aa1
2606#define SEA_mmDCP0_REGAMMA_LUT_INDEX                                                0x1aa1
2607#define SEA_mmDCP1_REGAMMA_LUT_INDEX                                                0x1da1
2608#define SEA_mmDCP2_REGAMMA_LUT_INDEX                                                0x40a1
2609#define SEA_mmDCP3_REGAMMA_LUT_INDEX                                                0x43a1
2610#define SEA_mmDCP4_REGAMMA_LUT_INDEX                                                0x46a1
2611#define SEA_mmDCP5_REGAMMA_LUT_INDEX                                                0x49a1
2612#define SEA_mmREGAMMA_LUT_DATA                                                      0x1aa2
2613#define SEA_mmDCP0_REGAMMA_LUT_DATA                                                 0x1aa2
2614#define SEA_mmDCP1_REGAMMA_LUT_DATA                                                 0x1da2
2615#define SEA_mmDCP2_REGAMMA_LUT_DATA                                                 0x40a2
2616#define SEA_mmDCP3_REGAMMA_LUT_DATA                                                 0x43a2
2617#define SEA_mmDCP4_REGAMMA_LUT_DATA                                                 0x46a2
2618#define SEA_mmDCP5_REGAMMA_LUT_DATA                                                 0x49a2
2619#define SEA_mmREGAMMA_LUT_WRITE_EN_MASK                                             0x1aa3
2620#define SEA_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK                                        0x1aa3
2621#define SEA_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK                                        0x1da3
2622#define SEA_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK                                        0x40a3
2623#define SEA_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK                                        0x43a3
2624#define SEA_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK                                        0x46a3
2625#define SEA_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK                                        0x49a3
2626#define SEA_mmREGAMMA_CNTLA_START_CNTL                                              0x1aa4
2627#define SEA_mmDCP0_REGAMMA_CNTLA_START_CNTL                                         0x1aa4
2628#define SEA_mmDCP1_REGAMMA_CNTLA_START_CNTL                                         0x1da4
2629#define SEA_mmDCP2_REGAMMA_CNTLA_START_CNTL                                         0x40a4
2630#define SEA_mmDCP3_REGAMMA_CNTLA_START_CNTL                                         0x43a4
2631#define SEA_mmDCP4_REGAMMA_CNTLA_START_CNTL                                         0x46a4
2632#define SEA_mmDCP5_REGAMMA_CNTLA_START_CNTL                                         0x49a4
2633#define SEA_mmREGAMMA_CNTLA_SLOPE_CNTL                                              0x1aa5
2634#define SEA_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1aa5
2635#define SEA_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1da5
2636#define SEA_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL                                         0x40a5
2637#define SEA_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL                                         0x43a5
2638#define SEA_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL                                         0x46a5
2639#define SEA_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL                                         0x49a5
2640#define SEA_mmREGAMMA_CNTLA_END_CNTL1                                               0x1aa6
2641#define SEA_mmDCP0_REGAMMA_CNTLA_END_CNTL1                                          0x1aa6
2642#define SEA_mmDCP1_REGAMMA_CNTLA_END_CNTL1                                          0x1da6
2643#define SEA_mmDCP2_REGAMMA_CNTLA_END_CNTL1                                          0x40a6
2644#define SEA_mmDCP3_REGAMMA_CNTLA_END_CNTL1                                          0x43a6
2645#define SEA_mmDCP4_REGAMMA_CNTLA_END_CNTL1                                          0x46a6
2646#define SEA_mmDCP5_REGAMMA_CNTLA_END_CNTL1                                          0x49a6
2647#define SEA_mmREGAMMA_CNTLA_END_CNTL2                                               0x1aa7
2648#define SEA_mmDCP0_REGAMMA_CNTLA_END_CNTL2                                          0x1aa7
2649#define SEA_mmDCP1_REGAMMA_CNTLA_END_CNTL2                                          0x1da7
2650#define SEA_mmDCP2_REGAMMA_CNTLA_END_CNTL2                                          0x40a7
2651#define SEA_mmDCP3_REGAMMA_CNTLA_END_CNTL2                                          0x43a7
2652#define SEA_mmDCP4_REGAMMA_CNTLA_END_CNTL2                                          0x46a7
2653#define SEA_mmDCP5_REGAMMA_CNTLA_END_CNTL2                                          0x49a7
2654#define SEA_mmREGAMMA_CNTLA_REGION_0_1                                              0x1aa8
2655#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_0_1                                         0x1aa8
2656#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_0_1                                         0x1da8
2657#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_0_1                                         0x40a8
2658#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_0_1                                         0x43a8
2659#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_0_1                                         0x46a8
2660#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_0_1                                         0x49a8
2661#define SEA_mmREGAMMA_CNTLA_REGION_2_3                                              0x1aa9
2662#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_2_3                                         0x1aa9
2663#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_2_3                                         0x1da9
2664#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_2_3                                         0x40a9
2665#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_2_3                                         0x43a9
2666#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_2_3                                         0x46a9
2667#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_2_3                                         0x49a9
2668#define SEA_mmREGAMMA_CNTLA_REGION_4_5                                              0x1aaa
2669#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_4_5                                         0x1aaa
2670#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_4_5                                         0x1daa
2671#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_4_5                                         0x40aa
2672#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_4_5                                         0x43aa
2673#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_4_5                                         0x46aa
2674#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_4_5                                         0x49aa
2675#define SEA_mmREGAMMA_CNTLA_REGION_6_7                                              0x1aab
2676#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_6_7                                         0x1aab
2677#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_6_7                                         0x1dab
2678#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_6_7                                         0x40ab
2679#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_6_7                                         0x43ab
2680#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_6_7                                         0x46ab
2681#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_6_7                                         0x49ab
2682#define SEA_mmREGAMMA_CNTLA_REGION_8_9                                              0x1aac
2683#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_8_9                                         0x1aac
2684#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_8_9                                         0x1dac
2685#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_8_9                                         0x40ac
2686#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_8_9                                         0x43ac
2687#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_8_9                                         0x46ac
2688#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_8_9                                         0x49ac
2689#define SEA_mmREGAMMA_CNTLA_REGION_10_11                                            0x1aad
2690#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_10_11                                       0x1aad
2691#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_10_11                                       0x1dad
2692#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_10_11                                       0x40ad
2693#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_10_11                                       0x43ad
2694#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_10_11                                       0x46ad
2695#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_10_11                                       0x49ad
2696#define SEA_mmREGAMMA_CNTLA_REGION_12_13                                            0x1aae
2697#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_12_13                                       0x1aae
2698#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_12_13                                       0x1dae
2699#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_12_13                                       0x40ae
2700#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_12_13                                       0x43ae
2701#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_12_13                                       0x46ae
2702#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_12_13                                       0x49ae
2703#define SEA_mmREGAMMA_CNTLA_REGION_14_15                                            0x1aaf
2704#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_14_15                                       0x1aaf
2705#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_14_15                                       0x1daf
2706#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_14_15                                       0x40af
2707#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_14_15                                       0x43af
2708#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_14_15                                       0x46af
2709#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_14_15                                       0x49af
2710#define SEA_mmREGAMMA_CNTLB_START_CNTL                                              0x1ab0
2711#define SEA_mmDCP0_REGAMMA_CNTLB_START_CNTL                                         0x1ab0
2712#define SEA_mmDCP1_REGAMMA_CNTLB_START_CNTL                                         0x1db0
2713#define SEA_mmDCP2_REGAMMA_CNTLB_START_CNTL                                         0x40b0
2714#define SEA_mmDCP3_REGAMMA_CNTLB_START_CNTL                                         0x43b0
2715#define SEA_mmDCP4_REGAMMA_CNTLB_START_CNTL                                         0x46b0
2716#define SEA_mmDCP5_REGAMMA_CNTLB_START_CNTL                                         0x49b0
2717#define SEA_mmREGAMMA_CNTLB_SLOPE_CNTL                                              0x1ab1
2718#define SEA_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1ab1
2719#define SEA_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1db1
2720#define SEA_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL                                         0x40b1
2721#define SEA_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL                                         0x43b1
2722#define SEA_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL                                         0x46b1
2723#define SEA_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL                                         0x49b1
2724#define SEA_mmREGAMMA_CNTLB_END_CNTL1                                               0x1ab2
2725#define SEA_mmDCP0_REGAMMA_CNTLB_END_CNTL1                                          0x1ab2
2726#define SEA_mmDCP1_REGAMMA_CNTLB_END_CNTL1                                          0x1db2
2727#define SEA_mmDCP2_REGAMMA_CNTLB_END_CNTL1                                          0x40b2
2728#define SEA_mmDCP3_REGAMMA_CNTLB_END_CNTL1                                          0x43b2
2729#define SEA_mmDCP4_REGAMMA_CNTLB_END_CNTL1                                          0x46b2
2730#define SEA_mmDCP5_REGAMMA_CNTLB_END_CNTL1                                          0x49b2
2731#define SEA_mmREGAMMA_CNTLB_END_CNTL2                                               0x1ab3
2732#define SEA_mmDCP0_REGAMMA_CNTLB_END_CNTL2                                          0x1ab3
2733#define SEA_mmDCP1_REGAMMA_CNTLB_END_CNTL2                                          0x1db3
2734#define SEA_mmDCP2_REGAMMA_CNTLB_END_CNTL2                                          0x40b3
2735#define SEA_mmDCP3_REGAMMA_CNTLB_END_CNTL2                                          0x43b3
2736#define SEA_mmDCP4_REGAMMA_CNTLB_END_CNTL2                                          0x46b3
2737#define SEA_mmDCP5_REGAMMA_CNTLB_END_CNTL2                                          0x49b3
2738#define SEA_mmREGAMMA_CNTLB_REGION_0_1                                              0x1ab4
2739#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_0_1                                         0x1ab4
2740#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_0_1                                         0x1db4
2741#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_0_1                                         0x40b4
2742#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_0_1                                         0x43b4
2743#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_0_1                                         0x46b4
2744#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_0_1                                         0x49b4
2745#define SEA_mmREGAMMA_CNTLB_REGION_2_3                                              0x1ab5
2746#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_2_3                                         0x1ab5
2747#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_2_3                                         0x1db5
2748#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_2_3                                         0x40b5
2749#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_2_3                                         0x43b5
2750#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_2_3                                         0x46b5
2751#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_2_3                                         0x49b5
2752#define SEA_mmREGAMMA_CNTLB_REGION_4_5                                              0x1ab6
2753#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_4_5                                         0x1ab6
2754#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_4_5                                         0x1db6
2755#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_4_5                                         0x40b6
2756#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_4_5                                         0x43b6
2757#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_4_5                                         0x46b6
2758#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_4_5                                         0x49b6
2759#define SEA_mmREGAMMA_CNTLB_REGION_6_7                                              0x1ab7
2760#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_6_7                                         0x1ab7
2761#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_6_7                                         0x1db7
2762#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_6_7                                         0x40b7
2763#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_6_7                                         0x43b7
2764#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_6_7                                         0x46b7
2765#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_6_7                                         0x49b7
2766#define SEA_mmREGAMMA_CNTLB_REGION_8_9                                              0x1ab8
2767#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_8_9                                         0x1ab8
2768#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_8_9                                         0x1db8
2769#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_8_9                                         0x40b8
2770#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_8_9                                         0x43b8
2771#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_8_9                                         0x46b8
2772#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_8_9                                         0x49b8
2773#define SEA_mmREGAMMA_CNTLB_REGION_10_11                                            0x1ab9
2774#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_10_11                                       0x1ab9
2775#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_10_11                                       0x1db9
2776#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_10_11                                       0x40b9
2777#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_10_11                                       0x43b9
2778#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_10_11                                       0x46b9
2779#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_10_11                                       0x49b9
2780#define SEA_mmREGAMMA_CNTLB_REGION_12_13                                            0x1aba
2781#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_12_13                                       0x1aba
2782#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_12_13                                       0x1dba
2783#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_12_13                                       0x40ba
2784#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_12_13                                       0x43ba
2785#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_12_13                                       0x46ba
2786#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_12_13                                       0x49ba
2787#define SEA_mmREGAMMA_CNTLB_REGION_14_15                                            0x1abb
2788#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_14_15                                       0x1abb
2789#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_14_15                                       0x1dbb
2790#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_14_15                                       0x40bb
2791#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_14_15                                       0x43bb
2792#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_14_15                                       0x46bb
2793#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_14_15                                       0x49bb
2794#define SEA_mmALPHA_CONTROL                                                         0x1abc
2795#define SEA_mmDCP0_ALPHA_CONTROL                                                    0x1abc
2796#define SEA_mmDCP1_ALPHA_CONTROL                                                    0x1dbc
2797#define SEA_mmDCP2_ALPHA_CONTROL                                                    0x40bc
2798#define SEA_mmDCP3_ALPHA_CONTROL                                                    0x43bc
2799#define SEA_mmDCP4_ALPHA_CONTROL                                                    0x46bc
2800#define SEA_mmDCP5_ALPHA_CONTROL                                                    0x49bc
2801#define SEA_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                    0x1abd
2802#define SEA_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1abd
2803#define SEA_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1dbd
2804#define SEA_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x40bd
2805#define SEA_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x43bd
2806#define SEA_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x46bd
2807#define SEA_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x49bd
2808#define SEA_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                               0x1abe
2809#define SEA_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1abe
2810#define SEA_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1dbe
2811#define SEA_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x40be
2812#define SEA_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x43be
2813#define SEA_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x46be
2814#define SEA_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x49be
2815#define SEA_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                  0x1abf
2816#define SEA_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1abf
2817#define SEA_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1dbf
2818#define SEA_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x40bf
2819#define SEA_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x43bf
2820#define SEA_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x46bf
2821#define SEA_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x49bf
2822#define SEA_mmDIG_FE_CNTL                                                           0x1c00
2823#define SEA_mmDIG0_DIG_FE_CNTL                                                      0x1c00
2824#define SEA_mmDIG1_DIG_FE_CNTL                                                      0x1f00
2825#define SEA_mmDIG2_DIG_FE_CNTL                                                      0x4200
2826#define SEA_mmDIG3_DIG_FE_CNTL                                                      0x4500
2827#define SEA_mmDIG4_DIG_FE_CNTL                                                      0x4800
2828#define SEA_mmDIG5_DIG_FE_CNTL                                                      0x4b00
2829#define SEA_mmDIG6_DIG_FE_CNTL                                                      0x4e00
2830#define SEA_mmDIG_OUTPUT_CRC_CNTL                                                   0x1c01
2831#define SEA_mmDIG0_DIG_OUTPUT_CRC_CNTL                                              0x1c01
2832#define SEA_mmDIG1_DIG_OUTPUT_CRC_CNTL                                              0x1f01
2833#define SEA_mmDIG2_DIG_OUTPUT_CRC_CNTL                                              0x4201
2834#define SEA_mmDIG3_DIG_OUTPUT_CRC_CNTL                                              0x4501
2835#define SEA_mmDIG4_DIG_OUTPUT_CRC_CNTL                                              0x4801
2836#define SEA_mmDIG5_DIG_OUTPUT_CRC_CNTL                                              0x4b01
2837#define SEA_mmDIG6_DIG_OUTPUT_CRC_CNTL                                              0x4e01
2838#define SEA_mmDIG_OUTPUT_CRC_RESULT                                                 0x1c02
2839#define SEA_mmDIG0_DIG_OUTPUT_CRC_RESULT                                            0x1c02
2840#define SEA_mmDIG1_DIG_OUTPUT_CRC_RESULT                                            0x1f02
2841#define SEA_mmDIG2_DIG_OUTPUT_CRC_RESULT                                            0x4202
2842#define SEA_mmDIG3_DIG_OUTPUT_CRC_RESULT                                            0x4502
2843#define SEA_mmDIG4_DIG_OUTPUT_CRC_RESULT                                            0x4802
2844#define SEA_mmDIG5_DIG_OUTPUT_CRC_RESULT                                            0x4b02
2845#define SEA_mmDIG6_DIG_OUTPUT_CRC_RESULT                                            0x4e02
2846#define SEA_mmDIG_CLOCK_PATTERN                                                     0x1c03
2847#define SEA_mmDIG0_DIG_CLOCK_PATTERN                                                0x1c03
2848#define SEA_mmDIG1_DIG_CLOCK_PATTERN                                                0x1f03
2849#define SEA_mmDIG2_DIG_CLOCK_PATTERN                                                0x4203
2850#define SEA_mmDIG3_DIG_CLOCK_PATTERN                                                0x4503
2851#define SEA_mmDIG4_DIG_CLOCK_PATTERN                                                0x4803
2852#define SEA_mmDIG5_DIG_CLOCK_PATTERN                                                0x4b03
2853#define SEA_mmDIG6_DIG_CLOCK_PATTERN                                                0x4e03
2854#define SEA_mmDIG_TEST_PATTERN                                                      0x1c04
2855#define SEA_mmDIG0_DIG_TEST_PATTERN                                                 0x1c04
2856#define SEA_mmDIG1_DIG_TEST_PATTERN                                                 0x1f04
2857#define SEA_mmDIG2_DIG_TEST_PATTERN                                                 0x4204
2858#define SEA_mmDIG3_DIG_TEST_PATTERN                                                 0x4504
2859#define SEA_mmDIG4_DIG_TEST_PATTERN                                                 0x4804
2860#define SEA_mmDIG5_DIG_TEST_PATTERN                                                 0x4b04
2861#define SEA_mmDIG6_DIG_TEST_PATTERN                                                 0x4e04
2862#define SEA_mmDIG_RANDOM_PATTERN_SEED                                               0x1c05
2863#define SEA_mmDIG0_DIG_RANDOM_PATTERN_SEED                                          0x1c05
2864#define SEA_mmDIG1_DIG_RANDOM_PATTERN_SEED                                          0x1f05
2865#define SEA_mmDIG2_DIG_RANDOM_PATTERN_SEED                                          0x4205
2866#define SEA_mmDIG3_DIG_RANDOM_PATTERN_SEED                                          0x4505
2867#define SEA_mmDIG4_DIG_RANDOM_PATTERN_SEED                                          0x4805
2868#define SEA_mmDIG5_DIG_RANDOM_PATTERN_SEED                                          0x4b05
2869#define SEA_mmDIG6_DIG_RANDOM_PATTERN_SEED                                          0x4e05
2870#define SEA_mmDIG_FIFO_STATUS                                                       0x1c0a
2871#define SEA_mmDIG0_DIG_FIFO_STATUS                                                  0x1c0a
2872#define SEA_mmDIG1_DIG_FIFO_STATUS                                                  0x1f0a
2873#define SEA_mmDIG2_DIG_FIFO_STATUS                                                  0x420a
2874#define SEA_mmDIG3_DIG_FIFO_STATUS                                                  0x450a
2875#define SEA_mmDIG4_DIG_FIFO_STATUS                                                  0x480a
2876#define SEA_mmDIG5_DIG_FIFO_STATUS                                                  0x4b0a
2877#define SEA_mmDIG6_DIG_FIFO_STATUS                                                  0x4e0a
2878#define SEA_mmDIG_DISPCLK_SWITCH_CNTL                                               0x1c08
2879#define SEA_mmDIG0_DIG_DISPCLK_SWITCH_CNTL                                          0x1c08
2880#define SEA_mmDIG1_DIG_DISPCLK_SWITCH_CNTL                                          0x1f08
2881#define SEA_mmDIG2_DIG_DISPCLK_SWITCH_CNTL                                          0x4208
2882#define SEA_mmDIG3_DIG_DISPCLK_SWITCH_CNTL                                          0x4508
2883#define SEA_mmDIG4_DIG_DISPCLK_SWITCH_CNTL                                          0x4808
2884#define SEA_mmDIG5_DIG_DISPCLK_SWITCH_CNTL                                          0x4b08
2885#define SEA_mmDIG6_DIG_DISPCLK_SWITCH_CNTL                                          0x4e08
2886#define SEA_mmDIG_DISPCLK_SWITCH_STATUS                                             0x1c09
2887#define SEA_mmDIG0_DIG_DISPCLK_SWITCH_STATUS                                        0x1c09
2888#define SEA_mmDIG1_DIG_DISPCLK_SWITCH_STATUS                                        0x1f09
2889#define SEA_mmDIG2_DIG_DISPCLK_SWITCH_STATUS                                        0x4209
2890#define SEA_mmDIG3_DIG_DISPCLK_SWITCH_STATUS                                        0x4509
2891#define SEA_mmDIG4_DIG_DISPCLK_SWITCH_STATUS                                        0x4809
2892#define SEA_mmDIG5_DIG_DISPCLK_SWITCH_STATUS                                        0x4b09
2893#define SEA_mmDIG6_DIG_DISPCLK_SWITCH_STATUS                                        0x4e09
2894#define SEA_mmHDMI_CONTROL                                                          0x1c0c
2895#define SEA_mmDIG0_HDMI_CONTROL                                                     0x1c0c
2896#define SEA_mmDIG1_HDMI_CONTROL                                                     0x1f0c
2897#define SEA_mmDIG2_HDMI_CONTROL                                                     0x420c
2898#define SEA_mmDIG3_HDMI_CONTROL                                                     0x450c
2899#define SEA_mmDIG4_HDMI_CONTROL                                                     0x480c
2900#define SEA_mmDIG5_HDMI_CONTROL                                                     0x4b0c
2901#define SEA_mmDIG6_HDMI_CONTROL                                                     0x4e0c
2902#define SEA_mmHDMI_STATUS                                                           0x1c0d
2903#define SEA_mmDIG0_HDMI_STATUS                                                      0x1c0d
2904#define SEA_mmDIG1_HDMI_STATUS                                                      0x1f0d
2905#define SEA_mmDIG2_HDMI_STATUS                                                      0x420d
2906#define SEA_mmDIG3_HDMI_STATUS                                                      0x450d
2907#define SEA_mmDIG4_HDMI_STATUS                                                      0x480d
2908#define SEA_mmDIG5_HDMI_STATUS                                                      0x4b0d
2909#define SEA_mmDIG6_HDMI_STATUS                                                      0x4e0d
2910#define SEA_mmHDMI_AUDIO_PACKET_CONTROL                                             0x1c0e
2911#define SEA_mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                        0x1c0e
2912#define SEA_mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                        0x1f0e
2913#define SEA_mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                        0x420e
2914#define SEA_mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                        0x450e
2915#define SEA_mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                        0x480e
2916#define SEA_mmDIG5_HDMI_AUDIO_PACKET_CONTROL                                        0x4b0e
2917#define SEA_mmDIG6_HDMI_AUDIO_PACKET_CONTROL                                        0x4e0e
2918#define SEA_mmHDMI_ACR_PACKET_CONTROL                                               0x1c0f
2919#define SEA_mmDIG0_HDMI_ACR_PACKET_CONTROL                                          0x1c0f
2920#define SEA_mmDIG1_HDMI_ACR_PACKET_CONTROL                                          0x1f0f
2921#define SEA_mmDIG2_HDMI_ACR_PACKET_CONTROL                                          0x420f
2922#define SEA_mmDIG3_HDMI_ACR_PACKET_CONTROL                                          0x450f
2923#define SEA_mmDIG4_HDMI_ACR_PACKET_CONTROL                                          0x480f
2924#define SEA_mmDIG5_HDMI_ACR_PACKET_CONTROL                                          0x4b0f
2925#define SEA_mmDIG6_HDMI_ACR_PACKET_CONTROL                                          0x4e0f
2926#define SEA_mmHDMI_VBI_PACKET_CONTROL                                               0x1c10
2927#define SEA_mmDIG0_HDMI_VBI_PACKET_CONTROL                                          0x1c10
2928#define SEA_mmDIG1_HDMI_VBI_PACKET_CONTROL                                          0x1f10
2929#define SEA_mmDIG2_HDMI_VBI_PACKET_CONTROL                                          0x4210
2930#define SEA_mmDIG3_HDMI_VBI_PACKET_CONTROL                                          0x4510
2931#define SEA_mmDIG4_HDMI_VBI_PACKET_CONTROL                                          0x4810
2932#define SEA_mmDIG5_HDMI_VBI_PACKET_CONTROL                                          0x4b10
2933#define SEA_mmDIG6_HDMI_VBI_PACKET_CONTROL                                          0x4e10
2934#define SEA_mmHDMI_INFOFRAME_CONTROL0                                               0x1c11
2935#define SEA_mmDIG0_HDMI_INFOFRAME_CONTROL0                                          0x1c11
2936#define SEA_mmDIG1_HDMI_INFOFRAME_CONTROL0                                          0x1f11
2937#define SEA_mmDIG2_HDMI_INFOFRAME_CONTROL0                                          0x4211
2938#define SEA_mmDIG3_HDMI_INFOFRAME_CONTROL0                                          0x4511
2939#define SEA_mmDIG4_HDMI_INFOFRAME_CONTROL0                                          0x4811
2940#define SEA_mmDIG5_HDMI_INFOFRAME_CONTROL0                                          0x4b11
2941#define SEA_mmDIG6_HDMI_INFOFRAME_CONTROL0                                          0x4e11
2942#define SEA_mmHDMI_INFOFRAME_CONTROL1                                               0x1c12
2943#define SEA_mmDIG0_HDMI_INFOFRAME_CONTROL1                                          0x1c12
2944#define SEA_mmDIG1_HDMI_INFOFRAME_CONTROL1                                          0x1f12
2945#define SEA_mmDIG2_HDMI_INFOFRAME_CONTROL1                                          0x4212
2946#define SEA_mmDIG3_HDMI_INFOFRAME_CONTROL1                                          0x4512
2947#define SEA_mmDIG4_HDMI_INFOFRAME_CONTROL1                                          0x4812
2948#define SEA_mmDIG5_HDMI_INFOFRAME_CONTROL1                                          0x4b12
2949#define SEA_mmDIG6_HDMI_INFOFRAME_CONTROL1                                          0x4e12
2950#define SEA_mmHDMI_GENERIC_PACKET_CONTROL0                                          0x1c13
2951#define SEA_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                     0x1c13
2952#define SEA_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                     0x1f13
2953#define SEA_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                     0x4213
2954#define SEA_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                     0x4513
2955#define SEA_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                     0x4813
2956#define SEA_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0                                     0x4b13
2957#define SEA_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0                                     0x4e13
2958#define SEA_mmAFMT_INTERRUPT_STATUS                                                 0x1c14
2959#define SEA_mmDIG0_AFMT_INTERRUPT_STATUS                                            0x1c14
2960#define SEA_mmDIG1_AFMT_INTERRUPT_STATUS                                            0x1f14
2961#define SEA_mmDIG2_AFMT_INTERRUPT_STATUS                                            0x4214
2962#define SEA_mmDIG3_AFMT_INTERRUPT_STATUS                                            0x4514
2963#define SEA_mmDIG4_AFMT_INTERRUPT_STATUS                                            0x4814
2964#define SEA_mmDIG5_AFMT_INTERRUPT_STATUS                                            0x4b14
2965#define SEA_mmDIG6_AFMT_INTERRUPT_STATUS                                            0x4e14
2966#define SEA_mmHDMI_GC                                                               0x1c16
2967#define SEA_mmDIG0_HDMI_GC                                                          0x1c16
2968#define SEA_mmDIG1_HDMI_GC                                                          0x1f16
2969#define SEA_mmDIG2_HDMI_GC                                                          0x4216
2970#define SEA_mmDIG3_HDMI_GC                                                          0x4516
2971#define SEA_mmDIG4_HDMI_GC                                                          0x4816
2972#define SEA_mmDIG5_HDMI_GC                                                          0x4b16
2973#define SEA_mmDIG6_HDMI_GC                                                          0x4e16
2974#define SEA_mmAFMT_AUDIO_PACKET_CONTROL2                                            0x1c17
2975#define SEA_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2                                       0x1c17
2976#define SEA_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                                       0x1f17
2977#define SEA_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                                       0x4217
2978#define SEA_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                                       0x4517
2979#define SEA_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                                       0x4817
2980#define SEA_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2                                       0x4b17
2981#define SEA_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2                                       0x4e17
2982#define SEA_mmAFMT_ISRC1_0                                                          0x1c18
2983#define SEA_mmDIG0_AFMT_ISRC1_0                                                     0x1c18
2984#define SEA_mmDIG1_AFMT_ISRC1_0                                                     0x1f18
2985#define SEA_mmDIG2_AFMT_ISRC1_0                                                     0x4218
2986#define SEA_mmDIG3_AFMT_ISRC1_0                                                     0x4518
2987#define SEA_mmDIG4_AFMT_ISRC1_0                                                     0x4818
2988#define SEA_mmDIG5_AFMT_ISRC1_0                                                     0x4b18
2989#define SEA_mmDIG6_AFMT_ISRC1_0                                                     0x4e18
2990#define SEA_mmAFMT_ISRC1_1                                                          0x1c19
2991#define SEA_mmDIG0_AFMT_ISRC1_1                                                     0x1c19
2992#define SEA_mmDIG1_AFMT_ISRC1_1                                                     0x1f19
2993#define SEA_mmDIG2_AFMT_ISRC1_1                                                     0x4219
2994#define SEA_mmDIG3_AFMT_ISRC1_1                                                     0x4519
2995#define SEA_mmDIG4_AFMT_ISRC1_1                                                     0x4819
2996#define SEA_mmDIG5_AFMT_ISRC1_1                                                     0x4b19
2997#define SEA_mmDIG6_AFMT_ISRC1_1                                                     0x4e19
2998#define SEA_mmAFMT_ISRC1_2                                                          0x1c1a
2999#define SEA_mmDIG0_AFMT_ISRC1_2                                                     0x1c1a
3000#define SEA_mmDIG1_AFMT_ISRC1_2                                                     0x1f1a
3001#define SEA_mmDIG2_AFMT_ISRC1_2                                                     0x421a
3002#define SEA_mmDIG3_AFMT_ISRC1_2                                                     0x451a
3003#define SEA_mmDIG4_AFMT_ISRC1_2                                                     0x481a
3004#define SEA_mmDIG5_AFMT_ISRC1_2                                                     0x4b1a
3005#define SEA_mmDIG6_AFMT_ISRC1_2                                                     0x4e1a
3006#define SEA_mmAFMT_ISRC1_3                                                          0x1c1b
3007#define SEA_mmDIG0_AFMT_ISRC1_3                                                     0x1c1b
3008#define SEA_mmDIG1_AFMT_ISRC1_3                                                     0x1f1b
3009#define SEA_mmDIG2_AFMT_ISRC1_3                                                     0x421b
3010#define SEA_mmDIG3_AFMT_ISRC1_3                                                     0x451b
3011#define SEA_mmDIG4_AFMT_ISRC1_3                                                     0x481b
3012#define SEA_mmDIG5_AFMT_ISRC1_3                                                     0x4b1b
3013#define SEA_mmDIG6_AFMT_ISRC1_3                                                     0x4e1b
3014#define SEA_mmAFMT_ISRC1_4                                                          0x1c1c
3015#define SEA_mmDIG0_AFMT_ISRC1_4                                                     0x1c1c
3016#define SEA_mmDIG1_AFMT_ISRC1_4                                                     0x1f1c
3017#define SEA_mmDIG2_AFMT_ISRC1_4                                                     0x421c
3018#define SEA_mmDIG3_AFMT_ISRC1_4                                                     0x451c
3019#define SEA_mmDIG4_AFMT_ISRC1_4                                                     0x481c
3020#define SEA_mmDIG5_AFMT_ISRC1_4                                                     0x4b1c
3021#define SEA_mmDIG6_AFMT_ISRC1_4                                                     0x4e1c
3022#define SEA_mmAFMT_ISRC2_0                                                          0x1c1d
3023#define SEA_mmDIG0_AFMT_ISRC2_0                                                     0x1c1d
3024#define SEA_mmDIG1_AFMT_ISRC2_0                                                     0x1f1d
3025#define SEA_mmDIG2_AFMT_ISRC2_0                                                     0x421d
3026#define SEA_mmDIG3_AFMT_ISRC2_0                                                     0x451d
3027#define SEA_mmDIG4_AFMT_ISRC2_0                                                     0x481d
3028#define SEA_mmDIG5_AFMT_ISRC2_0                                                     0x4b1d
3029#define SEA_mmDIG6_AFMT_ISRC2_0                                                     0x4e1d
3030#define SEA_mmAFMT_ISRC2_1                                                          0x1c1e
3031#define SEA_mmDIG0_AFMT_ISRC2_1                                                     0x1c1e
3032#define SEA_mmDIG1_AFMT_ISRC2_1                                                     0x1f1e
3033#define SEA_mmDIG2_AFMT_ISRC2_1                                                     0x421e
3034#define SEA_mmDIG3_AFMT_ISRC2_1                                                     0x451e
3035#define SEA_mmDIG4_AFMT_ISRC2_1                                                     0x481e
3036#define SEA_mmDIG5_AFMT_ISRC2_1                                                     0x4b1e
3037#define SEA_mmDIG6_AFMT_ISRC2_1                                                     0x4e1e
3038#define SEA_mmAFMT_ISRC2_2                                                          0x1c1f
3039#define SEA_mmDIG0_AFMT_ISRC2_2                                                     0x1c1f
3040#define SEA_mmDIG1_AFMT_ISRC2_2                                                     0x1f1f
3041#define SEA_mmDIG2_AFMT_ISRC2_2                                                     0x421f
3042#define SEA_mmDIG3_AFMT_ISRC2_2                                                     0x451f
3043#define SEA_mmDIG4_AFMT_ISRC2_2                                                     0x481f
3044#define SEA_mmDIG5_AFMT_ISRC2_2                                                     0x4b1f
3045#define SEA_mmDIG6_AFMT_ISRC2_2                                                     0x4e1f
3046#define SEA_mmAFMT_ISRC2_3                                                          0x1c20
3047#define SEA_mmDIG0_AFMT_ISRC2_3                                                     0x1c20
3048#define SEA_mmDIG1_AFMT_ISRC2_3                                                     0x1f20
3049#define SEA_mmDIG2_AFMT_ISRC2_3                                                     0x4220
3050#define SEA_mmDIG3_AFMT_ISRC2_3                                                     0x4520
3051#define SEA_mmDIG4_AFMT_ISRC2_3                                                     0x4820
3052#define SEA_mmDIG5_AFMT_ISRC2_3                                                     0x4b20
3053#define SEA_mmDIG6_AFMT_ISRC2_3                                                     0x4e20
3054#define SEA_mmAFMT_AVI_INFO0                                                        0x1c21
3055#define SEA_mmDIG0_AFMT_AVI_INFO0                                                   0x1c21
3056#define SEA_mmDIG1_AFMT_AVI_INFO0                                                   0x1f21
3057#define SEA_mmDIG2_AFMT_AVI_INFO0                                                   0x4221
3058#define SEA_mmDIG3_AFMT_AVI_INFO0                                                   0x4521
3059#define SEA_mmDIG4_AFMT_AVI_INFO0                                                   0x4821
3060#define SEA_mmDIG5_AFMT_AVI_INFO0                                                   0x4b21
3061#define SEA_mmDIG6_AFMT_AVI_INFO0                                                   0x4e21
3062#define SEA_mmAFMT_AVI_INFO1                                                        0x1c22
3063#define SEA_mmDIG0_AFMT_AVI_INFO1                                                   0x1c22
3064#define SEA_mmDIG1_AFMT_AVI_INFO1                                                   0x1f22
3065#define SEA_mmDIG2_AFMT_AVI_INFO1                                                   0x4222
3066#define SEA_mmDIG3_AFMT_AVI_INFO1                                                   0x4522
3067#define SEA_mmDIG4_AFMT_AVI_INFO1                                                   0x4822
3068#define SEA_mmDIG5_AFMT_AVI_INFO1                                                   0x4b22
3069#define SEA_mmDIG6_AFMT_AVI_INFO1                                                   0x4e22
3070#define SEA_mmAFMT_AVI_INFO2                                                        0x1c23
3071#define SEA_mmDIG0_AFMT_AVI_INFO2                                                   0x1c23
3072#define SEA_mmDIG1_AFMT_AVI_INFO2                                                   0x1f23
3073#define SEA_mmDIG2_AFMT_AVI_INFO2                                                   0x4223
3074#define SEA_mmDIG3_AFMT_AVI_INFO2                                                   0x4523
3075#define SEA_mmDIG4_AFMT_AVI_INFO2                                                   0x4823
3076#define SEA_mmDIG5_AFMT_AVI_INFO2                                                   0x4b23
3077#define SEA_mmDIG6_AFMT_AVI_INFO2                                                   0x4e23
3078#define SEA_mmAFMT_AVI_INFO3                                                        0x1c24
3079#define SEA_mmDIG0_AFMT_AVI_INFO3                                                   0x1c24
3080#define SEA_mmDIG1_AFMT_AVI_INFO3                                                   0x1f24
3081#define SEA_mmDIG2_AFMT_AVI_INFO3                                                   0x4224
3082#define SEA_mmDIG3_AFMT_AVI_INFO3                                                   0x4524
3083#define SEA_mmDIG4_AFMT_AVI_INFO3                                                   0x4824
3084#define SEA_mmDIG5_AFMT_AVI_INFO3                                                   0x4b24
3085#define SEA_mmDIG6_AFMT_AVI_INFO3                                                   0x4e24
3086#define SEA_mmAFMT_MPEG_INFO0                                                       0x1c25
3087#define SEA_mmDIG0_AFMT_MPEG_INFO0                                                  0x1c25
3088#define SEA_mmDIG1_AFMT_MPEG_INFO0                                                  0x1f25
3089#define SEA_mmDIG2_AFMT_MPEG_INFO0                                                  0x4225
3090#define SEA_mmDIG3_AFMT_MPEG_INFO0                                                  0x4525
3091#define SEA_mmDIG4_AFMT_MPEG_INFO0                                                  0x4825
3092#define SEA_mmDIG5_AFMT_MPEG_INFO0                                                  0x4b25
3093#define SEA_mmDIG6_AFMT_MPEG_INFO0                                                  0x4e25
3094#define SEA_mmAFMT_MPEG_INFO1                                                       0x1c26
3095#define SEA_mmDIG0_AFMT_MPEG_INFO1                                                  0x1c26
3096#define SEA_mmDIG1_AFMT_MPEG_INFO1                                                  0x1f26
3097#define SEA_mmDIG2_AFMT_MPEG_INFO1                                                  0x4226
3098#define SEA_mmDIG3_AFMT_MPEG_INFO1                                                  0x4526
3099#define SEA_mmDIG4_AFMT_MPEG_INFO1                                                  0x4826
3100#define SEA_mmDIG5_AFMT_MPEG_INFO1                                                  0x4b26
3101#define SEA_mmDIG6_AFMT_MPEG_INFO1                                                  0x4e26
3102#define SEA_mmAFMT_GENERIC_HDR                                                      0x1c27
3103#define SEA_mmDIG0_AFMT_GENERIC_HDR                                                 0x1c27
3104#define SEA_mmDIG1_AFMT_GENERIC_HDR                                                 0x1f27
3105#define SEA_mmDIG2_AFMT_GENERIC_HDR                                                 0x4227
3106#define SEA_mmDIG3_AFMT_GENERIC_HDR                                                 0x4527
3107#define SEA_mmDIG4_AFMT_GENERIC_HDR                                                 0x4827
3108#define SEA_mmDIG5_AFMT_GENERIC_HDR                                                 0x4b27
3109#define SEA_mmDIG6_AFMT_GENERIC_HDR                                                 0x4e27
3110#define SEA_mmAFMT_GENERIC_0                                                        0x1c28
3111#define SEA_mmDIG0_AFMT_GENERIC_0                                                   0x1c28
3112#define SEA_mmDIG1_AFMT_GENERIC_0                                                   0x1f28
3113#define SEA_mmDIG2_AFMT_GENERIC_0                                                   0x4228
3114#define SEA_mmDIG3_AFMT_GENERIC_0                                                   0x4528
3115#define SEA_mmDIG4_AFMT_GENERIC_0                                                   0x4828
3116#define SEA_mmDIG5_AFMT_GENERIC_0                                                   0x4b28
3117#define SEA_mmDIG6_AFMT_GENERIC_0                                                   0x4e28
3118#define SEA_mmAFMT_GENERIC_1                                                        0x1c29
3119#define SEA_mmDIG0_AFMT_GENERIC_1                                                   0x1c29
3120#define SEA_mmDIG1_AFMT_GENERIC_1                                                   0x1f29
3121#define SEA_mmDIG2_AFMT_GENERIC_1                                                   0x4229
3122#define SEA_mmDIG3_AFMT_GENERIC_1                                                   0x4529
3123#define SEA_mmDIG4_AFMT_GENERIC_1                                                   0x4829
3124#define SEA_mmDIG5_AFMT_GENERIC_1                                                   0x4b29
3125#define SEA_mmDIG6_AFMT_GENERIC_1                                                   0x4e29
3126#define SEA_mmAFMT_GENERIC_2                                                        0x1c2a
3127#define SEA_mmDIG0_AFMT_GENERIC_2                                                   0x1c2a
3128#define SEA_mmDIG1_AFMT_GENERIC_2                                                   0x1f2a
3129#define SEA_mmDIG2_AFMT_GENERIC_2                                                   0x422a
3130#define SEA_mmDIG3_AFMT_GENERIC_2                                                   0x452a
3131#define SEA_mmDIG4_AFMT_GENERIC_2                                                   0x482a
3132#define SEA_mmDIG5_AFMT_GENERIC_2                                                   0x4b2a
3133#define SEA_mmDIG6_AFMT_GENERIC_2                                                   0x4e2a
3134#define SEA_mmAFMT_GENERIC_3                                                        0x1c2b
3135#define SEA_mmDIG0_AFMT_GENERIC_3                                                   0x1c2b
3136#define SEA_mmDIG1_AFMT_GENERIC_3                                                   0x1f2b
3137#define SEA_mmDIG2_AFMT_GENERIC_3                                                   0x422b
3138#define SEA_mmDIG3_AFMT_GENERIC_3                                                   0x452b
3139#define SEA_mmDIG4_AFMT_GENERIC_3                                                   0x482b
3140#define SEA_mmDIG5_AFMT_GENERIC_3                                                   0x4b2b
3141#define SEA_mmDIG6_AFMT_GENERIC_3                                                   0x4e2b
3142#define SEA_mmAFMT_GENERIC_4                                                        0x1c2c
3143#define SEA_mmDIG0_AFMT_GENERIC_4                                                   0x1c2c
3144#define SEA_mmDIG1_AFMT_GENERIC_4                                                   0x1f2c
3145#define SEA_mmDIG2_AFMT_GENERIC_4                                                   0x422c
3146#define SEA_mmDIG3_AFMT_GENERIC_4                                                   0x452c
3147#define SEA_mmDIG4_AFMT_GENERIC_4                                                   0x482c
3148#define SEA_mmDIG5_AFMT_GENERIC_4                                                   0x4b2c
3149#define SEA_mmDIG6_AFMT_GENERIC_4                                                   0x4e2c
3150#define SEA_mmAFMT_GENERIC_5                                                        0x1c2d
3151#define SEA_mmDIG0_AFMT_GENERIC_5                                                   0x1c2d
3152#define SEA_mmDIG1_AFMT_GENERIC_5                                                   0x1f2d
3153#define SEA_mmDIG2_AFMT_GENERIC_5                                                   0x422d
3154#define SEA_mmDIG3_AFMT_GENERIC_5                                                   0x452d
3155#define SEA_mmDIG4_AFMT_GENERIC_5                                                   0x482d
3156#define SEA_mmDIG5_AFMT_GENERIC_5                                                   0x4b2d
3157#define SEA_mmDIG6_AFMT_GENERIC_5                                                   0x4e2d
3158#define SEA_mmAFMT_GENERIC_6                                                        0x1c2e
3159#define SEA_mmDIG0_AFMT_GENERIC_6                                                   0x1c2e
3160#define SEA_mmDIG1_AFMT_GENERIC_6                                                   0x1f2e
3161#define SEA_mmDIG2_AFMT_GENERIC_6                                                   0x422e
3162#define SEA_mmDIG3_AFMT_GENERIC_6                                                   0x452e
3163#define SEA_mmDIG4_AFMT_GENERIC_6                                                   0x482e
3164#define SEA_mmDIG5_AFMT_GENERIC_6                                                   0x4b2e
3165#define SEA_mmDIG6_AFMT_GENERIC_6                                                   0x4e2e
3166#define SEA_mmAFMT_GENERIC_7                                                        0x1c2f
3167#define SEA_mmDIG0_AFMT_GENERIC_7                                                   0x1c2f
3168#define SEA_mmDIG1_AFMT_GENERIC_7                                                   0x1f2f
3169#define SEA_mmDIG2_AFMT_GENERIC_7                                                   0x422f
3170#define SEA_mmDIG3_AFMT_GENERIC_7                                                   0x452f
3171#define SEA_mmDIG4_AFMT_GENERIC_7                                                   0x482f
3172#define SEA_mmDIG5_AFMT_GENERIC_7                                                   0x4b2f
3173#define SEA_mmDIG6_AFMT_GENERIC_7                                                   0x4e2f
3174#define SEA_mmHDMI_GENERIC_PACKET_CONTROL1                                          0x1c30
3175#define SEA_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                     0x1c30
3176#define SEA_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                     0x1f30
3177#define SEA_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                     0x4230
3178#define SEA_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                     0x4530
3179#define SEA_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                     0x4830
3180#define SEA_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1                                     0x4b30
3181#define SEA_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1                                     0x4e30
3182#define SEA_mmHDMI_ACR_32_0                                                         0x1c37
3183#define SEA_mmDIG0_HDMI_ACR_32_0                                                    0x1c37
3184#define SEA_mmDIG1_HDMI_ACR_32_0                                                    0x1f37
3185#define SEA_mmDIG2_HDMI_ACR_32_0                                                    0x4237
3186#define SEA_mmDIG3_HDMI_ACR_32_0                                                    0x4537
3187#define SEA_mmDIG4_HDMI_ACR_32_0                                                    0x4837
3188#define SEA_mmDIG5_HDMI_ACR_32_0                                                    0x4b37
3189#define SEA_mmDIG6_HDMI_ACR_32_0                                                    0x4e37
3190#define SEA_mmHDMI_ACR_32_1                                                         0x1c38
3191#define SEA_mmDIG0_HDMI_ACR_32_1                                                    0x1c38
3192#define SEA_mmDIG1_HDMI_ACR_32_1                                                    0x1f38
3193#define SEA_mmDIG2_HDMI_ACR_32_1                                                    0x4238
3194#define SEA_mmDIG3_HDMI_ACR_32_1                                                    0x4538
3195#define SEA_mmDIG4_HDMI_ACR_32_1                                                    0x4838
3196#define SEA_mmDIG5_HDMI_ACR_32_1                                                    0x4b38
3197#define SEA_mmDIG6_HDMI_ACR_32_1                                                    0x4e38
3198#define SEA_mmHDMI_ACR_44_0                                                         0x1c39
3199#define SEA_mmDIG0_HDMI_ACR_44_0                                                    0x1c39
3200#define SEA_mmDIG1_HDMI_ACR_44_0                                                    0x1f39
3201#define SEA_mmDIG2_HDMI_ACR_44_0                                                    0x4239
3202#define SEA_mmDIG3_HDMI_ACR_44_0                                                    0x4539
3203#define SEA_mmDIG4_HDMI_ACR_44_0                                                    0x4839
3204#define SEA_mmDIG5_HDMI_ACR_44_0                                                    0x4b39
3205#define SEA_mmDIG6_HDMI_ACR_44_0                                                    0x4e39
3206#define SEA_mmHDMI_ACR_44_1                                                         0x1c3a
3207#define SEA_mmDIG0_HDMI_ACR_44_1                                                    0x1c3a
3208#define SEA_mmDIG1_HDMI_ACR_44_1                                                    0x1f3a
3209#define SEA_mmDIG2_HDMI_ACR_44_1                                                    0x423a
3210#define SEA_mmDIG3_HDMI_ACR_44_1                                                    0x453a
3211#define SEA_mmDIG4_HDMI_ACR_44_1                                                    0x483a
3212#define SEA_mmDIG5_HDMI_ACR_44_1                                                    0x4b3a
3213#define SEA_mmDIG6_HDMI_ACR_44_1                                                    0x4e3a
3214#define SEA_mmHDMI_ACR_48_0                                                         0x1c3b
3215#define SEA_mmDIG0_HDMI_ACR_48_0                                                    0x1c3b
3216#define SEA_mmDIG1_HDMI_ACR_48_0                                                    0x1f3b
3217#define SEA_mmDIG2_HDMI_ACR_48_0                                                    0x423b
3218#define SEA_mmDIG3_HDMI_ACR_48_0                                                    0x453b
3219#define SEA_mmDIG4_HDMI_ACR_48_0                                                    0x483b
3220#define SEA_mmDIG5_HDMI_ACR_48_0                                                    0x4b3b
3221#define SEA_mmDIG6_HDMI_ACR_48_0                                                    0x4e3b
3222#define SEA_mmHDMI_ACR_48_1                                                         0x1c3c
3223#define SEA_mmDIG0_HDMI_ACR_48_1                                                    0x1c3c
3224#define SEA_mmDIG1_HDMI_ACR_48_1                                                    0x1f3c
3225#define SEA_mmDIG2_HDMI_ACR_48_1                                                    0x423c
3226#define SEA_mmDIG3_HDMI_ACR_48_1                                                    0x453c
3227#define SEA_mmDIG4_HDMI_ACR_48_1                                                    0x483c
3228#define SEA_mmDIG5_HDMI_ACR_48_1                                                    0x4b3c
3229#define SEA_mmDIG6_HDMI_ACR_48_1                                                    0x4e3c
3230#define SEA_mmHDMI_ACR_STATUS_0                                                     0x1c3d
3231#define SEA_mmDIG0_HDMI_ACR_STATUS_0                                                0x1c3d
3232#define SEA_mmDIG1_HDMI_ACR_STATUS_0                                                0x1f3d
3233#define SEA_mmDIG2_HDMI_ACR_STATUS_0                                                0x423d
3234#define SEA_mmDIG3_HDMI_ACR_STATUS_0                                                0x453d
3235#define SEA_mmDIG4_HDMI_ACR_STATUS_0                                                0x483d
3236#define SEA_mmDIG5_HDMI_ACR_STATUS_0                                                0x4b3d
3237#define SEA_mmDIG6_HDMI_ACR_STATUS_0                                                0x4e3d
3238#define SEA_mmHDMI_ACR_STATUS_1                                                     0x1c3e
3239#define SEA_mmDIG0_HDMI_ACR_STATUS_1                                                0x1c3e
3240#define SEA_mmDIG1_HDMI_ACR_STATUS_1                                                0x1f3e
3241#define SEA_mmDIG2_HDMI_ACR_STATUS_1                                                0x423e
3242#define SEA_mmDIG3_HDMI_ACR_STATUS_1                                                0x453e
3243#define SEA_mmDIG4_HDMI_ACR_STATUS_1                                                0x483e
3244#define SEA_mmDIG5_HDMI_ACR_STATUS_1                                                0x4b3e
3245#define SEA_mmDIG6_HDMI_ACR_STATUS_1                                                0x4e3e
3246#define SEA_mmAFMT_AUDIO_INFO0                                                      0x1c3f
3247#define SEA_mmDIG0_AFMT_AUDIO_INFO0                                                 0x1c3f
3248#define SEA_mmDIG1_AFMT_AUDIO_INFO0                                                 0x1f3f
3249#define SEA_mmDIG2_AFMT_AUDIO_INFO0                                                 0x423f
3250#define SEA_mmDIG3_AFMT_AUDIO_INFO0                                                 0x453f
3251#define SEA_mmDIG4_AFMT_AUDIO_INFO0                                                 0x483f
3252#define SEA_mmDIG5_AFMT_AUDIO_INFO0                                                 0x4b3f
3253#define SEA_mmDIG6_AFMT_AUDIO_INFO0                                                 0x4e3f
3254#define SEA_mmAFMT_AUDIO_INFO1                                                      0x1c40
3255#define SEA_mmDIG0_AFMT_AUDIO_INFO1                                                 0x1c40
3256#define SEA_mmDIG1_AFMT_AUDIO_INFO1                                                 0x1f40
3257#define SEA_mmDIG2_AFMT_AUDIO_INFO1                                                 0x4240
3258#define SEA_mmDIG3_AFMT_AUDIO_INFO1                                                 0x4540
3259#define SEA_mmDIG4_AFMT_AUDIO_INFO1                                                 0x4840
3260#define SEA_mmDIG5_AFMT_AUDIO_INFO1                                                 0x4b40
3261#define SEA_mmDIG6_AFMT_AUDIO_INFO1                                                 0x4e40
3262#define SEA_mmAFMT_60958_0                                                          0x1c41
3263#define SEA_mmDIG0_AFMT_60958_0                                                     0x1c41
3264#define SEA_mmDIG1_AFMT_60958_0                                                     0x1f41
3265#define SEA_mmDIG2_AFMT_60958_0                                                     0x4241
3266#define SEA_mmDIG3_AFMT_60958_0                                                     0x4541
3267#define SEA_mmDIG4_AFMT_60958_0                                                     0x4841
3268#define SEA_mmDIG5_AFMT_60958_0                                                     0x4b41
3269#define SEA_mmDIG6_AFMT_60958_0                                                     0x4e41
3270#define SEA_mmAFMT_60958_1                                                          0x1c42
3271#define SEA_mmDIG0_AFMT_60958_1                                                     0x1c42
3272#define SEA_mmDIG1_AFMT_60958_1                                                     0x1f42
3273#define SEA_mmDIG2_AFMT_60958_1                                                     0x4242
3274#define SEA_mmDIG3_AFMT_60958_1                                                     0x4542
3275#define SEA_mmDIG4_AFMT_60958_1                                                     0x4842
3276#define SEA_mmDIG5_AFMT_60958_1                                                     0x4b42
3277#define SEA_mmDIG6_AFMT_60958_1                                                     0x4e42
3278#define SEA_mmAFMT_AUDIO_CRC_CONTROL                                                0x1c43
3279#define SEA_mmDIG0_AFMT_AUDIO_CRC_CONTROL                                           0x1c43
3280#define SEA_mmDIG1_AFMT_AUDIO_CRC_CONTROL                                           0x1f43
3281#define SEA_mmDIG2_AFMT_AUDIO_CRC_CONTROL                                           0x4243
3282#define SEA_mmDIG3_AFMT_AUDIO_CRC_CONTROL                                           0x4543
3283#define SEA_mmDIG4_AFMT_AUDIO_CRC_CONTROL                                           0x4843
3284#define SEA_mmDIG5_AFMT_AUDIO_CRC_CONTROL                                           0x4b43
3285#define SEA_mmDIG6_AFMT_AUDIO_CRC_CONTROL                                           0x4e43
3286#define SEA_mmAFMT_RAMP_CONTROL0                                                    0x1c44
3287#define SEA_mmDIG0_AFMT_RAMP_CONTROL0                                               0x1c44
3288#define SEA_mmDIG1_AFMT_RAMP_CONTROL0                                               0x1f44
3289#define SEA_mmDIG2_AFMT_RAMP_CONTROL0                                               0x4244
3290#define SEA_mmDIG3_AFMT_RAMP_CONTROL0                                               0x4544
3291#define SEA_mmDIG4_AFMT_RAMP_CONTROL0                                               0x4844
3292#define SEA_mmDIG5_AFMT_RAMP_CONTROL0                                               0x4b44
3293#define SEA_mmDIG6_AFMT_RAMP_CONTROL0                                               0x4e44
3294#define SEA_mmAFMT_RAMP_CONTROL1                                                    0x1c45
3295#define SEA_mmDIG0_AFMT_RAMP_CONTROL1                                               0x1c45
3296#define SEA_mmDIG1_AFMT_RAMP_CONTROL1                                               0x1f45
3297#define SEA_mmDIG2_AFMT_RAMP_CONTROL1                                               0x4245
3298#define SEA_mmDIG3_AFMT_RAMP_CONTROL1                                               0x4545
3299#define SEA_mmDIG4_AFMT_RAMP_CONTROL1                                               0x4845
3300#define SEA_mmDIG5_AFMT_RAMP_CONTROL1                                               0x4b45
3301#define SEA_mmDIG6_AFMT_RAMP_CONTROL1                                               0x4e45
3302#define SEA_mmAFMT_RAMP_CONTROL2                                                    0x1c46
3303#define SEA_mmDIG0_AFMT_RAMP_CONTROL2                                               0x1c46
3304#define SEA_mmDIG1_AFMT_RAMP_CONTROL2                                               0x1f46
3305#define SEA_mmDIG2_AFMT_RAMP_CONTROL2                                               0x4246
3306#define SEA_mmDIG3_AFMT_RAMP_CONTROL2                                               0x4546
3307#define SEA_mmDIG4_AFMT_RAMP_CONTROL2                                               0x4846
3308#define SEA_mmDIG5_AFMT_RAMP_CONTROL2                                               0x4b46
3309#define SEA_mmDIG6_AFMT_RAMP_CONTROL2                                               0x4e46
3310#define SEA_mmAFMT_RAMP_CONTROL3                                                    0x1c47
3311#define SEA_mmDIG0_AFMT_RAMP_CONTROL3                                               0x1c47
3312#define SEA_mmDIG1_AFMT_RAMP_CONTROL3                                               0x1f47
3313#define SEA_mmDIG2_AFMT_RAMP_CONTROL3                                               0x4247
3314#define SEA_mmDIG3_AFMT_RAMP_CONTROL3                                               0x4547
3315#define SEA_mmDIG4_AFMT_RAMP_CONTROL3                                               0x4847
3316#define SEA_mmDIG5_AFMT_RAMP_CONTROL3                                               0x4b47
3317#define SEA_mmDIG6_AFMT_RAMP_CONTROL3                                               0x4e47
3318#define SEA_mmAFMT_60958_2                                                          0x1c48
3319#define SEA_mmDIG0_AFMT_60958_2                                                     0x1c48
3320#define SEA_mmDIG1_AFMT_60958_2                                                     0x1f48
3321#define SEA_mmDIG2_AFMT_60958_2                                                     0x4248
3322#define SEA_mmDIG3_AFMT_60958_2                                                     0x4548
3323#define SEA_mmDIG4_AFMT_60958_2                                                     0x4848
3324#define SEA_mmDIG5_AFMT_60958_2                                                     0x4b48
3325#define SEA_mmDIG6_AFMT_60958_2                                                     0x4e48
3326#define SEA_mmAFMT_AUDIO_CRC_RESULT                                                 0x1c49
3327#define SEA_mmDIG0_AFMT_AUDIO_CRC_RESULT                                            0x1c49
3328#define SEA_mmDIG1_AFMT_AUDIO_CRC_RESULT                                            0x1f49
3329#define SEA_mmDIG2_AFMT_AUDIO_CRC_RESULT                                            0x4249
3330#define SEA_mmDIG3_AFMT_AUDIO_CRC_RESULT                                            0x4549
3331#define SEA_mmDIG4_AFMT_AUDIO_CRC_RESULT                                            0x4849
3332#define SEA_mmDIG5_AFMT_AUDIO_CRC_RESULT                                            0x4b49
3333#define SEA_mmDIG6_AFMT_AUDIO_CRC_RESULT                                            0x4e49
3334#define SEA_mmAFMT_STATUS                                                           0x1c4a
3335#define SEA_mmDIG0_AFMT_STATUS                                                      0x1c4a
3336#define SEA_mmDIG1_AFMT_STATUS                                                      0x1f4a
3337#define SEA_mmDIG2_AFMT_STATUS                                                      0x424a
3338#define SEA_mmDIG3_AFMT_STATUS                                                      0x454a
3339#define SEA_mmDIG4_AFMT_STATUS                                                      0x484a
3340#define SEA_mmDIG5_AFMT_STATUS                                                      0x4b4a
3341#define SEA_mmDIG6_AFMT_STATUS                                                      0x4e4a
3342#define SEA_mmAFMT_AUDIO_PACKET_CONTROL                                             0x1c4b
3343#define SEA_mmDIG0_AFMT_AUDIO_PACKET_CONTROL                                        0x1c4b
3344#define SEA_mmDIG1_AFMT_AUDIO_PACKET_CONTROL                                        0x1f4b
3345#define SEA_mmDIG2_AFMT_AUDIO_PACKET_CONTROL                                        0x424b
3346#define SEA_mmDIG3_AFMT_AUDIO_PACKET_CONTROL                                        0x454b
3347#define SEA_mmDIG4_AFMT_AUDIO_PACKET_CONTROL                                        0x484b
3348#define SEA_mmDIG5_AFMT_AUDIO_PACKET_CONTROL                                        0x4b4b
3349#define SEA_mmDIG6_AFMT_AUDIO_PACKET_CONTROL                                        0x4e4b
3350#define SEA_mmAFMT_VBI_PACKET_CONTROL                                               0x1c4c
3351#define SEA_mmDIG0_AFMT_VBI_PACKET_CONTROL                                          0x1c4c
3352#define SEA_mmDIG1_AFMT_VBI_PACKET_CONTROL                                          0x1f4c
3353#define SEA_mmDIG2_AFMT_VBI_PACKET_CONTROL                                          0x424c
3354#define SEA_mmDIG3_AFMT_VBI_PACKET_CONTROL                                          0x454c
3355#define SEA_mmDIG4_AFMT_VBI_PACKET_CONTROL                                          0x484c
3356#define SEA_mmDIG5_AFMT_VBI_PACKET_CONTROL                                          0x4b4c
3357#define SEA_mmDIG6_AFMT_VBI_PACKET_CONTROL                                          0x4e4c
3358#define SEA_mmAFMT_INFOFRAME_CONTROL0                                               0x1c4d
3359#define SEA_mmDIG0_AFMT_INFOFRAME_CONTROL0                                          0x1c4d
3360#define SEA_mmDIG1_AFMT_INFOFRAME_CONTROL0                                          0x1f4d
3361#define SEA_mmDIG2_AFMT_INFOFRAME_CONTROL0                                          0x424d
3362#define SEA_mmDIG3_AFMT_INFOFRAME_CONTROL0                                          0x454d
3363#define SEA_mmDIG4_AFMT_INFOFRAME_CONTROL0                                          0x484d
3364#define SEA_mmDIG5_AFMT_INFOFRAME_CONTROL0                                          0x4b4d
3365#define SEA_mmDIG6_AFMT_INFOFRAME_CONTROL0                                          0x4e4d
3366#define SEA_mmAFMT_AUDIO_SRC_CONTROL                                                0x1c4f
3367#define SEA_mmDIG0_AFMT_AUDIO_SRC_CONTROL                                           0x1c4f
3368#define SEA_mmDIG1_AFMT_AUDIO_SRC_CONTROL                                           0x1f4f
3369#define SEA_mmDIG2_AFMT_AUDIO_SRC_CONTROL                                           0x424f
3370#define SEA_mmDIG3_AFMT_AUDIO_SRC_CONTROL                                           0x454f
3371#define SEA_mmDIG4_AFMT_AUDIO_SRC_CONTROL                                           0x484f
3372#define SEA_mmDIG5_AFMT_AUDIO_SRC_CONTROL                                           0x4b4f
3373#define SEA_mmDIG6_AFMT_AUDIO_SRC_CONTROL                                           0x4e4f
3374#define SEA_mmAFMT_AUDIO_DBG_DTO_CNTL                                               0x1c52
3375#define SEA_mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL                                          0x1c52
3376#define SEA_mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL                                          0x1f52
3377#define SEA_mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4252
3378#define SEA_mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4552
3379#define SEA_mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4852
3380#define SEA_mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4b52
3381#define SEA_mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4e52
3382#define SEA_mmDIG_BE_CNTL                                                           0x1c50
3383#define SEA_mmDIG0_DIG_BE_CNTL                                                      0x1c50
3384#define SEA_mmDIG1_DIG_BE_CNTL                                                      0x1f50
3385#define SEA_mmDIG2_DIG_BE_CNTL                                                      0x4250
3386#define SEA_mmDIG3_DIG_BE_CNTL                                                      0x4550
3387#define SEA_mmDIG4_DIG_BE_CNTL                                                      0x4850
3388#define SEA_mmDIG5_DIG_BE_CNTL                                                      0x4b50
3389#define SEA_mmDIG6_DIG_BE_CNTL                                                      0x4e50
3390#define SEA_mmDIG_BE_EN_CNTL                                                        0x1c51
3391#define SEA_mmDIG0_DIG_BE_EN_CNTL                                                   0x1c51
3392#define SEA_mmDIG1_DIG_BE_EN_CNTL                                                   0x1f51
3393#define SEA_mmDIG2_DIG_BE_EN_CNTL                                                   0x4251
3394#define SEA_mmDIG3_DIG_BE_EN_CNTL                                                   0x4551
3395#define SEA_mmDIG4_DIG_BE_EN_CNTL                                                   0x4851
3396#define SEA_mmDIG5_DIG_BE_EN_CNTL                                                   0x4b51
3397#define SEA_mmDIG6_DIG_BE_EN_CNTL                                                   0x4e51
3398#define SEA_mmTMDS_CNTL                                                             0x1c7c
3399#define SEA_mmDIG0_TMDS_CNTL                                                        0x1c7c
3400#define SEA_mmDIG1_TMDS_CNTL                                                        0x1f7c
3401#define SEA_mmDIG2_TMDS_CNTL                                                        0x427c
3402#define SEA_mmDIG3_TMDS_CNTL                                                        0x457c
3403#define SEA_mmDIG4_TMDS_CNTL                                                        0x487c
3404#define SEA_mmDIG5_TMDS_CNTL                                                        0x4b7c
3405#define SEA_mmDIG6_TMDS_CNTL                                                        0x4e7c
3406#define SEA_mmTMDS_CONTROL_CHAR                                                     0x1c7d
3407#define SEA_mmDIG0_TMDS_CONTROL_CHAR                                                0x1c7d
3408#define SEA_mmDIG1_TMDS_CONTROL_CHAR                                                0x1f7d
3409#define SEA_mmDIG2_TMDS_CONTROL_CHAR                                                0x427d
3410#define SEA_mmDIG3_TMDS_CONTROL_CHAR                                                0x457d
3411#define SEA_mmDIG4_TMDS_CONTROL_CHAR                                                0x487d
3412#define SEA_mmDIG5_TMDS_CONTROL_CHAR                                                0x4b7d
3413#define SEA_mmDIG6_TMDS_CONTROL_CHAR                                                0x4e7d
3414#define SEA_mmTMDS_CONTROL0_FEEDBACK                                                0x1c7e
3415#define SEA_mmDIG0_TMDS_CONTROL0_FEEDBACK                                           0x1c7e
3416#define SEA_mmDIG1_TMDS_CONTROL0_FEEDBACK                                           0x1f7e
3417#define SEA_mmDIG2_TMDS_CONTROL0_FEEDBACK                                           0x427e
3418#define SEA_mmDIG3_TMDS_CONTROL0_FEEDBACK                                           0x457e
3419#define SEA_mmDIG4_TMDS_CONTROL0_FEEDBACK                                           0x487e
3420#define SEA_mmDIG5_TMDS_CONTROL0_FEEDBACK                                           0x4b7e
3421#define SEA_mmDIG6_TMDS_CONTROL0_FEEDBACK                                           0x4e7e
3422#define SEA_mmTMDS_STEREOSYNC_CTL_SEL                                               0x1c7f
3423#define SEA_mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                          0x1c7f
3424#define SEA_mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                          0x1f7f
3425#define SEA_mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                          0x427f
3426#define SEA_mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                          0x457f
3427#define SEA_mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                          0x487f
3428#define SEA_mmDIG5_TMDS_STEREOSYNC_CTL_SEL                                          0x4b7f
3429#define SEA_mmDIG6_TMDS_STEREOSYNC_CTL_SEL                                          0x4e7f
3430#define SEA_mmTMDS_SYNC_CHAR_PATTERN_0_1                                            0x1c80
3431#define SEA_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x1c80
3432#define SEA_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x1f80
3433#define SEA_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4280
3434#define SEA_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4580
3435#define SEA_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4880
3436#define SEA_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4b80
3437#define SEA_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4e80
3438#define SEA_mmTMDS_SYNC_CHAR_PATTERN_2_3                                            0x1c81
3439#define SEA_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x1c81
3440#define SEA_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x1f81
3441#define SEA_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4281
3442#define SEA_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4581
3443#define SEA_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4881
3444#define SEA_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4b81
3445#define SEA_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4e81
3446#define SEA_mmTMDS_DEBUG                                                            0x1c82
3447#define SEA_mmDIG0_TMDS_DEBUG                                                       0x1c82
3448#define SEA_mmDIG1_TMDS_DEBUG                                                       0x1f82
3449#define SEA_mmDIG2_TMDS_DEBUG                                                       0x4282
3450#define SEA_mmDIG3_TMDS_DEBUG                                                       0x4582
3451#define SEA_mmDIG4_TMDS_DEBUG                                                       0x4882
3452#define SEA_mmDIG5_TMDS_DEBUG                                                       0x4b82
3453#define SEA_mmDIG6_TMDS_DEBUG                                                       0x4e82
3454#define SEA_mmTMDS_CTL_BITS                                                         0x1c83
3455#define SEA_mmDIG0_TMDS_CTL_BITS                                                    0x1c83
3456#define SEA_mmDIG1_TMDS_CTL_BITS                                                    0x1f83
3457#define SEA_mmDIG2_TMDS_CTL_BITS                                                    0x4283
3458#define SEA_mmDIG3_TMDS_CTL_BITS                                                    0x4583
3459#define SEA_mmDIG4_TMDS_CTL_BITS                                                    0x4883
3460#define SEA_mmDIG5_TMDS_CTL_BITS                                                    0x4b83
3461#define SEA_mmDIG6_TMDS_CTL_BITS                                                    0x4e83
3462#define SEA_mmTMDS_DCBALANCER_CONTROL                                               0x1c84
3463#define SEA_mmDIG0_TMDS_DCBALANCER_CONTROL                                          0x1c84
3464#define SEA_mmDIG1_TMDS_DCBALANCER_CONTROL                                          0x1f84
3465#define SEA_mmDIG2_TMDS_DCBALANCER_CONTROL                                          0x4284
3466#define SEA_mmDIG3_TMDS_DCBALANCER_CONTROL                                          0x4584
3467#define SEA_mmDIG4_TMDS_DCBALANCER_CONTROL                                          0x4884
3468#define SEA_mmDIG5_TMDS_DCBALANCER_CONTROL                                          0x4b84
3469#define SEA_mmDIG6_TMDS_DCBALANCER_CONTROL                                          0x4e84
3470#define SEA_mmTMDS_CTL0_1_GEN_CNTL                                                  0x1c86
3471#define SEA_mmDIG0_TMDS_CTL0_1_GEN_CNTL                                             0x1c86
3472#define SEA_mmDIG1_TMDS_CTL0_1_GEN_CNTL                                             0x1f86
3473#define SEA_mmDIG2_TMDS_CTL0_1_GEN_CNTL                                             0x4286
3474#define SEA_mmDIG3_TMDS_CTL0_1_GEN_CNTL                                             0x4586
3475#define SEA_mmDIG4_TMDS_CTL0_1_GEN_CNTL                                             0x4886
3476#define SEA_mmDIG5_TMDS_CTL0_1_GEN_CNTL                                             0x4b86
3477#define SEA_mmDIG6_TMDS_CTL0_1_GEN_CNTL                                             0x4e86
3478#define SEA_mmTMDS_CTL2_3_GEN_CNTL                                                  0x1c87
3479#define SEA_mmDIG0_TMDS_CTL2_3_GEN_CNTL                                             0x1c87
3480#define SEA_mmDIG1_TMDS_CTL2_3_GEN_CNTL                                             0x1f87
3481#define SEA_mmDIG2_TMDS_CTL2_3_GEN_CNTL                                             0x4287
3482#define SEA_mmDIG3_TMDS_CTL2_3_GEN_CNTL                                             0x4587
3483#define SEA_mmDIG4_TMDS_CTL2_3_GEN_CNTL                                             0x4887
3484#define SEA_mmDIG5_TMDS_CTL2_3_GEN_CNTL                                             0x4b87
3485#define SEA_mmDIG6_TMDS_CTL2_3_GEN_CNTL                                             0x4e87
3486#define SEA_mmLVDS_DATA_CNTL                                                        0x1c8c
3487#define SEA_mmDIG0_LVDS_DATA_CNTL                                                   0x1c8c
3488#define SEA_mmDIG1_LVDS_DATA_CNTL                                                   0x1f8c
3489#define SEA_mmDIG2_LVDS_DATA_CNTL                                                   0x428c
3490#define SEA_mmDIG3_LVDS_DATA_CNTL                                                   0x458c
3491#define SEA_mmDIG4_LVDS_DATA_CNTL                                                   0x488c
3492#define SEA_mmDIG5_LVDS_DATA_CNTL                                                   0x4b8c
3493#define SEA_mmDIG6_LVDS_DATA_CNTL                                                   0x4e8c
3494#define SEA_mmDIG_LANE_ENABLE                                                       0x1c8d
3495#define SEA_mmDIG0_DIG_LANE_ENABLE                                                  0x1c8d
3496#define SEA_mmDIG1_DIG_LANE_ENABLE                                                  0x1f8d
3497#define SEA_mmDIG2_DIG_LANE_ENABLE                                                  0x428d
3498#define SEA_mmDIG3_DIG_LANE_ENABLE                                                  0x458d
3499#define SEA_mmDIG4_DIG_LANE_ENABLE                                                  0x488d
3500#define SEA_mmDIG5_DIG_LANE_ENABLE                                                  0x4b8d
3501#define SEA_mmDIG6_DIG_LANE_ENABLE                                                  0x4e8d
3502#define SEA_mmDOUT_SCRATCH0                                                         0x1844
3503#define SEA_mmDOUT_SCRATCH1                                                         0x1845
3504#define SEA_mmDOUT_SCRATCH2                                                         0x1846
3505#define SEA_mmDOUT_SCRATCH3                                                         0x1847
3506#define SEA_mmDOUT_SCRATCH4                                                         0x1848
3507#define SEA_mmDOUT_SCRATCH5                                                         0x1849
3508#define SEA_mmDOUT_SCRATCH6                                                         0x184a
3509#define SEA_mmDOUT_SCRATCH7                                                         0x184b
3510#define SEA_mmDOUT_DCE_VCE_CONTROL                                                  0x18ff
3511#define SEA_mmDC_HPD1_INT_STATUS                                                    0x1807
3512#define SEA_mmDC_HPD1_INT_CONTROL                                                   0x1808
3513#define SEA_mmDC_HPD1_CONTROL                                                       0x1809
3514#define SEA_mmDC_HPD2_INT_STATUS                                                    0x180a
3515#define SEA_mmDC_HPD2_INT_CONTROL                                                   0x180b
3516#define SEA_mmDC_HPD2_CONTROL                                                       0x180c
3517#define SEA_mmDC_HPD3_INT_STATUS                                                    0x180d
3518#define SEA_mmDC_HPD3_INT_CONTROL                                                   0x180e
3519#define SEA_mmDC_HPD3_CONTROL                                                       0x180f
3520#define SEA_mmDC_HPD4_INT_STATUS                                                    0x1810
3521#define SEA_mmDC_HPD4_INT_CONTROL                                                   0x1811
3522#define SEA_mmDC_HPD4_CONTROL                                                       0x1812
3523#define SEA_mmDC_HPD5_INT_STATUS                                                    0x1813
3524#define SEA_mmDC_HPD5_INT_CONTROL                                                   0x1814
3525#define SEA_mmDC_HPD5_CONTROL                                                       0x1815
3526#define SEA_mmDC_HPD6_INT_STATUS                                                    0x1816
3527#define SEA_mmDC_HPD6_INT_CONTROL                                                   0x1817
3528#define SEA_mmDC_HPD6_CONTROL                                                       0x1818
3529#define SEA_mmDC_HPD1_FAST_TRAIN_CNTL                                               0x1864
3530#define SEA_mmDC_HPD2_FAST_TRAIN_CNTL                                               0x1865
3531#define SEA_mmDC_HPD3_FAST_TRAIN_CNTL                                               0x1866
3532#define SEA_mmDC_HPD4_FAST_TRAIN_CNTL                                               0x1867
3533#define SEA_mmDC_HPD5_FAST_TRAIN_CNTL                                               0x1868
3534#define SEA_mmDC_HPD6_FAST_TRAIN_CNTL                                               0x1869
3535#define SEA_mmDC_HPD1_TOGGLE_FILT_CNTL                                              0x18bc
3536#define SEA_mmDC_HPD2_TOGGLE_FILT_CNTL                                              0x18bd
3537#define SEA_mmDC_HPD3_TOGGLE_FILT_CNTL                                              0x18be
3538#define SEA_mmDC_HPD4_TOGGLE_FILT_CNTL                                              0x18fc
3539#define SEA_mmDC_HPD5_TOGGLE_FILT_CNTL                                              0x18fd
3540#define SEA_mmDC_HPD6_TOGGLE_FILT_CNTL                                              0x18fe
3541#define SEA_mmDC_I2C_CONTROL                                                        0x1819
3542#define SEA_mmDC_I2C_ARBITRATION                                                    0x181a
3543#define SEA_mmDC_I2C_INTERRUPT_CONTROL                                              0x181b
3544#define SEA_mmDC_I2C_SW_STATUS                                                      0x181c
3545#define SEA_mmDC_I2C_DDC1_HW_STATUS                                                 0x181d
3546#define SEA_mmDC_I2C_DDC2_HW_STATUS                                                 0x181e
3547#define SEA_mmDC_I2C_DDC3_HW_STATUS                                                 0x181f
3548#define SEA_mmDC_I2C_DDC4_HW_STATUS                                                 0x1820
3549#define SEA_mmDC_I2C_DDC5_HW_STATUS                                                 0x1821
3550#define SEA_mmDC_I2C_DDC6_HW_STATUS                                                 0x1822
3551#define SEA_mmDC_I2C_DDC1_SPEED                                                     0x1823
3552#define SEA_mmDC_I2C_DDC1_SETUP                                                     0x1824
3553#define SEA_mmDC_I2C_DDC2_SPEED                                                     0x1825
3554#define SEA_mmDC_I2C_DDC2_SETUP                                                     0x1826
3555#define SEA_mmDC_I2C_DDC3_SPEED                                                     0x1827
3556#define SEA_mmDC_I2C_DDC3_SETUP                                                     0x1828
3557#define SEA_mmDC_I2C_DDC4_SPEED                                                     0x1829
3558#define SEA_mmDC_I2C_DDC4_SETUP                                                     0x182a
3559#define SEA_mmDC_I2C_DDC5_SPEED                                                     0x182b
3560#define SEA_mmDC_I2C_DDC5_SETUP                                                     0x182c
3561#define SEA_mmDC_I2C_DDC6_SPEED                                                     0x182d
3562#define SEA_mmDC_I2C_DDC6_SETUP                                                     0x182e
3563#define SEA_mmDC_I2C_TRANSACTION0                                                   0x182f
3564#define SEA_mmDC_I2C_TRANSACTION1                                                   0x1830
3565#define SEA_mmDC_I2C_TRANSACTION2                                                   0x1831
3566#define SEA_mmDC_I2C_TRANSACTION3                                                   0x1832
3567#define SEA_mmDC_I2C_DATA                                                           0x1833
3568#define SEA_mmGENERIC_I2C_CONTROL                                                   0x1834
3569#define SEA_mmGENERIC_I2C_INTERRUPT_CONTROL                                         0x1835
3570#define SEA_mmGENERIC_I2C_STATUS                                                    0x1836
3571#define SEA_mmGENERIC_I2C_SPEED                                                     0x1837
3572#define SEA_mmGENERIC_I2C_SETUP                                                     0x1838
3573#define SEA_mmGENERIC_I2C_TRANSACTION                                               0x1839
3574#define SEA_mmGENERIC_I2C_DATA                                                      0x183a
3575#define SEA_mmGENERIC_I2C_PIN_SELECTION                                             0x183b
3576#define SEA_mmGENERIC_I2C_PIN_DEBUG                                                 0x183c
3577#define SEA_mmDISP_INTERRUPT_STATUS                                                 0x183d
3578#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE                                        0x183e
3579#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE2                                       0x183f
3580#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE3                                       0x1840
3581#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE4                                       0x1853
3582#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE5                                       0x1854
3583#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE6                                       0x19e0
3584#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE7                                       0x19e1
3585#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE8                                       0x19e2
3586#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE9                                       0x19e3
3587#define SEA_mmDOUT_POWER_MANAGEMENT_CNTL                                            0x1841
3588#define SEA_mmDISP_TIMER_CONTROL                                                    0x1842
3589#define SEA_mmDC_I2C_DDCVGA_HW_STATUS                                               0x1855
3590#define SEA_mmDC_I2C_DDCVGA_SPEED                                                   0x1856
3591#define SEA_mmDC_I2C_DDCVGA_SETUP                                                   0x1857
3592#define SEA_mmDC_I2C_EDID_DETECT_CTRL                                               0x186f
3593#define SEA_mmDISPOUT_STEREOSYNC_SEL                                                0x18bf
3594#define SEA_mmDOUT_TEST_DEBUG_INDEX                                                 0x184d
3595#define SEA_mmDOUT_TEST_DEBUG_DATA                                                  0x184e
3596#define SEA_ixDP_AUX1_DEBUG_A                                                       0x10
3597#define SEA_ixDP_AUX1_DEBUG_B                                                       0x11
3598#define SEA_ixDP_AUX1_DEBUG_C                                                       0x12
3599#define SEA_ixDP_AUX1_DEBUG_D                                                       0x13
3600#define SEA_ixDP_AUX1_DEBUG_E                                                       0x14
3601#define SEA_ixDP_AUX1_DEBUG_F                                                       0x15
3602#define SEA_ixDP_AUX1_DEBUG_G                                                       0x16
3603#define SEA_ixDP_AUX1_DEBUG_H                                                       0x17
3604#define SEA_ixDP_AUX1_DEBUG_I                                                       0x18
3605#define SEA_ixDP_AUX1_DEBUG_J                                                       0x19
3606#define SEA_ixDP_AUX1_DEBUG_K                                                       0x1a
3607#define SEA_ixDP_AUX1_DEBUG_L                                                       0x1b
3608#define SEA_ixDP_AUX1_DEBUG_M                                                       0x1c
3609#define SEA_ixDP_AUX1_DEBUG_N                                                       0x1d
3610#define SEA_ixDP_AUX1_DEBUG_O                                                       0x1e
3611#define SEA_ixDP_AUX1_DEBUG_P                                                       0x1f
3612#define SEA_ixDP_AUX1_DEBUG_Q                                                       0x90
3613#define SEA_ixDP_AUX2_DEBUG_A                                                       0x20
3614#define SEA_ixDP_AUX2_DEBUG_B                                                       0x21
3615#define SEA_ixDP_AUX2_DEBUG_C                                                       0x22
3616#define SEA_ixDP_AUX2_DEBUG_D                                                       0x23
3617#define SEA_ixDP_AUX2_DEBUG_E                                                       0x24
3618#define SEA_ixDP_AUX2_DEBUG_F                                                       0x25
3619#define SEA_ixDP_AUX2_DEBUG_G                                                       0x26
3620#define SEA_ixDP_AUX2_DEBUG_H                                                       0x27
3621#define SEA_ixDP_AUX2_DEBUG_I                                                       0x28
3622#define SEA_ixDP_AUX2_DEBUG_J                                                       0x29
3623#define SEA_ixDP_AUX2_DEBUG_K                                                       0x2a
3624#define SEA_ixDP_AUX2_DEBUG_L                                                       0x2b
3625#define SEA_ixDP_AUX2_DEBUG_M                                                       0x2c
3626#define SEA_ixDP_AUX2_DEBUG_N                                                       0x2d
3627#define SEA_ixDP_AUX2_DEBUG_O                                                       0x2e
3628#define SEA_ixDP_AUX2_DEBUG_P                                                       0x2f
3629#define SEA_ixDP_AUX2_DEBUG_Q                                                       0x91
3630#define SEA_ixDP_AUX3_DEBUG_A                                                       0x30
3631#define SEA_ixDP_AUX3_DEBUG_B                                                       0x31
3632#define SEA_ixDP_AUX3_DEBUG_C                                                       0x32
3633#define SEA_ixDP_AUX3_DEBUG_D                                                       0x33
3634#define SEA_ixDP_AUX3_DEBUG_E                                                       0x34
3635#define SEA_ixDP_AUX3_DEBUG_F                                                       0x35
3636#define SEA_ixDP_AUX3_DEBUG_G                                                       0x36
3637#define SEA_ixDP_AUX3_DEBUG_H                                                       0x37
3638#define SEA_ixDP_AUX3_DEBUG_I                                                       0x38
3639#define SEA_ixDP_AUX3_DEBUG_J                                                       0x39
3640#define SEA_ixDP_AUX3_DEBUG_K                                                       0x3a
3641#define SEA_ixDP_AUX3_DEBUG_L                                                       0x3b
3642#define SEA_ixDP_AUX3_DEBUG_M                                                       0x3c
3643#define SEA_ixDP_AUX3_DEBUG_N                                                       0x3d
3644#define SEA_ixDP_AUX3_DEBUG_O                                                       0x3e
3645#define SEA_ixDP_AUX3_DEBUG_P                                                       0x3f
3646#define SEA_ixDP_AUX3_DEBUG_Q                                                       0x92
3647#define SEA_ixDP_AUX4_DEBUG_A                                                       0x40
3648#define SEA_ixDP_AUX4_DEBUG_B                                                       0x41
3649#define SEA_ixDP_AUX4_DEBUG_C                                                       0x42
3650#define SEA_ixDP_AUX4_DEBUG_D                                                       0x43
3651#define SEA_ixDP_AUX4_DEBUG_E                                                       0x44
3652#define SEA_ixDP_AUX4_DEBUG_F                                                       0x45
3653#define SEA_ixDP_AUX4_DEBUG_G                                                       0x46
3654#define SEA_ixDP_AUX4_DEBUG_H                                                       0x47
3655#define SEA_ixDP_AUX4_DEBUG_I                                                       0x48
3656#define SEA_ixDP_AUX4_DEBUG_J                                                       0x49
3657#define SEA_ixDP_AUX4_DEBUG_K                                                       0x4a
3658#define SEA_ixDP_AUX4_DEBUG_L                                                       0x4b
3659#define SEA_ixDP_AUX4_DEBUG_M                                                       0x4c
3660#define SEA_ixDP_AUX4_DEBUG_N                                                       0x4d
3661#define SEA_ixDP_AUX4_DEBUG_O                                                       0x4e
3662#define SEA_ixDP_AUX4_DEBUG_P                                                       0x4f
3663#define SEA_ixDP_AUX4_DEBUG_Q                                                       0x93
3664#define SEA_ixDP_AUX5_DEBUG_A                                                       0x70
3665#define SEA_ixDP_AUX5_DEBUG_B                                                       0x71
3666#define SEA_ixDP_AUX5_DEBUG_C                                                       0x72
3667#define SEA_ixDP_AUX5_DEBUG_D                                                       0x73
3668#define SEA_ixDP_AUX5_DEBUG_E                                                       0x74
3669#define SEA_ixDP_AUX5_DEBUG_F                                                       0x75
3670#define SEA_ixDP_AUX5_DEBUG_G                                                       0x76
3671#define SEA_ixDP_AUX5_DEBUG_H                                                       0x77
3672#define SEA_ixDP_AUX5_DEBUG_I                                                       0x78
3673#define SEA_ixDP_AUX5_DEBUG_J                                                       0x79
3674#define SEA_ixDP_AUX5_DEBUG_K                                                       0x7a
3675#define SEA_ixDP_AUX5_DEBUG_L                                                       0x7b
3676#define SEA_ixDP_AUX5_DEBUG_M                                                       0x7c
3677#define SEA_ixDP_AUX5_DEBUG_N                                                       0x7d
3678#define SEA_ixDP_AUX5_DEBUG_O                                                       0x7f
3679#define SEA_ixDP_AUX5_DEBUG_P                                                       0x94
3680#define SEA_ixDP_AUX5_DEBUG_Q                                                       0x95
3681#define SEA_ixDP_AUX6_DEBUG_A                                                       0x80
3682#define SEA_ixDP_AUX6_DEBUG_B                                                       0x81
3683#define SEA_ixDP_AUX6_DEBUG_C                                                       0x82
3684#define SEA_ixDP_AUX6_DEBUG_D                                                       0x83
3685#define SEA_ixDP_AUX6_DEBUG_E                                                       0x84
3686#define SEA_ixDP_AUX6_DEBUG_F                                                       0x85
3687#define SEA_ixDP_AUX6_DEBUG_G                                                       0x86
3688#define SEA_ixDP_AUX6_DEBUG_H                                                       0x87
3689#define SEA_ixDP_AUX6_DEBUG_I                                                       0x88
3690#define SEA_ixDP_AUX6_DEBUG_J                                                       0x89
3691#define SEA_ixDP_AUX6_DEBUG_K                                                       0x8a
3692#define SEA_ixDP_AUX6_DEBUG_L                                                       0x8b
3693#define SEA_ixDP_AUX6_DEBUG_M                                                       0x8c
3694#define SEA_ixDP_AUX6_DEBUG_N                                                       0x8d
3695#define SEA_ixDP_AUX6_DEBUG_O                                                       0x8f
3696#define SEA_ixDP_AUX6_DEBUG_P                                                       0x96
3697#define SEA_ixDP_AUX6_DEBUG_Q                                                       0x97
3698#define SEA_mmDMCU_CTRL                                                             0x1600
3699#define SEA_mmDMCU_STATUS                                                           0x1601
3700#define SEA_mmDMCU_PC_START_ADDR                                                    0x1602
3701#define SEA_mmDMCU_FW_START_ADDR                                                    0x1603
3702#define SEA_mmDMCU_FW_END_ADDR                                                      0x1604
3703#define SEA_mmDMCU_FW_ISR_START_ADDR                                                0x1605
3704#define SEA_mmDMCU_FW_CS_HI                                                         0x1606
3705#define SEA_mmDMCU_FW_CS_LO                                                         0x1607
3706#define SEA_mmDMCU_RAM_ACCESS_CTRL                                                  0x1608
3707#define SEA_mmDMCU_ERAM_WR_CTRL                                                     0x1609
3708#define SEA_mmDMCU_ERAM_WR_DATA                                                     0x160a
3709#define SEA_mmDMCU_ERAM_RD_CTRL                                                     0x160b
3710#define SEA_mmDMCU_ERAM_RD_DATA                                                     0x160c
3711#define SEA_mmDMCU_IRAM_WR_CTRL                                                     0x160d
3712#define SEA_mmDMCU_IRAM_WR_DATA                                                     0x160e
3713#define SEA_mmDMCU_IRAM_RD_CTRL                                                     0x160f
3714#define SEA_mmDMCU_IRAM_RD_DATA                                                     0x1610
3715#define SEA_mmDMCU_EVENT_TRIGGER                                                    0x1611
3716#define SEA_mmDMCU_UC_INTERNAL_INT_STATUS                                           0x1612
3717#define SEA_mmDMCU_SS_INTERRUPT_CNTL_STATUS                                         0x1613
3718#define SEA_mmDMCU_INTERRUPT_STATUS                                                 0x1614
3719#define SEA_mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                        0x1615
3720#define SEA_mmDMCU_INTERRUPT_TO_UC_EN_MASK                                          0x1616
3721#define SEA_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                     0x1617
3722#define SEA_mmDC_DMCU_SCRATCH                                                       0x1618
3723#define SEA_mmDMCU_INT_CNT                                                          0x1619
3724#define SEA_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                        0x161a
3725#define SEA_mmDMCU_UC_CLK_GATING_CNTL                                               0x161b
3726#define SEA_mmMASTER_COMM_DATA_REG1                                                 0x161c
3727#define SEA_mmMASTER_COMM_DATA_REG2                                                 0x161d
3728#define SEA_mmMASTER_COMM_DATA_REG3                                                 0x161e
3729#define SEA_mmMASTER_COMM_CMD_REG                                                   0x161f
3730#define SEA_mmMASTER_COMM_CNTL_REG                                                  0x1620
3731#define SEA_mmSLAVE_COMM_DATA_REG1                                                  0x1621
3732#define SEA_mmSLAVE_COMM_DATA_REG2                                                  0x1622
3733#define SEA_mmSLAVE_COMM_DATA_REG3                                                  0x1623
3734#define SEA_mmSLAVE_COMM_CMD_REG                                                    0x1624
3735#define SEA_mmSLAVE_COMM_CNTL_REG                                                   0x1625
3736#define SEA_mmDMCU_TEST_DEBUG_INDEX                                                 0x1626
3737#define SEA_mmDMCU_TEST_DEBUG_DATA                                                  0x1627
3738#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS1                                        0x1750
3739#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS2                                        0x1751
3740#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS3                                        0x1752
3741#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS4                                        0x1753
3742#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                 0x1754
3743#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                 0x1755
3744#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                 0x1756
3745#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                 0x1757
3746#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                            0x1758
3747#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                            0x1759
3748#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                            0x175a
3749#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                            0x175b
3750#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1                               0x175c
3751#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2                               0x175d
3752#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3                               0x175e
3753#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4                               0x175f
3754#define SEA_mmDP_LINK_CNTL                                                          0x1cc0
3755#define SEA_mmDP0_DP_LINK_CNTL                                                      0x1cc0
3756#define SEA_mmDP1_DP_LINK_CNTL                                                      0x1fc0
3757#define SEA_mmDP2_DP_LINK_CNTL                                                      0x42c0
3758#define SEA_mmDP3_DP_LINK_CNTL                                                      0x45c0
3759#define SEA_mmDP4_DP_LINK_CNTL                                                      0x48c0
3760#define SEA_mmDP5_DP_LINK_CNTL                                                      0x4bc0
3761#define SEA_mmDP6_DP_LINK_CNTL                                                      0x4ec0
3762#define SEA_mmDP_PIXEL_FORMAT                                                       0x1cc1
3763#define SEA_mmDP0_DP_PIXEL_FORMAT                                                   0x1cc1
3764#define SEA_mmDP1_DP_PIXEL_FORMAT                                                   0x1fc1
3765#define SEA_mmDP2_DP_PIXEL_FORMAT                                                   0x42c1
3766#define SEA_mmDP3_DP_PIXEL_FORMAT                                                   0x45c1
3767#define SEA_mmDP4_DP_PIXEL_FORMAT                                                   0x48c1
3768#define SEA_mmDP5_DP_PIXEL_FORMAT                                                   0x4bc1
3769#define SEA_mmDP6_DP_PIXEL_FORMAT                                                   0x4ec1
3770#define SEA_mmDP_MSA_COLORIMETRY                                                    0x1cda
3771#define SEA_mmDP0_DP_MSA_COLORIMETRY                                                0x1cda
3772#define SEA_mmDP1_DP_MSA_COLORIMETRY                                                0x1fda
3773#define SEA_mmDP2_DP_MSA_COLORIMETRY                                                0x42da
3774#define SEA_mmDP3_DP_MSA_COLORIMETRY                                                0x45da
3775#define SEA_mmDP4_DP_MSA_COLORIMETRY                                                0x48da
3776#define SEA_mmDP5_DP_MSA_COLORIMETRY                                                0x4bda
3777#define SEA_mmDP6_DP_MSA_COLORIMETRY                                                0x4eda
3778#define SEA_mmDP_CONFIG                                                             0x1cc2
3779#define SEA_mmDP0_DP_CONFIG                                                         0x1cc2
3780#define SEA_mmDP1_DP_CONFIG                                                         0x1fc2
3781#define SEA_mmDP2_DP_CONFIG                                                         0x42c2
3782#define SEA_mmDP3_DP_CONFIG                                                         0x45c2
3783#define SEA_mmDP4_DP_CONFIG                                                         0x48c2
3784#define SEA_mmDP5_DP_CONFIG                                                         0x4bc2
3785#define SEA_mmDP6_DP_CONFIG                                                         0x4ec2
3786#define SEA_mmDP_VID_STREAM_CNTL                                                    0x1cc3
3787#define SEA_mmDP0_DP_VID_STREAM_CNTL                                                0x1cc3
3788#define SEA_mmDP1_DP_VID_STREAM_CNTL                                                0x1fc3
3789#define SEA_mmDP2_DP_VID_STREAM_CNTL                                                0x42c3
3790#define SEA_mmDP3_DP_VID_STREAM_CNTL                                                0x45c3
3791#define SEA_mmDP4_DP_VID_STREAM_CNTL                                                0x48c3
3792#define SEA_mmDP5_DP_VID_STREAM_CNTL                                                0x4bc3
3793#define SEA_mmDP6_DP_VID_STREAM_CNTL                                                0x4ec3
3794#define SEA_mmDP_STEER_FIFO                                                         0x1cc4
3795#define SEA_mmDP0_DP_STEER_FIFO                                                     0x1cc4
3796#define SEA_mmDP1_DP_STEER_FIFO                                                     0x1fc4
3797#define SEA_mmDP2_DP_STEER_FIFO                                                     0x42c4
3798#define SEA_mmDP3_DP_STEER_FIFO                                                     0x45c4
3799#define SEA_mmDP4_DP_STEER_FIFO                                                     0x48c4
3800#define SEA_mmDP5_DP_STEER_FIFO                                                     0x4bc4
3801#define SEA_mmDP6_DP_STEER_FIFO                                                     0x4ec4
3802#define SEA_mmDP_MSA_MISC                                                           0x1cc5
3803#define SEA_mmDP0_DP_MSA_MISC                                                       0x1cc5
3804#define SEA_mmDP1_DP_MSA_MISC                                                       0x1fc5
3805#define SEA_mmDP2_DP_MSA_MISC                                                       0x42c5
3806#define SEA_mmDP3_DP_MSA_MISC                                                       0x45c5
3807#define SEA_mmDP4_DP_MSA_MISC                                                       0x48c5
3808#define SEA_mmDP5_DP_MSA_MISC                                                       0x4bc5
3809#define SEA_mmDP6_DP_MSA_MISC                                                       0x4ec5
3810#define SEA_mmDP_VID_TIMING                                                         0x1cc9
3811#define SEA_mmDP0_DP_VID_TIMING                                                     0x1cc9
3812#define SEA_mmDP1_DP_VID_TIMING                                                     0x1fc9
3813#define SEA_mmDP2_DP_VID_TIMING                                                     0x42c9
3814#define SEA_mmDP3_DP_VID_TIMING                                                     0x45c9
3815#define SEA_mmDP4_DP_VID_TIMING                                                     0x48c9
3816#define SEA_mmDP5_DP_VID_TIMING                                                     0x4bc9
3817#define SEA_mmDP6_DP_VID_TIMING                                                     0x4ec9
3818#define SEA_mmDP_VID_N                                                              0x1cca
3819#define SEA_mmDP0_DP_VID_N                                                          0x1cca
3820#define SEA_mmDP1_DP_VID_N                                                          0x1fca
3821#define SEA_mmDP2_DP_VID_N                                                          0x42ca
3822#define SEA_mmDP3_DP_VID_N                                                          0x45ca
3823#define SEA_mmDP4_DP_VID_N                                                          0x48ca
3824#define SEA_mmDP5_DP_VID_N                                                          0x4bca
3825#define SEA_mmDP6_DP_VID_N                                                          0x4eca
3826#define SEA_mmDP_VID_M                                                              0x1ccb
3827#define SEA_mmDP0_DP_VID_M                                                          0x1ccb
3828#define SEA_mmDP1_DP_VID_M                                                          0x1fcb
3829#define SEA_mmDP2_DP_VID_M                                                          0x42cb
3830#define SEA_mmDP3_DP_VID_M                                                          0x45cb
3831#define SEA_mmDP4_DP_VID_M                                                          0x48cb
3832#define SEA_mmDP5_DP_VID_M                                                          0x4bcb
3833#define SEA_mmDP6_DP_VID_M                                                          0x4ecb
3834#define SEA_mmDP_LINK_FRAMING_CNTL                                                  0x1ccc
3835#define SEA_mmDP0_DP_LINK_FRAMING_CNTL                                              0x1ccc
3836#define SEA_mmDP1_DP_LINK_FRAMING_CNTL                                              0x1fcc
3837#define SEA_mmDP2_DP_LINK_FRAMING_CNTL                                              0x42cc
3838#define SEA_mmDP3_DP_LINK_FRAMING_CNTL                                              0x45cc
3839#define SEA_mmDP4_DP_LINK_FRAMING_CNTL                                              0x48cc
3840#define SEA_mmDP5_DP_LINK_FRAMING_CNTL                                              0x4bcc
3841#define SEA_mmDP6_DP_LINK_FRAMING_CNTL                                              0x4ecc
3842#define SEA_mmDP_HBR2_EYE_PATTERN                                                   0x1cc8
3843#define SEA_mmDP0_DP_HBR2_EYE_PATTERN                                               0x1cc8
3844#define SEA_mmDP1_DP_HBR2_EYE_PATTERN                                               0x1fc8
3845#define SEA_mmDP2_DP_HBR2_EYE_PATTERN                                               0x42c8
3846#define SEA_mmDP3_DP_HBR2_EYE_PATTERN                                               0x45c8
3847#define SEA_mmDP4_DP_HBR2_EYE_PATTERN                                               0x48c8
3848#define SEA_mmDP5_DP_HBR2_EYE_PATTERN                                               0x4bc8
3849#define SEA_mmDP6_DP_HBR2_EYE_PATTERN                                               0x4ec8
3850#define SEA_mmDP_VID_MSA_VBID                                                       0x1ccd
3851#define SEA_mmDP0_DP_VID_MSA_VBID                                                   0x1ccd
3852#define SEA_mmDP1_DP_VID_MSA_VBID                                                   0x1fcd
3853#define SEA_mmDP2_DP_VID_MSA_VBID                                                   0x42cd
3854#define SEA_mmDP3_DP_VID_MSA_VBID                                                   0x45cd
3855#define SEA_mmDP4_DP_VID_MSA_VBID                                                   0x48cd
3856#define SEA_mmDP5_DP_VID_MSA_VBID                                                   0x4bcd
3857#define SEA_mmDP6_DP_VID_MSA_VBID                                                   0x4ecd
3858#define SEA_mmDP_VID_INTERRUPT_CNTL                                                 0x1ccf
3859#define SEA_mmDP0_DP_VID_INTERRUPT_CNTL                                             0x1ccf
3860#define SEA_mmDP1_DP_VID_INTERRUPT_CNTL                                             0x1fcf
3861#define SEA_mmDP2_DP_VID_INTERRUPT_CNTL                                             0x42cf
3862#define SEA_mmDP3_DP_VID_INTERRUPT_CNTL                                             0x45cf
3863#define SEA_mmDP4_DP_VID_INTERRUPT_CNTL                                             0x48cf
3864#define SEA_mmDP5_DP_VID_INTERRUPT_CNTL                                             0x4bcf
3865#define SEA_mmDP6_DP_VID_INTERRUPT_CNTL                                             0x4ecf
3866#define SEA_mmDP_DPHY_CNTL                                                          0x1cd0
3867#define SEA_mmDP0_DP_DPHY_CNTL                                                      0x1cd0
3868#define SEA_mmDP1_DP_DPHY_CNTL                                                      0x1fd0
3869#define SEA_mmDP2_DP_DPHY_CNTL                                                      0x42d0
3870#define SEA_mmDP3_DP_DPHY_CNTL                                                      0x45d0
3871#define SEA_mmDP4_DP_DPHY_CNTL                                                      0x48d0
3872#define SEA_mmDP5_DP_DPHY_CNTL                                                      0x4bd0
3873#define SEA_mmDP6_DP_DPHY_CNTL                                                      0x4ed0
3874#define SEA_mmDP_DPHY_TRAINING_PATTERN_SEL                                          0x1cd1
3875#define SEA_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                      0x1cd1
3876#define SEA_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                      0x1fd1
3877#define SEA_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                      0x42d1
3878#define SEA_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                      0x45d1
3879#define SEA_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                      0x48d1
3880#define SEA_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4bd1
3881#define SEA_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4ed1
3882#define SEA_mmDP_DPHY_SYM0                                                          0x1cd2
3883#define SEA_mmDP0_DP_DPHY_SYM0                                                      0x1cd2
3884#define SEA_mmDP1_DP_DPHY_SYM0                                                      0x1fd2
3885#define SEA_mmDP2_DP_DPHY_SYM0                                                      0x42d2
3886#define SEA_mmDP3_DP_DPHY_SYM0                                                      0x45d2
3887#define SEA_mmDP4_DP_DPHY_SYM0                                                      0x48d2
3888#define SEA_mmDP5_DP_DPHY_SYM0                                                      0x4bd2
3889#define SEA_mmDP6_DP_DPHY_SYM0                                                      0x4ed2
3890#define SEA_mmDP_DPHY_SYM1                                                          0x1ce0
3891#define SEA_mmDP0_DP_DPHY_SYM1                                                      0x1ce0
3892#define SEA_mmDP1_DP_DPHY_SYM1                                                      0x1fe0
3893#define SEA_mmDP2_DP_DPHY_SYM1                                                      0x42e0
3894#define SEA_mmDP3_DP_DPHY_SYM1                                                      0x45e0
3895#define SEA_mmDP4_DP_DPHY_SYM1                                                      0x48e0
3896#define SEA_mmDP5_DP_DPHY_SYM1                                                      0x4be0
3897#define SEA_mmDP6_DP_DPHY_SYM1                                                      0x4ee0
3898#define SEA_mmDP_DPHY_SYM2                                                          0x1cdf
3899#define SEA_mmDP0_DP_DPHY_SYM2                                                      0x1cdf
3900#define SEA_mmDP1_DP_DPHY_SYM2                                                      0x1fdf
3901#define SEA_mmDP2_DP_DPHY_SYM2                                                      0x42df
3902#define SEA_mmDP3_DP_DPHY_SYM2                                                      0x45df
3903#define SEA_mmDP4_DP_DPHY_SYM2                                                      0x48df
3904#define SEA_mmDP5_DP_DPHY_SYM2                                                      0x4bdf
3905#define SEA_mmDP6_DP_DPHY_SYM2                                                      0x4edf
3906#define SEA_mmDP_DPHY_8B10B_CNTL                                                    0x1cd3
3907#define SEA_mmDP0_DP_DPHY_8B10B_CNTL                                                0x1cd3
3908#define SEA_mmDP1_DP_DPHY_8B10B_CNTL                                                0x1fd3
3909#define SEA_mmDP2_DP_DPHY_8B10B_CNTL                                                0x42d3
3910#define SEA_mmDP3_DP_DPHY_8B10B_CNTL                                                0x45d3
3911#define SEA_mmDP4_DP_DPHY_8B10B_CNTL                                                0x48d3
3912#define SEA_mmDP5_DP_DPHY_8B10B_CNTL                                                0x4bd3
3913#define SEA_mmDP6_DP_DPHY_8B10B_CNTL                                                0x4ed3
3914#define SEA_mmDP_DPHY_PRBS_CNTL                                                     0x1cd4
3915#define SEA_mmDP0_DP_DPHY_PRBS_CNTL                                                 0x1cd4
3916#define SEA_mmDP1_DP_DPHY_PRBS_CNTL                                                 0x1fd4
3917#define SEA_mmDP2_DP_DPHY_PRBS_CNTL                                                 0x42d4
3918#define SEA_mmDP3_DP_DPHY_PRBS_CNTL                                                 0x45d4
3919#define SEA_mmDP4_DP_DPHY_PRBS_CNTL                                                 0x48d4
3920#define SEA_mmDP5_DP_DPHY_PRBS_CNTL                                                 0x4bd4
3921#define SEA_mmDP6_DP_DPHY_PRBS_CNTL                                                 0x4ed4
3922#define SEA_mmDP_DPHY_CRC_EN                                                        0x1cd6
3923#define SEA_mmDP0_DP_DPHY_CRC_EN                                                    0x1cd6
3924#define SEA_mmDP1_DP_DPHY_CRC_EN                                                    0x1fd6
3925#define SEA_mmDP2_DP_DPHY_CRC_EN                                                    0x42d6
3926#define SEA_mmDP3_DP_DPHY_CRC_EN                                                    0x45d6
3927#define SEA_mmDP4_DP_DPHY_CRC_EN                                                    0x48d6
3928#define SEA_mmDP5_DP_DPHY_CRC_EN                                                    0x4bd6
3929#define SEA_mmDP6_DP_DPHY_CRC_EN                                                    0x4ed6
3930#define SEA_mmDP_DPHY_CRC_CNTL                                                      0x1cd7
3931#define SEA_mmDP0_DP_DPHY_CRC_CNTL                                                  0x1cd7
3932#define SEA_mmDP1_DP_DPHY_CRC_CNTL                                                  0x1fd7
3933#define SEA_mmDP2_DP_DPHY_CRC_CNTL                                                  0x42d7
3934#define SEA_mmDP3_DP_DPHY_CRC_CNTL                                                  0x45d7
3935#define SEA_mmDP4_DP_DPHY_CRC_CNTL                                                  0x48d7
3936#define SEA_mmDP5_DP_DPHY_CRC_CNTL                                                  0x4bd7
3937#define SEA_mmDP6_DP_DPHY_CRC_CNTL                                                  0x4ed7
3938#define SEA_mmDP_DPHY_CRC_RESULT                                                    0x1cd8
3939#define SEA_mmDP0_DP_DPHY_CRC_RESULT                                                0x1cd8
3940#define SEA_mmDP1_DP_DPHY_CRC_RESULT                                                0x1fd8
3941#define SEA_mmDP2_DP_DPHY_CRC_RESULT                                                0x42d8
3942#define SEA_mmDP3_DP_DPHY_CRC_RESULT                                                0x45d8
3943#define SEA_mmDP4_DP_DPHY_CRC_RESULT                                                0x48d8
3944#define SEA_mmDP5_DP_DPHY_CRC_RESULT                                                0x4bd8
3945#define SEA_mmDP6_DP_DPHY_CRC_RESULT                                                0x4ed8
3946#define SEA_mmDP_DPHY_CRC_MST_CNTL                                                  0x1cc6
3947#define SEA_mmDP0_DP_DPHY_CRC_MST_CNTL                                              0x1cc6
3948#define SEA_mmDP1_DP_DPHY_CRC_MST_CNTL                                              0x1fc6
3949#define SEA_mmDP2_DP_DPHY_CRC_MST_CNTL                                              0x42c6
3950#define SEA_mmDP3_DP_DPHY_CRC_MST_CNTL                                              0x45c6
3951#define SEA_mmDP4_DP_DPHY_CRC_MST_CNTL                                              0x48c6
3952#define SEA_mmDP5_DP_DPHY_CRC_MST_CNTL                                              0x4bc6
3953#define SEA_mmDP6_DP_DPHY_CRC_MST_CNTL                                              0x4ec6
3954#define SEA_mmDP_DPHY_CRC_MST_STATUS                                                0x1cc7
3955#define SEA_mmDP0_DP_DPHY_CRC_MST_STATUS                                            0x1cc7
3956#define SEA_mmDP1_DP_DPHY_CRC_MST_STATUS                                            0x1fc7
3957#define SEA_mmDP2_DP_DPHY_CRC_MST_STATUS                                            0x42c7
3958#define SEA_mmDP3_DP_DPHY_CRC_MST_STATUS                                            0x45c7
3959#define SEA_mmDP4_DP_DPHY_CRC_MST_STATUS                                            0x48c7
3960#define SEA_mmDP5_DP_DPHY_CRC_MST_STATUS                                            0x4bc7
3961#define SEA_mmDP6_DP_DPHY_CRC_MST_STATUS                                            0x4ec7
3962#define SEA_mmDP_DPHY_FAST_TRAINING                                                 0x1cce
3963#define SEA_mmDP0_DP_DPHY_FAST_TRAINING                                             0x1cce
3964#define SEA_mmDP1_DP_DPHY_FAST_TRAINING                                             0x1fce
3965#define SEA_mmDP2_DP_DPHY_FAST_TRAINING                                             0x42ce
3966#define SEA_mmDP3_DP_DPHY_FAST_TRAINING                                             0x45ce
3967#define SEA_mmDP4_DP_DPHY_FAST_TRAINING                                             0x48ce
3968#define SEA_mmDP5_DP_DPHY_FAST_TRAINING                                             0x4bce
3969#define SEA_mmDP6_DP_DPHY_FAST_TRAINING                                             0x4ece
3970#define SEA_mmDP_DPHY_FAST_TRAINING_STATUS                                          0x1ce9
3971#define SEA_mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                      0x1ce9
3972#define SEA_mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                      0x1fe9
3973#define SEA_mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                      0x42e9
3974#define SEA_mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                      0x45e9
3975#define SEA_mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                      0x48e9
3976#define SEA_mmDP5_DP_DPHY_FAST_TRAINING_STATUS                                      0x4be9
3977#define SEA_mmDP6_DP_DPHY_FAST_TRAINING_STATUS                                      0x4ee9
3978#define SEA_mmDP_MSA_V_TIMING_OVERRIDE1                                             0x1cea
3979#define SEA_mmDP0_DP_MSA_V_TIMING_OVERRIDE1                                         0x1cea
3980#define SEA_mmDP1_DP_MSA_V_TIMING_OVERRIDE1                                         0x1fea
3981#define SEA_mmDP2_DP_MSA_V_TIMING_OVERRIDE1                                         0x42ea
3982#define SEA_mmDP3_DP_MSA_V_TIMING_OVERRIDE1                                         0x45ea
3983#define SEA_mmDP4_DP_MSA_V_TIMING_OVERRIDE1                                         0x48ea
3984#define SEA_mmDP5_DP_MSA_V_TIMING_OVERRIDE1                                         0x4bea
3985#define SEA_mmDP6_DP_MSA_V_TIMING_OVERRIDE1                                         0x4eea
3986#define SEA_mmDP_MSA_V_TIMING_OVERRIDE2                                             0x1ceb
3987#define SEA_mmDP0_DP_MSA_V_TIMING_OVERRIDE2                                         0x1ceb
3988#define SEA_mmDP1_DP_MSA_V_TIMING_OVERRIDE2                                         0x1feb
3989#define SEA_mmDP2_DP_MSA_V_TIMING_OVERRIDE2                                         0x42eb
3990#define SEA_mmDP3_DP_MSA_V_TIMING_OVERRIDE2                                         0x45eb
3991#define SEA_mmDP4_DP_MSA_V_TIMING_OVERRIDE2                                         0x48eb
3992#define SEA_mmDP5_DP_MSA_V_TIMING_OVERRIDE2                                         0x4beb
3993#define SEA_mmDP6_DP_MSA_V_TIMING_OVERRIDE2                                         0x4eeb
3994#define SEA_mmDP_SEC_CNTL                                                           0x1ca0
3995#define SEA_mmDP0_DP_SEC_CNTL                                                       0x1ca0
3996#define SEA_mmDP1_DP_SEC_CNTL                                                       0x1fa0
3997#define SEA_mmDP2_DP_SEC_CNTL                                                       0x42a0
3998#define SEA_mmDP3_DP_SEC_CNTL                                                       0x45a0
3999#define SEA_mmDP4_DP_SEC_CNTL                                                       0x48a0
4000#define SEA_mmDP5_DP_SEC_CNTL                                                       0x4ba0
4001#define SEA_mmDP6_DP_SEC_CNTL                                                       0x4ea0
4002#define SEA_mmDP_SEC_CNTL1                                                          0x1cab
4003#define SEA_mmDP0_DP_SEC_CNTL1                                                      0x1cab
4004#define SEA_mmDP1_DP_SEC_CNTL1                                                      0x1fab
4005#define SEA_mmDP2_DP_SEC_CNTL1                                                      0x42ab
4006#define SEA_mmDP3_DP_SEC_CNTL1                                                      0x45ab
4007#define SEA_mmDP4_DP_SEC_CNTL1                                                      0x48ab
4008#define SEA_mmDP5_DP_SEC_CNTL1                                                      0x4bab
4009#define SEA_mmDP6_DP_SEC_CNTL1                                                      0x4eab
4010#define SEA_mmDP_SEC_FRAMING1                                                       0x1ca1
4011#define SEA_mmDP0_DP_SEC_FRAMING1                                                   0x1ca1
4012#define SEA_mmDP1_DP_SEC_FRAMING1                                                   0x1fa1
4013#define SEA_mmDP2_DP_SEC_FRAMING1                                                   0x42a1
4014#define SEA_mmDP3_DP_SEC_FRAMING1                                                   0x45a1
4015#define SEA_mmDP4_DP_SEC_FRAMING1                                                   0x48a1
4016#define SEA_mmDP5_DP_SEC_FRAMING1                                                   0x4ba1
4017#define SEA_mmDP6_DP_SEC_FRAMING1                                                   0x4ea1
4018#define SEA_mmDP_SEC_FRAMING2                                                       0x1ca2
4019#define SEA_mmDP0_DP_SEC_FRAMING2                                                   0x1ca2
4020#define SEA_mmDP1_DP_SEC_FRAMING2                                                   0x1fa2
4021#define SEA_mmDP2_DP_SEC_FRAMING2                                                   0x42a2
4022#define SEA_mmDP3_DP_SEC_FRAMING2                                                   0x45a2
4023#define SEA_mmDP4_DP_SEC_FRAMING2                                                   0x48a2
4024#define SEA_mmDP5_DP_SEC_FRAMING2                                                   0x4ba2
4025#define SEA_mmDP6_DP_SEC_FRAMING2                                                   0x4ea2
4026#define SEA_mmDP_SEC_FRAMING3                                                       0x1ca3
4027#define SEA_mmDP0_DP_SEC_FRAMING3                                                   0x1ca3
4028#define SEA_mmDP1_DP_SEC_FRAMING3                                                   0x1fa3
4029#define SEA_mmDP2_DP_SEC_FRAMING3                                                   0x42a3
4030#define SEA_mmDP3_DP_SEC_FRAMING3                                                   0x45a3
4031#define SEA_mmDP4_DP_SEC_FRAMING3                                                   0x48a3
4032#define SEA_mmDP5_DP_SEC_FRAMING3                                                   0x4ba3
4033#define SEA_mmDP6_DP_SEC_FRAMING3                                                   0x4ea3
4034#define SEA_mmDP_SEC_FRAMING4                                                       0x1ca4
4035#define SEA_mmDP0_DP_SEC_FRAMING4                                                   0x1ca4
4036#define SEA_mmDP1_DP_SEC_FRAMING4                                                   0x1fa4
4037#define SEA_mmDP2_DP_SEC_FRAMING4                                                   0x42a4
4038#define SEA_mmDP3_DP_SEC_FRAMING4                                                   0x45a4
4039#define SEA_mmDP4_DP_SEC_FRAMING4                                                   0x48a4
4040#define SEA_mmDP5_DP_SEC_FRAMING4                                                   0x4ba4
4041#define SEA_mmDP6_DP_SEC_FRAMING4                                                   0x4ea4
4042#define SEA_mmDP_SEC_AUD_N                                                          0x1ca5
4043#define SEA_mmDP0_DP_SEC_AUD_N                                                      0x1ca5
4044#define SEA_mmDP1_DP_SEC_AUD_N                                                      0x1fa5
4045#define SEA_mmDP2_DP_SEC_AUD_N                                                      0x42a5
4046#define SEA_mmDP3_DP_SEC_AUD_N                                                      0x45a5
4047#define SEA_mmDP4_DP_SEC_AUD_N                                                      0x48a5
4048#define SEA_mmDP5_DP_SEC_AUD_N                                                      0x4ba5
4049#define SEA_mmDP6_DP_SEC_AUD_N                                                      0x4ea5
4050#define SEA_mmDP_SEC_AUD_N_READBACK                                                 0x1ca6
4051#define SEA_mmDP0_DP_SEC_AUD_N_READBACK                                             0x1ca6
4052#define SEA_mmDP1_DP_SEC_AUD_N_READBACK                                             0x1fa6
4053#define SEA_mmDP2_DP_SEC_AUD_N_READBACK                                             0x42a6
4054#define SEA_mmDP3_DP_SEC_AUD_N_READBACK                                             0x45a6
4055#define SEA_mmDP4_DP_SEC_AUD_N_READBACK                                             0x48a6
4056#define SEA_mmDP5_DP_SEC_AUD_N_READBACK                                             0x4ba6
4057#define SEA_mmDP6_DP_SEC_AUD_N_READBACK                                             0x4ea6
4058#define SEA_mmDP_SEC_AUD_M                                                          0x1ca7
4059#define SEA_mmDP0_DP_SEC_AUD_M                                                      0x1ca7
4060#define SEA_mmDP1_DP_SEC_AUD_M                                                      0x1fa7
4061#define SEA_mmDP2_DP_SEC_AUD_M                                                      0x42a7
4062#define SEA_mmDP3_DP_SEC_AUD_M                                                      0x45a7
4063#define SEA_mmDP4_DP_SEC_AUD_M                                                      0x48a7
4064#define SEA_mmDP5_DP_SEC_AUD_M                                                      0x4ba7
4065#define SEA_mmDP6_DP_SEC_AUD_M                                                      0x4ea7
4066#define SEA_mmDP_SEC_AUD_M_READBACK                                                 0x1ca8
4067#define SEA_mmDP0_DP_SEC_AUD_M_READBACK                                             0x1ca8
4068#define SEA_mmDP1_DP_SEC_AUD_M_READBACK                                             0x1fa8
4069#define SEA_mmDP2_DP_SEC_AUD_M_READBACK                                             0x42a8
4070#define SEA_mmDP3_DP_SEC_AUD_M_READBACK                                             0x45a8
4071#define SEA_mmDP4_DP_SEC_AUD_M_READBACK                                             0x48a8
4072#define SEA_mmDP5_DP_SEC_AUD_M_READBACK                                             0x4ba8
4073#define SEA_mmDP6_DP_SEC_AUD_M_READBACK                                             0x4ea8
4074#define SEA_mmDP_SEC_TIMESTAMP                                                      0x1ca9
4075#define SEA_mmDP0_DP_SEC_TIMESTAMP                                                  0x1ca9
4076#define SEA_mmDP1_DP_SEC_TIMESTAMP                                                  0x1fa9
4077#define SEA_mmDP2_DP_SEC_TIMESTAMP                                                  0x42a9
4078#define SEA_mmDP3_DP_SEC_TIMESTAMP                                                  0x45a9
4079#define SEA_mmDP4_DP_SEC_TIMESTAMP                                                  0x48a9
4080#define SEA_mmDP5_DP_SEC_TIMESTAMP                                                  0x4ba9
4081#define SEA_mmDP6_DP_SEC_TIMESTAMP                                                  0x4ea9
4082#define SEA_mmDP_SEC_PACKET_CNTL                                                    0x1caa
4083#define SEA_mmDP0_DP_SEC_PACKET_CNTL                                                0x1caa
4084#define SEA_mmDP1_DP_SEC_PACKET_CNTL                                                0x1faa
4085#define SEA_mmDP2_DP_SEC_PACKET_CNTL                                                0x42aa
4086#define SEA_mmDP3_DP_SEC_PACKET_CNTL                                                0x45aa
4087#define SEA_mmDP4_DP_SEC_PACKET_CNTL                                                0x48aa
4088#define SEA_mmDP5_DP_SEC_PACKET_CNTL                                                0x4baa
4089#define SEA_mmDP6_DP_SEC_PACKET_CNTL                                                0x4eaa
4090#define SEA_mmDP_MSE_RATE_CNTL                                                      0x1ce1
4091#define SEA_mmDP0_DP_MSE_RATE_CNTL                                                  0x1ce1
4092#define SEA_mmDP1_DP_MSE_RATE_CNTL                                                  0x1fe1
4093#define SEA_mmDP2_DP_MSE_RATE_CNTL                                                  0x42e1
4094#define SEA_mmDP3_DP_MSE_RATE_CNTL                                                  0x45e1
4095#define SEA_mmDP4_DP_MSE_RATE_CNTL                                                  0x48e1
4096#define SEA_mmDP5_DP_MSE_RATE_CNTL                                                  0x4be1
4097#define SEA_mmDP6_DP_MSE_RATE_CNTL                                                  0x4ee1
4098#define SEA_mmDP_MSE_RATE_UPDATE                                                    0x1ce3
4099#define SEA_mmDP0_DP_MSE_RATE_UPDATE                                                0x1ce3
4100#define SEA_mmDP1_DP_MSE_RATE_UPDATE                                                0x1fe3
4101#define SEA_mmDP2_DP_MSE_RATE_UPDATE                                                0x42e3
4102#define SEA_mmDP3_DP_MSE_RATE_UPDATE                                                0x45e3
4103#define SEA_mmDP4_DP_MSE_RATE_UPDATE                                                0x48e3
4104#define SEA_mmDP5_DP_MSE_RATE_UPDATE                                                0x4be3
4105#define SEA_mmDP6_DP_MSE_RATE_UPDATE                                                0x4ee3
4106#define SEA_mmDP_MSE_SAT0                                                           0x1ce4
4107#define SEA_mmDP0_DP_MSE_SAT0                                                       0x1ce4
4108#define SEA_mmDP1_DP_MSE_SAT0                                                       0x1fe4
4109#define SEA_mmDP2_DP_MSE_SAT0                                                       0x42e4
4110#define SEA_mmDP3_DP_MSE_SAT0                                                       0x45e4
4111#define SEA_mmDP4_DP_MSE_SAT0                                                       0x48e4
4112#define SEA_mmDP5_DP_MSE_SAT0                                                       0x4be4
4113#define SEA_mmDP6_DP_MSE_SAT0                                                       0x4ee4
4114#define SEA_mmDP_MSE_SAT1                                                           0x1ce5
4115#define SEA_mmDP0_DP_MSE_SAT1                                                       0x1ce5
4116#define SEA_mmDP1_DP_MSE_SAT1                                                       0x1fe5
4117#define SEA_mmDP2_DP_MSE_SAT1                                                       0x42e5
4118#define SEA_mmDP3_DP_MSE_SAT1                                                       0x45e5
4119#define SEA_mmDP4_DP_MSE_SAT1                                                       0x48e5
4120#define SEA_mmDP5_DP_MSE_SAT1                                                       0x4be5
4121#define SEA_mmDP6_DP_MSE_SAT1                                                       0x4ee5
4122#define SEA_mmDP_MSE_SAT2                                                           0x1ce6
4123#define SEA_mmDP0_DP_MSE_SAT2                                                       0x1ce6
4124#define SEA_mmDP1_DP_MSE_SAT2                                                       0x1fe6
4125#define SEA_mmDP2_DP_MSE_SAT2                                                       0x42e6
4126#define SEA_mmDP3_DP_MSE_SAT2                                                       0x45e6
4127#define SEA_mmDP4_DP_MSE_SAT2                                                       0x48e6
4128#define SEA_mmDP5_DP_MSE_SAT2                                                       0x4be6
4129#define SEA_mmDP6_DP_MSE_SAT2                                                       0x4ee6
4130#define SEA_mmDP_MSE_SAT_UPDATE                                                     0x1ce7
4131#define SEA_mmDP0_DP_MSE_SAT_UPDATE                                                 0x1ce7
4132#define SEA_mmDP1_DP_MSE_SAT_UPDATE                                                 0x1fe7
4133#define SEA_mmDP2_DP_MSE_SAT_UPDATE                                                 0x42e7
4134#define SEA_mmDP3_DP_MSE_SAT_UPDATE                                                 0x45e7
4135#define SEA_mmDP4_DP_MSE_SAT_UPDATE                                                 0x48e7
4136#define SEA_mmDP5_DP_MSE_SAT_UPDATE                                                 0x4be7
4137#define SEA_mmDP6_DP_MSE_SAT_UPDATE                                                 0x4ee7
4138#define SEA_mmDP_MSE_LINK_TIMING                                                    0x1ce8
4139#define SEA_mmDP0_DP_MSE_LINK_TIMING                                                0x1ce8
4140#define SEA_mmDP1_DP_MSE_LINK_TIMING                                                0x1fe8
4141#define SEA_mmDP2_DP_MSE_LINK_TIMING                                                0x42e8
4142#define SEA_mmDP3_DP_MSE_LINK_TIMING                                                0x45e8
4143#define SEA_mmDP4_DP_MSE_LINK_TIMING                                                0x48e8
4144#define SEA_mmDP5_DP_MSE_LINK_TIMING                                                0x4be8
4145#define SEA_mmDP6_DP_MSE_LINK_TIMING                                                0x4ee8
4146#define SEA_mmDP_MSE_MISC_CNTL                                                      0x1cdb
4147#define SEA_mmDP0_DP_MSE_MISC_CNTL                                                  0x1cdb
4148#define SEA_mmDP1_DP_MSE_MISC_CNTL                                                  0x1fdb
4149#define SEA_mmDP2_DP_MSE_MISC_CNTL                                                  0x42db
4150#define SEA_mmDP3_DP_MSE_MISC_CNTL                                                  0x45db
4151#define SEA_mmDP4_DP_MSE_MISC_CNTL                                                  0x48db
4152#define SEA_mmDP5_DP_MSE_MISC_CNTL                                                  0x4bdb
4153#define SEA_mmDP6_DP_MSE_MISC_CNTL                                                  0x4edb
4154#define SEA_mmDP_TEST_DEBUG_INDEX                                                   0x1cfc
4155#define SEA_mmDP0_DP_TEST_DEBUG_INDEX                                               0x1cfc
4156#define SEA_mmDP1_DP_TEST_DEBUG_INDEX                                               0x1ffc
4157#define SEA_mmDP2_DP_TEST_DEBUG_INDEX                                               0x42fc
4158#define SEA_mmDP3_DP_TEST_DEBUG_INDEX                                               0x45fc
4159#define SEA_mmDP4_DP_TEST_DEBUG_INDEX                                               0x48fc
4160#define SEA_mmDP5_DP_TEST_DEBUG_INDEX                                               0x4bfc
4161#define SEA_mmDP6_DP_TEST_DEBUG_INDEX                                               0x4efc
4162#define SEA_mmDP_TEST_DEBUG_DATA                                                    0x1cfd
4163#define SEA_mmDP0_DP_TEST_DEBUG_DATA                                                0x1cfd
4164#define SEA_mmDP1_DP_TEST_DEBUG_DATA                                                0x1ffd
4165#define SEA_mmDP2_DP_TEST_DEBUG_DATA                                                0x42fd
4166#define SEA_mmDP3_DP_TEST_DEBUG_DATA                                                0x45fd
4167#define SEA_mmDP4_DP_TEST_DEBUG_DATA                                                0x48fd
4168#define SEA_mmDP5_DP_TEST_DEBUG_DATA                                                0x4bfd
4169#define SEA_mmDP6_DP_TEST_DEBUG_DATA                                                0x4efd
4170#define SEA_mmAUX_CONTROL                                                           0x1880
4171#define SEA_mmDP_AUX0_AUX_CONTROL                                                   0x1880
4172#define SEA_mmDP_AUX1_AUX_CONTROL                                                   0x1894
4173#define SEA_mmDP_AUX2_AUX_CONTROL                                                   0x18a8
4174#define SEA_mmDP_AUX3_AUX_CONTROL                                                   0x18c0
4175#define SEA_mmDP_AUX4_AUX_CONTROL                                                   0x18d4
4176#define SEA_mmDP_AUX5_AUX_CONTROL                                                   0x18e8
4177#define SEA_mmAUX_SW_CONTROL                                                        0x1881
4178#define SEA_mmDP_AUX0_AUX_SW_CONTROL                                                0x1881
4179#define SEA_mmDP_AUX1_AUX_SW_CONTROL                                                0x1895
4180#define SEA_mmDP_AUX2_AUX_SW_CONTROL                                                0x18a9
4181#define SEA_mmDP_AUX3_AUX_SW_CONTROL                                                0x18c1
4182#define SEA_mmDP_AUX4_AUX_SW_CONTROL                                                0x18d5
4183#define SEA_mmDP_AUX5_AUX_SW_CONTROL                                                0x18e9
4184#define SEA_mmAUX_ARB_CONTROL                                                       0x1882
4185#define SEA_mmDP_AUX0_AUX_ARB_CONTROL                                               0x1882
4186#define SEA_mmDP_AUX1_AUX_ARB_CONTROL                                               0x1896
4187#define SEA_mmDP_AUX2_AUX_ARB_CONTROL                                               0x18aa
4188#define SEA_mmDP_AUX3_AUX_ARB_CONTROL                                               0x18c2
4189#define SEA_mmDP_AUX4_AUX_ARB_CONTROL                                               0x18d6
4190#define SEA_mmDP_AUX5_AUX_ARB_CONTROL                                               0x18ea
4191#define SEA_mmAUX_INTERRUPT_CONTROL                                                 0x1883
4192#define SEA_mmDP_AUX0_AUX_INTERRUPT_CONTROL                                         0x1883
4193#define SEA_mmDP_AUX1_AUX_INTERRUPT_CONTROL                                         0x1897
4194#define SEA_mmDP_AUX2_AUX_INTERRUPT_CONTROL                                         0x18ab
4195#define SEA_mmDP_AUX3_AUX_INTERRUPT_CONTROL                                         0x18c3
4196#define SEA_mmDP_AUX4_AUX_INTERRUPT_CONTROL                                         0x18d7
4197#define SEA_mmDP_AUX5_AUX_INTERRUPT_CONTROL                                         0x18eb
4198#define SEA_mmAUX_SW_STATUS                                                         0x1884
4199#define SEA_mmDP_AUX0_AUX_SW_STATUS                                                 0x1884
4200#define SEA_mmDP_AUX1_AUX_SW_STATUS                                                 0x1898
4201#define SEA_mmDP_AUX2_AUX_SW_STATUS                                                 0x18ac
4202#define SEA_mmDP_AUX3_AUX_SW_STATUS                                                 0x18c4
4203#define SEA_mmDP_AUX4_AUX_SW_STATUS                                                 0x18d8
4204#define SEA_mmDP_AUX5_AUX_SW_STATUS                                                 0x18ec
4205#define SEA_mmAUX_LS_STATUS                                                         0x1885
4206#define SEA_mmDP_AUX0_AUX_LS_STATUS                                                 0x1885
4207#define SEA_mmDP_AUX1_AUX_LS_STATUS                                                 0x1899
4208#define SEA_mmDP_AUX2_AUX_LS_STATUS                                                 0x18ad
4209#define SEA_mmDP_AUX3_AUX_LS_STATUS                                                 0x18c5
4210#define SEA_mmDP_AUX4_AUX_LS_STATUS                                                 0x18d9
4211#define SEA_mmDP_AUX5_AUX_LS_STATUS                                                 0x18ed
4212#define SEA_mmAUX_SW_DATA                                                           0x1886
4213#define SEA_mmDP_AUX0_AUX_SW_DATA                                                   0x1886
4214#define SEA_mmDP_AUX1_AUX_SW_DATA                                                   0x189a
4215#define SEA_mmDP_AUX2_AUX_SW_DATA                                                   0x18ae
4216#define SEA_mmDP_AUX3_AUX_SW_DATA                                                   0x18c6
4217#define SEA_mmDP_AUX4_AUX_SW_DATA                                                   0x18da
4218#define SEA_mmDP_AUX5_AUX_SW_DATA                                                   0x18ee
4219#define SEA_mmAUX_LS_DATA                                                           0x1887
4220#define SEA_mmDP_AUX0_AUX_LS_DATA                                                   0x1887
4221#define SEA_mmDP_AUX1_AUX_LS_DATA                                                   0x189b
4222#define SEA_mmDP_AUX2_AUX_LS_DATA                                                   0x18af
4223#define SEA_mmDP_AUX3_AUX_LS_DATA                                                   0x18c7
4224#define SEA_mmDP_AUX4_AUX_LS_DATA                                                   0x18db
4225#define SEA_mmDP_AUX5_AUX_LS_DATA                                                   0x18ef
4226#define SEA_mmAUX_DPHY_TX_REF_CONTROL                                               0x1888
4227#define SEA_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                       0x1888
4228#define SEA_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                       0x189c
4229#define SEA_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                       0x18b0
4230#define SEA_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                       0x18c8
4231#define SEA_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                       0x18dc
4232#define SEA_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL                                       0x18f0
4233#define SEA_mmAUX_DPHY_TX_CONTROL                                                   0x1889
4234#define SEA_mmDP_AUX0_AUX_DPHY_TX_CONTROL                                           0x1889
4235#define SEA_mmDP_AUX1_AUX_DPHY_TX_CONTROL                                           0x189d
4236#define SEA_mmDP_AUX2_AUX_DPHY_TX_CONTROL                                           0x18b1
4237#define SEA_mmDP_AUX3_AUX_DPHY_TX_CONTROL                                           0x18c9
4238#define SEA_mmDP_AUX4_AUX_DPHY_TX_CONTROL                                           0x18dd
4239#define SEA_mmDP_AUX5_AUX_DPHY_TX_CONTROL                                           0x18f1
4240#define SEA_mmAUX_DPHY_RX_CONTROL0                                                  0x188a
4241#define SEA_mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                          0x188a
4242#define SEA_mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                          0x189e
4243#define SEA_mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                          0x18b2
4244#define SEA_mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                          0x18ca
4245#define SEA_mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                          0x18de
4246#define SEA_mmDP_AUX5_AUX_DPHY_RX_CONTROL0                                          0x18f2
4247#define SEA_mmAUX_DPHY_RX_CONTROL1                                                  0x188b
4248#define SEA_mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                          0x188b
4249#define SEA_mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                          0x189f
4250#define SEA_mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                          0x18b3
4251#define SEA_mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                          0x18cb
4252#define SEA_mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                          0x18df
4253#define SEA_mmDP_AUX5_AUX_DPHY_RX_CONTROL1                                          0x18f3
4254#define SEA_mmAUX_DPHY_TX_STATUS                                                    0x188c
4255#define SEA_mmDP_AUX0_AUX_DPHY_TX_STATUS                                            0x188c
4256#define SEA_mmDP_AUX1_AUX_DPHY_TX_STATUS                                            0x18a0
4257#define SEA_mmDP_AUX2_AUX_DPHY_TX_STATUS                                            0x18b4
4258#define SEA_mmDP_AUX3_AUX_DPHY_TX_STATUS                                            0x18cc
4259#define SEA_mmDP_AUX4_AUX_DPHY_TX_STATUS                                            0x18e0
4260#define SEA_mmDP_AUX5_AUX_DPHY_TX_STATUS                                            0x18f4
4261#define SEA_mmAUX_DPHY_RX_STATUS                                                    0x188d
4262#define SEA_mmDP_AUX0_AUX_DPHY_RX_STATUS                                            0x188d
4263#define SEA_mmDP_AUX1_AUX_DPHY_RX_STATUS                                            0x18a1
4264#define SEA_mmDP_AUX2_AUX_DPHY_RX_STATUS                                            0x18b5
4265#define SEA_mmDP_AUX3_AUX_DPHY_RX_STATUS                                            0x18cd
4266#define SEA_mmDP_AUX4_AUX_DPHY_RX_STATUS                                            0x18e1
4267#define SEA_mmDP_AUX5_AUX_DPHY_RX_STATUS                                            0x18f5
4268#define SEA_mmAUX_GTC_SYNC_CONTROL                                                  0x188e
4269#define SEA_mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                          0x188e
4270#define SEA_mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                          0x18a2
4271#define SEA_mmDP_AUX2_AUX_GTC_SYNC_CONTROL                                          0x18b6
4272#define SEA_mmDP_AUX3_AUX_GTC_SYNC_CONTROL                                          0x18ce
4273#define SEA_mmDP_AUX4_AUX_GTC_SYNC_CONTROL                                          0x18e2
4274#define SEA_mmDP_AUX5_AUX_GTC_SYNC_CONTROL                                          0x18f6
4275#define SEA_mmAUX_GTC_SYNC_ERROR_CONTROL                                            0x188f
4276#define SEA_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                    0x188f
4277#define SEA_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                    0x18a3
4278#define SEA_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                    0x18b7
4279#define SEA_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                    0x18cf
4280#define SEA_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                    0x18e3
4281#define SEA_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL                                    0x18f7
4282#define SEA_mmAUX_GTC_SYNC_CONTROLLER_STATUS                                        0x1890
4283#define SEA_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x1890
4284#define SEA_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x18a4
4285#define SEA_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x18b8
4286#define SEA_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x18d0
4287#define SEA_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x18e4
4288#define SEA_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x18f8
4289#define SEA_mmAUX_GTC_SYNC_STATUS                                                   0x1891
4290#define SEA_mmDP_AUX0_AUX_GTC_SYNC_STATUS                                           0x1891
4291#define SEA_mmDP_AUX1_AUX_GTC_SYNC_STATUS                                           0x18a5
4292#define SEA_mmDP_AUX2_AUX_GTC_SYNC_STATUS                                           0x18b9
4293#define SEA_mmDP_AUX3_AUX_GTC_SYNC_STATUS                                           0x18d1
4294#define SEA_mmDP_AUX4_AUX_GTC_SYNC_STATUS                                           0x18e5
4295#define SEA_mmDP_AUX5_AUX_GTC_SYNC_STATUS                                           0x18f9
4296#define SEA_mmAUX_GTC_SYNC_DATA                                                     0x1892
4297#define SEA_mmDP_AUX0_AUX_GTC_SYNC_DATA                                             0x1892
4298#define SEA_mmDP_AUX1_AUX_GTC_SYNC_DATA                                             0x18a6
4299#define SEA_mmDP_AUX2_AUX_GTC_SYNC_DATA                                             0x18ba
4300#define SEA_mmDP_AUX3_AUX_GTC_SYNC_DATA                                             0x18d2
4301#define SEA_mmDP_AUX4_AUX_GTC_SYNC_DATA                                             0x18e6
4302#define SEA_mmDP_AUX5_AUX_GTC_SYNC_DATA                                             0x18fa
4303#define SEA_mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                                    0x1893
4304#define SEA_mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x1893
4305#define SEA_mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x18a7
4306#define SEA_mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x18bb
4307#define SEA_mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x18d3
4308#define