radeon_hd.h revision bf8fe3dd
1/*
2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 *		Alexander von Gluck IV, kallisti5@unixzen.com
8 */
9#ifndef RADEON_HD_H
10#define RADEON_HD_H
11
12
13#include "lock.h"
14
15#include "radeon_reg.h"
16
17//#include "r500_reg.h"  // Not used atm
18#include "avivo_reg.h"
19#include "r600_reg.h"
20#include "r700_reg.h"
21#include "evergreen_reg.h"
22#include "si_reg.h"
23#include "ni_reg.h"
24
25#include <Accelerant.h>
26#include <Drivers.h>
27#include <edid.h>
28#include <PCI.h>
29
30
31#define VENDOR_ID_ATI	0x1002
32
33// Card chipset flags
34#define CHIP_STD		(1 << 0) // Standard chipset
35#define CHIP_X2			(1 << 1) // Dual cpu
36#define CHIP_IGP		(1 << 2) // IGP chipset
37#define CHIP_MOBILE		(1 << 3) // Mobile chipset
38#define CHIP_DISCREET	(1 << 4) // Discreet chipset
39#define CHIP_APU		(1 << 5) // APU chipset
40
41#define DEVICE_NAME				"radeon_hd"
42#define RADEON_ACCELERANT_NAME	"radeon_hd.accelerant"
43
44#define MAX_NAME_LENGTH		32
45
46// Used to collect EDID from boot loader
47#define EDID_BOOT_INFO "vesa_edid/v1"
48#define MODES_BOOT_INFO "vesa_modes/v1"
49
50#define RHD_POWER_ON       0
51#define RHD_POWER_RESET    1   /* off temporarily */
52#define RHD_POWER_SHUTDOWN 2   /* long term shutdown */
53#define RHD_POWER_UNKNOWN  3   /* initial state */
54
55
56// Radeon Chipsets
57// !! Must match chipset names below
58enum radeon_chipset {
59	RADEON_R420 = 0,	//r400, Radeon X700-X850
60	RADEON_R423,
61	RADEON_RV410,
62	RADEON_RS400,
63	RADEON_RS480,
64	RADEON_RS600,
65	RADEON_RS690,
66	RADEON_RS740,
67	RADEON_RV515,
68	RADEON_R520,		//r500, DCE 1.0
69	RADEON_RV530,		// DCE 1.0
70	RADEON_RV560,		// DCE 1.0
71	RADEON_RV570,		// DCE 1.0
72	RADEON_R580,		// DCE 1.0
73	RADEON_R600,		//r600, DCE 2.0
74	RADEON_RV610,		// DCE 2.0
75	RADEON_RV630,		// DCE 2.0
76	RADEON_RV670,		// DCE 2.0
77	RADEON_RV620,		// DCE 3.0
78	RADEON_RV635,		// DCE 3.0
79	RADEON_RS780,		// DCE 3.0
80	RADEON_RS880,		// DCE 3.0
81	RADEON_RV770,		//r700, DCE 3.1
82	RADEON_RV730,		// DCE 3.2
83	RADEON_RV710,		// DCE 3.2
84	RADEON_RV740,		// DCE 3.2
85	RADEON_CEDAR,		//Evergreen, DCE 4.0
86	RADEON_REDWOOD,		// DCE 4.0
87	RADEON_JUNIPER,		// DCE 4.0
88	RADEON_CYPRESS,		// DCE 4.0
89	RADEON_HEMLOCK,		// DCE 4.0?
90	RADEON_PALM,		//Fusion APU (NI), DCE 4.1
91	RADEON_SUMO,		// DCE 4.1
92	RADEON_SUMO2,		// DCE 4.1
93	RADEON_CAICOS,		//Nothern Islands, DCE 5.0
94	RADEON_TURKS,		// DCE 5.0
95	RADEON_BARTS,		// DCE 5.0
96	RADEON_CAYMAN,		// DCE 5.0
97	RADEON_ANTILLES,	// DCE 5.0?
98	RADEON_CAPEVERDE,	//Southern Islands, DCE 6.0
99	RADEON_PITCAIRN,	// DCE 6.0
100	RADEON_TAHITI,		// DCE 6.0
101	RADEON_ARUBA,		// DCE 6.1 Trinity/Richland
102	RADEON_OLAND,		// DCE 6.4
103	RADEON_HAINAN,		// NO DCE, only compute
104	RADEON_KAVERI,		//Sea Islands, DCE 8.1
105	RADEON_BONAIRE,		// DCE 8.2
106	RADEON_KABINI,		// DCE 8.3
107	RADEON_MULLINS,		// DCE 8.3
108	RADEON_HAWAII,		// DCE 8.5
109	RADEON_TOPAZ,		//Volcanic Islands, NO DCE
110	RADEON_TONGA,		// DCE 10.0
111	RADEON_CARRIZO		// DCE 11.0
112};
113
114// !! Must match chipset families above
115static const char radeon_chip_name[][MAX_NAME_LENGTH] = {
116	"R420",
117	"R423",
118	"RV410",
119	"RS400",
120	"RS480",
121	"RS600",
122	"RS690",
123	"RS740",
124	"RV515",
125	"R520",
126	"RV530",
127	"RV560",
128	"RV570",
129	"R580",
130	"R600",
131	"RV610",
132	"RV630",
133	"RV670",
134	"RV620",
135	"RV635",
136	"RS780",
137	"RS880",
138	"RV770",
139	"RV730",
140	"RV710",
141	"RV740",
142	"Cedar",
143	"Redwood",
144	"Juniper",
145	"Cypress",
146	"Hemlock",
147	"Palm",
148	"Sumo",
149	"Sumo2",
150	"Caicos",
151	"Turks",
152	"Barts",
153	"Cayman",
154	"Antilles",
155	"Cape Verde",
156	"Pitcairn",
157	"Tahiti",
158	"Aruba",
159	"Oland",
160	"Hainan",
161	"Kaveri",
162	"Bonaire",
163	"Kabini",
164	"Mullins",
165	"Hawaii",
166	"Topaz",
167	"Tonga",
168	"Carrizo"
169};
170
171
172struct ring_buffer {
173	struct lock		lock;
174	uint32			register_base;
175	uint32			offset;
176	uint32			size;
177	uint32			position;
178	uint32			space_left;
179	uint8*			base;
180};
181
182
183struct overlay_registers;
184
185
186struct radeon_shared_info {
187	uint32			deviceIndex;		// accelerant index
188	uint32			pciID;				// device pciid
189	area_id			mode_list_area;		// area containing display mode list
190	uint32			mode_count;
191
192	bool			has_rom;			// was rom mapped?
193	area_id			rom_area;			// area of mapped rom
194	uint32			rom_phys;			// rom base location
195	uint32			rom_size;			// rom size
196	uint8*			rom;				// cloned, memory mapped PCI ROM
197
198	display_mode	current_mode;
199	uint32			bytes_per_row;
200	uint32			bits_per_pixel;
201	uint32			dpms_mode;
202
203	area_id			registers_area;			// area of memory mapped registers
204	uint8*			status_page;
205	addr_t			physical_status_page;
206	uint32			graphics_memory_size;
207
208	uint8*			frame_buffer;			// virtual memory mapped FB
209	area_id			frame_buffer_area;		// area of memory mapped FB
210	addr_t			frame_buffer_phys;		// card PCI BAR address of FB
211	uint32			frame_buffer_size;		// FB size mapped
212
213	bool			has_edid;
214	edid1_info		edid_info;
215
216	struct lock		accelerant_lock;
217	struct lock		engine_lock;
218
219	ring_buffer		primary_ring_buffer;
220
221	int32			overlay_channel_used;
222	bool			overlay_active;
223	uint32			overlay_token;
224	addr_t			physical_overlay_registers;
225	uint32			overlay_offset;
226
227	bool			hardware_cursor_enabled;
228	sem_id			vblank_sem;
229
230	uint8*			cursor_memory;
231	addr_t			physical_cursor_memory;
232	uint32			cursor_buffer_offset;
233	uint32			cursor_format;
234	bool			cursor_visible;
235	uint16			cursor_hot_x;
236	uint16			cursor_hot_y;
237
238	char			deviceName[MAX_NAME_LENGTH];
239	uint16			chipsetID;
240	char			chipsetName[MAX_NAME_LENGTH];
241	uint32			chipsetFlags;
242	uint8			dceMajor;
243	uint8			dceMinor;
244
245	uint16			color_data[3 * 256];    // colour lookup table
246};
247
248//----------------- ioctl() interface ----------------
249
250// magic code for ioctls
251#define RADEON_PRIVATE_DATA_MAGIC		'rdhd'
252
253// list ioctls
254enum {
255	RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
256
257	RADEON_GET_DEVICE_NAME,
258	RADEON_ALLOCATE_GRAPHICS_MEMORY,
259	RADEON_FREE_GRAPHICS_MEMORY
260};
261
262// retrieve the area_id of the kernel/accelerant shared info
263struct radeon_get_private_data {
264	uint32	magic;				// magic number
265	area_id	shared_info_area;
266};
267
268// allocate graphics memory
269struct radeon_allocate_graphics_memory {
270	uint32	magic;
271	uint32	size;
272	uint32	alignment;
273	uint32	flags;
274	uint32	buffer_base;
275};
276
277// free graphics memory
278struct radeon_free_graphics_memory {
279	uint32 	magic;
280	uint32	buffer_base;
281};
282
283// registers
284#define R6XX_CONFIG_APER_SIZE			0x5430	// r600>
285#define OLD_CONFIG_APER_SIZE			0x0108	// <r600
286#define CONFIG_MEMSIZE                  0x5428	// r600>
287
288// PCI bridge memory management
289
290// overlay
291
292#define RADEON_OVERLAY_UPDATE			0x30000
293#define RADEON_OVERLAY_TEST				0x30004
294#define RADEON_OVERLAY_STATUS			0x30008
295#define RADEON_OVERLAY_EXTENDED_STATUS	0x3000c
296#define RADEON_OVERLAY_GAMMA_5			0x30010
297#define RADEON_OVERLAY_GAMMA_4			0x30014
298#define RADEON_OVERLAY_GAMMA_3			0x30018
299#define RADEON_OVERLAY_GAMMA_2			0x3001c
300#define RADEON_OVERLAY_GAMMA_1			0x30020
301#define RADEON_OVERLAY_GAMMA_0			0x30024
302
303struct overlay_scale {
304	uint32 _reserved0 : 3;
305	uint32 horizontal_scale_fraction : 12;
306	uint32 _reserved1 : 1;
307	uint32 horizontal_downscale_factor : 3;
308	uint32 _reserved2 : 1;
309	uint32 vertical_scale_fraction : 12;
310};
311
312#define OVERLAY_FORMAT_RGB15			0x2
313#define OVERLAY_FORMAT_RGB16			0x3
314#define OVERLAY_FORMAT_RGB32			0x1
315#define OVERLAY_FORMAT_YCbCr422			0x8
316#define OVERLAY_FORMAT_YCbCr411			0x9
317#define OVERLAY_FORMAT_YCbCr420			0xc
318
319#define OVERLAY_MIRROR_NORMAL			0x0
320#define OVERLAY_MIRROR_HORIZONTAL		0x1
321#define OVERLAY_MIRROR_VERTICAL			0x2
322
323// The real overlay registers are written to using an update buffer
324
325struct overlay_registers {
326	uint32 buffer_rgb0;
327	uint32 buffer_rgb1;
328	uint32 buffer_u0;
329	uint32 buffer_v0;
330	uint32 buffer_u1;
331	uint32 buffer_v1;
332	// (0x18) OSTRIDE - overlay stride
333	uint16 stride_rgb;
334	uint16 stride_uv;
335	// (0x1c) YRGB_VPH - Y/RGB vertical phase
336	uint16 vertical_phase0_rgb;
337	uint16 vertical_phase1_rgb;
338	// (0x20) UV_VPH - UV vertical phase
339	uint16 vertical_phase0_uv;
340	uint16 vertical_phase1_uv;
341	// (0x24) HORZ_PH - horizontal phase
342	uint16 horizontal_phase_rgb;
343	uint16 horizontal_phase_uv;
344	// (0x28) INIT_PHS - initial phase shift
345	uint32 initial_vertical_phase0_shift_rgb0 : 4;
346	uint32 initial_vertical_phase1_shift_rgb0 : 4;
347	uint32 initial_horizontal_phase_shift_rgb0 : 4;
348	uint32 initial_vertical_phase0_shift_uv : 4;
349	uint32 initial_vertical_phase1_shift_uv : 4;
350	uint32 initial_horizontal_phase_shift_uv : 4;
351	uint32 _reserved0 : 8;
352	// (0x2c) DWINPOS - destination window position
353	uint16 window_left;
354	uint16 window_top;
355	// (0x30) DWINSZ - destination window size
356	uint16 window_width;
357	uint16 window_height;
358	// (0x34) SWIDTH - source width
359	uint16 source_width_rgb;
360	uint16 source_width_uv;
361	// (0x38) SWITDHSW - source width in 8 byte steps
362	uint16 source_bytes_per_row_rgb;
363	uint16 source_bytes_per_row_uv;
364	uint16 source_height_rgb;
365	uint16 source_height_uv;
366	overlay_scale scale_rgb;
367	overlay_scale scale_uv;
368	// (0x48) OCLRC0 - overlay color correction 0
369	uint32 brightness_correction : 8;		// signed, -128 to 127
370	uint32 _reserved1 : 10;
371	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
372	uint32 _reserved2 : 5;
373	// (0x4c) OCLRC1 - overlay color correction 1
374	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
375	uint32 _reserved3 : 6;
376	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
377	uint32 _reserved4 : 5;
378	// (0x50) DCLRKV - destination color key value
379	uint32 color_key_blue : 8;
380	uint32 color_key_green : 8;
381	uint32 color_key_red : 8;
382	uint32 _reserved5 : 8;
383	// (0x54) DCLRKM - destination color key mask
384	uint32 color_key_mask_blue : 8;
385	uint32 color_key_mask_green : 8;
386	uint32 color_key_mask_red : 8;
387	uint32 _reserved6 : 7;
388	uint32 color_key_enabled : 1;
389	// (0x58) SCHRKVH - source chroma key high value
390	uint32 source_chroma_key_high_red : 8;
391	uint32 source_chroma_key_high_blue : 8;
392	uint32 source_chroma_key_high_green : 8;
393	uint32 _reserved7 : 8;
394	// (0x5c) SCHRKVL - source chroma key low value
395	uint32 source_chroma_key_low_red : 8;
396	uint32 source_chroma_key_low_blue : 8;
397	uint32 source_chroma_key_low_green : 8;
398	uint32 _reserved8 : 8;
399	// (0x60) SCHRKEN - source chroma key enable
400	uint32 _reserved9 : 24;
401	uint32 source_chroma_key_red_enabled : 1;
402	uint32 source_chroma_key_blue_enabled : 1;
403	uint32 source_chroma_key_green_enabled : 1;
404	uint32 _reserved10 : 5;
405	// (0x64) OCONFIG - overlay configuration
406	uint32 _reserved11 : 3;
407	uint32 color_control_output_mode : 1;
408	uint32 yuv_to_rgb_bypass : 1;
409	uint32 _reserved12 : 11;
410	uint32 gamma2_enabled : 1;
411	uint32 _reserved13 : 1;
412	uint32 select_pipe : 1;
413	uint32 slot_time : 8;
414	uint32 _reserved14 : 5;
415	// (0x68) OCOMD - overlay command
416	uint32 overlay_enabled : 1;
417	uint32 active_field : 1;
418	uint32 active_buffer : 2;
419	uint32 test_mode : 1;
420	uint32 buffer_field_mode : 1;
421	uint32 _reserved15 : 1;
422	uint32 tv_flip_field_enabled : 1;
423	uint32 _reserved16 : 1;
424	uint32 tv_flip_field_parity : 1;
425	uint32 source_format : 4;
426	uint32 ycbcr422_order : 2;
427	uint32 _reserved18 : 1;
428	uint32 mirroring_mode : 2;
429	uint32 _reserved19 : 13;
430
431	uint32 _reserved20;
432
433	uint32 start_0y;
434	uint32 start_1y;
435	uint32 start_0u;
436	uint32 start_0v;
437	uint32 start_1u;
438	uint32 start_1v;
439	uint32 _reserved21[6];
440#if 0
441	// (0x70) AWINPOS - alpha blend window position
442	uint32 awinpos;
443	// (0x74) AWINSZ - alpha blend window size
444	uint32 awinsz;
445
446	uint32 _reserved21[10];
447#endif
448
449	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
450	// the next two registers switch the usual Y/RGB vs. UV order)
451	uint16 horizontal_scale_uv;
452	uint16 horizontal_scale_rgb;
453	// (0xa4) UVSCALEV - vertical downscale
454	uint16 vertical_scale_uv;
455	uint16 vertical_scale_rgb;
456
457	uint32 _reserved22[86];
458
459	// (0x200) polyphase filter coefficients
460	uint16 vertical_coefficients_rgb[128];
461	uint16 horizontal_coefficients_rgb[128];
462
463	uint32	_reserved23[64];
464
465	// (0x500)
466	uint16 vertical_coefficients_uv[128];
467	uint16 horizontal_coefficients_uv[128];
468};
469
470
471struct hardware_status {
472	uint32	interrupt_status_register;
473	uint32	_reserved0[3];
474	void*	primary_ring_head_storage;
475	uint32	_reserved1[3];
476	void*	secondary_ring_0_head_storage;
477	void*	secondary_ring_1_head_storage;
478	uint32	_reserved2[2];
479	void*	binning_head_storage;
480	uint32	_reserved3[3];
481	uint32	store[1008];
482};
483
484#endif	/* RADEON_HD_H */
485