radeon_hd.h revision 1b69f339
1/*
2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 *		Alexander von Gluck IV, kallisti5@unixzen.com
8 */
9#ifndef RADEON_HD_H
10#define RADEON_HD_H
11
12
13#include "lock.h"
14
15#include "radeon_reg.h"
16
17//#include "r500_reg.h"  // Not used atm. DCE 0
18#include "avivo_reg.h"		// DCE 1
19#include "r600_reg.h"		// DCE 2
20#include "r700_reg.h"		// DCE 3
21#include "evergreen_reg.h"	// DCE 4
22#include "ni_reg.h"			// DCE 5
23#include "si_reg.h"			// DCE 6
24#include "sea_reg.h"		// DCE 8
25#include "vol_reg.h"		// DCE 10
26#include "car_reg.h"		// DCE 11
27
28#include <Accelerant.h>
29#include <Drivers.h>
30#include <edid.h>
31#include <PCI.h>
32
33
34#define VENDOR_ID_ATI	0x1002
35
36// Card chipset flags
37#define CHIP_STD		(1 << 0) // Standard chipset
38#define CHIP_X2			(1 << 1) // Dual cpu
39#define CHIP_IGP		(1 << 2) // IGP chipset
40#define CHIP_MOBILE		(1 << 3) // Mobile chipset
41#define CHIP_DISCREET	(1 << 4) // Discreet chipset
42#define CHIP_APU		(1 << 5) // APU chipset
43
44#define DEVICE_NAME				"radeon_hd"
45#define RADEON_ACCELERANT_NAME	"radeon_hd.accelerant"
46
47#define MAX_NAME_LENGTH		32
48
49// Used to collect EDID from boot loader
50#define EDID_BOOT_INFO "vesa_edid/v1"
51#define MODES_BOOT_INFO "vesa_modes/v1"
52
53#define RHD_POWER_ON       0
54#define RHD_POWER_RESET    1   /* off temporarily */
55#define RHD_POWER_SHUTDOWN 2   /* long term shutdown */
56#define RHD_POWER_UNKNOWN  3   /* initial state */
57
58
59// Radeon Chipsets
60// !! Must match chipset names below
61enum radeon_chipset {
62	RADEON_R420 = 0,	//r400, Radeon X700-X850
63	RADEON_R423,
64	RADEON_RV410,
65	RADEON_RS400,
66	RADEON_RS480,
67	RADEON_RS600,
68	RADEON_RS690,
69	RADEON_RS740,
70	RADEON_RV515,
71	RADEON_R520,		//r500, DCE 1.0
72	RADEON_RV530,		// DCE 1.0
73	RADEON_RV560,		// DCE 1.0
74	RADEON_RV570,		// DCE 1.0
75	RADEON_R580,		// DCE 1.0
76	RADEON_R600,		//r600, DCE 2.0
77	RADEON_RV610,		// DCE 2.0
78	RADEON_RV630,		// DCE 2.0
79	RADEON_RV670,		// DCE 2.0
80	RADEON_RV620,		// DCE 3.0
81	RADEON_RV635,		// DCE 3.0
82	RADEON_RS780,		// DCE 3.0
83	RADEON_RS880,		// DCE 3.0
84	RADEON_RV770,		//r700, DCE 3.1
85	RADEON_RV730,		// DCE 3.2
86	RADEON_RV710,		// DCE 3.2
87	RADEON_RV740,		// DCE 3.2
88	RADEON_CEDAR,		//Evergreen, DCE 4.0
89	RADEON_REDWOOD,		// DCE 4.0
90	RADEON_JUNIPER,		// DCE 4.0
91	RADEON_CYPRESS,		// DCE 4.0
92	RADEON_HEMLOCK,		// DCE 4.0?
93	RADEON_PALM,		//Fusion APU (NI), DCE 4.1
94	RADEON_SUMO,		// DCE 4.1
95	RADEON_SUMO2,		// DCE 4.1
96	RADEON_CAICOS,		//Nothern Islands, DCE 5.0
97	RADEON_TURKS,		// DCE 5.0
98	RADEON_BARTS,		// DCE 5.0
99	RADEON_CAYMAN,		// DCE 5.0
100	RADEON_ANTILLES,	// DCE 5.0?
101	RADEON_CAPEVERDE,	//Southern Islands, DCE 6.0
102	RADEON_PITCAIRN,	// DCE 6.0
103	RADEON_TAHITI,		// DCE 6.0
104	RADEON_ARUBA,		// DCE 6.1 Trinity/Richland
105	RADEON_OLAND,		// DCE 6.4
106	RADEON_HAINAN,		// NO DCE, only compute
107	RADEON_KAVERI,		//Sea Islands, DCE 8.1
108	RADEON_BONAIRE,		// DCE 8.2
109	RADEON_KABINI,		// DCE 8.3
110	RADEON_MULLINS,		// DCE 8.3
111	RADEON_HAWAII,		// DCE 8.5
112	RADEON_TOPAZ,		//Volcanic Islands, NO DCE
113	RADEON_TONGA,		// DCE 10.0
114	RADEON_CARRIZO		// DCE 11.0
115};
116
117// !! Must match chipset families above
118static const char radeon_chip_name[][MAX_NAME_LENGTH] = {
119	"R420",
120	"R423",
121	"RV410",
122	"RS400",
123	"RS480",
124	"RS600",
125	"RS690",
126	"RS740",
127	"RV515",
128	"R520",
129	"RV530",
130	"RV560",
131	"RV570",
132	"R580",
133	"R600",
134	"RV610",
135	"RV630",
136	"RV670",
137	"RV620",
138	"RV635",
139	"RS780",
140	"RS880",
141	"RV770",
142	"RV730",
143	"RV710",
144	"RV740",
145	"Cedar",
146	"Redwood",
147	"Juniper",
148	"Cypress",
149	"Hemlock",
150	"Palm",
151	"Sumo",
152	"Sumo2",
153	"Caicos",
154	"Turks",
155	"Barts",
156	"Cayman",
157	"Antilles",
158	"Cape Verde",
159	"Pitcairn",
160	"Tahiti",
161	"Aruba",
162	"Oland",
163	"Hainan",
164	"Kaveri",
165	"Bonaire",
166	"Kabini",
167	"Mullins",
168	"Hawaii",
169	"Topaz",
170	"Tonga",
171	"Carrizo"
172};
173
174
175struct ring_buffer {
176	struct lock		lock;
177	uint32			register_base;
178	uint32			offset;
179	uint32			size;
180	uint32			position;
181	uint32			space_left;
182	uint8*			base;
183};
184
185
186struct overlay_registers;
187
188
189struct radeon_shared_info {
190	uint32			deviceIndex;		// accelerant index
191	uint32			pciID;				// device pciid
192	area_id			mode_list_area;		// area containing display mode list
193	uint32			mode_count;
194
195	bool			has_rom;			// was rom mapped?
196	area_id			rom_area;			// area of mapped rom
197	uint32			rom_phys;			// rom base location
198	uint32			rom_size;			// rom size
199	uint8*			rom;				// cloned, memory mapped PCI ROM
200
201	display_mode	current_mode;
202	uint32			bytes_per_row;
203	uint32			bits_per_pixel;
204	uint32			dpms_mode;
205
206	area_id			registers_area;			// area of memory mapped registers
207	uint8*			status_page;
208	addr_t			physical_status_page;
209	uint32			graphics_memory_size;
210
211	uint8*			frame_buffer;			// virtual memory mapped FB
212	area_id			frame_buffer_area;		// area of memory mapped FB
213	addr_t			frame_buffer_phys;		// card PCI BAR address of FB
214	uint32			frame_buffer_size;		// FB size mapped
215
216	bool			has_edid;
217	edid1_info		edid_info;
218
219	struct lock		accelerant_lock;
220	struct lock		engine_lock;
221
222	ring_buffer		primary_ring_buffer;
223
224	int32			overlay_channel_used;
225	bool			overlay_active;
226	uint32			overlay_token;
227	addr_t			physical_overlay_registers;
228	uint32			overlay_offset;
229
230	bool			hardware_cursor_enabled;
231	sem_id			vblank_sem;
232
233	uint8*			cursor_memory;
234	addr_t			physical_cursor_memory;
235	uint32			cursor_buffer_offset;
236	uint32			cursor_format;
237	bool			cursor_visible;
238	uint16			cursor_hot_x;
239	uint16			cursor_hot_y;
240
241	char			deviceName[MAX_NAME_LENGTH];
242	uint16			chipsetID;
243	char			chipsetName[MAX_NAME_LENGTH];
244	uint32			chipsetFlags;
245	uint8			dceMajor;
246	uint8			dceMinor;
247
248	uint16			color_data[3 * 256];    // colour lookup table
249};
250
251//----------------- ioctl() interface ----------------
252
253// magic code for ioctls
254#define RADEON_PRIVATE_DATA_MAGIC		'rdhd'
255
256// list ioctls
257enum {
258	RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
259
260	RADEON_GET_DEVICE_NAME,
261	RADEON_ALLOCATE_GRAPHICS_MEMORY,
262	RADEON_FREE_GRAPHICS_MEMORY
263};
264
265// retrieve the area_id of the kernel/accelerant shared info
266struct radeon_get_private_data {
267	uint32	magic;				// magic number
268	area_id	shared_info_area;
269};
270
271// allocate graphics memory
272struct radeon_allocate_graphics_memory {
273	uint32	magic;
274	uint32	size;
275	uint32	alignment;
276	uint32	flags;
277	uint32	buffer_base;
278};
279
280// free graphics memory
281struct radeon_free_graphics_memory {
282	uint32 	magic;
283	uint32	buffer_base;
284};
285
286// registers
287#define R6XX_CONFIG_APER_SIZE			0x5430	// r600>
288#define OLD_CONFIG_APER_SIZE			0x0108	// <r600
289#define CONFIG_MEMSIZE                  0x5428	// r600>
290
291// PCI bridge memory management
292
293// overlay
294
295#define RADEON_OVERLAY_UPDATE			0x30000
296#define RADEON_OVERLAY_TEST				0x30004
297#define RADEON_OVERLAY_STATUS			0x30008
298#define RADEON_OVERLAY_EXTENDED_STATUS	0x3000c
299#define RADEON_OVERLAY_GAMMA_5			0x30010
300#define RADEON_OVERLAY_GAMMA_4			0x30014
301#define RADEON_OVERLAY_GAMMA_3			0x30018
302#define RADEON_OVERLAY_GAMMA_2			0x3001c
303#define RADEON_OVERLAY_GAMMA_1			0x30020
304#define RADEON_OVERLAY_GAMMA_0			0x30024
305
306struct overlay_scale {
307	uint32 _reserved0 : 3;
308	uint32 horizontal_scale_fraction : 12;
309	uint32 _reserved1 : 1;
310	uint32 horizontal_downscale_factor : 3;
311	uint32 _reserved2 : 1;
312	uint32 vertical_scale_fraction : 12;
313};
314
315#define OVERLAY_FORMAT_RGB15			0x2
316#define OVERLAY_FORMAT_RGB16			0x3
317#define OVERLAY_FORMAT_RGB32			0x1
318#define OVERLAY_FORMAT_YCbCr422			0x8
319#define OVERLAY_FORMAT_YCbCr411			0x9
320#define OVERLAY_FORMAT_YCbCr420			0xc
321
322#define OVERLAY_MIRROR_NORMAL			0x0
323#define OVERLAY_MIRROR_HORIZONTAL		0x1
324#define OVERLAY_MIRROR_VERTICAL			0x2
325
326// The real overlay registers are written to using an update buffer
327
328struct overlay_registers {
329	uint32 buffer_rgb0;
330	uint32 buffer_rgb1;
331	uint32 buffer_u0;
332	uint32 buffer_v0;
333	uint32 buffer_u1;
334	uint32 buffer_v1;
335	// (0x18) OSTRIDE - overlay stride
336	uint16 stride_rgb;
337	uint16 stride_uv;
338	// (0x1c) YRGB_VPH - Y/RGB vertical phase
339	uint16 vertical_phase0_rgb;
340	uint16 vertical_phase1_rgb;
341	// (0x20) UV_VPH - UV vertical phase
342	uint16 vertical_phase0_uv;
343	uint16 vertical_phase1_uv;
344	// (0x24) HORZ_PH - horizontal phase
345	uint16 horizontal_phase_rgb;
346	uint16 horizontal_phase_uv;
347	// (0x28) INIT_PHS - initial phase shift
348	uint32 initial_vertical_phase0_shift_rgb0 : 4;
349	uint32 initial_vertical_phase1_shift_rgb0 : 4;
350	uint32 initial_horizontal_phase_shift_rgb0 : 4;
351	uint32 initial_vertical_phase0_shift_uv : 4;
352	uint32 initial_vertical_phase1_shift_uv : 4;
353	uint32 initial_horizontal_phase_shift_uv : 4;
354	uint32 _reserved0 : 8;
355	// (0x2c) DWINPOS - destination window position
356	uint16 window_left;
357	uint16 window_top;
358	// (0x30) DWINSZ - destination window size
359	uint16 window_width;
360	uint16 window_height;
361	// (0x34) SWIDTH - source width
362	uint16 source_width_rgb;
363	uint16 source_width_uv;
364	// (0x38) SWITDHSW - source width in 8 byte steps
365	uint16 source_bytes_per_row_rgb;
366	uint16 source_bytes_per_row_uv;
367	uint16 source_height_rgb;
368	uint16 source_height_uv;
369	overlay_scale scale_rgb;
370	overlay_scale scale_uv;
371	// (0x48) OCLRC0 - overlay color correction 0
372	uint32 brightness_correction : 8;		// signed, -128 to 127
373	uint32 _reserved1 : 10;
374	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
375	uint32 _reserved2 : 5;
376	// (0x4c) OCLRC1 - overlay color correction 1
377	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
378	uint32 _reserved3 : 6;
379	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
380	uint32 _reserved4 : 5;
381	// (0x50) DCLRKV - destination color key value
382	uint32 color_key_blue : 8;
383	uint32 color_key_green : 8;
384	uint32 color_key_red : 8;
385	uint32 _reserved5 : 8;
386	// (0x54) DCLRKM - destination color key mask
387	uint32 color_key_mask_blue : 8;
388	uint32 color_key_mask_green : 8;
389	uint32 color_key_mask_red : 8;
390	uint32 _reserved6 : 7;
391	uint32 color_key_enabled : 1;
392	// (0x58) SCHRKVH - source chroma key high value
393	uint32 source_chroma_key_high_red : 8;
394	uint32 source_chroma_key_high_blue : 8;
395	uint32 source_chroma_key_high_green : 8;
396	uint32 _reserved7 : 8;
397	// (0x5c) SCHRKVL - source chroma key low value
398	uint32 source_chroma_key_low_red : 8;
399	uint32 source_chroma_key_low_blue : 8;
400	uint32 source_chroma_key_low_green : 8;
401	uint32 _reserved8 : 8;
402	// (0x60) SCHRKEN - source chroma key enable
403	uint32 _reserved9 : 24;
404	uint32 source_chroma_key_red_enabled : 1;
405	uint32 source_chroma_key_blue_enabled : 1;
406	uint32 source_chroma_key_green_enabled : 1;
407	uint32 _reserved10 : 5;
408	// (0x64) OCONFIG - overlay configuration
409	uint32 _reserved11 : 3;
410	uint32 color_control_output_mode : 1;
411	uint32 yuv_to_rgb_bypass : 1;
412	uint32 _reserved12 : 11;
413	uint32 gamma2_enabled : 1;
414	uint32 _reserved13 : 1;
415	uint32 select_pipe : 1;
416	uint32 slot_time : 8;
417	uint32 _reserved14 : 5;
418	// (0x68) OCOMD - overlay command
419	uint32 overlay_enabled : 1;
420	uint32 active_field : 1;
421	uint32 active_buffer : 2;
422	uint32 test_mode : 1;
423	uint32 buffer_field_mode : 1;
424	uint32 _reserved15 : 1;
425	uint32 tv_flip_field_enabled : 1;
426	uint32 _reserved16 : 1;
427	uint32 tv_flip_field_parity : 1;
428	uint32 source_format : 4;
429	uint32 ycbcr422_order : 2;
430	uint32 _reserved18 : 1;
431	uint32 mirroring_mode : 2;
432	uint32 _reserved19 : 13;
433
434	uint32 _reserved20;
435
436	uint32 start_0y;
437	uint32 start_1y;
438	uint32 start_0u;
439	uint32 start_0v;
440	uint32 start_1u;
441	uint32 start_1v;
442	uint32 _reserved21[6];
443#if 0
444	// (0x70) AWINPOS - alpha blend window position
445	uint32 awinpos;
446	// (0x74) AWINSZ - alpha blend window size
447	uint32 awinsz;
448
449	uint32 _reserved21[10];
450#endif
451
452	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
453	// the next two registers switch the usual Y/RGB vs. UV order)
454	uint16 horizontal_scale_uv;
455	uint16 horizontal_scale_rgb;
456	// (0xa4) UVSCALEV - vertical downscale
457	uint16 vertical_scale_uv;
458	uint16 vertical_scale_rgb;
459
460	uint32 _reserved22[86];
461
462	// (0x200) polyphase filter coefficients
463	uint16 vertical_coefficients_rgb[128];
464	uint16 horizontal_coefficients_rgb[128];
465
466	uint32	_reserved23[64];
467
468	// (0x500)
469	uint16 vertical_coefficients_uv[128];
470	uint16 horizontal_coefficients_uv[128];
471};
472
473
474struct hardware_status {
475	uint32	interrupt_status_register;
476	uint32	_reserved0[3];
477	void*	primary_ring_head_storage;
478	uint32	_reserved1[3];
479	void*	secondary_ring_0_head_storage;
480	void*	secondary_ring_1_head_storage;
481	uint32	_reserved2[2];
482	void*	binning_head_storage;
483	uint32	_reserved3[3];
484	uint32	store[1008];
485};
486
487#endif	/* RADEON_HD_H */
488