1/*
2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 *		Alexander von Gluck IV, kallisti5@unixzen.com
8 */
9#ifndef RADEON_HD_H
10#define RADEON_HD_H
11
12
13#include "lock.h"
14
15#include "radeon_reg.h"
16
17//#include "r500_reg.h"  // Not used atm. DCE 0
18#include "avivo_reg.h"		// DCE 1
19#include "r600_reg.h"		// DCE 2
20#include "r700_reg.h"		// DCE 3
21#include "evergreen_reg.h"	// DCE 4
22#include "ni_reg.h"			// DCE 5
23#include "si_reg.h"			// DCE 6
24#include "sea_reg.h"		// DCE 8
25#include "vol_reg.h"		// DCE 10
26#include "car_reg.h"		// DCE 11
27
28#include <Accelerant.h>
29#include <Drivers.h>
30#include <edid.h>
31#include <PCI.h>
32
33
34#define VENDOR_ID_ATI	0x1002
35
36// Card chipset flags
37#define CHIP_STD		(1 << 0) // Standard chipset
38#define CHIP_X2			(1 << 1) // Dual cpu
39#define CHIP_IGP		(1 << 2) // IGP chipset
40#define CHIP_MOBILE		(1 << 3) // Mobile chipset
41#define CHIP_DISCREET	(1 << 4) // Discreet chipset
42#define CHIP_APU		(1 << 5) // APU chipset
43
44#define DEVICE_NAME				"radeon_hd"
45#define RADEON_ACCELERANT_NAME	"radeon_hd.accelerant"
46
47#define MAX_NAME_LENGTH		32
48
49// Used to collect EDID from boot loader
50#define EDID_BOOT_INFO "vesa_edid/v1"
51#define MODES_BOOT_INFO "vesa_modes/v1"
52
53#define RHD_POWER_ON       0
54#define RHD_POWER_RESET    1   /* off temporarily */
55#define RHD_POWER_SHUTDOWN 2   /* long term shutdown */
56#define RHD_POWER_UNKNOWN  3   /* initial state */
57
58
59// Radeon Chipsets
60// !! Must match chipset names below
61enum radeon_chipset {
62	RADEON_R420 = 0,	//r400, Radeon X700-X850
63	RADEON_R423,
64	RADEON_RV410,
65	RADEON_RS400,
66	RADEON_RS480,
67	RADEON_RS600,
68	RADEON_RS690,
69	RADEON_RS740,
70	RADEON_RV515,
71	RADEON_R520,		//r500, DCE 1.0
72	RADEON_RV530,		// DCE 1.0
73	RADEON_RV560,		// DCE 1.0
74	RADEON_RV570,		// DCE 1.0
75	RADEON_R580,		// DCE 1.0
76	RADEON_R600,		//r600, DCE 2.0
77	RADEON_RV610,		// DCE 2.0
78	RADEON_RV630,		// DCE 2.0
79	RADEON_RV670,		// DCE 2.0
80	RADEON_RV620,		// DCE 3.0
81	RADEON_RV635,		// DCE 3.0
82	RADEON_RS780,		// DCE 3.0
83	RADEON_RS880,		// DCE 3.0
84	RADEON_RV770,		//r700, DCE 3.1
85	RADEON_RV730,		// DCE 3.2
86	RADEON_RV710,		// DCE 3.2
87	RADEON_RV740,		// DCE 3.2
88	RADEON_CEDAR,		//Evergreen, DCE 4.0
89	RADEON_REDWOOD,		// DCE 4.0
90	RADEON_JUNIPER,		// DCE 4.0
91	RADEON_CYPRESS,		// DCE 4.0
92	RADEON_HEMLOCK,		// DCE 4.0?
93	RADEON_PALM,		//Fusion APU (NI), DCE 4.1
94	RADEON_SUMO,		// DCE 4.1
95	RADEON_SUMO2,		// DCE 4.1
96	RADEON_CAICOS,		//Nothern Islands, DCE 5.0
97	RADEON_TURKS,		// DCE 5.0
98	RADEON_BARTS,		// DCE 5.0
99	RADEON_CAYMAN,		// DCE 5.0
100	RADEON_ANTILLES,	// DCE 5.0?
101	RADEON_CAPEVERDE,	//Southern Islands, DCE 6.0
102	RADEON_PITCAIRN,	// DCE 6.0
103	RADEON_TAHITI,		// DCE 6.0
104	RADEON_ARUBA,		// DCE 6.1 Trinity/Richland
105	RADEON_OLAND,		// DCE 6.4
106	RADEON_HAINAN,		// NO DCE, only compute
107	RADEON_KAVERI,		//Sea Islands, DCE 8.1
108	RADEON_BONAIRE,		// DCE 8.2
109	RADEON_KABINI,		// DCE 8.3
110	RADEON_MULLINS,		// DCE 8.3
111	RADEON_HAWAII,		// DCE 8.5
112	RADEON_TOPAZ,		//Volcanic Islands, NO DCE
113	RADEON_TONGA,		// DCE 10.0
114	RADEON_CARRIZO,		// DCE 11.0
115	RADEON_POLARIS,		//Artic Islands, DCE 12.0*
116	RADEON_VEGA,		// DCE 13.0*
117};
118
119// !! Must match chipset families above
120static const char radeon_chip_name[][MAX_NAME_LENGTH] = {
121	"R420",
122	"R423",
123	"RV410",
124	"RS400",
125	"RS480",
126	"RS600",
127	"RS690",
128	"RS740",
129	"RV515",
130	"R520",
131	"RV530",
132	"RV560",
133	"RV570",
134	"R580",
135	"R600",
136	"RV610",
137	"RV630",
138	"RV670",
139	"RV620",
140	"RV635",
141	"RS780",
142	"RS880",
143	"RV770",
144	"RV730",
145	"RV710",
146	"RV740",
147	"Cedar",
148	"Redwood",
149	"Juniper",
150	"Cypress",
151	"Hemlock",
152	"Palm",
153	"Sumo",
154	"Sumo2",
155	"Caicos",
156	"Turks",
157	"Barts",
158	"Cayman",
159	"Antilles",
160	"Cape Verde",
161	"Pitcairn",
162	"Tahiti",
163	"Aruba",
164	"Oland",
165	"Hainan",
166	"Kaveri",
167	"Bonaire",
168	"Kabini",
169	"Mullins",
170	"Hawaii",
171	"Topaz",
172	"Tonga",
173	"Carrizo",
174	"Polaris"
175};
176
177
178struct ring_buffer {
179	struct lock		lock;
180	uint32			register_base;
181	uint32			offset;
182	uint32			size;
183	uint32			position;
184	uint32			space_left;
185	uint8*			base;
186};
187
188
189struct overlay_registers;
190
191
192struct radeon_shared_info {
193	uint32			deviceIndex;		// accelerant index
194	uint32			pciID;				// device pci id
195	uint32			pciRev;				// device pci revision
196	area_id			mode_list_area;		// area containing display mode list
197	uint32			mode_count;
198
199	bool			has_rom;			// was rom mapped?
200	area_id			rom_area;			// area of mapped rom
201	uint32			rom_phys;			// rom base location
202	uint32			rom_size;			// rom size
203	uint8*			rom;				// cloned, memory mapped PCI ROM
204
205	display_mode	current_mode;
206	uint32			bytes_per_row;
207	uint32			bits_per_pixel;
208	uint32			dpms_mode;
209
210	area_id			registers_area;			// area of memory mapped registers
211	uint8*			status_page;
212	addr_t			physical_status_page;
213	uint32			graphics_memory_size;
214
215	uint8*			frame_buffer;			// virtual memory mapped FB
216	area_id			frame_buffer_area;		// area of memory mapped FB
217	addr_t			frame_buffer_phys;		// card PCI BAR address of FB
218	uint32			frame_buffer_size;		// FB size mapped
219
220	bool			has_edid;
221	edid1_info		edid_info;
222
223	struct lock		accelerant_lock;
224	struct lock		engine_lock;
225
226	ring_buffer		primary_ring_buffer;
227
228	int32			overlay_channel_used;
229	bool			overlay_active;
230	uint32			overlay_token;
231	addr_t			physical_overlay_registers;
232	uint32			overlay_offset;
233
234	bool			hardware_cursor_enabled;
235	sem_id			vblank_sem;
236
237	uint8*			cursor_memory;
238	addr_t			physical_cursor_memory;
239	uint32			cursor_buffer_offset;
240	uint32			cursor_format;
241	bool			cursor_visible;
242	uint16			cursor_hot_x;
243	uint16			cursor_hot_y;
244
245	char			deviceName[MAX_NAME_LENGTH];
246	uint16			chipsetID;
247	char			chipsetName[MAX_NAME_LENGTH];
248	uint32			chipsetFlags;
249	uint8			dceMajor;
250	uint8			dceMinor;
251
252	uint16			color_data[3 * 256];    // colour lookup table
253};
254
255//----------------- ioctl() interface ----------------
256
257// magic code for ioctls
258#define RADEON_PRIVATE_DATA_MAGIC		'rdhd'
259
260// list ioctls
261enum {
262	RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
263
264	RADEON_GET_DEVICE_NAME,
265	RADEON_ALLOCATE_GRAPHICS_MEMORY,
266	RADEON_FREE_GRAPHICS_MEMORY
267};
268
269// retrieve the area_id of the kernel/accelerant shared info
270struct radeon_get_private_data {
271	uint32	magic;				// magic number
272	area_id	shared_info_area;
273};
274
275// allocate graphics memory
276struct radeon_allocate_graphics_memory {
277	uint32	magic;
278	uint32	size;
279	uint32	alignment;
280	uint32	flags;
281	uint32	buffer_base;
282};
283
284// free graphics memory
285struct radeon_free_graphics_memory {
286	uint32 	magic;
287	uint32	buffer_base;
288};
289
290// registers
291#define R6XX_CONFIG_APER_SIZE			0x5430	// r600>
292#define OLD_CONFIG_APER_SIZE			0x0108	// <r600
293#define CONFIG_MEMSIZE                  0x5428	// r600>
294
295// PCI bridge memory management
296
297// overlay
298
299#define RADEON_OVERLAY_UPDATE			0x30000
300#define RADEON_OVERLAY_TEST				0x30004
301#define RADEON_OVERLAY_STATUS			0x30008
302#define RADEON_OVERLAY_EXTENDED_STATUS	0x3000c
303#define RADEON_OVERLAY_GAMMA_5			0x30010
304#define RADEON_OVERLAY_GAMMA_4			0x30014
305#define RADEON_OVERLAY_GAMMA_3			0x30018
306#define RADEON_OVERLAY_GAMMA_2			0x3001c
307#define RADEON_OVERLAY_GAMMA_1			0x30020
308#define RADEON_OVERLAY_GAMMA_0			0x30024
309
310struct overlay_scale {
311	uint32 _reserved0 : 3;
312	uint32 horizontal_scale_fraction : 12;
313	uint32 _reserved1 : 1;
314	uint32 horizontal_downscale_factor : 3;
315	uint32 _reserved2 : 1;
316	uint32 vertical_scale_fraction : 12;
317};
318
319#define OVERLAY_FORMAT_RGB15			0x2
320#define OVERLAY_FORMAT_RGB16			0x3
321#define OVERLAY_FORMAT_RGB32			0x1
322#define OVERLAY_FORMAT_YCbCr422			0x8
323#define OVERLAY_FORMAT_YCbCr411			0x9
324#define OVERLAY_FORMAT_YCbCr420			0xc
325
326#define OVERLAY_MIRROR_NORMAL			0x0
327#define OVERLAY_MIRROR_HORIZONTAL		0x1
328#define OVERLAY_MIRROR_VERTICAL			0x2
329
330// The real overlay registers are written to using an update buffer
331
332struct overlay_registers {
333	uint32 buffer_rgb0;
334	uint32 buffer_rgb1;
335	uint32 buffer_u0;
336	uint32 buffer_v0;
337	uint32 buffer_u1;
338	uint32 buffer_v1;
339	// (0x18) OSTRIDE - overlay stride
340	uint16 stride_rgb;
341	uint16 stride_uv;
342	// (0x1c) YRGB_VPH - Y/RGB vertical phase
343	uint16 vertical_phase0_rgb;
344	uint16 vertical_phase1_rgb;
345	// (0x20) UV_VPH - UV vertical phase
346	uint16 vertical_phase0_uv;
347	uint16 vertical_phase1_uv;
348	// (0x24) HORZ_PH - horizontal phase
349	uint16 horizontal_phase_rgb;
350	uint16 horizontal_phase_uv;
351	// (0x28) INIT_PHS - initial phase shift
352	uint32 initial_vertical_phase0_shift_rgb0 : 4;
353	uint32 initial_vertical_phase1_shift_rgb0 : 4;
354	uint32 initial_horizontal_phase_shift_rgb0 : 4;
355	uint32 initial_vertical_phase0_shift_uv : 4;
356	uint32 initial_vertical_phase1_shift_uv : 4;
357	uint32 initial_horizontal_phase_shift_uv : 4;
358	uint32 _reserved0 : 8;
359	// (0x2c) DWINPOS - destination window position
360	uint16 window_left;
361	uint16 window_top;
362	// (0x30) DWINSZ - destination window size
363	uint16 window_width;
364	uint16 window_height;
365	// (0x34) SWIDTH - source width
366	uint16 source_width_rgb;
367	uint16 source_width_uv;
368	// (0x38) SWITDHSW - source width in 8 byte steps
369	uint16 source_bytes_per_row_rgb;
370	uint16 source_bytes_per_row_uv;
371	uint16 source_height_rgb;
372	uint16 source_height_uv;
373	overlay_scale scale_rgb;
374	overlay_scale scale_uv;
375	// (0x48) OCLRC0 - overlay color correction 0
376	uint32 brightness_correction : 8;		// signed, -128 to 127
377	uint32 _reserved1 : 10;
378	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
379	uint32 _reserved2 : 5;
380	// (0x4c) OCLRC1 - overlay color correction 1
381	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
382	uint32 _reserved3 : 6;
383	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
384	uint32 _reserved4 : 5;
385	// (0x50) DCLRKV - destination color key value
386	uint32 color_key_blue : 8;
387	uint32 color_key_green : 8;
388	uint32 color_key_red : 8;
389	uint32 _reserved5 : 8;
390	// (0x54) DCLRKM - destination color key mask
391	uint32 color_key_mask_blue : 8;
392	uint32 color_key_mask_green : 8;
393	uint32 color_key_mask_red : 8;
394	uint32 _reserved6 : 7;
395	uint32 color_key_enabled : 1;
396	// (0x58) SCHRKVH - source chroma key high value
397	uint32 source_chroma_key_high_red : 8;
398	uint32 source_chroma_key_high_blue : 8;
399	uint32 source_chroma_key_high_green : 8;
400	uint32 _reserved7 : 8;
401	// (0x5c) SCHRKVL - source chroma key low value
402	uint32 source_chroma_key_low_red : 8;
403	uint32 source_chroma_key_low_blue : 8;
404	uint32 source_chroma_key_low_green : 8;
405	uint32 _reserved8 : 8;
406	// (0x60) SCHRKEN - source chroma key enable
407	uint32 _reserved9 : 24;
408	uint32 source_chroma_key_red_enabled : 1;
409	uint32 source_chroma_key_blue_enabled : 1;
410	uint32 source_chroma_key_green_enabled : 1;
411	uint32 _reserved10 : 5;
412	// (0x64) OCONFIG - overlay configuration
413	uint32 _reserved11 : 3;
414	uint32 color_control_output_mode : 1;
415	uint32 yuv_to_rgb_bypass : 1;
416	uint32 _reserved12 : 11;
417	uint32 gamma2_enabled : 1;
418	uint32 _reserved13 : 1;
419	uint32 select_pipe : 1;
420	uint32 slot_time : 8;
421	uint32 _reserved14 : 5;
422	// (0x68) OCOMD - overlay command
423	uint32 overlay_enabled : 1;
424	uint32 active_field : 1;
425	uint32 active_buffer : 2;
426	uint32 test_mode : 1;
427	uint32 buffer_field_mode : 1;
428	uint32 _reserved15 : 1;
429	uint32 tv_flip_field_enabled : 1;
430	uint32 _reserved16 : 1;
431	uint32 tv_flip_field_parity : 1;
432	uint32 source_format : 4;
433	uint32 ycbcr422_order : 2;
434	uint32 _reserved18 : 1;
435	uint32 mirroring_mode : 2;
436	uint32 _reserved19 : 13;
437
438	uint32 _reserved20;
439
440	uint32 start_0y;
441	uint32 start_1y;
442	uint32 start_0u;
443	uint32 start_0v;
444	uint32 start_1u;
445	uint32 start_1v;
446	uint32 _reserved21[6];
447#if 0
448	// (0x70) AWINPOS - alpha blend window position
449	uint32 awinpos;
450	// (0x74) AWINSZ - alpha blend window size
451	uint32 awinsz;
452
453	uint32 _reserved21[10];
454#endif
455
456	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
457	// the next two registers switch the usual Y/RGB vs. UV order)
458	uint16 horizontal_scale_uv;
459	uint16 horizontal_scale_rgb;
460	// (0xa4) UVSCALEV - vertical downscale
461	uint16 vertical_scale_uv;
462	uint16 vertical_scale_rgb;
463
464	uint32 _reserved22[86];
465
466	// (0x200) polyphase filter coefficients
467	uint16 vertical_coefficients_rgb[128];
468	uint16 horizontal_coefficients_rgb[128];
469
470	uint32	_reserved23[64];
471
472	// (0x500)
473	uint16 vertical_coefficients_uv[128];
474	uint16 horizontal_coefficients_uv[128];
475};
476
477
478struct hardware_status {
479	uint32	interrupt_status_register;
480	uint32	_reserved0[3];
481	void*	primary_ring_head_storage;
482	uint32	_reserved1[3];
483	void*	secondary_ring_0_head_storage;
484	void*	secondary_ring_1_head_storage;
485	uint32	_reserved2[2];
486	void*	binning_head_storage;
487	uint32	_reserved3[3];
488	uint32	store[1008];
489};
490
491#endif	/* RADEON_HD_H */
492