DriverInterface.h revision b0c69e84
1/*
2	Copyright 1999, Be Incorporated.   All Rights Reserved.
3	This file may be used under the terms of the Be Sample Code License.
4
5	Other authors:
6	Mark Watson;
7	Apsed;
8	Rudolf Cornelissen 10/2002-1/2016.
9*/
10
11#ifndef DRIVERINTERFACE_H
12#define DRIVERINTERFACE_H
13
14#include <Accelerant.h>
15#include <video_overlay.h>
16#include <Drivers.h>
17#include <PCI.h>
18#include <OS.h>
19#include <edid.h>
20#include <AGP.h>
21
22#define DRIVER_PREFIX "nvidia"
23#define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x"
24
25/*
26	Internal driver state (also for sharing info between driver and accelerant)
27*/
28#if defined(__cplusplus)
29extern "C" {
30#endif
31
32typedef struct {
33	sem_id	sem;
34	int32	ben;
35} benaphore;
36
37#define INIT_BEN(x)		x.sem = create_sem(0, "NV "#x" benaphore");  x.ben = 0;
38#define AQUIRE_BEN(x)	if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
39#define RELEASE_BEN(x)	if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
40#define	DELETE_BEN(x)	delete_sem(x.sem);
41
42
43#define NV_PRIVATE_DATA_MAGIC	0x0009 /* a private driver rev, of sorts */
44
45/* monitor setup */
46#define CRTC1_TMDS	0x01
47#define CRTC2_TMDS	0x10
48#define CRTC1_VGA	0x02
49#define CRTC2_VGA	0x20
50
51/* dualhead extensions to flags */
52#define DUALHEAD_OFF (0<<6)
53#define DUALHEAD_CLONE (1<<6)
54#define DUALHEAD_ON (2<<6)
55#define DUALHEAD_SWITCH (3<<6)
56#define DUALHEAD_BITS (3<<6)
57#define DUALHEAD_CAPABLE (1<<8)
58#define TV_BITS (3<<9)
59#define TV_MON (0<<9)
60#define TV_PAL (1<<9)
61#define TV_NTSC (2<<9)
62#define TV_CAPABLE (1<<11)
63#define TV_VIDEO (1<<12)
64#define TV_PRIMARY (1<<13)
65
66/* additional timing flags for GetMode/SetMode for Haiku ScreenPrefs panel */
67enum {
68	RADEON_MODE_MULTIMON_REQUEST = 1 << 25,
69	RADEON_MODE_MULTIMON_REPLY = 1 << 26
70};
71
72/* operation codes tunneled via ProposeDisplayMode for Haiku ScreenPrefs panel */
73typedef enum {
74	ms_swap 			= 'sw',
75	ms_use_laptop_panel	= 'up',
76	ms_tv_standard		= 'tv'
77} multi_mon_settings;
78
79
80#define SKD_MOVE_CURSOR    0x00000001
81#define SKD_PROGRAM_CLUT   0x00000002
82#define SKD_SET_START_ADDR 0x00000004
83#define SKD_SET_CURSOR     0x00000008
84#define SKD_HANDLER_INSTALLED 0x80000000
85
86enum {
87	NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
88	NV_GET_PCI,
89	NV_SET_PCI,
90	NV_DEVICE_NAME,
91	NV_RUN_INTERRUPTS,
92	NV_GET_NTH_AGP_INFO,
93	NV_ENABLE_AGP,
94	NV_ISA_OUT,
95	NV_ISA_IN
96};
97
98/* card_type in order of date of NV chip design */
99enum {
100	NV04 = 0,
101	NV05,
102	NV05M64,
103	NV06,
104	NV10,
105	NV11,
106	NV15,
107	NV17,
108	NV18,
109	NV20,
110	NV25,
111	NV28,
112	NV30,
113	NV31,
114	NV34,
115	NV35,
116	NV36,
117	NV38,
118	NV40,
119	NV41,
120	NV43,
121	NV44,
122	NV45,
123	G70,
124	G71,
125	G72,
126	G73
127};
128
129/* card_arch in order of date of NV chip design */
130enum {
131	NV04A = 0,
132	NV10A,
133	NV20A,
134	NV30A,
135	NV40A
136};
137
138/* card info - information gathered from PINS (and other sources) */
139enum
140{	// tv_encoder_type in order of capability (more or less)
141	NONE = 0,
142	CH7003,
143	CH7004,
144	CH7005,
145	CH7006,
146	CH7007,
147	CH7008,
148	SAA7102,
149	SAA7103,
150	SAA7104,
151	SAA7105,
152	BT868,
153	BT869,
154	CX25870,
155	CX25871,
156	NVIDIA
157};
158
159/* handles to pre-defined engine commands */
160#define NV_ROP5_SOLID					0x00000000 /* 2D */
161#define NV_IMAGE_BLACK_RECTANGLE		0x00000001 /* 2D/3D */
162#define NV_IMAGE_PATTERN				0x00000002 /* 2D */
163#define NV_SCALED_IMAGE_FROM_MEMORY		0x00000003 /* 2D */
164#define NV_TCL_PRIMITIVE_3D				0x00000004 /* 3D */ //2007
165#define NV4_SURFACE						0x00000010 /* 2D */
166#define NV10_CONTEXT_SURFACES_2D		0x00000010 /* 2D */
167#define NV_IMAGE_BLIT					0x00000011 /* 2D */
168#define NV12_IMAGE_BLIT					0x00000011 /* 2D */
169/* fixme:
170 * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration:
171 * There's a hardware fault in the input->output colorspace conversion here.
172 * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed
173 * by testing.
174 */
175//#define NV3_GDI_RECTANGLE_TEXT			0x00000012 /* 2D */
176#define NV4_GDI_RECTANGLE_TEXT			0x00000012 /* 2D */
177#define NV4_CONTEXT_SURFACES_ARGB_ZS	0x00000013 /* 3D */
178#define NV10_CONTEXT_SURFACES_ARGB_ZS	0x00000013 /* 3D */
179#define NV4_DX5_TEXTURE_TRIANGLE		0x00000014 /* 3D */
180#define NV10_DX5_TEXTURE_TRIANGLE		0x00000014 /* 3D */
181#define NV4_DX6_MULTI_TEXTURE_TRIANGLE	0x00000015 /* unused (yet?) */
182#define NV10_DX6_MULTI_TEXTURE_TRIANGLE	0x00000015 /* unused (yet?) */
183#define NV1_RENDER_SOLID_LIN			0x00000016 /* 2D: unused */
184
185/* max. number of overlay buffers */
186#define MAXBUFFERS 3
187
188//-----------------------------------------------------------------------------------
189/* safety byte-offset from end of cardRAM for preventing acceleration engine crashes
190 * caused by the existance of DMA engine command buffers in cardRAM and/or fifo
191 * channel engine command re-assigning on-the-fly */
192
193/* pre-NV40 notes:
194 * - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug'
195 *   (confirmed on a TNT1);
196 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */
197#define PRE_NV40_OFFSET		80 * 1024
198
199/* NV40 and higher notes:
200 * - we need at least 416kB distance from the DMA command buffer:
201 *   If you get too close to the DMA command buffer on NV40 and NV43 at least (both
202 *   confirmed), the source DMA instance will mess-up for at least engine command
203 *   NV_IMAGE_BLIT and NV12_IMAGE_BLIT;
204 * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug'
205 *   (fixme: unknown yet because fifo assignment switching isn't used here atm);
206 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */
207#define NV40_PLUS_OFFSET	512 * 1024
208
209/* fifo re-assigning bug definition:
210 * if the fifo assignment is changed while at the same time card memory in the
211 * dangerous region is being accessed by some application, the engine will crash.
212 * This bug applies for both PIO and DMA mode acceleration! */
213
214/* source-DMA instance bug definition:
215 * if card memory in the dangerous region is being accessed by some application while
216 * a DMA command buffer exists in the same memory (though in a different place),
217 * the engine will crash. */
218//-----------------------------------------------------------------------------------
219
220/* internal used info on overlay buffers */
221typedef	struct {
222	uint16 slopspace;
223	uint32 size;
224} int_buf_info;
225
226typedef struct { // apsed, see comments in nvidia.settings
227	// for driver
228	char   accelerant[B_FILE_NAME_LENGTH];
229	char   primary[B_FILE_NAME_LENGTH];
230	bool   dumprom;
231	// for accelerant
232	uint32 logmask;
233	uint32 memory;
234	uint32 tv_output;
235	bool   usebios;
236	bool   hardcursor;
237	bool   switchhead;
238	bool   force_pci;
239	bool   unhide_fw;
240	bool   pgm_panel;
241	bool   dma_acc;
242	bool   vga_on_tv;
243	bool   force_sync;
244	bool   force_ws;
245	bool   block_acc;
246	uint32 gpu_clk;
247	uint32 ram_clk;
248	bool   check_edid;
249} nv_settings;
250
251/* monitor info gathered via EDID */
252typedef struct {
253	bool have_native_edid;	/* gathered 'native' EDID either via DDC or via GPU */
254	bool digital;			/* screen connection type: analog (VGA) or digital (DVI) */
255	display_timing timing;	/* 'native modeline' fetched for screen */
256	float aspect;			/* screen's aspect ratio */
257	bool have_full_edid;	/* EDID read succesfully via DDC  */
258	edid1_info full_edid;	/* complete EDID info as fetched via DDC */
259} edid_specs;
260
261/* shared info */
262typedef struct {
263  /* a few ID things */
264	uint16	vendor_id;	/* PCI vendor ID, from pci_info */
265	uint16	device_id;	/* PCI device ID, from pci_info */
266	uint8	revision;	/* PCI device revsion, from pci_info */
267	uint8	bus;		/* PCI bus number, from pci_info */
268	uint8	device;		/* PCI device number on bus, from pci_info */
269	uint8	function;	/* PCI function number in device, from pci_info */
270
271  /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */
272	bool	accelerant_in_use;
273
274  /* bug workaround for 4.5.0 */
275	uint32 use_clone_bugfix;	/*for 4.5.0, cloning of physical memory does not work*/
276	uint32 * clone_bugfix_regs;
277
278  /*memory mappings*/
279	area_id	regs_area;	/* Kernel's area_id for the memory mapped registers.
280							It will be cloned into the accelerant's	address
281							space. */
282
283	area_id	fb_area;	/* Frame buffer's area_id.  The addresses are shared with all teams. */
284	area_id	unaligned_dma_area;	/* Area assigned for DMA. It will be (partially) mapped to an
285									aligned area using MTRR-WC. */
286	area_id	dma_area;	/* Aligned area assigned for DMA. The addresses are shared with all teams. */
287
288	void	*framebuffer;		/* As viewed from virtual memory */
289	void	*framebuffer_pci;	/* As viewed from the PCI bus (for DMA) */
290	void	*dma_buffer;		/* As viewed from virtual memory */
291	void	*dma_buffer_pci;	/* As viewed from the PCI bus (for DMA) */
292
293  /*screenmode list*/
294	area_id	mode_area;              /* Contains the list of display modes the driver supports */
295	uint32	mode_count;             /* Number of display modes in the list */
296
297  /*flags - used by driver*/
298	uint32 flags;
299
300  /*vblank semaphore*/
301	sem_id	vblank;	                /* The vertical blank semaphore. Ownership will be
302						transfered to the team opening the device first */
303  /*cursor information*/
304	struct {
305		uint16	hot_x;		/* Cursor hot spot. The top left corner of the cursor */
306		uint16	hot_y;		/* is 0,0 */
307		uint16	x;		/* The location of the cursor hot spot on the */
308		uint16	y;		/* desktop */
309		uint16	width;		/* Width and height of the cursor shape (always 16!) */
310		uint16	height;
311		bool	is_visible;	/* Is the cursor currently displayed? */
312		bool	dh_right;	/* Is cursor on right side of stretched screen? */
313	} cursor;
314
315  /*colour lookup table*/
316	uint8	color_data[3 * 256];	/* Colour lookup table - as used by DAC */
317
318  /*more display mode stuff*/
319	display_mode dm;		/* current display mode configuration: head1 */
320	uint32 dpms_flags;		/* current DPMS mode */
321	bool acc_mode;			/* signals (non)accelerated mode */
322	bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */
323	bool crtc_switch_mode;	/* signals dualhead switch mode if panels are used */
324	bool haiku_prefs_used;	/* signals use of Haiku ScreenPrefs app for special modes */
325	bool Haiku_switch_head;	/* signals Haiku ScreenPrefs panel want inverted mode later on */
326
327  /*frame buffer config - for BDirectScreen*/
328	frame_buffer_config fbc;	/* bytes_per_row and start of frame buffer: head1 */
329	accelerant_device_info adi;	/* as returned by hook GET_ACCELERANT_DEVICE_INFO */
330
331  /*acceleration engine*/
332	struct {
333		uint32		count;		/* last dwgsync slot used */
334		uint32		last_idle;	/* last dwgsync slot we *know* the engine was idle after */
335		benaphore	lock;		/* for serializing access to the acc engine */
336		struct {
337			uint32	handle[0x08];	/* FIFO channel's cmd handle for the owning cmd */
338			uint32	ch_ptr[0x20];	/* cmd handle's ptr to it's assigned FIFO ch (if any) */
339		} fifo;
340		struct {
341			uint32 put;			/* last 32-bit-word adress given to engine to exec. to */
342			uint32 current;		/* first free 32-bit-word adress in buffer */
343			uint32 free;		/* nr. of useable free 32-bit words remaining in buffer */
344			uint32 max;			/* command buffer's useable size in 32-bit words */
345		} dma;
346		bool agp_mode;			/* card is running in AGP mode */
347		struct {
348			uint32 clones;		/* clone 'number' (mask, slot) (one bit per clone) */
349			uint32 reload;		/* reload state and surfaces (one bit per clone) */
350			uint32 newmode;		/* re-allocate all buffers (one bit per clone) */
351			//fixme: memory stuff needs to be expanded (shared texture allocation?)
352			uint32 mem_low;		/* ptr to first free mem adress: cardmem local offset */
353			uint32 mem_high;	/* ptr to last free mem adress: cardmem local offset */
354			bool mode_changing;	/* a mode-change is in progress (set/clear by 2D drv) */
355		} threeD;
356	} engine;
357
358	struct
359	{
360		/* specialised registers for card initialisation read from NV BIOS (pins) */
361
362		/* general card information */
363		uint32 card_type;           /* see card_type enum above */
364		uint32 card_arch;           /* see card_arch enum above */
365		bool laptop;	            /* mobile chipset or not ('internal' flatpanel!) */
366		bool slaved_tmds1;			/* external TMDS encoder active on CRTC1 */
367		bool slaved_tmds2;			/* external TMDS encoder active on CRTC2 */
368		bool master_tmds1;			/* on die TMDS encoder active on CRTC1 */
369		bool master_tmds2;			/* on die TMDS encoder active on CRTC2 */
370		display_timing p1_timing;	/* 'modeline' fetched for panel at CRTC1 */
371		display_timing p2_timing;	/* 'modeline' fetched for panel at CRTC2 */
372		edid_specs con1_screen;		/* EDID properties of the screen connected to connector 1 */
373		edid_specs con2_screen;		/* EDID properties of the screen connected to connector 2 */
374		edid_specs crtc1_screen;	/* EDID properties of the screen connected to CRTC1 */
375		edid_specs crtc2_screen;	/* EDID properties of the screen connected to CRTC2 */
376		bool crtc2_prim;			/* using CRTC2 as primary CRTC */
377		bool i2c_bus0;				/* we have a wired I2C bus 0 on board */
378		bool i2c_bus1;				/* we have a wired I2C bus 1 on board */
379		bool i2c_bus2;				/* we have a wired I2C bus 2 on board */
380		struct
381		{
382			uint32 type;			/* see tvchip_type enum above */
383			uint8 version;			/* chip silicon version */
384			uint8 bus;				/* I2C bus on which TVout chip resides */
385			uint8 adress;			/* I2C adress on which TVout chip resides */
386		} tv_encoder;
387		uint8 monitors;				/* output devices connection matrix */
388		bool int_assigned;			/* card has a useable INT assigned to it */
389		status_t pins_status;		/* B_OK if read correctly, B_ERROR if faked */
390
391		/* PINS */
392		float f_ref;				/* PLL reference-oscillator frequency (Mhz) */
393		bool ext_pll;				/* the extended PLL contains more dividers */
394		uint32 max_system_vco;		/* graphics engine PLL VCO limits (Mhz) */
395		uint32 min_system_vco;
396		uint32 max_pixel_vco;		/* dac1 PLL VCO limits (Mhz) */
397		uint32 min_pixel_vco;
398		uint32 max_video_vco;		/* dac2 PLL VCO limits (Mhz) */
399		uint32 min_video_vco;
400		uint32 std_engine_clock;	/* graphics engine clock speed needed (Mhz) */
401		uint32 std_memory_clock;	/* card memory clock speed needed (Mhz) */
402		uint32 max_dac1_clock;		/* dac1 limits (Mhz) */
403		uint32 max_dac1_clock_8;	/* dac1 limits correlated to RAMspeed limits (Mhz) */
404		uint32 max_dac1_clock_16;
405		uint32 max_dac1_clock_24;
406		uint32 max_dac1_clock_32;
407		uint32 max_dac1_clock_32dh;
408		uint32 max_dac2_clock;		/* dac2 limits (Mhz) */
409		uint32 max_dac2_clock_8;	/* dac2, maven limits correlated to RAMspeed limits (Mhz) */
410		uint32 max_dac2_clock_16;
411		uint32 max_dac2_clock_24;
412		uint32 max_dac2_clock_32;
413		uint32 max_dac2_clock_32dh;
414		bool secondary_head;		/* presence of functions */
415		bool tvout;
416		bool primary_dvi;
417		bool secondary_dvi;
418		uint32 memory_size;			/* memory (in bytes) */
419	} ps;
420
421	/* mirror of the ROM (copied in driver, because may not be mapped permanently) */
422	uint8 rom_mirror[65536];
423
424	/* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */
425	nv_settings settings;
426
427	struct
428	{
429		overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */
430		int_buf_info myBufInfo[MAXBUFFERS];	/* extra info on scaler input buffers */
431		overlay_token myToken;				/* scaler is free/in use */
432		benaphore lock;						/* for creating buffers and aquiring overlay unit routines */
433		bool crtc;							/* location of overlay unit */
434		/* variables needed for virtualscreens (move_overlay()): */
435		bool active;						/* true is overlay currently in use */
436		overlay_window ow;					/* current position of overlay output window */
437		overlay_buffer ob;					/* current inputbuffer in use */
438		overlay_view my_ov;					/* current corrected view in inputbuffer */
439		uint32 h_ifactor;					/* current 'unclipped' horizontal inverse scaling factor */
440		uint32 v_ifactor;					/* current 'unclipped' vertical inverse scaling factor */
441	} overlay;
442
443} shared_info;
444
445/* Read or write a value in PCI configuration space */
446typedef struct {
447	uint32	magic;		/* magic number to make sure the caller groks us */
448	uint32	offset;		/* Offset to read/write */
449	uint32	size;		/* Number of bytes to transfer */
450	uint32	value;		/* The value read or written */
451} nv_get_set_pci;
452
453/* Enable or Disable CRTC (1,2) interrupts */
454typedef struct {
455	uint32	magic;		/* magic number to make sure the caller groks us */
456	bool	crtc;		/* adressed CRTC */
457	bool	do_it;		/* state to set */
458} nv_set_vblank_int;
459
460/* Retrieve the area_id of the kernel/accelerant shared info */
461typedef struct {
462	uint32	magic;		/* magic number to make sure the caller groks us */
463	area_id	shared_info_area;	/* area_id containing the shared information */
464} nv_get_private_data;
465
466/* Retrieve the device name.  Usefull for when we have a file handle, but want
467to know the device name (like when we are cloning the accelerant) */
468typedef struct {
469	uint32	magic;		/* magic number to make sure the caller groks us */
470	char	*name;		/* The name of the device, less the /dev root */
471} nv_device_name;
472
473/* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme
474used (pre 3.x or 3.x) */
475typedef struct {
476	uint32		magic;	/* magic number to make sure the caller groks us */
477	bool		agp_bus;/* indicates if we have access to the AGP busmanager */
478	uint8		index;	/* device index in list of devices found */
479	bool		exist;	/* we got AGP device info */
480	agp_info	agpi;	/* AGP interface info of a device */
481} nv_nth_agp_info;
482
483/* Execute an AGP command */
484typedef struct {
485	uint32		magic;	/* magic number to make sure the caller groks us */
486	bool		agp_bus;/* indicates if we have access to the AGP busmanager */
487	uint32		cmd;	/* actual command to execute */
488} nv_cmd_agp;
489
490/* Read or write a value in ISA I/O space */
491typedef struct {
492	uint32	magic;		/* magic number to make sure the caller groks us */
493	uint16	adress;		/* Offset to read/write */
494	uint8	size;		/* Number of bytes to transfer */
495	uint16	data;		/* The value read or written */
496} nv_in_out_isa;
497
498enum {
499
500	_WAIT_FOR_VBLANK = (1 << 0)
501};
502
503#if defined(__cplusplus)
504}
505#endif
506
507
508#endif
509