intel_extreme.h revision e747cbe1
1/*
2 * Copyright 2006-2014, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 */
8#ifndef INTEL_EXTREME_H
9#define INTEL_EXTREME_H
10
11
12#include "lock.h"
13
14#include <Accelerant.h>
15#include <Drivers.h>
16#include <PCI.h>
17
18#include <edid.h>
19
20
21#define VENDOR_ID_INTEL			0x8086
22
23#define INTEL_TYPE_FAMILY_MASK	0x00f00000
24#define INTEL_TYPE_GROUP_MASK	0x00fffff0
25#define INTEL_TYPE_MODEL_MASK	0x00ffffff
26// families
27#define INTEL_TYPE_7xx			0x00100000	// First Gen
28#define INTEL_TYPE_8xx			0x00200000	// Second Gen
29#define INTEL_TYPE_9xx			0x00400000	// Third Gen +
30// groups
31#define INTEL_TYPE_83x			(INTEL_TYPE_8xx | 0x00010)
32#define INTEL_TYPE_85x			(INTEL_TYPE_8xx | 0x00020)
33#define INTEL_TYPE_91x			(INTEL_TYPE_9xx | 0x00040)
34#define INTEL_TYPE_94x			(INTEL_TYPE_9xx | 0x00080)
35#define INTEL_TYPE_96x			(INTEL_TYPE_9xx | 0x00100)
36#define INTEL_TYPE_Gxx			(INTEL_TYPE_9xx | 0x00200)
37#define INTEL_TYPE_G4x			(INTEL_TYPE_9xx | 0x00400)
38#define INTEL_TYPE_IGD			(INTEL_TYPE_9xx | 0x00800)
39#define INTEL_TYPE_ILK			(INTEL_TYPE_9xx | 0x01000)
40#define INTEL_TYPE_SNB			(INTEL_TYPE_9xx | 0x02000)
41#define INTEL_TYPE_IVB			(INTEL_TYPE_9xx | 0x04000)
42#define INTEL_TYPE_HAS			(INTEL_TYPE_9xx | 0x08000)
43#define INTEL_TYPE_VLV			(INTEL_TYPE_9xx | 0x10000)
44// models
45#define INTEL_TYPE_SERVER		0x0004
46#define INTEL_TYPE_MOBILE		0x0008
47#define INTEL_TYPE_915			(INTEL_TYPE_91x)
48#define INTEL_TYPE_915M			(INTEL_TYPE_91x | INTEL_TYPE_MOBILE)
49#define INTEL_TYPE_945			(INTEL_TYPE_94x)
50#define INTEL_TYPE_945M			(INTEL_TYPE_94x | INTEL_TYPE_MOBILE)
51#define INTEL_TYPE_965			(INTEL_TYPE_96x)
52#define INTEL_TYPE_965M			(INTEL_TYPE_96x | INTEL_TYPE_MOBILE)
53#define INTEL_TYPE_G33			(INTEL_TYPE_Gxx)
54#define INTEL_TYPE_G45			(INTEL_TYPE_G4x)
55#define INTEL_TYPE_GM45			(INTEL_TYPE_G4x | INTEL_TYPE_MOBILE)
56#define INTEL_TYPE_IGDG			(INTEL_TYPE_IGD)
57#define INTEL_TYPE_IGDGM		(INTEL_TYPE_IGD | INTEL_TYPE_MOBILE)
58#define INTEL_TYPE_ILKG			(INTEL_TYPE_ILK)
59#define INTEL_TYPE_ILKGM		(INTEL_TYPE_ILK | INTEL_TYPE_MOBILE)
60#define INTEL_TYPE_SNBG			(INTEL_TYPE_SNB)
61#define INTEL_TYPE_SNBGM		(INTEL_TYPE_SNB | INTEL_TYPE_MOBILE)
62#define INTEL_TYPE_SNBGS		(INTEL_TYPE_SNB | INTEL_TYPE_SERVER)
63#define INTEL_TYPE_IVBG			(INTEL_TYPE_IVB)
64#define INTEL_TYPE_IVBGM		(INTEL_TYPE_IVB | INTEL_TYPE_MOBILE)
65#define INTEL_TYPE_IVBGS		(INTEL_TYPE_IVB | INTEL_TYPE_SERVER)
66#define INTEL_TYPE_VLVG			(INTEL_TYPE_VLV)
67#define INTEL_TYPE_VLVGM		(INTEL_TYPE_VLV | INTEL_TYPE_MOBILE)
68
69// ValleyView MMIO offset
70#define VLV_DISPLAY_BASE		0x180000
71
72#define DEVICE_NAME				"intel_extreme"
73#define INTEL_ACCELERANT_NAME	"intel_extreme.accelerant"
74
75// We encode the register block into the value and extract/translate it when
76// actually accessing.
77#define REGISTER_BLOCK_COUNT				6
78#define REGISTER_BLOCK_SHIFT				24
79#define REGISTER_BLOCK_MASK					0xff000000
80#define REGISTER_REGISTER_MASK				0x00ffffff
81#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
82#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
83
84#define REGS_FLAT							(0 << REGISTER_BLOCK_SHIFT)
85#define REGS_NORTH_SHARED					(1 << REGISTER_BLOCK_SHIFT)
86#define REGS_NORTH_PIPE_AND_PORT			(2 << REGISTER_BLOCK_SHIFT)
87#define REGS_NORTH_PLANE_CONTROL			(3 << REGISTER_BLOCK_SHIFT)
88#define REGS_SOUTH_SHARED					(4 << REGISTER_BLOCK_SHIFT)
89#define REGS_SOUTH_TRANSCODER_PORT			(5 << REGISTER_BLOCK_SHIFT)
90
91// register blocks for (G)MCH/ICH based platforms
92#define MCH_SHARED_REGISTER_BASE						0x00000
93#define MCH_PIPE_AND_PORT_REGISTER_BASE					0x60000
94#define MCH_PLANE_CONTROL_REGISTER_BASE					0x70000
95#define ICH_SHARED_REGISTER_BASE						0x00000
96#define ICH_PORT_REGISTER_BASE							0x60000
97
98// PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based
99// setup to a PCH based one, that means anything that used to communicate via
100// (G)MCH registers needs to use different ones on PCH based platforms
101// (Ironlake, SandyBridge, IvyBridge, Some Haswell).
102#define PCH_NORTH_SHARED_REGISTER_BASE					0x40000
103#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE			0x60000
104#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE			0x70000
105#define PCH_SOUTH_SHARED_REGISTER_BASE					0xc0000
106#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE		0xe0000
107
108
109struct DeviceType {
110	uint32			type;
111
112	DeviceType(int t)
113	{
114		type = t;
115	}
116
117	DeviceType& operator=(int t)
118	{
119		type = t;
120		return *this;
121	}
122
123	bool InFamily(uint32 family) const
124	{
125		return (type & INTEL_TYPE_FAMILY_MASK) == family;
126	}
127
128	bool InGroup(uint32 group) const
129	{
130		return (type & INTEL_TYPE_GROUP_MASK) == group;
131	}
132
133	bool IsModel(uint32 model) const
134	{
135		return (type & INTEL_TYPE_MODEL_MASK) == model;
136	}
137
138	bool IsMobile() const
139	{
140		return (type & INTEL_TYPE_MODEL_MASK) == INTEL_TYPE_MOBILE;
141	}
142
143	bool SupportsHDMI() const
144	{
145		return InGroup(INTEL_TYPE_G4x) || InGroup(INTEL_TYPE_ILK)
146			|| InGroup(INTEL_TYPE_SNB) || InGroup(INTEL_TYPE_IVBG)
147			|| InGroup(INTEL_TYPE_HAS) || InGroup(INTEL_TYPE_VLV);
148	}
149
150	bool HasPlatformControlHub() const
151	{
152		return InGroup(INTEL_TYPE_ILK) || InGroup(INTEL_TYPE_SNB)
153			|| InGroup(INTEL_TYPE_IVB) || InGroup(INTEL_TYPE_HAS);
154	}
155};
156
157// info about PLL on graphics card
158struct pll_info {
159	uint32			reference_frequency;
160	uint32			max_frequency;
161	uint32			min_frequency;
162	uint32			divisor_register;
163};
164
165struct ring_buffer {
166	struct lock		lock;
167	uint32			register_base;
168	uint32			offset;
169	uint32			size;
170	uint32			position;
171	uint32			space_left;
172	uint8*			base;
173};
174
175struct overlay_registers;
176
177struct intel_shared_info {
178	area_id			mode_list_area;		// area containing display mode list
179	uint32			mode_count;
180
181	display_mode	current_mode;
182	uint32			bytes_per_row;
183	uint32			bits_per_pixel;
184	uint32			dpms_mode;
185
186	area_id			registers_area;			// area of memory mapped registers
187	uint32			register_blocks[REGISTER_BLOCK_COUNT];
188
189	uint8*			status_page;
190	phys_addr_t		physical_status_page;
191	uint8*			graphics_memory;
192	phys_addr_t		physical_graphics_memory;
193	uint32			graphics_memory_size;
194
195	addr_t			frame_buffer;
196	uint32			frame_buffer_offset;
197
198	bool			got_vbt;
199	bool			single_head_locked;
200
201	struct lock		accelerant_lock;
202	struct lock		engine_lock;
203
204	ring_buffer		primary_ring_buffer;
205
206	int32			overlay_channel_used;
207	bool			overlay_active;
208	uintptr_t		overlay_token;
209	phys_addr_t		physical_overlay_registers;
210	uint32			overlay_offset;
211
212	bool			hardware_cursor_enabled;
213	sem_id			vblank_sem;
214
215	uint8*			cursor_memory;
216	phys_addr_t		physical_cursor_memory;
217	uint32			cursor_buffer_offset;
218	uint32			cursor_format;
219	bool			cursor_visible;
220	uint16			cursor_hot_x;
221	uint16			cursor_hot_y;
222
223	DeviceType		device_type;
224	char			device_identifier[32];
225	struct pll_info	pll_info;
226
227	edid1_info		vesa_edid_info;
228	bool			has_vesa_edid_info;
229};
230
231//----------------- ioctl() interface ----------------
232
233// magic code for ioctls
234#define INTEL_PRIVATE_DATA_MAGIC		'itic'
235
236// list ioctls
237enum {
238	INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
239
240	INTEL_GET_DEVICE_NAME,
241	INTEL_ALLOCATE_GRAPHICS_MEMORY,
242	INTEL_FREE_GRAPHICS_MEMORY
243};
244
245// retrieve the area_id of the kernel/accelerant shared info
246struct intel_get_private_data {
247	uint32	magic;				// magic number
248	area_id	shared_info_area;
249};
250
251// allocate graphics memory
252struct intel_allocate_graphics_memory {
253	uint32	magic;
254	uint32	size;
255	uint32	alignment;
256	uint32	flags;
257	addr_t	buffer_base;
258};
259
260// free graphics memory
261struct intel_free_graphics_memory {
262	uint32 	magic;
263	addr_t	buffer_base;
264};
265
266//----------------------------------------------------------
267// Register definitions, taken from X driver
268
269// PCI bridge memory management
270#define INTEL_GRAPHICS_MEMORY_CONTROL	0x52
271	// GGC - (G)MCH Graphics Control Register
272#define MEMORY_CONTROL_ENABLED			0x0004
273#define MEMORY_MASK						0x0001
274#define STOLEN_MEMORY_MASK				0x00f0
275#define i965_GTT_MASK					0x000e
276#define G33_GTT_MASK					0x0300
277#define G4X_GTT_MASK					0x0f00	// GGMS (GSM Memory Size) mask
278
279// models i830 and up
280#define i830_LOCAL_MEMORY_ONLY			0x10
281#define i830_STOLEN_512K				0x20
282#define i830_STOLEN_1M					0x30
283#define i830_STOLEN_8M					0x40
284#define i830_FRAME_BUFFER_64M			0x01
285#define i830_FRAME_BUFFER_128M			0x00
286
287// models i855 and up
288#define i855_STOLEN_MEMORY_1M			0x10
289#define i855_STOLEN_MEMORY_4M			0x20
290#define i855_STOLEN_MEMORY_8M			0x30
291#define i855_STOLEN_MEMORY_16M			0x40
292#define i855_STOLEN_MEMORY_32M			0x50
293#define i855_STOLEN_MEMORY_48M			0x60
294#define i855_STOLEN_MEMORY_64M			0x70
295#define i855_STOLEN_MEMORY_128M			0x80
296#define i855_STOLEN_MEMORY_256M			0x90
297
298#define G4X_STOLEN_MEMORY_96MB			0xa0	// GMS - Graphics Mode Select
299#define G4X_STOLEN_MEMORY_160MB			0xb0
300#define G4X_STOLEN_MEMORY_224MB			0xc0
301#define G4X_STOLEN_MEMORY_352MB			0xd0
302
303// SandyBridge (SNB)
304#define SNB_GRAPHICS_MEMORY_CONTROL		0x50
305
306#define SNB_STOLEN_MEMORY_MASK			0xf8
307#define SNB_STOLEN_MEMORY_32MB			(1 << 3)
308#define SNB_STOLEN_MEMORY_64MB			(2 << 3)
309#define SNB_STOLEN_MEMORY_96MB			(3 << 3)
310#define SNB_STOLEN_MEMORY_128MB			(4 << 3)
311#define SNB_STOLEN_MEMORY_160MB			(5 << 3)
312#define SNB_STOLEN_MEMORY_192MB			(6 << 3)
313#define SNB_STOLEN_MEMORY_224MB			(7 << 3)
314#define SNB_STOLEN_MEMORY_256MB			(8 << 3)
315#define SNB_STOLEN_MEMORY_288MB			(9 << 3)
316#define SNB_STOLEN_MEMORY_320MB			(10 << 3)
317#define SNB_STOLEN_MEMORY_352MB			(11 << 3)
318#define SNB_STOLEN_MEMORY_384MB			(12 << 3)
319#define SNB_STOLEN_MEMORY_416MB			(13 << 3)
320#define SNB_STOLEN_MEMORY_448MB			(14 << 3)
321#define SNB_STOLEN_MEMORY_480MB			(15 << 3)
322#define SNB_STOLEN_MEMORY_512MB			(16 << 3)
323
324#define SNB_GTT_SIZE_MASK				(3 << 8)
325#define SNB_GTT_SIZE_NONE				(0 << 8)
326#define SNB_GTT_SIZE_1MB				(1 << 8)
327#define SNB_GTT_SIZE_2MB				(2 << 8)
328
329// graphics page translation table
330#define INTEL_PAGE_TABLE_CONTROL		0x02020
331#define PAGE_TABLE_ENABLED				0x00000001
332#define INTEL_PAGE_TABLE_ERROR			0x02024
333#define INTEL_HARDWARE_STATUS_PAGE		0x02080
334#define i915_GTT_BASE					0x1c
335#define i830_GTT_BASE					0x10000	// (- 0x2ffff)
336#define i830_GTT_SIZE					0x20000
337#define i965_GTT_BASE					0x80000	// (- 0xfffff)
338#define i965_GTT_SIZE					0x80000
339#define i965_GTT_128K					(2 << 1)
340#define i965_GTT_256K					(1 << 1)
341#define i965_GTT_512K					(0 << 1)
342#define G33_GTT_1M						(1 << 8)
343#define G33_GTT_2M						(2 << 8)
344#define G4X_GTT_NONE					0x000	// GGMS - GSM Memory Size
345#define G4X_GTT_1M_NO_IVT				0x100	// no Intel Virtualization Tech.
346#define G4X_GTT_2M_NO_IVT				0x300
347#define G4X_GTT_2M_IVT					0x900	// with Intel Virt. Tech.
348#define G4X_GTT_3M_IVT					0xa00
349#define G4X_GTT_4M_IVT					0xb00
350
351
352#define GTT_ENTRY_VALID					0x01
353#define GTT_ENTRY_LOCAL_MEMORY			0x02
354#define GTT_PAGE_SHIFT					12
355
356
357// ring buffer
358#define INTEL_PRIMARY_RING_BUFFER		0x02030
359#define INTEL_SECONDARY_RING_BUFFER_0	0x02100
360#define INTEL_SECONDARY_RING_BUFFER_1	0x02110
361// offsets for the ring buffer base registers above
362#define RING_BUFFER_TAIL				0x0
363#define RING_BUFFER_HEAD				0x4
364#define RING_BUFFER_START				0x8
365#define RING_BUFFER_CONTROL				0xc
366#define INTEL_RING_BUFFER_SIZE_MASK		0x001ff000
367#define INTEL_RING_BUFFER_HEAD_MASK		0x001ffffc
368#define INTEL_RING_BUFFER_ENABLED		1
369
370// interrupts
371#define INTEL_INTERRUPT_ENABLED			0x020a0
372#define INTEL_INTERRUPT_IDENTITY		0x020a4
373#define INTEL_INTERRUPT_MASK			0x020a8
374#define INTEL_INTERRUPT_STATUS			0x020ac
375#define INTERRUPT_VBLANK_PIPEA			(1 << 7)
376#define INTERRUPT_VBLANK_PIPEB			(1 << 5)
377
378// PCH interrupts
379#define PCH_INTERRUPT_STATUS			0x44000
380#define PCH_INTERRUPT_MASK				0x44004
381#define PCH_INTERRUPT_IDENTITY			0x44008
382#define PCH_INTERRUPT_ENABLED			0x4400c
383#define PCH_INTERRUPT_VBLANK_PIPEA		(1 << 0)
384#define PCH_INTERRUPT_VBLANK_PIPEB		(1 << 5)
385#define PCH_INTERRUPT_VBLANK_PIPEC		(1 << 10)
386
387#define PCH_INTERRUPT_VBLANK_PIPEA_SNB		(1 << 7)
388#define PCH_INTERRUPT_VBLANK_PIPEB_SNB		(1 << 15)
389
390// display ports
391#define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
392#define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
393#define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
394#define DISPLAY_MONITOR_MODE_MASK		(3UL << 10)
395#define DISPLAY_MONITOR_ON				0
396#define DISPLAY_MONITOR_SUSPEND			(1UL << 10)
397#define DISPLAY_MONITOR_STAND_BY		(2UL << 10)
398#define DISPLAY_MONITOR_OFF				(3UL << 10)
399#define DISPLAY_MONITOR_POLARITY_MASK	(3UL << 3)
400#define DISPLAY_MONITOR_POSITIVE_HSYNC	(1UL << 3)
401#define DISPLAY_MONITOR_POSITIVE_VSYNC	(2UL << 3)
402#define LVDS_POST2_RATE_SLOW			14 // PLL Divisors
403#define LVDS_POST2_RATE_FAST			7
404#define LVDS_CLKB_POWER_MASK			(3 << 4)
405#define LVDS_CLKB_POWER_UP				(3 << 4)
406#define LVDS_PORT_EN					(1 << 31)
407#define LVDS_A0A2_CLKA_POWER_UP			(3 << 8)
408#define LVDS_PIPEB_SELECT				(1 << 30)
409#define LVDS_B0B3PAIRS_POWER_UP			(3 << 2)
410#define LVDS_PLL_MODE_LVDS				(2 << 26)
411#define LVDS_18BIT_DITHER				(1 << 25)
412
413// PLL flags
414#define DISPLAY_PLL_ENABLED				(1UL << 31)
415#define DISPLAY_PLL_2X_CLOCK			(1UL << 30)
416#define DISPLAY_PLL_SYNC_LOCK_ENABLED	(1UL << 29)
417#define DISPLAY_PLL_NO_VGA_CONTROL		(1UL << 28)
418#define DISPLAY_PLL_MODE_ANALOG			(1UL << 26)
419#define DISPLAY_PLL_DIVIDE_HIGH			(1UL << 24)
420#define DISPLAY_PLL_DIVIDE_4X			(1UL << 23)
421#define DISPLAY_PLL_POST1_DIVIDE_2		(1UL << 21)
422#define DISPLAY_PLL_POST1_DIVISOR_MASK	0x001f0000
423#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK	0x00ff0000
424#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK  0x00ff8000
425#define DISPLAY_PLL_POST1_DIVISOR_SHIFT	16
426#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT	15
427#define DISPLAY_PLL_DIVISOR_1			(1UL << 8)
428#define DISPLAY_PLL_N_DIVISOR_MASK		0x001f0000
429#define DISPLAY_PLL_IGD_N_DIVISOR_MASK	0x00ff0000
430#define DISPLAY_PLL_M1_DIVISOR_MASK		0x00001f00
431#define DISPLAY_PLL_M2_DIVISOR_MASK		0x0000001f
432#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK	0x000000ff
433#define DISPLAY_PLL_N_DIVISOR_SHIFT		16
434#define DISPLAY_PLL_M1_DIVISOR_SHIFT	8
435#define DISPLAY_PLL_M2_DIVISOR_SHIFT	0
436#define DISPLAY_PLL_PULSE_PHASE_SHIFT	9
437
438// display
439#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_SOUTH_TRANSCODER_PORT)
440#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_SOUTH_TRANSCODER_PORT)
441#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_SOUTH_TRANSCODER_PORT)
442#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_SOUTH_TRANSCODER_PORT)
443#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_SOUTH_TRANSCODER_PORT)
444#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_SOUTH_TRANSCODER_PORT)
445#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_SOUTH_TRANSCODER_PORT)
446#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_SOUTH_TRANSCODER_PORT)
447#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_SOUTH_TRANSCODER_PORT)
448#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_SOUTH_TRANSCODER_PORT)
449#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_SOUTH_TRANSCODER_PORT)
450#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_SOUTH_TRANSCODER_PORT)
451
452#define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
453#define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)
454
455#define INTEL_ANALOG_PORT				(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
456#define INTEL_DIGITAL_PORT_A			(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
457#define INTEL_DIGITAL_PORT_B			(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
458#define INTEL_DIGITAL_PORT_C			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
459#define INTEL_DIGITAL_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
460
461#define INTEL_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
462#define INTEL_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
463
464#define PCH_HDMI_PORT_B					(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
465#define PCH_HDMI_PORT_C					(0x1150 | REGS_SOUTH_TRANSCODER_PORT)
466#define PCH_HDMI_PORT_D					(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
467
468#define GEN4_HDMI_PORT_B				(0x1140 | REGS_NORTH_PIPE_AND_PORT)
469#define GEN4_HDMI_PORT_C				(0x1160 | REGS_NORTH_PIPE_AND_PORT)
470#define GEN4_HDMI_PORT_D				(0x116C | REGS_NORTH_PIPE_AND_PORT)
471
472#define INTEL_DISPLAY_PORT_A			(0x4000 | REGS_NORTH_PIPE_AND_PORT)
473#define INTEL_DISPLAY_PORT_B			(0x4100 | REGS_NORTH_PIPE_AND_PORT)
474#define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_NORTH_PIPE_AND_PORT)
475#define INTEL_DISPLAY_PORT_D			(0x4300 | REGS_NORTH_PIPE_AND_PORT)
476
477// valid for both DVI/HDMI and DisplayPort
478#define PORT_DETECTED					(1 << 2)
479
480// planes
481#define INTEL_PIPE_ENABLED				(1UL << 31)
482#define INTEL_PIPE_CONTROL				0x08
483#define INTEL_PIPE_STATUS				0x24
484#define INTEL_PIPE_OFFSET				0x1000
485#define INTEL_DISPLAY_A_PIPE_CONTROL	(0x0008	| REGS_NORTH_PLANE_CONTROL)
486#define INTEL_DISPLAY_B_PIPE_CONTROL	(0x1008 | REGS_NORTH_PLANE_CONTROL)
487#define INTEL_DISPLAY_A_PIPE_STATUS		(0x0024 | REGS_NORTH_PLANE_CONTROL)
488#define INTEL_DISPLAY_B_PIPE_STATUS		(0x1024 | REGS_NORTH_PLANE_CONTROL)
489
490#define DISPLAY_PIPE_VBLANK_ENABLED		(1UL << 17)
491#define DISPLAY_PIPE_VBLANK_STATUS		(1UL << 1)
492
493#define INTEL_DISPLAY_A_CONTROL			(0x0180 | REGS_NORTH_PLANE_CONTROL)
494#define INTEL_DISPLAY_A_BASE			(0x0184 | REGS_NORTH_PLANE_CONTROL)
495#define INTEL_DISPLAY_A_BYTES_PER_ROW	(0x0188 | REGS_NORTH_PLANE_CONTROL)
496#define INTEL_DISPLAY_A_POS				(0x018c | REGS_NORTH_PLANE_CONTROL)
497	// reserved on A
498#define INTEL_DISPLAY_A_PIPE_SIZE		(0x0190 | REGS_NORTH_PLANE_CONTROL)
499#define INTEL_DISPLAY_A_SURFACE			(0x019c | REGS_NORTH_PLANE_CONTROL)
500	// i965 and up only
501
502#define INTEL_DISPLAY_B_CONTROL			(0x1180 | REGS_NORTH_PLANE_CONTROL)
503#define INTEL_DISPLAY_B_BASE			(0x1184 | REGS_NORTH_PLANE_CONTROL)
504#define INTEL_DISPLAY_B_BYTES_PER_ROW	(0x1188 | REGS_NORTH_PLANE_CONTROL)
505#define INTEL_DISPLAY_B_POS				(0x118c | REGS_NORTH_PLANE_CONTROL)
506#define INTEL_DISPLAY_B_PIPE_SIZE		(0x1190 | REGS_NORTH_PLANE_CONTROL)
507#define INTEL_DISPLAY_B_SURFACE			(0x119c | REGS_NORTH_PLANE_CONTROL)
508	// i965 and up only
509
510#define DISPLAY_CONTROL_ENABLED			(1UL << 31)
511#define DISPLAY_CONTROL_GAMMA			(1UL << 30)
512#define DISPLAY_CONTROL_COLOR_MASK		(0x0fUL << 26)
513#define DISPLAY_CONTROL_CMAP8			(2UL << 26)
514#define DISPLAY_CONTROL_RGB15			(4UL << 26)
515#define DISPLAY_CONTROL_RGB16			(5UL << 26)
516#define DISPLAY_CONTROL_RGB32			(6UL << 26)
517
518// cursors
519#define INTEL_CURSOR_CONTROL			(0x0080 | REGS_NORTH_PLANE_CONTROL)
520#define INTEL_CURSOR_BASE				(0x0084 | REGS_NORTH_PLANE_CONTROL)
521#define INTEL_CURSOR_POSITION			(0x0088 | REGS_NORTH_PLANE_CONTROL)
522#define INTEL_CURSOR_PALETTE			(0x0090 | REGS_NORTH_PLANE_CONTROL)
523	// (- 0x009f)
524#define INTEL_CURSOR_SIZE				(0x00a0 | REGS_NORTH_PLANE_CONTROL)
525#define CURSOR_ENABLED					(1UL << 31)
526#define CURSOR_FORMAT_2_COLORS			(0UL << 24)
527#define CURSOR_FORMAT_3_COLORS			(1UL << 24)
528#define CURSOR_FORMAT_4_COLORS			(2UL << 24)
529#define CURSOR_FORMAT_ARGB				(4UL << 24)
530#define CURSOR_FORMAT_XRGB				(5UL << 24)
531#define CURSOR_POSITION_NEGATIVE		0x8000
532#define CURSOR_POSITION_MASK			0x3fff
533
534// palette registers
535#define INTEL_DISPLAY_A_PALETTE			(0xa000 | REGS_NORTH_SHARED)
536#define INTEL_DISPLAY_B_PALETTE			(0xa800 | REGS_NORTH_SHARED)
537
538// PLL registers
539#define INTEL_DISPLAY_A_PLL				(0x6014 | REGS_SOUTH_SHARED)
540#define INTEL_DISPLAY_B_PLL				(0x6018 | REGS_SOUTH_SHARED)
541#define INTEL_DISPLAY_A_PLL_MULTIPLIER_DIVISOR \
542										(0x601c | REGS_SOUTH_SHARED)
543#define INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR \
544										(0x6020 | REGS_SOUTH_SHARED)
545#define INTEL_DISPLAY_A_PLL_DIVISOR_0	(0x6040 | REGS_SOUTH_SHARED)
546#define INTEL_DISPLAY_A_PLL_DIVISOR_1	(0x6044 | REGS_SOUTH_SHARED)
547#define INTEL_DISPLAY_B_PLL_DIVISOR_0	(0x6048 | REGS_SOUTH_SHARED)
548#define INTEL_DISPLAY_B_PLL_DIVISOR_1	(0x604c | REGS_SOUTH_SHARED)
549
550// i2c
551#define INTEL_I2C_IO_A					(0x5010 | REGS_SOUTH_SHARED)
552#define INTEL_I2C_IO_B					(0x5014 | REGS_SOUTH_SHARED)
553#define INTEL_I2C_IO_C					(0x5018 | REGS_SOUTH_SHARED)
554#define INTEL_I2C_IO_D					(0x501c | REGS_SOUTH_SHARED)
555#define INTEL_I2C_IO_E					(0x5020 | REGS_SOUTH_SHARED)
556#define INTEL_I2C_IO_F					(0x5024 | REGS_SOUTH_SHARED)
557#define INTEL_I2C_IO_G					(0x5028 | REGS_SOUTH_SHARED)
558#define INTEL_I2C_IO_H					(0x502c | REGS_SOUTH_SHARED)
559
560#define I2C_CLOCK_DIRECTION_MASK		(1 << 0)
561#define I2C_CLOCK_DIRECTION_OUT			(1 << 1)
562#define I2C_CLOCK_VALUE_MASK			(1 << 2)
563#define I2C_CLOCK_VALUE_OUT				(1 << 3)
564#define I2C_CLOCK_VALUE_IN				(1 << 4)
565#define I2C_DATA_DIRECTION_MASK			(1 << 8)
566#define I2C_DATA_DIRECTION_OUT			(1 << 9)
567#define I2C_DATA_VALUE_MASK				(1 << 10)
568#define I2C_DATA_VALUE_OUT				(1 << 11)
569#define I2C_DATA_VALUE_IN				(1 << 12)
570#define I2C_RESERVED					((1 << 13) | (1 << 5))
571
572// TODO: on IronLake this is in the north shared block at 0x41000
573#define INTEL_VGA_DISPLAY_CONTROL		0x71400
574#define VGA_DISPLAY_DISABLED			(1UL << 31)
575
576// LVDS panel
577#define INTEL_PANEL_STATUS				0x61200
578#define PANEL_STATUS_POWER_ON			(1UL << 31)
579#define INTEL_PANEL_CONTROL				0x61204
580#define PANEL_CONTROL_POWER_TARGET_ON	(1UL << 0)
581#define INTEL_PANEL_FIT_CONTROL			0x61230
582#define INTEL_PANEL_FIT_RATIOS			0x61234
583
584// LVDS on IronLake and up
585#define PCH_PANEL_CONTROL				0xc7200
586#define PCH_PANEL_STATUS				0xc7204
587#define PANEL_REGISTER_UNLOCK			(0xabcd << 16)
588#define PCH_LVDS_DETECTED				(1 << 1)
589
590
591// ring buffer commands
592
593#define COMMAND_NOOP					0x00
594#define COMMAND_WAIT_FOR_EVENT			(0x03 << 23)
595#define COMMAND_WAIT_FOR_OVERLAY_FLIP	(1 << 16)
596
597#define COMMAND_FLUSH					(0x04 << 23)
598
599// overlay flip
600#define COMMAND_OVERLAY_FLIP			(0x11 << 23)
601#define COMMAND_OVERLAY_CONTINUE		(0 << 21)
602#define COMMAND_OVERLAY_ON				(1 << 21)
603#define COMMAND_OVERLAY_OFF				(2 << 21)
604#define OVERLAY_UPDATE_COEFFICIENTS		0x1
605
606// 2D acceleration
607#define XY_COMMAND_SOURCE_BLIT			0x54c00006
608#define XY_COMMAND_COLOR_BLIT			0x54000004
609#define XY_COMMAND_SETUP_MONO_PATTERN	0x44400007
610#define XY_COMMAND_SCANLINE_BLIT		0x49400001
611#define COMMAND_COLOR_BLIT				0x50000003
612#define COMMAND_BLIT_RGBA				0x00300000
613
614#define COMMAND_MODE_SOLID_PATTERN		0x80
615#define COMMAND_MODE_CMAP8				0x00
616#define COMMAND_MODE_RGB15				0x02
617#define COMMAND_MODE_RGB16				0x01
618#define COMMAND_MODE_RGB32				0x03
619
620// overlay
621#define INTEL_OVERLAY_UPDATE			0x30000
622#define INTEL_OVERLAY_TEST				0x30004
623#define INTEL_OVERLAY_STATUS			0x30008
624#define INTEL_OVERLAY_EXTENDED_STATUS	0x3000c
625#define INTEL_OVERLAY_GAMMA_5			0x30010
626#define INTEL_OVERLAY_GAMMA_4			0x30014
627#define INTEL_OVERLAY_GAMMA_3			0x30018
628#define INTEL_OVERLAY_GAMMA_2			0x3001c
629#define INTEL_OVERLAY_GAMMA_1			0x30020
630#define INTEL_OVERLAY_GAMMA_0			0x30024
631
632// FDI - Flexible Display Interface, the interface between the (CPU-internal)
633// GPU and the PCH display outputs. Proprietary interface, based on DisplayPort
634// though, so similar link training and all...
635// There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the
636// PCH for each display pipe.
637// FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to
638// transcoder B, so we have the same mapping as with the display pipes.
639#define PCH_FDI_RX_BASE_REGISTER		0xf0000
640#define PCH_FDI_RX_PIPE_OFFSET			0x01000
641
642#define PCH_FDI_RX_CONTROL				0x0c
643#define FDI_RX_CLOCK_MASK				(1 << 4)
644#define FDI_RX_CLOCK_RAW				(0 << 4)
645#define FDI_RX_CLOCK_PCD				(1 << 4)
646
647#define PCH_FDI_RX_TRANS_UNIT_SIZE_1	0x30
648#define PCH_FDI_RX_TRANS_UNIT_SIZE_2	0x38
649#define FDI_RX_TRANS_UNIT_SIZE(x)		((x - 1) << 25)
650#define FDI_RX_TRANS_UNIT_MASK			0x7e000000
651	// Transfer unit size 1 is the primary and fixed transfer unit size,
652	// TU size 2 is the lower power state transfer unit size when using dynamic
653	// refresh rates (we don't do that though).
654
655// CPU Panel Fitters - These are for IronLake and up and are the CPU internal
656// panel fitters.
657#define PCH_PANEL_FITTER_BASE_REGISTER	0x68000
658#define PCH_PANEL_FITTER_PIPE_OFFSET	0x00800
659
660#define PCH_PANEL_FITTER_WINDOW_POS		0x70
661#define PCH_PANEL_FITTER_WINDOW_SIZE	0x74
662#define PCH_PANEL_FITTER_CONTROL		0x80
663#define PCH_PANEL_FITTER_V_SCALE		0x84
664#define PCH_PANEL_FITTER_H_SCALE		0x90
665
666#define PANEL_FITTER_ENABLED			(1 << 31)
667#define PANEL_FITTER_FILTER_MASK		(3 << 23)
668
669struct overlay_scale {
670	uint32 _reserved0 : 3;
671	uint32 horizontal_scale_fraction : 12;
672	uint32 _reserved1 : 1;
673	uint32 horizontal_downscale_factor : 3;
674	uint32 _reserved2 : 1;
675	uint32 vertical_scale_fraction : 12;
676};
677
678#define OVERLAY_FORMAT_RGB15			0x2
679#define OVERLAY_FORMAT_RGB16			0x3
680#define OVERLAY_FORMAT_RGB32			0x1
681#define OVERLAY_FORMAT_YCbCr422			0x8
682#define OVERLAY_FORMAT_YCbCr411			0x9
683#define OVERLAY_FORMAT_YCbCr420			0xc
684
685#define OVERLAY_MIRROR_NORMAL			0x0
686#define OVERLAY_MIRROR_HORIZONTAL		0x1
687#define OVERLAY_MIRROR_VERTICAL			0x2
688
689// The real overlay registers are written to using an update buffer
690
691struct overlay_registers {
692	uint32 buffer_rgb0;
693	uint32 buffer_rgb1;
694	uint32 buffer_u0;
695	uint32 buffer_v0;
696	uint32 buffer_u1;
697	uint32 buffer_v1;
698	// (0x18) OSTRIDE - overlay stride
699	uint16 stride_rgb;
700	uint16 stride_uv;
701	// (0x1c) YRGB_VPH - Y/RGB vertical phase
702	uint16 vertical_phase0_rgb;
703	uint16 vertical_phase1_rgb;
704	// (0x20) UV_VPH - UV vertical phase
705	uint16 vertical_phase0_uv;
706	uint16 vertical_phase1_uv;
707	// (0x24) HORZ_PH - horizontal phase
708	uint16 horizontal_phase_rgb;
709	uint16 horizontal_phase_uv;
710	// (0x28) INIT_PHS - initial phase shift
711	uint32 initial_vertical_phase0_shift_rgb0 : 4;
712	uint32 initial_vertical_phase1_shift_rgb0 : 4;
713	uint32 initial_horizontal_phase_shift_rgb0 : 4;
714	uint32 initial_vertical_phase0_shift_uv : 4;
715	uint32 initial_vertical_phase1_shift_uv : 4;
716	uint32 initial_horizontal_phase_shift_uv : 4;
717	uint32 _reserved0 : 8;
718	// (0x2c) DWINPOS - destination window position
719	uint16 window_left;
720	uint16 window_top;
721	// (0x30) DWINSZ - destination window size
722	uint16 window_width;
723	uint16 window_height;
724	// (0x34) SWIDTH - source width
725	uint16 source_width_rgb;
726	uint16 source_width_uv;
727	// (0x38) SWITDHSW - source width in 8 byte steps
728	uint16 source_bytes_per_row_rgb;
729	uint16 source_bytes_per_row_uv;
730	uint16 source_height_rgb;
731	uint16 source_height_uv;
732	overlay_scale scale_rgb;
733	overlay_scale scale_uv;
734	// (0x48) OCLRC0 - overlay color correction 0
735	uint32 brightness_correction : 8;		// signed, -128 to 127
736	uint32 _reserved1 : 10;
737	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
738	uint32 _reserved2 : 5;
739	// (0x4c) OCLRC1 - overlay color correction 1
740	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
741	uint32 _reserved3 : 6;
742	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
743	uint32 _reserved4 : 5;
744	// (0x50) DCLRKV - destination color key value
745	uint32 color_key_blue : 8;
746	uint32 color_key_green : 8;
747	uint32 color_key_red : 8;
748	uint32 _reserved5 : 8;
749	// (0x54) DCLRKM - destination color key mask
750	uint32 color_key_mask_blue : 8;
751	uint32 color_key_mask_green : 8;
752	uint32 color_key_mask_red : 8;
753	uint32 _reserved6 : 7;
754	uint32 color_key_enabled : 1;
755	// (0x58) SCHRKVH - source chroma key high value
756	uint32 source_chroma_key_high_red : 8;
757	uint32 source_chroma_key_high_blue : 8;
758	uint32 source_chroma_key_high_green : 8;
759	uint32 _reserved7 : 8;
760	// (0x5c) SCHRKVL - source chroma key low value
761	uint32 source_chroma_key_low_red : 8;
762	uint32 source_chroma_key_low_blue : 8;
763	uint32 source_chroma_key_low_green : 8;
764	uint32 _reserved8 : 8;
765	// (0x60) SCHRKEN - source chroma key enable
766	uint32 _reserved9 : 24;
767	uint32 source_chroma_key_red_enabled : 1;
768	uint32 source_chroma_key_blue_enabled : 1;
769	uint32 source_chroma_key_green_enabled : 1;
770	uint32 _reserved10 : 5;
771	// (0x64) OCONFIG - overlay configuration
772	uint32 _reserved11 : 3;
773	uint32 color_control_output_mode : 1;
774	uint32 yuv_to_rgb_bypass : 1;
775	uint32 _reserved12 : 11;
776	uint32 gamma2_enabled : 1;
777	uint32 _reserved13 : 1;
778	uint32 select_pipe : 1;
779	uint32 slot_time : 8;
780	uint32 _reserved14 : 5;
781	// (0x68) OCOMD - overlay command
782	uint32 overlay_enabled : 1;
783	uint32 active_field : 1;
784	uint32 active_buffer : 2;
785	uint32 test_mode : 1;
786	uint32 buffer_field_mode : 1;
787	uint32 _reserved15 : 1;
788	uint32 tv_flip_field_enabled : 1;
789	uint32 _reserved16 : 1;
790	uint32 tv_flip_field_parity : 1;
791	uint32 source_format : 4;
792	uint32 ycbcr422_order : 2;
793	uint32 _reserved18 : 1;
794	uint32 mirroring_mode : 2;
795	uint32 _reserved19 : 13;
796
797	uint32 _reserved20;
798
799	uint32 start_0y;
800	uint32 start_1y;
801	uint32 start_0u;
802	uint32 start_0v;
803	uint32 start_1u;
804	uint32 start_1v;
805	uint32 _reserved21[6];
806#if 0
807	// (0x70) AWINPOS - alpha blend window position
808	uint32 awinpos;
809	// (0x74) AWINSZ - alpha blend window size
810	uint32 awinsz;
811
812	uint32 _reserved21[10];
813#endif
814
815	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
816	// the next two registers switch the usual Y/RGB vs. UV order)
817	uint16 horizontal_scale_uv;
818	uint16 horizontal_scale_rgb;
819	// (0xa4) UVSCALEV - vertical downscale
820	uint16 vertical_scale_uv;
821	uint16 vertical_scale_rgb;
822
823	uint32 _reserved22[86];
824
825	// (0x200) polyphase filter coefficients
826	uint16 vertical_coefficients_rgb[128];
827	uint16 horizontal_coefficients_rgb[128];
828
829	uint32	_reserved23[64];
830
831	// (0x500)
832	uint16 vertical_coefficients_uv[128];
833	uint16 horizontal_coefficients_uv[128];
834};
835
836// i965 overlay support is currently realized using its 3D hardware
837#define INTEL_i965_OVERLAY_STATE_SIZE	36864
838#define INTEL_i965_3D_CONTEXT_SIZE		32768
839
840inline bool
841intel_uses_physical_overlay(intel_shared_info &info)
842{
843	return !info.device_type.InGroup(INTEL_TYPE_Gxx);
844}
845
846
847struct hardware_status {
848	uint32	interrupt_status_register;
849	uint32	_reserved0[3];
850	void*	primary_ring_head_storage;
851	uint32	_reserved1[3];
852	void*	secondary_ring_0_head_storage;
853	void*	secondary_ring_1_head_storage;
854	uint32	_reserved2[2];
855	void*	binning_head_storage;
856	uint32	_reserved3[3];
857	uint32	store[1008];
858};
859
860#endif	/* INTEL_EXTREME_H */
861