intel_extreme.h revision c9c61669
1/*
2 * Copyright 2006-2015, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 *		Alexander von Gluck, kallisti5@unixzen.com
8 */
9#ifndef INTEL_EXTREME_H
10#define INTEL_EXTREME_H
11
12
13#include "lock.h"
14
15#include <Accelerant.h>
16#include <Drivers.h>
17#include <PCI.h>
18
19#include <edid.h>
20
21
22#define VENDOR_ID_INTEL			0x8086
23
24#define INTEL_FAMILY_MASK	0x00ff0000
25#define INTEL_GROUP_MASK	0x00fffff0
26#define INTEL_MODEL_MASK	0x00ffffff
27#define INTEL_TYPE_MASK		0x0000000f
28// families
29#define INTEL_FAMILY_7xx	0x00010000	// First Gen
30#define INTEL_FAMILY_8xx	0x00020000	// Second Gen
31#define INTEL_FAMILY_9xx	0x00040000	// Third Gen +
32#define INTEL_FAMILY_SER5	0x00080000	// Intel5 Series
33#define INTEL_FAMILY_POVR	0x00100000	// PowerVR (uugh)
34#define INTEL_FAMILY_SOC0	0x00200000  // Atom SOC
35// groups
36#define INTEL_GROUP_83x		(INTEL_FAMILY_8xx  | 0x0010)
37#define INTEL_GROUP_85x		(INTEL_FAMILY_8xx  | 0x0020)
38#define INTEL_GROUP_91x		(INTEL_FAMILY_9xx  | 0x0010)
39#define INTEL_GROUP_94x		(INTEL_FAMILY_9xx  | 0x0020)
40#define INTEL_GROUP_96x		(INTEL_FAMILY_9xx  | 0x0040)
41#define INTEL_GROUP_Gxx		(INTEL_FAMILY_9xx  | 0x0080)
42#define INTEL_GROUP_G4x		(INTEL_FAMILY_9xx  | 0x0100)
43#define INTEL_GROUP_PIN		(INTEL_FAMILY_9xx  | 0x0200)  // PineView
44#define INTEL_GROUP_ILK		(INTEL_FAMILY_SER5 | 0x0010)  // IronLake
45#define INTEL_GROUP_SNB		(INTEL_FAMILY_SER5 | 0x0020)  // SandyBridge
46#define INTEL_GROUP_IVB		(INTEL_FAMILY_SER5 | 0x0040)  // IvyBridge
47#define INTEL_GROUP_HAS		(INTEL_FAMILY_SER5 | 0x0080)  // Haswell
48#define INTEL_GROUP_SLT		(INTEL_FAMILY_POVR | 0x0010)  // Saltwell
49#define INTEL_GROUP_FSM		(INTEL_FAMILY_POVR | 0x0020)  // Fu.Silvermont
50#define INTEL_GROUP_VLV		(INTEL_FAMILY_SOC0 | 0x0010)  // ValleyView
51#define INTEL_GROUP_CHV		(INTEL_FAMILY_SOC0 | 0x0020)  // CherryView
52#define INTEL_GROUP_BXT		(INTEL_FAMILY_SOC0 | 0x0040)  // Broxton
53// models
54#define INTEL_TYPE_SERVER	0x0004
55#define INTEL_TYPE_MOBILE	0x0008
56#define INTEL_MODEL_915		(INTEL_GROUP_91x)
57#define INTEL_MODEL_915M	(INTEL_GROUP_91x | INTEL_TYPE_MOBILE)
58#define INTEL_MODEL_945		(INTEL_GROUP_94x)
59#define INTEL_MODEL_945M	(INTEL_GROUP_94x | INTEL_TYPE_MOBILE)
60#define INTEL_MODEL_965		(INTEL_GROUP_96x)
61#define INTEL_MODEL_965M	(INTEL_GROUP_96x | INTEL_TYPE_MOBILE)
62#define INTEL_MODEL_G33		(INTEL_GROUP_Gxx)
63#define INTEL_MODEL_G45		(INTEL_GROUP_G4x)
64#define INTEL_MODEL_GM45	(INTEL_GROUP_G4x | INTEL_TYPE_MOBILE)
65#define INTEL_MODEL_PINE	(INTEL_GROUP_PIN)
66#define INTEL_MODEL_PINEM	(INTEL_GROUP_PIN | INTEL_TYPE_MOBILE)
67#define INTEL_MODEL_ILKG	(INTEL_GROUP_ILK)
68#define INTEL_MODEL_ILKGM	(INTEL_GROUP_ILK | INTEL_TYPE_MOBILE)
69#define INTEL_MODEL_SNBG	(INTEL_GROUP_SNB)
70#define INTEL_MODEL_SNBGM	(INTEL_GROUP_SNB | INTEL_TYPE_MOBILE)
71#define INTEL_MODEL_SNBGS	(INTEL_GROUP_SNB | INTEL_TYPE_SERVER)
72#define INTEL_MODEL_IVBG	(INTEL_GROUP_IVB)
73#define INTEL_MODEL_IVBGM	(INTEL_GROUP_IVB | INTEL_TYPE_MOBILE)
74#define INTEL_MODEL_IVBGS	(INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
75#define INTEL_MODEL_HAS		(INTEL_GROUP_HAS)
76#define INTEL_MODEL_HASM	(INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
77#define INTEL_MODEL_VLV		(INTEL_GROUP_VLV)
78#define INTEL_MODEL_VLVM	(INTEL_GROUP_VLV | INTEL_TYPE_MOBILE)
79
80// ValleyView MMIO offset
81#define VLV_DISPLAY_BASE		0x180000
82
83#define DEVICE_NAME				"intel_extreme"
84#define INTEL_ACCELERANT_NAME	"intel_extreme.accelerant"
85
86// We encode the register block into the value and extract/translate it when
87// actually accessing.
88#define REGISTER_BLOCK_COUNT				6
89#define REGISTER_BLOCK_SHIFT				24
90#define REGISTER_BLOCK_MASK					0xff000000
91#define REGISTER_REGISTER_MASK				0x00ffffff
92#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
93#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
94
95#define REGS_FLAT							(0 << REGISTER_BLOCK_SHIFT)
96#define REGS_NORTH_SHARED					(1 << REGISTER_BLOCK_SHIFT)
97#define REGS_NORTH_PIPE_AND_PORT			(2 << REGISTER_BLOCK_SHIFT)
98#define REGS_NORTH_PLANE_CONTROL			(3 << REGISTER_BLOCK_SHIFT)
99#define REGS_SOUTH_SHARED					(4 << REGISTER_BLOCK_SHIFT)
100#define REGS_SOUTH_TRANSCODER_PORT			(5 << REGISTER_BLOCK_SHIFT)
101
102// register blocks for (G)MCH/ICH based platforms
103#define MCH_SHARED_REGISTER_BASE						0x00000
104#define MCH_PIPE_AND_PORT_REGISTER_BASE					0x60000
105#define MCH_PLANE_CONTROL_REGISTER_BASE					0x70000
106#define ICH_SHARED_REGISTER_BASE						0x00000
107#define ICH_PORT_REGISTER_BASE							0x60000
108
109// PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based
110// setup to a PCH based one, that means anything that used to communicate via
111// (G)MCH registers needs to use different ones on PCH based platforms
112// (Ironlake, SandyBridge, IvyBridge, Some Haswell).
113#define PCH_NORTH_SHARED_REGISTER_BASE					0x40000
114#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE			0x60000
115#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE			0x70000
116#define PCH_SOUTH_SHARED_REGISTER_BASE					0xc0000
117#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE		0xe0000
118
119
120struct DeviceType {
121	uint32			type;
122
123	DeviceType(int t)
124	{
125		type = t;
126	}
127
128	DeviceType& operator=(int t)
129	{
130		type = t;
131		return *this;
132	}
133
134	bool InFamily(uint32 family) const
135	{
136		return (type & INTEL_FAMILY_MASK) == family;
137	}
138
139	bool InGroup(uint32 group) const
140	{
141		return (type & INTEL_GROUP_MASK) == group;
142	}
143
144	bool IsModel(uint32 model) const
145	{
146		return (type & INTEL_MODEL_MASK) == model;
147	}
148
149	bool IsMobile() const
150	{
151		return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE;
152	}
153
154	bool SupportsHDMI() const
155	{
156		return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5)
157			|| InFamily(INTEL_FAMILY_SOC0);
158	}
159
160	bool HasPlatformControlHub() const
161	{
162		return InFamily(INTEL_FAMILY_SER5);
163	}
164
165	int Generation() const
166	{
167		if (InFamily(INTEL_FAMILY_7xx))
168			return 1;
169		if (InFamily(INTEL_FAMILY_8xx))
170			return 2;
171		if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
172				|| IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN))
173			return 3;
174		if (InFamily(INTEL_FAMILY_9xx))
175			return 4;
176		if (InGroup(INTEL_GROUP_ILK))
177			return 5;
178		if (InGroup(INTEL_GROUP_SNB))
179			return 6;
180		if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV))
181			return 7;
182		if (InGroup(INTEL_GROUP_CHV))
183			return 8;
184		if (InGroup(INTEL_GROUP_BXT))
185			return 9;
186
187		// Generation 0 means somethins is wrong :-)
188		return 0;
189	}
190};
191
192// info about PLL on graphics card
193struct pll_info {
194	uint32			reference_frequency;
195	uint32			max_frequency;
196	uint32			min_frequency;
197	uint32			divisor_register;
198};
199
200struct ring_buffer {
201	struct lock		lock;
202	uint32			register_base;
203	uint32			offset;
204	uint32			size;
205	uint32			position;
206	uint32			space_left;
207	uint8*			base;
208};
209
210struct overlay_registers;
211
212struct intel_shared_info {
213	area_id			mode_list_area;		// area containing display mode list
214	uint32			mode_count;
215
216	display_mode	current_mode;
217	uint32			bytes_per_row;
218	uint32			bits_per_pixel;
219	uint32			dpms_mode;
220
221	area_id			registers_area;			// area of memory mapped registers
222	uint32			register_blocks[REGISTER_BLOCK_COUNT];
223
224	uint8*			status_page;
225	phys_addr_t		physical_status_page;
226	uint8*			graphics_memory;
227	phys_addr_t		physical_graphics_memory;
228	uint32			graphics_memory_size;
229
230	addr_t			frame_buffer;
231	uint32			frame_buffer_offset;
232
233	uint32			fdi_link_frequency;	// In Mhz
234
235	bool			got_vbt;
236	bool			single_head_locked;
237
238	struct lock		accelerant_lock;
239	struct lock		engine_lock;
240
241	ring_buffer		primary_ring_buffer;
242
243	int32			overlay_channel_used;
244	bool			overlay_active;
245	uintptr_t		overlay_token;
246	phys_addr_t		physical_overlay_registers;
247	uint32			overlay_offset;
248
249	bool			hardware_cursor_enabled;
250	sem_id			vblank_sem;
251
252	uint8*			cursor_memory;
253	phys_addr_t		physical_cursor_memory;
254	uint32			cursor_buffer_offset;
255	uint32			cursor_format;
256	bool			cursor_visible;
257	uint16			cursor_hot_x;
258	uint16			cursor_hot_y;
259
260	DeviceType		device_type;
261	char			device_identifier[32];
262	struct pll_info	pll_info;
263
264	edid1_info		vesa_edid_info;
265	bool			has_vesa_edid_info;
266};
267
268enum pipe_index {
269    INTEL_PIPE_ANY,
270    INTEL_PIPE_A,
271    INTEL_PIPE_B
272};
273
274//----------------- ioctl() interface ----------------
275
276// magic code for ioctls
277#define INTEL_PRIVATE_DATA_MAGIC		'itic'
278
279// list ioctls
280enum {
281	INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
282
283	INTEL_GET_DEVICE_NAME,
284	INTEL_ALLOCATE_GRAPHICS_MEMORY,
285	INTEL_FREE_GRAPHICS_MEMORY
286};
287
288// retrieve the area_id of the kernel/accelerant shared info
289struct intel_get_private_data {
290	uint32	magic;				// magic number
291	area_id	shared_info_area;
292};
293
294// allocate graphics memory
295struct intel_allocate_graphics_memory {
296	uint32	magic;
297	uint32	size;
298	uint32	alignment;
299	uint32	flags;
300	addr_t	buffer_base;
301};
302
303// free graphics memory
304struct intel_free_graphics_memory {
305	uint32 	magic;
306	addr_t	buffer_base;
307};
308
309//----------------------------------------------------------
310// Register definitions, taken from X driver
311
312// PCI bridge memory management
313#define INTEL_GRAPHICS_MEMORY_CONTROL	0x52		// i830+
314
315	// GGC - (G)MCH Graphics Control Register
316#define MEMORY_CONTROL_ENABLED			0x0004
317#define MEMORY_MASK						0x0001
318#define STOLEN_MEMORY_MASK				0x00f0
319#define i965_GTT_MASK					0x000e
320#define G33_GTT_MASK					0x0300
321#define G4X_GTT_MASK					0x0f00	// GGMS (GSM Memory Size) mask
322
323// models i830 and up
324#define i830_LOCAL_MEMORY_ONLY			0x10
325#define i830_STOLEN_512K				0x20
326#define i830_STOLEN_1M					0x30
327#define i830_STOLEN_8M					0x40
328#define i830_FRAME_BUFFER_64M			0x01
329#define i830_FRAME_BUFFER_128M			0x00
330
331// models i855 and up
332#define i855_STOLEN_MEMORY_1M			0x10
333#define i855_STOLEN_MEMORY_4M			0x20
334#define i855_STOLEN_MEMORY_8M			0x30
335#define i855_STOLEN_MEMORY_16M			0x40
336#define i855_STOLEN_MEMORY_32M			0x50
337#define i855_STOLEN_MEMORY_48M			0x60
338#define i855_STOLEN_MEMORY_64M			0x70
339#define i855_STOLEN_MEMORY_128M			0x80
340#define i855_STOLEN_MEMORY_256M			0x90
341
342#define G4X_STOLEN_MEMORY_96MB			0xa0	// GMS - Graphics Mode Select
343#define G4X_STOLEN_MEMORY_160MB			0xb0
344#define G4X_STOLEN_MEMORY_224MB			0xc0
345#define G4X_STOLEN_MEMORY_352MB			0xd0
346
347// SandyBridge (SNB)
348
349#define SNB_GRAPHICS_MEMORY_CONTROL		0x50
350
351#define SNB_STOLEN_MEMORY_MASK			0xf8
352#define SNB_STOLEN_MEMORY_32MB			(1 << 3)
353#define SNB_STOLEN_MEMORY_64MB			(2 << 3)
354#define SNB_STOLEN_MEMORY_96MB			(3 << 3)
355#define SNB_STOLEN_MEMORY_128MB			(4 << 3)
356#define SNB_STOLEN_MEMORY_160MB			(5 << 3)
357#define SNB_STOLEN_MEMORY_192MB			(6 << 3)
358#define SNB_STOLEN_MEMORY_224MB			(7 << 3)
359#define SNB_STOLEN_MEMORY_256MB			(8 << 3)
360#define SNB_STOLEN_MEMORY_288MB			(9 << 3)
361#define SNB_STOLEN_MEMORY_320MB			(10 << 3)
362#define SNB_STOLEN_MEMORY_352MB			(11 << 3)
363#define SNB_STOLEN_MEMORY_384MB			(12 << 3)
364#define SNB_STOLEN_MEMORY_416MB			(13 << 3)
365#define SNB_STOLEN_MEMORY_448MB			(14 << 3)
366#define SNB_STOLEN_MEMORY_480MB			(15 << 3)
367#define SNB_STOLEN_MEMORY_512MB			(16 << 3)
368
369#define SNB_GTT_SIZE_MASK				(3 << 8)
370#define SNB_GTT_SIZE_NONE				(0 << 8)
371#define SNB_GTT_SIZE_1MB				(1 << 8)
372#define SNB_GTT_SIZE_2MB				(2 << 8)
373
374// graphics page translation table
375#define INTEL_PAGE_TABLE_CONTROL		0x02020
376#define PAGE_TABLE_ENABLED				0x00000001
377#define INTEL_PAGE_TABLE_ERROR			0x02024
378#define INTEL_HARDWARE_STATUS_PAGE		0x02080
379#define i915_GTT_BASE					0x1c
380#define i830_GTT_BASE					0x10000	// (- 0x2ffff)
381#define i830_GTT_SIZE					0x20000
382#define i965_GTT_BASE					0x80000	// (- 0xfffff)
383#define i965_GTT_SIZE					0x80000
384#define i965_GTT_128K					(2 << 1)
385#define i965_GTT_256K					(1 << 1)
386#define i965_GTT_512K					(0 << 1)
387#define G33_GTT_1M						(1 << 8)
388#define G33_GTT_2M						(2 << 8)
389#define G4X_GTT_NONE					0x000	// GGMS - GSM Memory Size
390#define G4X_GTT_1M_NO_IVT				0x100	// no Intel Virtualization Tech.
391#define G4X_GTT_2M_NO_IVT				0x300
392#define G4X_GTT_2M_IVT					0x900	// with Intel Virt. Tech.
393#define G4X_GTT_3M_IVT					0xa00
394#define G4X_GTT_4M_IVT					0xb00
395
396
397#define GTT_ENTRY_VALID					0x01
398#define GTT_ENTRY_LOCAL_MEMORY			0x02
399#define GTT_PAGE_SHIFT					12
400
401
402// ring buffer
403#define INTEL_PRIMARY_RING_BUFFER		0x02030
404#define INTEL_SECONDARY_RING_BUFFER_0	0x02100
405#define INTEL_SECONDARY_RING_BUFFER_1	0x02110
406// offsets for the ring buffer base registers above
407#define RING_BUFFER_TAIL				0x0
408#define RING_BUFFER_HEAD				0x4
409#define RING_BUFFER_START				0x8
410#define RING_BUFFER_CONTROL				0xc
411#define INTEL_RING_BUFFER_SIZE_MASK		0x001ff000
412#define INTEL_RING_BUFFER_HEAD_MASK		0x001ffffc
413#define INTEL_RING_BUFFER_ENABLED		1
414
415// interrupts
416#define INTEL_INTERRUPT_ENABLED			0x020a0
417#define INTEL_INTERRUPT_IDENTITY		0x020a4
418#define INTEL_INTERRUPT_MASK			0x020a8
419#define INTEL_INTERRUPT_STATUS			0x020ac
420#define INTERRUPT_VBLANK_PIPEA			(1 << 7)
421#define INTERRUPT_VBLANK_PIPEB			(1 << 5)
422
423// PCH interrupts
424#define PCH_INTERRUPT_STATUS			0x44000
425#define PCH_INTERRUPT_MASK				0x44004
426#define PCH_INTERRUPT_IDENTITY			0x44008
427#define PCH_INTERRUPT_ENABLED			0x4400c
428#define PCH_INTERRUPT_VBLANK_PIPEA		(1 << 0)
429#define PCH_INTERRUPT_VBLANK_PIPEB		(1 << 5)
430#define PCH_INTERRUPT_VBLANK_PIPEC		(1 << 10)
431
432#define PCH_INTERRUPT_VBLANK_PIPEA_SNB		(1 << 7)
433#define PCH_INTERRUPT_VBLANK_PIPEB_SNB		(1 << 15)
434
435// graphics port control
436#define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
437#define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
438#define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
439#define DISPLAY_MONITOR_MODE_MASK		(3UL << 10)
440#define DISPLAY_MONITOR_ON				0
441#define DISPLAY_MONITOR_SUSPEND			(1UL << 10)
442#define DISPLAY_MONITOR_STAND_BY		(2UL << 10)
443#define DISPLAY_MONITOR_OFF				(3UL << 10)
444#define DISPLAY_MONITOR_POLARITY_MASK	(3UL << 3)
445#define DISPLAY_MONITOR_POSITIVE_HSYNC	(1UL << 3)
446#define DISPLAY_MONITOR_POSITIVE_VSYNC	(2UL << 3)
447#define DISPLAY_MONITOR_PORT_DETECTED	(1UL << 2) // TMDS/DisplayPort only
448
449#define LVDS_POST2_RATE_SLOW			14 // PLL Divisors
450#define LVDS_POST2_RATE_FAST			7
451#define LVDS_B0B3_POWER_MASK			(3UL << 2)
452#define LVDS_B0B3_POWER_UP				(3UL << 2)
453#define LVDS_CLKB_POWER_MASK			(3UL << 4)
454#define LVDS_CLKB_POWER_UP				(3UL << 4)
455#define LVDS_A3_POWER_MASK				(3UL << 6)
456#define LVDS_A3_POWER_UP				(3UL << 6)
457#define LVDS_A0A2_CLKA_POWER_UP			(3UL << 8)
458#define LVDS_BORDER_ENABLE				(1UL << 15)
459#define LVDS_HSYNC_POLARITY				(1UL << 20)
460#define LVDS_VSYNC_POLARITY				(1UL << 21)
461#define LVDS_18BIT_DITHER				(1UL << 25)
462#define LVDS_PORT_EN					(1UL << 31)
463
464
465// PLL flags
466#define DISPLAY_PLL_ENABLED				(1UL << 31)
467#define DISPLAY_PLL_2X_CLOCK			(1UL << 30)
468#define DISPLAY_PLL_SYNC_LOCK_ENABLED	(1UL << 29)
469#define DISPLAY_PLL_NO_VGA_CONTROL		(1UL << 28)
470#define DISPLAY_PLL_MODE_NORMAL			(1UL << 26)
471#define DISPLAY_PLL_MODE_LVDS			(2UL << 26)
472#define DISPLAY_PLL_DIVIDE_HIGH			(1UL << 24)
473#define DISPLAY_PLL_DIVIDE_4X			(1UL << 23)
474#define DISPLAY_PLL_POST1_DIVIDE_2		(1UL << 21)
475#define DISPLAY_PLL_POST1_DIVISOR_MASK	0x001f0000
476#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK	0x00ff0000
477#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK  0x00ff8000
478#define DISPLAY_PLL_POST1_DIVISOR_SHIFT	16
479#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT	15
480#define DISPLAY_PLL_DIVISOR_1			(1UL << 8)
481#define DISPLAY_PLL_N_DIVISOR_MASK		0x001f0000
482#define DISPLAY_PLL_IGD_N_DIVISOR_MASK	0x00ff0000
483#define DISPLAY_PLL_M1_DIVISOR_MASK		0x00001f00
484#define DISPLAY_PLL_M2_DIVISOR_MASK		0x0000001f
485#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK	0x000000ff
486#define DISPLAY_PLL_N_DIVISOR_SHIFT		16
487#define DISPLAY_PLL_M1_DIVISOR_SHIFT	8
488#define DISPLAY_PLL_M2_DIVISOR_SHIFT	0
489#define DISPLAY_PLL_PULSE_PHASE_SHIFT	9
490
491// display
492
493#define INTEL_DISPLAY_OFFSET			0x1000
494
495#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_NORTH_PIPE_AND_PORT)
496#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_NORTH_PIPE_AND_PORT)
497#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_NORTH_PIPE_AND_PORT)
498#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_NORTH_PIPE_AND_PORT)
499#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_NORTH_PIPE_AND_PORT)
500#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_NORTH_PIPE_AND_PORT)
501#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_NORTH_PIPE_AND_PORT)
502#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_NORTH_PIPE_AND_PORT)
503#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_NORTH_PIPE_AND_PORT)
504#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_NORTH_PIPE_AND_PORT)
505#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_NORTH_PIPE_AND_PORT)
506#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_NORTH_PIPE_AND_PORT)
507
508#define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
509#define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)
510
511// on PCH we also have to set the transcoder
512#define INTEL_TRANSCODER_A_HTOTAL			(0x0000 | REGS_SOUTH_TRANSCODER_PORT)
513#define INTEL_TRANSCODER_A_HBLANK			(0x0004 | REGS_SOUTH_TRANSCODER_PORT)
514#define INTEL_TRANSCODER_A_HSYNC			(0x0008 | REGS_SOUTH_TRANSCODER_PORT)
515#define INTEL_TRANSCODER_A_VTOTAL			(0x000c | REGS_SOUTH_TRANSCODER_PORT)
516#define INTEL_TRANSCODER_A_VBLANK			(0x0010 | REGS_SOUTH_TRANSCODER_PORT)
517#define INTEL_TRANSCODER_A_VSYNC			(0x0014 | REGS_SOUTH_TRANSCODER_PORT)
518#define INTEL_TRANSCODER_B_HTOTAL			(0x1000 | REGS_SOUTH_TRANSCODER_PORT)
519#define INTEL_TRANSCODER_B_HBLANK			(0x1004 | REGS_SOUTH_TRANSCODER_PORT)
520#define INTEL_TRANSCODER_B_HSYNC			(0x1008 | REGS_SOUTH_TRANSCODER_PORT)
521#define INTEL_TRANSCODER_B_VTOTAL			(0x100c | REGS_SOUTH_TRANSCODER_PORT)
522#define INTEL_TRANSCODER_B_VBLANK			(0x1010 | REGS_SOUTH_TRANSCODER_PORT)
523#define INTEL_TRANSCODER_B_VSYNC			(0x1014 | REGS_SOUTH_TRANSCODER_PORT)
524
525#define INTEL_TRANSCODER_A_IMAGE_SIZE		(0x001c | REGS_SOUTH_TRANSCODER_PORT)
526#define INTEL_TRANSCODER_B_IMAGE_SIZE		(0x101c | REGS_SOUTH_TRANSCODER_PORT)
527
528#define INTEL_ANALOG_PORT				(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
529#define INTEL_DIGITAL_PORT_A			(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
530#define INTEL_DIGITAL_PORT_B			(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
531#define INTEL_DIGITAL_PORT_C			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
532#define INTEL_DIGITAL_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
533
534#define INTEL_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
535#define INTEL_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
536
537#define PCH_HDMI_PORT_B					(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
538#define PCH_HDMI_PORT_C					(0x1150 | REGS_SOUTH_TRANSCODER_PORT)
539#define PCH_HDMI_PORT_D					(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
540
541#define GEN4_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
542#define GEN4_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
543#define CHV_HDMI_PORT_D					(0x116C | REGS_SOUTH_TRANSCODER_PORT)
544
545// DP_A always @ 6xxxx, DP_B-DP_D move with PCH
546#define INTEL_DISPLAY_PORT_A			(0x4000 | REGS_NORTH_PIPE_AND_PORT)
547#define INTEL_DISPLAY_PORT_B			(0x4100 | REGS_SOUTH_TRANSCODER_PORT)
548#define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_SOUTH_TRANSCODER_PORT)
549#define INTEL_DISPLAY_PORT_D			(0x4300 | REGS_SOUTH_TRANSCODER_PORT)
550
551// Unless you're a damn Valley/CherryView unicorn :-(
552#define VLV_DISPLAY_PORT_B				(VLV_DISPLAY_BASE + 0x64100)
553#define VLV_DISPLAY_PORT_C				(VLV_DISPLAY_BASE + 0x64200)
554#define CHV_DISPLAY_PORT_D				(VLV_DISPLAY_BASE + 0x64300)
555
556// planes
557#define INTEL_PIPE_ENABLED				(1UL << 31)
558#define INTEL_PIPE_CONTROL				0x0008
559#define INTEL_PIPE_STATUS				0x0024
560
561#define INTEL_PLANE_OFFSET				0x1000
562
563#define INTEL_DISPLAY_A_PIPE_CONTROL	(0x0008	| REGS_NORTH_PLANE_CONTROL)
564#define INTEL_DISPLAY_B_PIPE_CONTROL	(0x1008 | REGS_NORTH_PLANE_CONTROL)
565#define INTEL_DISPLAY_A_PIPE_STATUS		(0x0024 | REGS_NORTH_PLANE_CONTROL)
566#define INTEL_DISPLAY_B_PIPE_STATUS		(0x1024 | REGS_NORTH_PLANE_CONTROL)
567
568#define DISPLAY_PIPE_VBLANK_ENABLED		(1UL << 17)
569#define DISPLAY_PIPE_VBLANK_STATUS		(1UL << 1)
570
571#define INTEL_DISPLAY_A_CONTROL			(0x0180 | REGS_NORTH_PLANE_CONTROL)
572#define INTEL_DISPLAY_A_BASE			(0x0184 | REGS_NORTH_PLANE_CONTROL)
573#define INTEL_DISPLAY_A_BYTES_PER_ROW	(0x0188 | REGS_NORTH_PLANE_CONTROL)
574#define INTEL_DISPLAY_A_POS				(0x018c | REGS_NORTH_PLANE_CONTROL)
575	// reserved on A
576#define INTEL_DISPLAY_A_PIPE_SIZE		(0x0190 | REGS_NORTH_PLANE_CONTROL)
577#define INTEL_DISPLAY_A_SURFACE			(0x019c | REGS_NORTH_PLANE_CONTROL)
578	// i965 and up only
579
580#define INTEL_DISPLAY_B_CONTROL			(0x1180 | REGS_NORTH_PLANE_CONTROL)
581#define INTEL_DISPLAY_B_BASE			(0x1184 | REGS_NORTH_PLANE_CONTROL)
582#define INTEL_DISPLAY_B_BYTES_PER_ROW	(0x1188 | REGS_NORTH_PLANE_CONTROL)
583#define INTEL_DISPLAY_B_POS				(0x118c | REGS_NORTH_PLANE_CONTROL)
584#define INTEL_DISPLAY_B_PIPE_SIZE		(0x1190 | REGS_NORTH_PLANE_CONTROL)
585#define INTEL_DISPLAY_B_SURFACE			(0x119c | REGS_NORTH_PLANE_CONTROL)
586	// i965 and up only
587
588// INTEL_DISPLAY_A_CONTROL source pixel format
589#define DISPLAY_CONTROL_ENABLED			(1UL << 31)
590#define DISPLAY_CONTROL_GAMMA			(1UL << 30)
591#define DISPLAY_CONTROL_COLOR_MASK		(0x0fUL << 26)
592#define DISPLAY_CONTROL_CMAP8			(2UL << 26)
593#define DISPLAY_CONTROL_RGB15			(4UL << 26)
594#define DISPLAY_CONTROL_RGB16			(5UL << 26)
595#define DISPLAY_CONTROL_RGB32			(6UL << 26)
596
597// INTEL_DISPLAY_A_PIPE_CONTROL ILK+
598#define INTEL_PIPE_DITHER_TYPE_MASK		(0x0000000c)
599#define INTEL_PIPE_DITHER_TYPE_SP		(0 << 2)
600#define INTEL_PIPE_DITHER_TYPE_ST1		(1 << 2)
601#define INTEL_PIPE_DITHER_TYPE_ST2		(2 << 2)
602#define INTEL_PIPE_DITHER_TYPE_TEMP		(3 << 2)
603#define INTEL_PIPE_DITHER_EN			(1 << 4)
604#define INTEL_PIPE_8BPC					(0 << 5)
605#define INTEL_PIPE_10BPC				(1 << 5)
606#define INTEL_PIPE_6BPC					(2 << 5)
607#define INTEL_PIPE_12BPC				(3 << 5)
608#define INTEL_PIPE_PROGRESSIVE			(0 << 21)
609
610// cursors
611#define INTEL_CURSOR_CONTROL			(0x0080 | REGS_NORTH_PLANE_CONTROL)
612#define INTEL_CURSOR_BASE				(0x0084 | REGS_NORTH_PLANE_CONTROL)
613#define INTEL_CURSOR_POSITION			(0x0088 | REGS_NORTH_PLANE_CONTROL)
614#define INTEL_CURSOR_PALETTE			(0x0090 | REGS_NORTH_PLANE_CONTROL)
615	// (- 0x009f)
616#define INTEL_CURSOR_SIZE				(0x00a0 | REGS_NORTH_PLANE_CONTROL)
617#define CURSOR_ENABLED					(1UL << 31)
618#define CURSOR_FORMAT_2_COLORS			(0UL << 24)
619#define CURSOR_FORMAT_3_COLORS			(1UL << 24)
620#define CURSOR_FORMAT_4_COLORS			(2UL << 24)
621#define CURSOR_FORMAT_ARGB				(4UL << 24)
622#define CURSOR_FORMAT_XRGB				(5UL << 24)
623#define CURSOR_POSITION_NEGATIVE		0x8000
624#define CURSOR_POSITION_MASK			0x3fff
625
626// palette registers
627#define INTEL_DISPLAY_A_PALETTE			(0xa000 | REGS_NORTH_SHARED)
628#define INTEL_DISPLAY_B_PALETTE			(0xa800 | REGS_NORTH_SHARED)
629
630// PLL registers
631#define INTEL_DISPLAY_A_PLL				(0x6014 | REGS_SOUTH_SHARED)
632#define INTEL_DISPLAY_B_PLL				(0x6018 | REGS_SOUTH_SHARED)
633#define CHV_DISPLAY_C_PLL				(0x6030 | REGS_SOUTH_SHARED)
634
635//  Multiplier Divisor
636#define INTEL_DISPLAY_A_PLL_MD			(0x601C | REGS_SOUTH_SHARED)
637#define INTEL_DISPLAY_B_PLL_MD			(0x6020 | REGS_SOUTH_SHARED)
638#define CHV_DISPLAY_B_PLL_MD			(0x603C | REGS_SOUTH_SHARED)
639
640#define INTEL_DISPLAY_A_PLL_DIVISOR_0	(0x6040 | REGS_SOUTH_SHARED)
641#define INTEL_DISPLAY_A_PLL_DIVISOR_1	(0x6044 | REGS_SOUTH_SHARED)
642#define INTEL_DISPLAY_B_PLL_DIVISOR_0	(0x6048 | REGS_SOUTH_SHARED)
643#define INTEL_DISPLAY_B_PLL_DIVISOR_1	(0x604c | REGS_SOUTH_SHARED)
644
645// i2c
646#define INTEL_I2C_IO_A					(0x5010 | REGS_SOUTH_SHARED)
647#define INTEL_I2C_IO_B					(0x5014 | REGS_SOUTH_SHARED)
648#define INTEL_I2C_IO_C					(0x5018 | REGS_SOUTH_SHARED)
649#define INTEL_I2C_IO_D					(0x501c | REGS_SOUTH_SHARED)
650#define INTEL_I2C_IO_E					(0x5020 | REGS_SOUTH_SHARED)
651#define INTEL_I2C_IO_F					(0x5024 | REGS_SOUTH_SHARED)
652#define INTEL_I2C_IO_G					(0x5028 | REGS_SOUTH_SHARED)
653#define INTEL_I2C_IO_H					(0x502c | REGS_SOUTH_SHARED)
654
655#define I2C_CLOCK_DIRECTION_MASK		(1 << 0)
656#define I2C_CLOCK_DIRECTION_OUT			(1 << 1)
657#define I2C_CLOCK_VALUE_MASK			(1 << 2)
658#define I2C_CLOCK_VALUE_OUT				(1 << 3)
659#define I2C_CLOCK_VALUE_IN				(1 << 4)
660#define I2C_DATA_DIRECTION_MASK			(1 << 8)
661#define I2C_DATA_DIRECTION_OUT			(1 << 9)
662#define I2C_DATA_VALUE_MASK				(1 << 10)
663#define I2C_DATA_VALUE_OUT				(1 << 11)
664#define I2C_DATA_VALUE_IN				(1 << 12)
665#define I2C_RESERVED					((1 << 13) | (1 << 5))
666
667// TODO: on IronLake this is in the north shared block at 0x41000
668#define INTEL_VGA_DISPLAY_CONTROL		(0x1400 | REGS_NORTH_PLANE_CONTROL)
669#define VGA_DISPLAY_DISABLED			(1UL << 31)
670
671// LVDS panel
672#define INTEL_PANEL_STATUS				(0x1200 | REGS_NORTH_PIPE_AND_PORT)
673#define INTEL_PANEL_CONTROL				(0x1204 | REGS_NORTH_PIPE_AND_PORT)
674#define INTEL_PANEL_FIT_CONTROL			(0x1230 | REGS_NORTH_PIPE_AND_PORT)
675#define INTEL_PANEL_FIT_RATIOS			(0x1234 | REGS_NORTH_PIPE_AND_PORT)
676
677// LVDS on IronLake and up
678#define PCH_PANEL_STATUS				(0x7200 | REGS_SOUTH_SHARED)
679#define PCH_PANEL_CONTROL				(0x7204 | REGS_SOUTH_SHARED)
680#define PCH_PANEL_ON_DELAYS				(0x7208 | REGS_SOUTH_SHARED)
681#define PCH_PANEL_OFF_DELAYS			(0x720c | REGS_SOUTH_SHARED)
682#define PCH_PANEL_DIVISOR				(0x7210 | REGS_SOUTH_SHARED)
683#define PCH_LVDS_DETECTED				(1 << 1)
684
685#define PANEL_STATUS_POWER_ON			(1UL << 31)
686#define PANEL_CONTROL_POWER_TARGET_OFF	(0UL << 0)
687#define PANEL_CONTROL_POWER_TARGET_ON	(1UL << 0)
688#define PANEL_CONTROL_POWER_TARGET_RST	(1UL << 1)
689#define PANEL_REGISTER_UNLOCK			(0xabcd << 16)
690
691// PCH_PANEL_ON_DELAYS
692#define PANEL_DELAY_PORT_SELECT_MASK	(3 << 30)
693#define PANEL_DELAY_PORT_SELECT_LVDS	(0 << 30)
694#define PANEL_DELAY_PORT_SELECT_DPA		(1 << 30)
695#define PANEL_DELAY_PORT_SELECT_DPC		(2 << 30)
696#define PANEL_DELAY_PORT_SELECT_DPD		(3 << 30)
697
698// PCH_PANEL_DIVISOR
699#define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00
700#define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8
701#define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f
702#define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f
703
704// ring buffer commands
705
706#define COMMAND_NOOP					0x00
707#define COMMAND_WAIT_FOR_EVENT			(0x03 << 23)
708#define COMMAND_WAIT_FOR_OVERLAY_FLIP	(1 << 16)
709
710#define COMMAND_FLUSH					(0x04 << 23)
711
712// overlay flip
713#define COMMAND_OVERLAY_FLIP			(0x11 << 23)
714#define COMMAND_OVERLAY_CONTINUE		(0 << 21)
715#define COMMAND_OVERLAY_ON				(1 << 21)
716#define COMMAND_OVERLAY_OFF				(2 << 21)
717#define OVERLAY_UPDATE_COEFFICIENTS		0x1
718
719// 2D acceleration
720#define XY_COMMAND_SOURCE_BLIT			0x54c00006
721#define XY_COMMAND_COLOR_BLIT			0x54000004
722#define XY_COMMAND_SETUP_MONO_PATTERN	0x44400007
723#define XY_COMMAND_SCANLINE_BLIT		0x49400001
724#define COMMAND_COLOR_BLIT				0x50000003
725#define COMMAND_BLIT_RGBA				0x00300000
726
727#define COMMAND_MODE_SOLID_PATTERN		0x80
728#define COMMAND_MODE_CMAP8				0x00
729#define COMMAND_MODE_RGB15				0x02
730#define COMMAND_MODE_RGB16				0x01
731#define COMMAND_MODE_RGB32				0x03
732
733// overlay
734#define INTEL_OVERLAY_UPDATE			0x30000
735#define INTEL_OVERLAY_TEST				0x30004
736#define INTEL_OVERLAY_STATUS			0x30008
737#define INTEL_OVERLAY_EXTENDED_STATUS	0x3000c
738#define INTEL_OVERLAY_GAMMA_5			0x30010
739#define INTEL_OVERLAY_GAMMA_4			0x30014
740#define INTEL_OVERLAY_GAMMA_3			0x30018
741#define INTEL_OVERLAY_GAMMA_2			0x3001c
742#define INTEL_OVERLAY_GAMMA_1			0x30020
743#define INTEL_OVERLAY_GAMMA_0			0x30024
744
745// FDI - Flexible Display Interface, the interface between the (CPU-internal)
746// GPU and the PCH display outputs. Proprietary interface, based on DisplayPort
747// though, so similar link training and all...
748// There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the
749// PCH for each display pipe.
750// FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to
751// transcoder B, so we have the same mapping as with the display pipes.
752#define PCH_FDI_RX_BASE_REGISTER		0xf0000
753#define PCH_FDI_RX_PIPE_OFFSET			0x01000
754#define PCH_FDI_RX_CONTROL				0x00c
755#define FDI_RX_ENABLE					(1 << 31)
756#define FDI_RX_PLL_ENABLED				(1 << 13)
757
758#define FDI_FS_ERRC_ENABLE				(1 << 27)
759#define FDI_FE_ERRC_ENABLE				(1 << 26)
760
761#define PCH_FDI_RX_TRANS_UNIT_SIZE_1	0x30
762#define PCH_FDI_RX_TRANS_UNIT_SIZE_2	0x38
763#define FDI_RX_TRANS_UNIT_SIZE(x)		((x - 1) << 25)
764#define FDI_RX_TRANS_UNIT_MASK			0x7e000000
765
766#define FDI_RX_ENHANCE_FRAME_ENABLE		(1 << 6)
767#define FDI_RX_CLOCK_MASK				(1 << 4)
768#define FDI_RX_CLOCK_RAW				(0 << 4)
769#define FDI_RX_CLOCK_PCD				(1 << 4)
770
771#define PCH_FDI_TX_BASE_REGISTER		0x60000
772#define PCH_FDI_TX_PIPE_OFFSET			0x01000
773#define PCH_FDI_TX_CONTROL				0x100
774#define FDI_TX_ENABLE					(1 << 31)
775#define FDI_TX_ENHANCE_FRAME_ENABLE		(1 << 18)
776#define FDI_TX_PLL_ENABLED				(1 << 14)
777
778#define FDI_PLL_BIOS_0					0x46000
779#define FDI_PLL_FB_CLOCK_MASK			0xff
780#define FDI_PLL_BIOS_1					0x46004
781#define FDI_PLL_BIOS_2					0x46008
782
783#define FDI_LINK_TRAIN_PATTERN_1		(0 << 28)
784#define FDI_LINK_TRAIN_PATTERN_2		(1 << 28)
785#define FDI_LINK_TRAIN_PATTERN_IDLE		(2 << 28)
786#define FDI_LINK_TRAIN_NONE				(3 << 28)
787#define FDI_LINK_TRAIN_VOLTAGE_0_4V		(0 << 25)
788#define FDI_LINK_TRAIN_VOLTAGE_0_6V		(1 << 25)
789#define FDI_LINK_TRAIN_VOLTAGE_0_8V		(2 << 25)
790#define FDI_LINK_TRAIN_VOLTAGE_1_2V		(3 << 25)
791#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
792#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
793#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X	(2 << 22)
794#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X	(3 << 22)
795
796#define FDI_AUTO_TRAINING				(1 << 10)
797#define FDI_AUTO_TRAIN_DONE				(1 << 1)
798
799// SNB A-stepping
800#define FDI_LINK_TRAIN_400MV_0DB_SNB_A	(0x38 << 22)
801#define FDI_LINK_TRAIN_400MV_6DB_SNB_A	(0x02 << 22)
802#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
803#define FDI_LINK_TRAIN_800MV_0DB_SNB_A	(0x00 << 22)
804
805// SNB B-stepping
806#define FDI_LINK_TRAIN_400MV_0DB_SNB_B	(0x00 << 22)
807#define FDI_LINK_TRAIN_400MV_6DB_SNB_B	(0x3a << 22)
808#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
809#define FDI_LINK_TRAIN_800MV_0DB_SNB_B	(0x38 << 22)
810#define FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f << 22)
811
812#define FDI_LINK_TRAIN_PATTERN_1_CPT	(0 << 8)
813#define FDI_LINK_TRAIN_PATTERN_2_CPT	(1 << 8)
814#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2 << 8)
815#define FDI_LINK_TRAIN_NORMAL_CPT		(3 << 8)
816#define FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3 << 8)
817
818// IvyBridge changes it up because... they hate developers?
819#define FDI_LINK_TRAIN_PATTERN_1_IVB	(0 << 8)
820#define FDI_LINK_TRAIN_PATTERN_2_IVB	(1 << 8)
821#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB	(2 << 8)
822#define FDI_LINK_TRAIN_NONE_IVB			(3 << 8)
823
824// CPU Panel Fitters - These are for IronLake and up and are the CPU internal
825// panel fitters.
826#define PCH_PANEL_FITTER_BASE_REGISTER	0x68000
827#define PCH_PANEL_FITTER_PIPE_OFFSET	0x00800
828
829#define PCH_PANEL_FITTER_WINDOW_POS		0x70
830#define PCH_PANEL_FITTER_WINDOW_SIZE	0x74
831#define PCH_PANEL_FITTER_CONTROL		0x80
832#define PCH_PANEL_FITTER_V_SCALE		0x84
833#define PCH_PANEL_FITTER_H_SCALE		0x90
834
835#define PANEL_FITTER_ENABLED			(1 << 31)
836#define PANEL_FITTER_FILTER_MASK		(3 << 23)
837
838struct overlay_scale {
839	uint32 _reserved0 : 3;
840	uint32 horizontal_scale_fraction : 12;
841	uint32 _reserved1 : 1;
842	uint32 horizontal_downscale_factor : 3;
843	uint32 _reserved2 : 1;
844	uint32 vertical_scale_fraction : 12;
845};
846
847#define OVERLAY_FORMAT_RGB15			0x2
848#define OVERLAY_FORMAT_RGB16			0x3
849#define OVERLAY_FORMAT_RGB32			0x1
850#define OVERLAY_FORMAT_YCbCr422			0x8
851#define OVERLAY_FORMAT_YCbCr411			0x9
852#define OVERLAY_FORMAT_YCbCr420			0xc
853
854#define OVERLAY_MIRROR_NORMAL			0x0
855#define OVERLAY_MIRROR_HORIZONTAL		0x1
856#define OVERLAY_MIRROR_VERTICAL			0x2
857
858// The real overlay registers are written to using an update buffer
859
860struct overlay_registers {
861	uint32 buffer_rgb0;
862	uint32 buffer_rgb1;
863	uint32 buffer_u0;
864	uint32 buffer_v0;
865	uint32 buffer_u1;
866	uint32 buffer_v1;
867	// (0x18) OSTRIDE - overlay stride
868	uint16 stride_rgb;
869	uint16 stride_uv;
870	// (0x1c) YRGB_VPH - Y/RGB vertical phase
871	uint16 vertical_phase0_rgb;
872	uint16 vertical_phase1_rgb;
873	// (0x20) UV_VPH - UV vertical phase
874	uint16 vertical_phase0_uv;
875	uint16 vertical_phase1_uv;
876	// (0x24) HORZ_PH - horizontal phase
877	uint16 horizontal_phase_rgb;
878	uint16 horizontal_phase_uv;
879	// (0x28) INIT_PHS - initial phase shift
880	uint32 initial_vertical_phase0_shift_rgb0 : 4;
881	uint32 initial_vertical_phase1_shift_rgb0 : 4;
882	uint32 initial_horizontal_phase_shift_rgb0 : 4;
883	uint32 initial_vertical_phase0_shift_uv : 4;
884	uint32 initial_vertical_phase1_shift_uv : 4;
885	uint32 initial_horizontal_phase_shift_uv : 4;
886	uint32 _reserved0 : 8;
887	// (0x2c) DWINPOS - destination window position
888	uint16 window_left;
889	uint16 window_top;
890	// (0x30) DWINSZ - destination window size
891	uint16 window_width;
892	uint16 window_height;
893	// (0x34) SWIDTH - source width
894	uint16 source_width_rgb;
895	uint16 source_width_uv;
896	// (0x38) SWITDHSW - source width in 8 byte steps
897	uint16 source_bytes_per_row_rgb;
898	uint16 source_bytes_per_row_uv;
899	uint16 source_height_rgb;
900	uint16 source_height_uv;
901	overlay_scale scale_rgb;
902	overlay_scale scale_uv;
903	// (0x48) OCLRC0 - overlay color correction 0
904	uint32 brightness_correction : 8;		// signed, -128 to 127
905	uint32 _reserved1 : 10;
906	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
907	uint32 _reserved2 : 5;
908	// (0x4c) OCLRC1 - overlay color correction 1
909	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
910	uint32 _reserved3 : 6;
911	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
912	uint32 _reserved4 : 5;
913	// (0x50) DCLRKV - destination color key value
914	uint32 color_key_blue : 8;
915	uint32 color_key_green : 8;
916	uint32 color_key_red : 8;
917	uint32 _reserved5 : 8;
918	// (0x54) DCLRKM - destination color key mask
919	uint32 color_key_mask_blue : 8;
920	uint32 color_key_mask_green : 8;
921	uint32 color_key_mask_red : 8;
922	uint32 _reserved6 : 7;
923	uint32 color_key_enabled : 1;
924	// (0x58) SCHRKVH - source chroma key high value
925	uint32 source_chroma_key_high_red : 8;
926	uint32 source_chroma_key_high_blue : 8;
927	uint32 source_chroma_key_high_green : 8;
928	uint32 _reserved7 : 8;
929	// (0x5c) SCHRKVL - source chroma key low value
930	uint32 source_chroma_key_low_red : 8;
931	uint32 source_chroma_key_low_blue : 8;
932	uint32 source_chroma_key_low_green : 8;
933	uint32 _reserved8 : 8;
934	// (0x60) SCHRKEN - source chroma key enable
935	uint32 _reserved9 : 24;
936	uint32 source_chroma_key_red_enabled : 1;
937	uint32 source_chroma_key_blue_enabled : 1;
938	uint32 source_chroma_key_green_enabled : 1;
939	uint32 _reserved10 : 5;
940	// (0x64) OCONFIG - overlay configuration
941	uint32 _reserved11 : 3;
942	uint32 color_control_output_mode : 1;
943	uint32 yuv_to_rgb_bypass : 1;
944	uint32 _reserved12 : 11;
945	uint32 gamma2_enabled : 1;
946	uint32 _reserved13 : 1;
947	uint32 select_pipe : 1;
948	uint32 slot_time : 8;
949	uint32 _reserved14 : 5;
950	// (0x68) OCOMD - overlay command
951	uint32 overlay_enabled : 1;
952	uint32 active_field : 1;
953	uint32 active_buffer : 2;
954	uint32 test_mode : 1;
955	uint32 buffer_field_mode : 1;
956	uint32 _reserved15 : 1;
957	uint32 tv_flip_field_enabled : 1;
958	uint32 _reserved16 : 1;
959	uint32 tv_flip_field_parity : 1;
960	uint32 source_format : 4;
961	uint32 ycbcr422_order : 2;
962	uint32 _reserved18 : 1;
963	uint32 mirroring_mode : 2;
964	uint32 _reserved19 : 13;
965
966	uint32 _reserved20;
967
968	uint32 start_0y;
969	uint32 start_1y;
970	uint32 start_0u;
971	uint32 start_0v;
972	uint32 start_1u;
973	uint32 start_1v;
974	uint32 _reserved21[6];
975#if 0
976	// (0x70) AWINPOS - alpha blend window position
977	uint32 awinpos;
978	// (0x74) AWINSZ - alpha blend window size
979	uint32 awinsz;
980
981	uint32 _reserved21[10];
982#endif
983
984	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
985	// the next two registers switch the usual Y/RGB vs. UV order)
986	uint16 horizontal_scale_uv;
987	uint16 horizontal_scale_rgb;
988	// (0xa4) UVSCALEV - vertical downscale
989	uint16 vertical_scale_uv;
990	uint16 vertical_scale_rgb;
991
992	uint32 _reserved22[86];
993
994	// (0x200) polyphase filter coefficients
995	uint16 vertical_coefficients_rgb[128];
996	uint16 horizontal_coefficients_rgb[128];
997
998	uint32	_reserved23[64];
999
1000	// (0x500)
1001	uint16 vertical_coefficients_uv[128];
1002	uint16 horizontal_coefficients_uv[128];
1003};
1004
1005// i965 overlay support is currently realized using its 3D hardware
1006#define INTEL_i965_OVERLAY_STATE_SIZE	36864
1007#define INTEL_i965_3D_CONTEXT_SIZE		32768
1008
1009inline bool
1010intel_uses_physical_overlay(intel_shared_info &info)
1011{
1012	return !info.device_type.InGroup(INTEL_GROUP_Gxx);
1013}
1014
1015
1016struct hardware_status {
1017	uint32	interrupt_status_register;
1018	uint32	_reserved0[3];
1019	void*	primary_ring_head_storage;
1020	uint32	_reserved1[3];
1021	void*	secondary_ring_0_head_storage;
1022	void*	secondary_ring_1_head_storage;
1023	uint32	_reserved2[2];
1024	void*	binning_head_storage;
1025	uint32	_reserved3[3];
1026	uint32	store[1008];
1027};
1028
1029#endif	/* INTEL_EXTREME_H */
1030