intel_extreme.h revision 95b6439e
1/*
2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 *		Alexander von Gluck, kallisti5@unixzen.com
8 */
9#ifndef INTEL_EXTREME_H
10#define INTEL_EXTREME_H
11
12
13#include "lock.h"
14
15#include <Accelerant.h>
16#include <Drivers.h>
17#include <PCI.h>
18
19#include <edid.h>
20
21
22#define VENDOR_ID_INTEL			0x8086
23
24#define INTEL_FAMILY_MASK	0x00ff0000
25#define INTEL_GROUP_MASK	0x00fffff0
26#define INTEL_MODEL_MASK	0x00ffffff
27#define INTEL_TYPE_MASK		0x0000000f
28// families
29#define INTEL_FAMILY_7xx	0x00010000	// First Gen
30#define INTEL_FAMILY_8xx	0x00020000	// Second Gen
31#define INTEL_FAMILY_9xx	0x00040000	// Third Gen +
32#define INTEL_FAMILY_SER5	0x00080000	// Intel5 Series
33#define INTEL_FAMILY_POVR	0x00100000	// PowerVR (uugh)
34#define INTEL_FAMILY_SOC0	0x00200000  // Atom SOC
35#define INTEL_FAMILY_LAKE	0x00400000	// Intel Lakes
36// groups
37#define INTEL_GROUP_83x		(INTEL_FAMILY_8xx  | 0x0010)
38#define INTEL_GROUP_85x		(INTEL_FAMILY_8xx  | 0x0020)
39#define INTEL_GROUP_91x		(INTEL_FAMILY_9xx  | 0x0010)
40#define INTEL_GROUP_94x		(INTEL_FAMILY_9xx  | 0x0020)
41#define INTEL_GROUP_96x		(INTEL_FAMILY_9xx  | 0x0040)
42#define INTEL_GROUP_Gxx		(INTEL_FAMILY_9xx  | 0x0080)
43#define INTEL_GROUP_G4x		(INTEL_FAMILY_9xx  | 0x0100)
44#define INTEL_GROUP_PIN		(INTEL_FAMILY_9xx  | 0x0200)  // PineView
45#define INTEL_GROUP_ILK		(INTEL_FAMILY_SER5 | 0x0010)  // IronLake
46#define INTEL_GROUP_SNB		(INTEL_FAMILY_SER5 | 0x0020)  // SandyBridge
47#define INTEL_GROUP_IVB		(INTEL_FAMILY_SER5 | 0x0040)  // IvyBridge
48#define INTEL_GROUP_HAS		(INTEL_FAMILY_SER5 | 0x0080)  // Haswell
49#define INTEL_GROUP_SLT		(INTEL_FAMILY_POVR | 0x0010)  // Saltwell
50#define INTEL_GROUP_FSM		(INTEL_FAMILY_POVR | 0x0020)  // Fu.Silvermont
51#define INTEL_GROUP_VLV		(INTEL_FAMILY_SOC0 | 0x0010)  // ValleyView
52#define INTEL_GROUP_CHV		(INTEL_FAMILY_SOC0 | 0x0020)  // CherryView
53#define INTEL_GROUP_BXT		(INTEL_FAMILY_SOC0 | 0x0040)  // Broxton
54#define INTEL_GROUP_SKY		(INTEL_FAMILY_LAKE | 0x0010)  // SkyLake
55#define INTEL_GROUP_KBY		(INTEL_FAMILY_LAKE | 0x0020)  // KabyLake
56// models
57#define INTEL_TYPE_SERVER	0x0004
58#define INTEL_TYPE_MOBILE	0x0008
59#define INTEL_MODEL_915		(INTEL_GROUP_91x)
60#define INTEL_MODEL_915M	(INTEL_GROUP_91x | INTEL_TYPE_MOBILE)
61#define INTEL_MODEL_945		(INTEL_GROUP_94x)
62#define INTEL_MODEL_945M	(INTEL_GROUP_94x | INTEL_TYPE_MOBILE)
63#define INTEL_MODEL_965		(INTEL_GROUP_96x)
64#define INTEL_MODEL_965M	(INTEL_GROUP_96x | INTEL_TYPE_MOBILE)
65#define INTEL_MODEL_G33		(INTEL_GROUP_Gxx)
66#define INTEL_MODEL_G45		(INTEL_GROUP_G4x)
67#define INTEL_MODEL_GM45	(INTEL_GROUP_G4x | INTEL_TYPE_MOBILE)
68#define INTEL_MODEL_PINE	(INTEL_GROUP_PIN)
69#define INTEL_MODEL_PINEM	(INTEL_GROUP_PIN | INTEL_TYPE_MOBILE)
70#define INTEL_MODEL_ILKG	(INTEL_GROUP_ILK)
71#define INTEL_MODEL_ILKGM	(INTEL_GROUP_ILK | INTEL_TYPE_MOBILE)
72#define INTEL_MODEL_SNBG	(INTEL_GROUP_SNB)
73#define INTEL_MODEL_SNBGM	(INTEL_GROUP_SNB | INTEL_TYPE_MOBILE)
74#define INTEL_MODEL_SNBGS	(INTEL_GROUP_SNB | INTEL_TYPE_SERVER)
75#define INTEL_MODEL_IVBG	(INTEL_GROUP_IVB)
76#define INTEL_MODEL_IVBGM	(INTEL_GROUP_IVB | INTEL_TYPE_MOBILE)
77#define INTEL_MODEL_IVBGS	(INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
78#define INTEL_MODEL_HAS		(INTEL_GROUP_HAS)
79#define INTEL_MODEL_HASM	(INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
80#define INTEL_MODEL_VLV		(INTEL_GROUP_VLV)
81#define INTEL_MODEL_VLVM	(INTEL_GROUP_VLV | INTEL_TYPE_MOBILE)
82#define INTEL_MODEL_SKY		(INTEL_GROUP_SKY)
83#define INTEL_MODEL_SKYM	(INTEL_GROUP_SKY | INTEL_TYPE_MOBILE)
84#define INTEL_MODEL_SKYS	(INTEL_GROUP_SKY | INTEL_TYPE_SERVER)
85
86#define INTEL_PCH_DEVICE_ID_MASK			0xff00
87#define INTEL_PCH_IBX_DEVICE_ID		0x3b00
88#define INTEL_PCH_CPT_DEVICE_ID		0x1c00
89#define INTEL_PCH_PPT_DEVICE_ID		0x1e00
90#define INTEL_PCH_LPT_DEVICE_ID		0x8c00
91#define INTEL_PCH_LPT_LP_DEVICE_ID	0x9c00
92#define INTEL_PCH_SPT_DEVICE_ID		0xa100
93#define INTEL_PCH_SPT_LP_DEVICE_ID	0x9d00
94#define INTEL_PCH_P2X_DEVICE_ID		0x7100
95#define INTEL_PCH_P3X_DEVICE_ID		0x7000
96
97// ValleyView MMIO offset
98#define VLV_DISPLAY_BASE		0x180000
99
100#define DEVICE_NAME				"intel_extreme"
101#define INTEL_ACCELERANT_NAME	"intel_extreme.accelerant"
102
103// We encode the register block into the value and extract/translate it when
104// actually accessing.
105#define REGISTER_BLOCK_COUNT				6
106#define REGISTER_BLOCK_SHIFT				24
107#define REGISTER_BLOCK_MASK					0xff000000
108#define REGISTER_REGISTER_MASK				0x00ffffff
109#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
110#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
111
112#define REGS_FLAT							(0 << REGISTER_BLOCK_SHIFT)
113#define REGS_NORTH_SHARED					(1 << REGISTER_BLOCK_SHIFT)
114#define REGS_NORTH_PIPE_AND_PORT			(2 << REGISTER_BLOCK_SHIFT)
115#define REGS_NORTH_PLANE_CONTROL			(3 << REGISTER_BLOCK_SHIFT)
116#define REGS_SOUTH_SHARED					(4 << REGISTER_BLOCK_SHIFT)
117#define REGS_SOUTH_TRANSCODER_PORT			(5 << REGISTER_BLOCK_SHIFT)
118
119// register blocks for (G)MCH/ICH based platforms
120#define MCH_SHARED_REGISTER_BASE						0x00000
121#define MCH_PIPE_AND_PORT_REGISTER_BASE					0x60000
122#define MCH_PLANE_CONTROL_REGISTER_BASE					0x70000
123#define ICH_SHARED_REGISTER_BASE						0x00000
124#define ICH_PORT_REGISTER_BASE							0x60000
125
126// PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based
127// setup to a PCH based one, that means anything that used to communicate via
128// (G)MCH registers needs to use different ones on PCH based platforms
129// (Ironlake, SandyBridge, IvyBridge, Some Haswell).
130#define PCH_NORTH_SHARED_REGISTER_BASE					0x40000
131#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE			0x60000
132#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE			0x70000
133#define PCH_SOUTH_SHARED_REGISTER_BASE					0xc0000
134#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE		0xe0000
135
136
137struct DeviceType {
138	uint32			type;
139
140	DeviceType(int t)
141	{
142		type = t;
143	}
144
145	DeviceType& operator=(int t)
146	{
147		type = t;
148		return *this;
149	}
150
151	bool InFamily(uint32 family) const
152	{
153		return (type & INTEL_FAMILY_MASK) == family;
154	}
155
156	bool InGroup(uint32 group) const
157	{
158		return (type & INTEL_GROUP_MASK) == group;
159	}
160
161	bool IsModel(uint32 model) const
162	{
163		return (type & INTEL_MODEL_MASK) == model;
164	}
165
166	bool IsMobile() const
167	{
168		return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE;
169	}
170
171	bool SupportsHDMI() const
172	{
173		return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5)
174			|| InFamily(INTEL_FAMILY_SOC0);
175	}
176
177	bool HasDDI() const
178	{
179		// Intel Digital Display Interface
180		return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8);
181	}
182
183	int Generation() const
184	{
185		if (InFamily(INTEL_FAMILY_7xx))
186			return 1;
187		if (InFamily(INTEL_FAMILY_8xx))
188			return 2;
189		if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
190				|| IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN))
191			return 3;
192		if (InFamily(INTEL_FAMILY_9xx))
193			return 4;
194		if (InGroup(INTEL_GROUP_ILK))
195			return 5;
196		if (InGroup(INTEL_GROUP_SNB))
197			return 6;
198		if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV))
199			return 7;
200		if (InGroup(INTEL_GROUP_CHV))
201			return 8;
202		if (InGroup(INTEL_GROUP_BXT) || InFamily(INTEL_FAMILY_LAKE))
203			return 9;
204
205		// Generation 0 means somethins is wrong :-)
206		return 0;
207	}
208};
209
210enum pch_info {
211	INTEL_PCH_NONE = 0,		// No PCH present
212	INTEL_PCH_IBX,			// Ibexpeak
213	INTEL_PCH_CPT,			// Cougarpoint
214	INTEL_PCH_LPT,			// Lynxpoint
215	INTEL_PCH_SPT,			// Sunrisepoint
216	INTEL_PCH_NOP
217};
218
219// info about PLL on graphics card
220struct pll_info {
221	uint32			reference_frequency;
222	uint32			max_frequency;
223	uint32			min_frequency;
224	uint32			divisor_register;
225};
226
227struct ring_buffer {
228	struct lock		lock;
229	uint32			register_base;
230	uint32			offset;
231	uint32			size;
232	uint32			position;
233	uint32			space_left;
234	uint8*			base;
235};
236
237struct overlay_registers;
238
239struct intel_shared_info {
240	area_id			mode_list_area;		// area containing display mode list
241	uint32			mode_count;
242
243	display_mode	panel_mode;			// VBIOS VBT panel mode
244	uint32			bytes_per_row;
245	uint32			bits_per_pixel;
246	uint32			dpms_mode;
247
248	area_id			registers_area;		// area of memory mapped registers
249	uint32			register_blocks[REGISTER_BLOCK_COUNT];
250
251	uint8*			status_page;
252	phys_addr_t		physical_status_page;
253	uint8*			graphics_memory;
254	phys_addr_t		physical_graphics_memory;
255	uint32			graphics_memory_size;
256
257	addr_t			frame_buffer;
258	uint32			frame_buffer_offset;
259
260	uint32			fdi_link_frequency;	// In Mhz
261
262	bool			got_vbt;
263	bool			single_head_locked;
264
265	struct lock		accelerant_lock;
266	struct lock		engine_lock;
267
268	ring_buffer		primary_ring_buffer;
269
270	int32			overlay_channel_used;
271	bool			overlay_active;
272	uintptr_t		overlay_token;
273	phys_addr_t		physical_overlay_registers;
274	uint32			overlay_offset;
275
276	bool			hardware_cursor_enabled;
277	sem_id			vblank_sem;
278
279	uint8*			cursor_memory;
280	phys_addr_t		physical_cursor_memory;
281	uint32			cursor_buffer_offset;
282	uint32			cursor_format;
283	bool			cursor_visible;
284	uint16			cursor_hot_x;
285	uint16			cursor_hot_y;
286
287	DeviceType		device_type;
288	char			device_identifier[32];
289	struct pll_info	pll_info;
290
291	enum pch_info	pch_info;
292
293	edid1_info		vesa_edid_info;
294	bool			has_vesa_edid_info;
295};
296
297enum pipe_index {
298    INTEL_PIPE_ANY,
299    INTEL_PIPE_A,
300    INTEL_PIPE_B
301};
302
303//----------------- ioctl() interface ----------------
304
305// magic code for ioctls
306#define INTEL_PRIVATE_DATA_MAGIC		'itic'
307
308// list ioctls
309enum {
310	INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
311
312	INTEL_GET_DEVICE_NAME,
313	INTEL_ALLOCATE_GRAPHICS_MEMORY,
314	INTEL_FREE_GRAPHICS_MEMORY
315};
316
317// retrieve the area_id of the kernel/accelerant shared info
318struct intel_get_private_data {
319	uint32	magic;				// magic number
320	area_id	shared_info_area;
321};
322
323// allocate graphics memory
324struct intel_allocate_graphics_memory {
325	uint32	magic;
326	uint32	size;
327	uint32	alignment;
328	uint32	flags;
329	addr_t	buffer_base;
330};
331
332// free graphics memory
333struct intel_free_graphics_memory {
334	uint32 	magic;
335	addr_t	buffer_base;
336};
337
338//----------------------------------------------------------
339// Register definitions, taken from X driver
340
341// PCI bridge memory management
342#define INTEL_GRAPHICS_MEMORY_CONTROL	0x52		// i830+
343
344	// GGC - (G)MCH Graphics Control Register
345#define MEMORY_CONTROL_ENABLED			0x0004
346#define MEMORY_MASK						0x0001
347#define STOLEN_MEMORY_MASK				0x00f0
348#define i965_GTT_MASK					0x000e
349#define G33_GTT_MASK					0x0300
350#define G4X_GTT_MASK					0x0f00	// GGMS (GSM Memory Size) mask
351
352// models i830 and up
353#define i830_LOCAL_MEMORY_ONLY			0x10
354#define i830_STOLEN_512K				0x20
355#define i830_STOLEN_1M					0x30
356#define i830_STOLEN_8M					0x40
357#define i830_FRAME_BUFFER_64M			0x01
358#define i830_FRAME_BUFFER_128M			0x00
359
360// models i855 and up
361#define i855_STOLEN_MEMORY_1M			0x10
362#define i855_STOLEN_MEMORY_4M			0x20
363#define i855_STOLEN_MEMORY_8M			0x30
364#define i855_STOLEN_MEMORY_16M			0x40
365#define i855_STOLEN_MEMORY_32M			0x50
366#define i855_STOLEN_MEMORY_48M			0x60
367#define i855_STOLEN_MEMORY_64M			0x70
368#define i855_STOLEN_MEMORY_128M			0x80
369#define i855_STOLEN_MEMORY_256M			0x90
370
371#define G4X_STOLEN_MEMORY_96MB			0xa0	// GMS - Graphics Mode Select
372#define G4X_STOLEN_MEMORY_160MB			0xb0
373#define G4X_STOLEN_MEMORY_224MB			0xc0
374#define G4X_STOLEN_MEMORY_352MB			0xd0
375
376// SandyBridge (SNB)
377
378#define SNB_GRAPHICS_MEMORY_CONTROL		0x50
379
380#define SNB_STOLEN_MEMORY_MASK			0xf8
381#define SNB_STOLEN_MEMORY_32MB			(1 << 3)
382#define SNB_STOLEN_MEMORY_64MB			(2 << 3)
383#define SNB_STOLEN_MEMORY_96MB			(3 << 3)
384#define SNB_STOLEN_MEMORY_128MB			(4 << 3)
385#define SNB_STOLEN_MEMORY_160MB			(5 << 3)
386#define SNB_STOLEN_MEMORY_192MB			(6 << 3)
387#define SNB_STOLEN_MEMORY_224MB			(7 << 3)
388#define SNB_STOLEN_MEMORY_256MB			(8 << 3)
389#define SNB_STOLEN_MEMORY_288MB			(9 << 3)
390#define SNB_STOLEN_MEMORY_320MB			(10 << 3)
391#define SNB_STOLEN_MEMORY_352MB			(11 << 3)
392#define SNB_STOLEN_MEMORY_384MB			(12 << 3)
393#define SNB_STOLEN_MEMORY_416MB			(13 << 3)
394#define SNB_STOLEN_MEMORY_448MB			(14 << 3)
395#define SNB_STOLEN_MEMORY_480MB			(15 << 3)
396#define SNB_STOLEN_MEMORY_512MB			(16 << 3)
397
398#define SNB_GTT_SIZE_MASK				(3 << 8)
399#define SNB_GTT_SIZE_NONE				(0 << 8)
400#define SNB_GTT_SIZE_1MB				(1 << 8)
401#define SNB_GTT_SIZE_2MB				(2 << 8)
402
403// graphics page translation table
404#define INTEL_PAGE_TABLE_CONTROL		0x02020
405#define PAGE_TABLE_ENABLED				0x00000001
406#define INTEL_PAGE_TABLE_ERROR			0x02024
407#define INTEL_HARDWARE_STATUS_PAGE		0x02080
408#define i915_GTT_BASE					0x1c
409#define i830_GTT_BASE					0x10000	// (- 0x2ffff)
410#define i830_GTT_SIZE					0x20000
411#define i965_GTT_BASE					0x80000	// (- 0xfffff)
412#define i965_GTT_SIZE					0x80000
413#define i965_GTT_128K					(2 << 1)
414#define i965_GTT_256K					(1 << 1)
415#define i965_GTT_512K					(0 << 1)
416#define G33_GTT_1M						(1 << 8)
417#define G33_GTT_2M						(2 << 8)
418#define G4X_GTT_NONE					0x000	// GGMS - GSM Memory Size
419#define G4X_GTT_1M_NO_IVT				0x100	// no Intel Virtualization Tech.
420#define G4X_GTT_2M_NO_IVT				0x300
421#define G4X_GTT_2M_IVT					0x900	// with Intel Virt. Tech.
422#define G4X_GTT_3M_IVT					0xa00
423#define G4X_GTT_4M_IVT					0xb00
424
425
426#define GTT_ENTRY_VALID					0x01
427#define GTT_ENTRY_LOCAL_MEMORY			0x02
428#define GTT_PAGE_SHIFT					12
429
430
431// ring buffer
432#define INTEL_PRIMARY_RING_BUFFER		0x02030
433#define INTEL_SECONDARY_RING_BUFFER_0	0x02100
434#define INTEL_SECONDARY_RING_BUFFER_1	0x02110
435// offsets for the ring buffer base registers above
436#define RING_BUFFER_TAIL				0x0
437#define RING_BUFFER_HEAD				0x4
438#define RING_BUFFER_START				0x8
439#define RING_BUFFER_CONTROL				0xc
440#define INTEL_RING_BUFFER_SIZE_MASK		0x001ff000
441#define INTEL_RING_BUFFER_HEAD_MASK		0x001ffffc
442#define INTEL_RING_BUFFER_ENABLED		1
443
444// interrupts
445#define INTEL_INTERRUPT_ENABLED			0x020a0
446#define INTEL_INTERRUPT_IDENTITY		0x020a4
447#define INTEL_INTERRUPT_MASK			0x020a8
448#define INTEL_INTERRUPT_STATUS			0x020ac
449#define INTERRUPT_VBLANK_PIPEA			(1 << 7)
450#define INTERRUPT_VBLANK_PIPEB			(1 << 5)
451
452// PCH interrupts
453#define PCH_INTERRUPT_STATUS			0x44000
454#define PCH_INTERRUPT_MASK				0x44004
455#define PCH_INTERRUPT_IDENTITY			0x44008
456#define PCH_INTERRUPT_ENABLED			0x4400c
457#define PCH_INTERRUPT_VBLANK_PIPEA		(1 << 0)
458#define PCH_INTERRUPT_VBLANK_PIPEB		(1 << 5)
459#define PCH_INTERRUPT_VBLANK_PIPEC		(1 << 10)
460
461#define PCH_INTERRUPT_VBLANK_PIPEA_SNB		(1 << 7)
462#define PCH_INTERRUPT_VBLANK_PIPEB_SNB		(1 << 15)
463
464// graphics port control
465#define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
466#define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
467#define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
468#define DISPLAY_MONITOR_MODE_MASK		(3UL << 10)
469#define DISPLAY_MONITOR_ON				0
470#define DISPLAY_MONITOR_SUSPEND			(1UL << 10)
471#define DISPLAY_MONITOR_STAND_BY		(2UL << 10)
472#define DISPLAY_MONITOR_OFF				(3UL << 10)
473#define DISPLAY_MONITOR_POLARITY_MASK	(3UL << 3)
474#define DISPLAY_MONITOR_POSITIVE_HSYNC	(1UL << 3)
475#define DISPLAY_MONITOR_POSITIVE_VSYNC	(2UL << 3)
476#define DISPLAY_MONITOR_PORT_DETECTED	(1UL << 2) // TMDS/DisplayPort only
477
478#define LVDS_POST2_RATE_SLOW			14 // PLL Divisors
479#define LVDS_POST2_RATE_FAST			7
480#define LVDS_B0B3_POWER_MASK			(3UL << 2)
481#define LVDS_B0B3_POWER_UP				(3UL << 2)
482#define LVDS_CLKB_POWER_MASK			(3UL << 4)
483#define LVDS_CLKB_POWER_UP				(3UL << 4)
484#define LVDS_A3_POWER_MASK				(3UL << 6)
485#define LVDS_A3_POWER_UP				(3UL << 6)
486#define LVDS_A0A2_CLKA_POWER_UP			(3UL << 8)
487#define LVDS_BORDER_ENABLE				(1UL << 15)
488#define LVDS_HSYNC_POLARITY				(1UL << 20)
489#define LVDS_VSYNC_POLARITY				(1UL << 21)
490#define LVDS_18BIT_DITHER				(1UL << 25)
491#define LVDS_PORT_EN					(1UL << 31)
492
493// PLL flags
494#define DISPLAY_PLL_ENABLED				(1UL << 31)
495#define DISPLAY_PLL_2X_CLOCK			(1UL << 30)
496#define DISPLAY_PLL_SYNC_LOCK_ENABLED	(1UL << 29)
497#define DISPLAY_PLL_NO_VGA_CONTROL		(1UL << 28)
498#define DISPLAY_PLL_MODE_NORMAL			(1UL << 26)
499#define DISPLAY_PLL_MODE_LVDS			(2UL << 26)
500#define DISPLAY_PLL_DIVIDE_HIGH			(1UL << 24)
501#define DISPLAY_PLL_DIVIDE_4X			(1UL << 23)
502#define DISPLAY_PLL_POST1_DIVIDE_2		(1UL << 21)
503#define DISPLAY_PLL_POST1_DIVISOR_MASK	0x001f0000
504#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK	0x00ff0000
505#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK  0x00ff8000
506#define DISPLAY_PLL_POST1_DIVISOR_SHIFT	16
507#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT	15
508#define DISPLAY_PLL_DIVISOR_1			(1UL << 8)
509#define DISPLAY_PLL_N_DIVISOR_MASK		0x001f0000
510#define DISPLAY_PLL_IGD_N_DIVISOR_MASK	0x00ff0000
511#define DISPLAY_PLL_M1_DIVISOR_MASK		0x00001f00
512#define DISPLAY_PLL_M2_DIVISOR_MASK		0x0000001f
513#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK	0x000000ff
514#define DISPLAY_PLL_N_DIVISOR_SHIFT		16
515#define DISPLAY_PLL_M1_DIVISOR_SHIFT	8
516#define DISPLAY_PLL_M2_DIVISOR_SHIFT	0
517#define DISPLAY_PLL_PULSE_PHASE_SHIFT	9
518
519// display
520
521#define INTEL_DISPLAY_OFFSET			0x1000
522
523#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_NORTH_PIPE_AND_PORT)
524#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_NORTH_PIPE_AND_PORT)
525#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_NORTH_PIPE_AND_PORT)
526#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_NORTH_PIPE_AND_PORT)
527#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_NORTH_PIPE_AND_PORT)
528#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_NORTH_PIPE_AND_PORT)
529#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_NORTH_PIPE_AND_PORT)
530#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_NORTH_PIPE_AND_PORT)
531#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_NORTH_PIPE_AND_PORT)
532#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_NORTH_PIPE_AND_PORT)
533#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_NORTH_PIPE_AND_PORT)
534#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_NORTH_PIPE_AND_PORT)
535
536#define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
537#define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)
538
539// Cougar Point transcoder pipe selection
540#define  PORT_TRANS_A_SEL_CPT			0
541#define  PORT_TRANS_B_SEL_CPT			(1<<29)
542#define  PORT_TRANS_C_SEL_CPT			(2<<29)
543#define  PORT_TRANS_SEL_MASK			(3<<29)
544
545// on PCH we also have to set the transcoder
546#define INTEL_TRANSCODER_A_HTOTAL		(0x0000 | REGS_SOUTH_TRANSCODER_PORT)
547#define INTEL_TRANSCODER_A_HBLANK		(0x0004 | REGS_SOUTH_TRANSCODER_PORT)
548#define INTEL_TRANSCODER_A_HSYNC		(0x0008 | REGS_SOUTH_TRANSCODER_PORT)
549#define INTEL_TRANSCODER_A_VTOTAL		(0x000c | REGS_SOUTH_TRANSCODER_PORT)
550#define INTEL_TRANSCODER_A_VBLANK		(0x0010 | REGS_SOUTH_TRANSCODER_PORT)
551#define INTEL_TRANSCODER_A_VSYNC		(0x0014 | REGS_SOUTH_TRANSCODER_PORT)
552#define INTEL_TRANSCODER_B_HTOTAL		(0x1000 | REGS_SOUTH_TRANSCODER_PORT)
553#define INTEL_TRANSCODER_B_HBLANK		(0x1004 | REGS_SOUTH_TRANSCODER_PORT)
554#define INTEL_TRANSCODER_B_HSYNC		(0x1008 | REGS_SOUTH_TRANSCODER_PORT)
555#define INTEL_TRANSCODER_B_VTOTAL		(0x100c | REGS_SOUTH_TRANSCODER_PORT)
556#define INTEL_TRANSCODER_B_VBLANK		(0x1010 | REGS_SOUTH_TRANSCODER_PORT)
557#define INTEL_TRANSCODER_B_VSYNC		(0x1014 | REGS_SOUTH_TRANSCODER_PORT)
558
559#define INTEL_TRANSCODER_A_IMAGE_SIZE	(0x001c | REGS_SOUTH_TRANSCODER_PORT)
560#define INTEL_TRANSCODER_B_IMAGE_SIZE	(0x101c | REGS_SOUTH_TRANSCODER_PORT)
561
562// TODO: Is there consolidation that could happen here with digital ports?
563
564#define INTEL_ANALOG_PORT				(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
565#define INTEL_DIGITAL_PORT_A			(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
566#define INTEL_DIGITAL_PORT_B			(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
567#define INTEL_DIGITAL_PORT_C			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
568#define INTEL_DIGITAL_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
569
570#define INTEL_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
571#define INTEL_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
572
573#define PCH_HDMI_PORT_B					(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
574#define PCH_HDMI_PORT_C					(0x1150 | REGS_SOUTH_TRANSCODER_PORT)
575#define PCH_HDMI_PORT_D					(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
576
577#define GEN4_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
578#define GEN4_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
579#define CHV_HDMI_PORT_D					(0x116C | REGS_SOUTH_TRANSCODER_PORT)
580
581// DDI Buffer Control (This replaces DP on Haswell+)
582#define DDI_BUF_CTL_A					(0x4000 | REGS_NORTH_PIPE_AND_PORT)
583#define DDI_BUF_CTL_B					(0x4100 | REGS_NORTH_PIPE_AND_PORT)
584#define DDI_BUF_CTL_C					(0x4200 | REGS_NORTH_PIPE_AND_PORT)
585#define DDI_BUF_CTL_D					(0x4300 | REGS_NORTH_PIPE_AND_PORT)
586#define DDI_BUF_CTL_E					(0x4400 | REGS_NORTH_PIPE_AND_PORT)
587#define 	DDI_BUF_CTL_ENABLE			(1 << 31)
588#define 	DDI_BUF_TRANS_SELECT(n)		((n) << 24)
589#define 	DDI_BUF_EMP_MASK			(0xf << 24)
590#define 	DDI_BUF_PORT_REVERSAL		(1 << 16)
591#define 	DDI_BUF_IS_IDLE				(1 << 7)
592#define 	DDI_A_4_LANES				(1 << 4)
593#define 	DDI_PORT_WIDTH(width)		(((width) - 1) << 1)
594#define 	DDI_INIT_DISPLAY_DETECTED	(1 << 0)
595
596// DP_A always @ 6xxxx, DP_B-DP_D move with PCH
597#define INTEL_DISPLAY_PORT_A			(0x4000 | REGS_NORTH_PIPE_AND_PORT)
598#define INTEL_DISPLAY_PORT_B			(0x4100 | REGS_SOUTH_TRANSCODER_PORT)
599#define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_SOUTH_TRANSCODER_PORT)
600#define INTEL_DISPLAY_PORT_D			(0x4300 | REGS_SOUTH_TRANSCODER_PORT)
601
602// Unless you're a damn Valley/CherryView unicorn :-(
603#define VLV_DISPLAY_PORT_B				(VLV_DISPLAY_BASE + 0x64100)
604#define VLV_DISPLAY_PORT_C				(VLV_DISPLAY_BASE + 0x64200)
605#define CHV_DISPLAY_PORT_D				(VLV_DISPLAY_BASE + 0x64300)
606
607// DP AUX channels
608#define INTEL_DP_AUX_CTL_A				(0x4010 | REGS_NORTH_PIPE_AND_PORT)
609#define INTEL_DP_AUX_CTL_B				(0x4110 | REGS_SOUTH_TRANSCODER_PORT)
610#define INTEL_DP_AUX_CTL_C				(0x4210 | REGS_SOUTH_TRANSCODER_PORT)
611#define INTEL_DP_AUX_CTL_D				(0x4310 | REGS_SOUTH_TRANSCODER_PORT)
612
613#define VLV_DP_AUX_CTL_B				(VLV_DISPLAY_BASE + 0x64110)
614#define VLV_DP_AUX_CTL_C				(VLV_DISPLAY_BASE + 0x64210)
615#define CHV_DP_AUX_CTL_D				(VLV_DISPLAY_BASE + 0x64310)
616
617#define INTEL_DP_AUX_CTL_BUSY			(1 << 31)
618#define INTEL_DP_AUX_CTL_DONE			(1 << 30)
619#define INTEL_DP_AUX_CTL_INTERRUPT		(1 << 29)
620#define INTEL_DP_AUX_CTL_TIMEOUT_ERROR	(1 << 28)
621#define INTEL_DP_AUX_CTL_TIMEOUT_400us	(0 << 26)
622#define INTEL_DP_AUX_CTL_TIMEOUT_600us	(1 << 26)
623#define INTEL_DP_AUX_CTL_TIMEOUT_800us	(2 << 26)
624#define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26)
625#define INTEL_DP_AUX_CTL_TIMEOUT_MASK	(3 << 26)
626#define INTEL_DP_AUX_CTL_RECEIVE_ERROR	(1 << 25)
627#define INTEL_DP_AUX_CTL_MSG_SIZE_MASK	(0x1f << 20)
628#define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20
629#define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
630#define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16
631#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
632#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0
633#define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
634
635// planes
636#define INTEL_PIPE_ENABLED				(1UL << 31)
637#define INTEL_PIPE_CONTROL				0x0008
638#define INTEL_PIPE_STATUS				0x0024
639
640#define INTEL_PLANE_OFFSET				0x1000
641
642#define INTEL_DISPLAY_A_PIPE_CONTROL	(0x0008	| REGS_NORTH_PLANE_CONTROL)
643#define INTEL_DISPLAY_B_PIPE_CONTROL	(0x1008 | REGS_NORTH_PLANE_CONTROL)
644#define INTEL_DISPLAY_A_PIPE_STATUS		(0x0024 | REGS_NORTH_PLANE_CONTROL)
645#define INTEL_DISPLAY_B_PIPE_STATUS		(0x1024 | REGS_NORTH_PLANE_CONTROL)
646
647#define DISPLAY_PIPE_VBLANK_ENABLED		(1UL << 17)
648#define DISPLAY_PIPE_VBLANK_STATUS		(1UL << 1)
649
650#define INTEL_DISPLAY_A_CONTROL			(0x0180 | REGS_NORTH_PLANE_CONTROL)
651#define INTEL_DISPLAY_A_BASE			(0x0184 | REGS_NORTH_PLANE_CONTROL)
652#define INTEL_DISPLAY_A_BYTES_PER_ROW	(0x0188 | REGS_NORTH_PLANE_CONTROL)
653#define INTEL_DISPLAY_A_POS				(0x018c | REGS_NORTH_PLANE_CONTROL)
654	// reserved on A
655#define INTEL_DISPLAY_A_PIPE_SIZE		(0x0190 | REGS_NORTH_PLANE_CONTROL)
656#define INTEL_DISPLAY_A_SURFACE			(0x019c | REGS_NORTH_PLANE_CONTROL)
657	// i965 and up only
658
659#define INTEL_DISPLAY_B_CONTROL			(0x1180 | REGS_NORTH_PLANE_CONTROL)
660#define INTEL_DISPLAY_B_BASE			(0x1184 | REGS_NORTH_PLANE_CONTROL)
661#define INTEL_DISPLAY_B_BYTES_PER_ROW	(0x1188 | REGS_NORTH_PLANE_CONTROL)
662#define INTEL_DISPLAY_B_POS				(0x118c | REGS_NORTH_PLANE_CONTROL)
663#define INTEL_DISPLAY_B_PIPE_SIZE		(0x1190 | REGS_NORTH_PLANE_CONTROL)
664#define INTEL_DISPLAY_B_SURFACE			(0x119c | REGS_NORTH_PLANE_CONTROL)
665	// i965 and up only
666
667// INTEL_DISPLAY_A_CONTROL source pixel format
668#define DISPLAY_CONTROL_ENABLED			(1UL << 31)
669#define DISPLAY_CONTROL_GAMMA			(1UL << 30)
670#define DISPLAY_CONTROL_COLOR_MASK		(0x0fUL << 26)
671#define DISPLAY_CONTROL_CMAP8			(2UL << 26)
672#define DISPLAY_CONTROL_RGB15			(4UL << 26)
673#define DISPLAY_CONTROL_RGB16			(5UL << 26)
674#define DISPLAY_CONTROL_RGB32			(6UL << 26)
675
676// INTEL_DISPLAY_A_PIPE_CONTROL ILK+
677#define INTEL_PIPE_DITHER_TYPE_MASK		(0x0000000c)
678#define INTEL_PIPE_DITHER_TYPE_SP		(0 << 2)
679#define INTEL_PIPE_DITHER_TYPE_ST1		(1 << 2)
680#define INTEL_PIPE_DITHER_TYPE_ST2		(2 << 2)
681#define INTEL_PIPE_DITHER_TYPE_TEMP		(3 << 2)
682#define INTEL_PIPE_DITHER_EN			(1 << 4)
683#define INTEL_PIPE_8BPC					(0 << 5)
684#define INTEL_PIPE_10BPC				(1 << 5)
685#define INTEL_PIPE_6BPC					(2 << 5)
686#define INTEL_PIPE_12BPC				(3 << 5)
687#define INTEL_PIPE_PROGRESSIVE			(0 << 21)
688
689// cursors
690#define INTEL_CURSOR_CONTROL			(0x0080 | REGS_NORTH_PLANE_CONTROL)
691#define INTEL_CURSOR_BASE				(0x0084 | REGS_NORTH_PLANE_CONTROL)
692#define INTEL_CURSOR_POSITION			(0x0088 | REGS_NORTH_PLANE_CONTROL)
693#define INTEL_CURSOR_PALETTE			(0x0090 | REGS_NORTH_PLANE_CONTROL)
694	// (- 0x009f)
695#define INTEL_CURSOR_SIZE				(0x00a0 | REGS_NORTH_PLANE_CONTROL)
696#define CURSOR_ENABLED					(1UL << 31)
697#define CURSOR_FORMAT_2_COLORS			(0UL << 24)
698#define CURSOR_FORMAT_3_COLORS			(1UL << 24)
699#define CURSOR_FORMAT_4_COLORS			(2UL << 24)
700#define CURSOR_FORMAT_ARGB				(4UL << 24)
701#define CURSOR_FORMAT_XRGB				(5UL << 24)
702#define CURSOR_POSITION_NEGATIVE		0x8000
703#define CURSOR_POSITION_MASK			0x3fff
704
705// palette registers
706#define INTEL_DISPLAY_A_PALETTE			(0xa000 | REGS_NORTH_SHARED)
707#define INTEL_DISPLAY_B_PALETTE			(0xa800 | REGS_NORTH_SHARED)
708
709// PLL registers
710#define INTEL_DISPLAY_A_PLL				(0x6014 | REGS_SOUTH_SHARED)
711#define INTEL_DISPLAY_B_PLL				(0x6018 | REGS_SOUTH_SHARED)
712#define CHV_DISPLAY_C_PLL				(0x6030 | REGS_SOUTH_SHARED)
713
714// Ironlake PCH reference clk control
715#define PCH_DREF_CONTROL					(0x6200 | REGS_SOUTH_SHARED)
716#define DREF_CONTROL_MASK					0x7fc3
717#define DREF_CPU_SOURCE_OUTPUT_DISABLE		(0 << 13)
718#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD	(2 << 13)
719#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD	(3 << 13)
720#define DREF_CPU_SOURCE_OUTPUT_MASK			(3 << 13)
721#define DREF_SSC_SOURCE_DISABLE				(0 << 11)
722#define DREF_SSC_SOURCE_ENABLE				(2 << 11)
723#define DREF_SSC_SOURCE_MASK				(3 << 11)
724#define DREF_NONSPREAD_SOURCE_DISABLE		(0 << 9)
725#define DREF_NONSPREAD_CK505_ENABLE			(1 << 9)
726#define DREF_NONSPREAD_SOURCE_ENABLE		(2 << 9)
727#define DREF_NONSPREAD_SOURCE_MASK			(3 << 9)
728#define DREF_SUPERSPREAD_SOURCE_DISABLE 	(0 << 7)
729#define DREF_SUPERSPREAD_SOURCE_ENABLE		(2 << 7)
730#define DREF_SUPERSPREAD_SOURCE_MASK		(3 << 7)
731#define DREF_SSC4_DOWNSPREAD				(0 << 6)
732#define DREF_SSC4_CENTERSPREAD				(1 << 6)
733#define DREF_SSC1_DISABLE					(0 << 1)
734#define DREF_SSC1_ENABLE					(1 << 1)
735#define DREF_SSC4_DISABLE					(0 << 0)
736#define DREF_SSC4_ENABLE					(1 << 0)
737
738//  Multiplier Divisor
739#define INTEL_DISPLAY_A_PLL_MD			(0x601C | REGS_SOUTH_SHARED)
740#define INTEL_DISPLAY_B_PLL_MD			(0x6020 | REGS_SOUTH_SHARED)
741#define CHV_DISPLAY_B_PLL_MD			(0x603C | REGS_SOUTH_SHARED)
742
743#define INTEL_DISPLAY_A_PLL_DIVISOR_0	(0x6040 | REGS_SOUTH_SHARED)
744#define INTEL_DISPLAY_A_PLL_DIVISOR_1	(0x6044 | REGS_SOUTH_SHARED)
745#define INTEL_DISPLAY_B_PLL_DIVISOR_0	(0x6048 | REGS_SOUTH_SHARED)
746#define INTEL_DISPLAY_B_PLL_DIVISOR_1	(0x604c | REGS_SOUTH_SHARED)
747
748// i2c
749#define INTEL_I2C_IO_A					(0x5010 | REGS_SOUTH_SHARED)
750#define INTEL_I2C_IO_B					(0x5014 | REGS_SOUTH_SHARED)
751#define INTEL_I2C_IO_C					(0x5018 | REGS_SOUTH_SHARED)
752#define INTEL_I2C_IO_D					(0x501c | REGS_SOUTH_SHARED)
753#define INTEL_I2C_IO_E					(0x5020 | REGS_SOUTH_SHARED)
754#define INTEL_I2C_IO_F					(0x5024 | REGS_SOUTH_SHARED)
755#define INTEL_I2C_IO_G					(0x5028 | REGS_SOUTH_SHARED)
756#define INTEL_I2C_IO_H					(0x502c | REGS_SOUTH_SHARED)
757
758#define I2C_CLOCK_DIRECTION_MASK		(1 << 0)
759#define I2C_CLOCK_DIRECTION_OUT			(1 << 1)
760#define I2C_CLOCK_VALUE_MASK			(1 << 2)
761#define I2C_CLOCK_VALUE_OUT				(1 << 3)
762#define I2C_CLOCK_VALUE_IN				(1 << 4)
763#define I2C_DATA_DIRECTION_MASK			(1 << 8)
764#define I2C_DATA_DIRECTION_OUT			(1 << 9)
765#define I2C_DATA_VALUE_MASK				(1 << 10)
766#define I2C_DATA_VALUE_OUT				(1 << 11)
767#define I2C_DATA_VALUE_IN				(1 << 12)
768#define I2C_RESERVED					((1 << 13) | (1 << 5))
769
770// TODO: on IronLake this is in the north shared block at 0x41000
771#define INTEL_VGA_DISPLAY_CONTROL		(0x1400 | REGS_NORTH_PLANE_CONTROL)
772#define VGA_DISPLAY_DISABLED			(1UL << 31)
773
774// LVDS panel
775#define INTEL_PANEL_STATUS				(0x1200 | REGS_NORTH_PIPE_AND_PORT)
776#define INTEL_PANEL_CONTROL				(0x1204 | REGS_NORTH_PIPE_AND_PORT)
777#define INTEL_PANEL_FIT_CONTROL			(0x1230 | REGS_NORTH_PIPE_AND_PORT)
778#define INTEL_PANEL_FIT_RATIOS			(0x1234 | REGS_NORTH_PIPE_AND_PORT)
779
780// LVDS on IronLake and up
781#define PCH_PANEL_STATUS				(0x7200 | REGS_SOUTH_SHARED)
782#define PCH_PANEL_CONTROL				(0x7204 | REGS_SOUTH_SHARED)
783#define PCH_PANEL_ON_DELAYS				(0x7208 | REGS_SOUTH_SHARED)
784#define PCH_PANEL_OFF_DELAYS			(0x720c | REGS_SOUTH_SHARED)
785#define PCH_PANEL_DIVISOR				(0x7210 | REGS_SOUTH_SHARED)
786#define PCH_LVDS_DETECTED				(1 << 1)
787
788#define PANEL_STATUS_POWER_ON			(1UL << 31)
789#define PANEL_CONTROL_POWER_TARGET_OFF	(0UL << 0)
790#define PANEL_CONTROL_POWER_TARGET_ON	(1UL << 0)
791#define PANEL_CONTROL_POWER_TARGET_RST	(1UL << 1)
792#define PANEL_REGISTER_UNLOCK			(0xabcd << 16)
793
794// PCH_PANEL_ON_DELAYS
795#define PANEL_DELAY_PORT_SELECT_MASK	(3 << 30)
796#define PANEL_DELAY_PORT_SELECT_LVDS	(0 << 30)
797#define PANEL_DELAY_PORT_SELECT_DPA		(1 << 30)
798#define PANEL_DELAY_PORT_SELECT_DPC		(2 << 30)
799#define PANEL_DELAY_PORT_SELECT_DPD		(3 << 30)
800
801// PCH_PANEL_DIVISOR
802#define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00
803#define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8
804#define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f
805#define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f
806
807// ring buffer commands
808
809#define COMMAND_NOOP					0x00
810#define COMMAND_WAIT_FOR_EVENT			(0x03 << 23)
811#define COMMAND_WAIT_FOR_OVERLAY_FLIP	(1 << 16)
812
813#define COMMAND_FLUSH					(0x04 << 23)
814
815// overlay flip
816#define COMMAND_OVERLAY_FLIP			(0x11 << 23)
817#define COMMAND_OVERLAY_CONTINUE		(0 << 21)
818#define COMMAND_OVERLAY_ON				(1 << 21)
819#define COMMAND_OVERLAY_OFF				(2 << 21)
820#define OVERLAY_UPDATE_COEFFICIENTS		0x1
821
822// 2D acceleration
823#define XY_COMMAND_SOURCE_BLIT			0x54c00006
824#define XY_COMMAND_COLOR_BLIT			0x54000004
825#define XY_COMMAND_SETUP_MONO_PATTERN	0x44400007
826#define XY_COMMAND_SCANLINE_BLIT		0x49400001
827#define COMMAND_COLOR_BLIT				0x50000003
828#define COMMAND_BLIT_RGBA				0x00300000
829
830#define COMMAND_MODE_SOLID_PATTERN		0x80
831#define COMMAND_MODE_CMAP8				0x00
832#define COMMAND_MODE_RGB15				0x02
833#define COMMAND_MODE_RGB16				0x01
834#define COMMAND_MODE_RGB32				0x03
835
836// overlay
837#define INTEL_OVERLAY_UPDATE			0x30000
838#define INTEL_OVERLAY_TEST				0x30004
839#define INTEL_OVERLAY_STATUS			0x30008
840#define INTEL_OVERLAY_EXTENDED_STATUS	0x3000c
841#define INTEL_OVERLAY_GAMMA_5			0x30010
842#define INTEL_OVERLAY_GAMMA_4			0x30014
843#define INTEL_OVERLAY_GAMMA_3			0x30018
844#define INTEL_OVERLAY_GAMMA_2			0x3001c
845#define INTEL_OVERLAY_GAMMA_1			0x30020
846#define INTEL_OVERLAY_GAMMA_0			0x30024
847
848// FDI - Flexible Display Interface, the interface between the (CPU-internal)
849// GPU and the PCH display outputs. Proprietary interface, based on DisplayPort
850// though, so similar link training and all...
851// There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the
852// PCH for each display pipe.
853// FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to
854// transcoder B, so we have the same mapping as with the display pipes.
855#define PCH_FDI_RX_BASE_REGISTER		0xf0000
856#define PCH_FDI_RX_PIPE_OFFSET			0x01000
857#define PCH_FDI_RX_CONTROL				0x00c
858#define PCH_FDI_RX_MISC					0x010
859#define PCH_FDI_RX_IIR					0x014
860#define PCH_FDI_RX_IMR					0x018
861
862#define FDI_RX_ENABLE					(1 << 31)
863#define FDI_RX_PLL_ENABLED				(1 << 13)
864
865// FDI_tX interrupt register
866#define FDI_RX_INTER_LANE_ALIGN         (1 << 10)
867#define FDI_RX_SYMBOL_LOCK              (1 << 9)
868#define FDI_RX_BIT_LOCK                 (1 << 8)
869#define FDI_RX_TRAIN_PATTERN_2_FAIL     (1 << 7)
870#define FDI_RX_FS_CODE_ERR              (1 << 6)
871#define FDI_RX_FE_CODE_ERR              (1 << 5)
872#define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1 << 4)
873#define FDI_RX_HDCP_LINK_FAIL           (1 << 3)
874#define FDI_RX_PIXEL_FIFO_OVERFLOW      (1 << 2)
875#define FDI_RX_CROSS_CLOCK_OVERFLOW     (1 << 1)
876#define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
877
878#define FDI_FS_ERRC_ENABLE				(1 << 27)
879#define FDI_FE_ERRC_ENABLE				(1 << 26)
880
881#define PCH_FDI_RX_TRANS_UNIT_SIZE_1	0x30
882#define PCH_FDI_RX_TRANS_UNIT_SIZE_2	0x38
883#define FDI_RX_TRANS_UNIT_SIZE(x)		((x - 1) << 25)
884#define FDI_RX_TRANS_UNIT_MASK			0x7e000000
885
886#define FDI_RX_ENHANCE_FRAME_ENABLE		(1 << 6)
887#define FDI_RX_CLOCK_MASK				(1 << 4)
888#define FDI_RX_CLOCK_RAW				(0 << 4)
889#define FDI_RX_CLOCK_PCD				(1 << 4)
890
891// FDI RX MISC
892#define FDI_RX_PWRDN_LANE1_MASK		(3 << 26)
893#define FDI_RX_PWRDN_LANE1_VAL(x)	((x) << 26)
894#define FDI_RX_PWRDN_LANE0_MASK		(3 << 24)
895#define FDI_RX_PWRDN_LANE0_VAL(x)	((x) << 24)
896#define FDI_RX_TP1_TO_TP2_48		(2 << 20)
897#define FDI_RX_TP1_TO_TP2_64		(3 << 20)
898#define FDI_RX_FDI_DELAY_90			(0x90 << 0)
899
900#define PCH_FDI_TX_BASE_REGISTER			0x60000
901#define PCH_FDI_TX_PIPE_OFFSET				0x01000
902#define PCH_FDI_TX_CONTROL					0x100
903#define FDI_TX_ENABLE						(1 << 31)
904#define FDI_LINK_TRAIN_PATTERN_1			(0 << 28)
905#define FDI_LINK_TRAIN_PATTERN_2			(1 << 28)
906#define FDI_LINK_TRAIN_PATTERN_IDLE			(2 << 28)
907#define FDI_LINK_TRAIN_NONE					(3 << 28)
908#define FDI_LINK_TRAIN_VOLTAGE_0_4V			(0 << 25)
909#define FDI_LINK_TRAIN_VOLTAGE_0_6V			(1 << 25)
910#define FDI_LINK_TRAIN_VOLTAGE_0_8V			(2 << 25)
911#define FDI_LINK_TRAIN_VOLTAGE_1_2V			(3 << 25)
912#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE	(0 << 22)
913#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X	(1 << 22)
914#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X		(2 << 22)
915#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X		(3 << 22)
916
917// SNB A stepping
918#define FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
919#define FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
920#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
921#define FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x00 << 22)
922
923// SNB B stepping
924#define FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x00 << 22)
925#define FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
926#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
927#define FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
928#define FDI_LINK_TRAIN_VOL_EMP_MASK			(0x3f << 22)
929#define FDI_TX_ENHANCE_FRAME_ENABLE			(1 << 18)
930#define FDI_TX_PLL_ENABLED					(1 << 14)
931
932#define FDI_DP_PORT_WIDTH_SHIFT			19
933#define FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
934#define FDI_DP_PORT_WIDTH(width)		(((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
935
936#define FDI_PLL_BIOS_0					0x46000
937#define FDI_PLL_FB_CLOCK_MASK			0xff
938#define FDI_PLL_BIOS_1					0x46004
939#define FDI_PLL_BIOS_2					0x46008
940
941#define FDI_AUTO_TRAINING				(1 << 10)
942#define FDI_AUTO_TRAIN_DONE				(1 << 1)
943
944#define FDI_LINK_TRAIN_PATTERN_1_CPT	(0 << 8)
945#define FDI_LINK_TRAIN_PATTERN_2_CPT	(1 << 8)
946#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2 << 8)
947#define FDI_LINK_TRAIN_NORMAL_CPT		(3 << 8)
948#define FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3 << 8)
949
950// IvyBridge changes it up because... they hate developers?
951#define FDI_LINK_TRAIN_PATTERN_1_IVB	(0 << 8)
952#define FDI_LINK_TRAIN_PATTERN_2_IVB	(1 << 8)
953#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB	(2 << 8)
954#define FDI_LINK_TRAIN_NONE_IVB			(3 << 8)
955
956#define PCH_FDI_RXA_CHICKEN				(0x200c | REGS_SOUTH_SHARED)
957#define PCH_FDI_RXB_CHICKEN				(0x2010 | REGS_SOUTH_SHARED)
958#define FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
959#define FDI_RX_PHASE_SYNC_POINTER_OVR	(1 << 1)
960
961// CPU Panel Fitters - These are for IronLake and up and are the CPU internal
962// panel fitters.
963#define PCH_PANEL_FITTER_BASE_REGISTER	0x68000
964#define PCH_PANEL_FITTER_PIPE_OFFSET	0x00800
965
966#define PCH_PANEL_FITTER_WINDOW_POS		0x70
967#define PCH_PANEL_FITTER_WINDOW_SIZE	0x74
968#define PCH_PANEL_FITTER_CONTROL		0x80
969#define PCH_PANEL_FITTER_V_SCALE		0x84
970#define PCH_PANEL_FITTER_H_SCALE		0x90
971
972#define PANEL_FITTER_ENABLED			(1 << 31)
973#define PANEL_FITTER_FILTER_MASK		(3 << 23)
974
975struct overlay_scale {
976	uint32 _reserved0 : 3;
977	uint32 horizontal_scale_fraction : 12;
978	uint32 _reserved1 : 1;
979	uint32 horizontal_downscale_factor : 3;
980	uint32 _reserved2 : 1;
981	uint32 vertical_scale_fraction : 12;
982};
983
984#define OVERLAY_FORMAT_RGB15			0x2
985#define OVERLAY_FORMAT_RGB16			0x3
986#define OVERLAY_FORMAT_RGB32			0x1
987#define OVERLAY_FORMAT_YCbCr422			0x8
988#define OVERLAY_FORMAT_YCbCr411			0x9
989#define OVERLAY_FORMAT_YCbCr420			0xc
990
991#define OVERLAY_MIRROR_NORMAL			0x0
992#define OVERLAY_MIRROR_HORIZONTAL		0x1
993#define OVERLAY_MIRROR_VERTICAL			0x2
994
995// The real overlay registers are written to using an update buffer
996
997struct overlay_registers {
998	uint32 buffer_rgb0;
999	uint32 buffer_rgb1;
1000	uint32 buffer_u0;
1001	uint32 buffer_v0;
1002	uint32 buffer_u1;
1003	uint32 buffer_v1;
1004	// (0x18) OSTRIDE - overlay stride
1005	uint16 stride_rgb;
1006	uint16 stride_uv;
1007	// (0x1c) YRGB_VPH - Y/RGB vertical phase
1008	uint16 vertical_phase0_rgb;
1009	uint16 vertical_phase1_rgb;
1010	// (0x20) UV_VPH - UV vertical phase
1011	uint16 vertical_phase0_uv;
1012	uint16 vertical_phase1_uv;
1013	// (0x24) HORZ_PH - horizontal phase
1014	uint16 horizontal_phase_rgb;
1015	uint16 horizontal_phase_uv;
1016	// (0x28) INIT_PHS - initial phase shift
1017	uint32 initial_vertical_phase0_shift_rgb0 : 4;
1018	uint32 initial_vertical_phase1_shift_rgb0 : 4;
1019	uint32 initial_horizontal_phase_shift_rgb0 : 4;
1020	uint32 initial_vertical_phase0_shift_uv : 4;
1021	uint32 initial_vertical_phase1_shift_uv : 4;
1022	uint32 initial_horizontal_phase_shift_uv : 4;
1023	uint32 _reserved0 : 8;
1024	// (0x2c) DWINPOS - destination window position
1025	uint16 window_left;
1026	uint16 window_top;
1027	// (0x30) DWINSZ - destination window size
1028	uint16 window_width;
1029	uint16 window_height;
1030	// (0x34) SWIDTH - source width
1031	uint16 source_width_rgb;
1032	uint16 source_width_uv;
1033	// (0x38) SWITDHSW - source width in 8 byte steps
1034	uint16 source_bytes_per_row_rgb;
1035	uint16 source_bytes_per_row_uv;
1036	uint16 source_height_rgb;
1037	uint16 source_height_uv;
1038	overlay_scale scale_rgb;
1039	overlay_scale scale_uv;
1040	// (0x48) OCLRC0 - overlay color correction 0
1041	uint32 brightness_correction : 8;		// signed, -128 to 127
1042	uint32 _reserved1 : 10;
1043	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
1044	uint32 _reserved2 : 5;
1045	// (0x4c) OCLRC1 - overlay color correction 1
1046	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
1047	uint32 _reserved3 : 6;
1048	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
1049	uint32 _reserved4 : 5;
1050	// (0x50) DCLRKV - destination color key value
1051	uint32 color_key_blue : 8;
1052	uint32 color_key_green : 8;
1053	uint32 color_key_red : 8;
1054	uint32 _reserved5 : 8;
1055	// (0x54) DCLRKM - destination color key mask
1056	uint32 color_key_mask_blue : 8;
1057	uint32 color_key_mask_green : 8;
1058	uint32 color_key_mask_red : 8;
1059	uint32 _reserved6 : 7;
1060	uint32 color_key_enabled : 1;
1061	// (0x58) SCHRKVH - source chroma key high value
1062	uint32 source_chroma_key_high_red : 8;
1063	uint32 source_chroma_key_high_blue : 8;
1064	uint32 source_chroma_key_high_green : 8;
1065	uint32 _reserved7 : 8;
1066	// (0x5c) SCHRKVL - source chroma key low value
1067	uint32 source_chroma_key_low_red : 8;
1068	uint32 source_chroma_key_low_blue : 8;
1069	uint32 source_chroma_key_low_green : 8;
1070	uint32 _reserved8 : 8;
1071	// (0x60) SCHRKEN - source chroma key enable
1072	uint32 _reserved9 : 24;
1073	uint32 source_chroma_key_red_enabled : 1;
1074	uint32 source_chroma_key_blue_enabled : 1;
1075	uint32 source_chroma_key_green_enabled : 1;
1076	uint32 _reserved10 : 5;
1077	// (0x64) OCONFIG - overlay configuration
1078	uint32 _reserved11 : 3;
1079	uint32 color_control_output_mode : 1;
1080	uint32 yuv_to_rgb_bypass : 1;
1081	uint32 _reserved12 : 11;
1082	uint32 gamma2_enabled : 1;
1083	uint32 _reserved13 : 1;
1084	uint32 select_pipe : 1;
1085	uint32 slot_time : 8;
1086	uint32 _reserved14 : 5;
1087	// (0x68) OCOMD - overlay command
1088	uint32 overlay_enabled : 1;
1089	uint32 active_field : 1;
1090	uint32 active_buffer : 2;
1091	uint32 test_mode : 1;
1092	uint32 buffer_field_mode : 1;
1093	uint32 _reserved15 : 1;
1094	uint32 tv_flip_field_enabled : 1;
1095	uint32 _reserved16 : 1;
1096	uint32 tv_flip_field_parity : 1;
1097	uint32 source_format : 4;
1098	uint32 ycbcr422_order : 2;
1099	uint32 _reserved18 : 1;
1100	uint32 mirroring_mode : 2;
1101	uint32 _reserved19 : 13;
1102
1103	uint32 _reserved20;
1104
1105	uint32 start_0y;
1106	uint32 start_1y;
1107	uint32 start_0u;
1108	uint32 start_0v;
1109	uint32 start_1u;
1110	uint32 start_1v;
1111	uint32 _reserved21[6];
1112#if 0
1113	// (0x70) AWINPOS - alpha blend window position
1114	uint32 awinpos;
1115	// (0x74) AWINSZ - alpha blend window size
1116	uint32 awinsz;
1117
1118	uint32 _reserved21[10];
1119#endif
1120
1121	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
1122	// the next two registers switch the usual Y/RGB vs. UV order)
1123	uint16 horizontal_scale_uv;
1124	uint16 horizontal_scale_rgb;
1125	// (0xa4) UVSCALEV - vertical downscale
1126	uint16 vertical_scale_uv;
1127	uint16 vertical_scale_rgb;
1128
1129	uint32 _reserved22[86];
1130
1131	// (0x200) polyphase filter coefficients
1132	uint16 vertical_coefficients_rgb[128];
1133	uint16 horizontal_coefficients_rgb[128];
1134
1135	uint32	_reserved23[64];
1136
1137	// (0x500)
1138	uint16 vertical_coefficients_uv[128];
1139	uint16 horizontal_coefficients_uv[128];
1140};
1141
1142// i965 overlay support is currently realized using its 3D hardware
1143#define INTEL_i965_OVERLAY_STATE_SIZE	36864
1144#define INTEL_i965_3D_CONTEXT_SIZE		32768
1145
1146inline bool
1147intel_uses_physical_overlay(intel_shared_info &info)
1148{
1149	return !info.device_type.InGroup(INTEL_GROUP_Gxx);
1150}
1151
1152
1153struct hardware_status {
1154	uint32	interrupt_status_register;
1155	uint32	_reserved0[3];
1156	void*	primary_ring_head_storage;
1157	uint32	_reserved1[3];
1158	void*	secondary_ring_0_head_storage;
1159	void*	secondary_ring_1_head_storage;
1160	uint32	_reserved2[2];
1161	void*	binning_head_storage;
1162	uint32	_reserved3[3];
1163	uint32	store[1008];
1164};
1165
1166#endif	/* INTEL_EXTREME_H */
1167