intel_extreme.h revision 84b7116d
1/*
2 * Copyright 2006-2015, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 *		Alexander von Gluck, kallisti5@unixzen.com
8 */
9#ifndef INTEL_EXTREME_H
10#define INTEL_EXTREME_H
11
12
13#include "lock.h"
14
15#include <Accelerant.h>
16#include <Drivers.h>
17#include <PCI.h>
18
19#include <edid.h>
20
21
22#define VENDOR_ID_INTEL			0x8086
23
24#define INTEL_FAMILY_MASK	0x00ff0000
25#define INTEL_GROUP_MASK	0x00fffff0
26#define INTEL_MODEL_MASK	0x00ffffff
27// families
28#define INTEL_FAMILY_7xx	0x00010000	// First Gen
29#define INTEL_FAMILY_8xx	0x00020000	// Second Gen
30#define INTEL_FAMILY_9xx	0x00040000	// Third Gen +
31#define INTEL_FAMILY_SER5	0x00080000	// Intel5 Series
32#define INTEL_FAMILY_POVR	0x00100000	// PowerVR (uugh)
33#define INTEL_FAMILY_SOC0	0x00200000  // Atom SOC
34// groups
35#define INTEL_GROUP_83x		(INTEL_FAMILY_8xx  | 0x0010)
36#define INTEL_GROUP_85x		(INTEL_FAMILY_8xx  | 0x0020)
37#define INTEL_GROUP_91x		(INTEL_FAMILY_9xx  | 0x0010)
38#define INTEL_GROUP_94x		(INTEL_FAMILY_9xx  | 0x0020)
39#define INTEL_GROUP_96x		(INTEL_FAMILY_9xx  | 0x0040)
40#define INTEL_GROUP_Gxx		(INTEL_FAMILY_9xx  | 0x0080)
41#define INTEL_GROUP_G4x		(INTEL_FAMILY_9xx  | 0x0100)
42#define INTEL_GROUP_IGD		(INTEL_FAMILY_9xx  | 0x0200)
43#define INTEL_GROUP_ILK		(INTEL_FAMILY_9xx  | 0x0400)  // IronLake
44#define INTEL_GROUP_SNB		(INTEL_FAMILY_SER5 | 0x0010)  // SandyBridge
45#define INTEL_GROUP_IVB		(INTEL_FAMILY_SER5 | 0x0020)  // IvyBridge
46#define INTEL_GROUP_HAS		(INTEL_FAMILY_SER5 | 0x0040)  // Haswell
47#define INTEL_GROUP_SLT		(INTEL_FAMILY_POVR | 0x0010)  // Saltwell
48#define INTEL_GROUP_FSM		(INTEL_FAMILY_POVR | 0x0020)  // Fu.Silvermont
49#define INTEL_GROUP_SLV		(INTEL_FAMILY_SOC0 | 0x0010)  // Silvermont
50#define INTEL_GROUP_AIR		(INTEL_FAMILY_SOC0 | 0x0020)  // Airmont
51#define INTEL_GROUP_GOL		(INTEL_FAMILY_SOC0 | 0x0040)  // Goldmont
52// models
53#define INTEL_TYPE_SERVER	0x0004
54#define INTEL_TYPE_MOBILE	0x0008
55#define INTEL_MODEL_915		(INTEL_GROUP_91x)
56#define INTEL_MODEL_915M	(INTEL_GROUP_91x | INTEL_TYPE_MOBILE)
57#define INTEL_MODEL_945		(INTEL_GROUP_94x)
58#define INTEL_MODEL_945M	(INTEL_GROUP_94x | INTEL_TYPE_MOBILE)
59#define INTEL_MODEL_965		(INTEL_GROUP_96x)
60#define INTEL_MODEL_965M	(INTEL_GROUP_96x | INTEL_TYPE_MOBILE)
61#define INTEL_MODEL_G33		(INTEL_GROUP_Gxx)
62#define INTEL_MODEL_G45		(INTEL_GROUP_G4x)
63#define INTEL_MODEL_GM45	(INTEL_GROUP_G4x | INTEL_TYPE_MOBILE)
64#define INTEL_MODEL_IGDG	(INTEL_GROUP_IGD)
65#define INTEL_MODEL_IGDGM	(INTEL_GROUP_IGD | INTEL_TYPE_MOBILE)
66#define INTEL_MODEL_ILKG	(INTEL_GROUP_ILK)
67#define INTEL_MODEL_ILKGM	(INTEL_GROUP_ILK | INTEL_TYPE_MOBILE)
68#define INTEL_MODEL_SNBG	(INTEL_GROUP_SNB)
69#define INTEL_MODEL_SNBGM	(INTEL_GROUP_SNB | INTEL_TYPE_MOBILE)
70#define INTEL_MODEL_SNBGS	(INTEL_GROUP_SNB | INTEL_TYPE_SERVER)
71#define INTEL_MODEL_IVBG	(INTEL_GROUP_IVB)
72#define INTEL_MODEL_IVBGM	(INTEL_GROUP_IVB | INTEL_TYPE_MOBILE)
73#define INTEL_MODEL_IVBGS	(INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
74#define INTEL_MODEL_HAS		(INTEL_GROUP_HAS)
75#define INTEL_MODEL_HASM	(INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
76#define INTEL_MODEL_VLV		(INTEL_GROUP_SLV)
77#define INTEL_MODEL_VLVM	(INTEL_GROUP_SLV | INTEL_TYPE_MOBILE)
78
79// ValleyView MMIO offset
80#define VLV_DISPLAY_BASE		0x180000
81
82#define DEVICE_NAME				"intel_extreme"
83#define INTEL_ACCELERANT_NAME	"intel_extreme.accelerant"
84
85// We encode the register block into the value and extract/translate it when
86// actually accessing.
87#define REGISTER_BLOCK_COUNT				6
88#define REGISTER_BLOCK_SHIFT				24
89#define REGISTER_BLOCK_MASK					0xff000000
90#define REGISTER_REGISTER_MASK				0x00ffffff
91#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
92#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
93
94#define REGS_FLAT							(0 << REGISTER_BLOCK_SHIFT)
95#define REGS_NORTH_SHARED					(1 << REGISTER_BLOCK_SHIFT)
96#define REGS_NORTH_PIPE_AND_PORT			(2 << REGISTER_BLOCK_SHIFT)
97#define REGS_NORTH_PLANE_CONTROL			(3 << REGISTER_BLOCK_SHIFT)
98#define REGS_SOUTH_SHARED					(4 << REGISTER_BLOCK_SHIFT)
99#define REGS_SOUTH_TRANSCODER_PORT			(5 << REGISTER_BLOCK_SHIFT)
100
101// register blocks for (G)MCH/ICH based platforms
102#define MCH_SHARED_REGISTER_BASE						0x00000
103#define MCH_PIPE_AND_PORT_REGISTER_BASE					0x60000
104#define MCH_PLANE_CONTROL_REGISTER_BASE					0x70000
105#define ICH_SHARED_REGISTER_BASE						0x00000
106#define ICH_PORT_REGISTER_BASE							0x60000
107
108// PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based
109// setup to a PCH based one, that means anything that used to communicate via
110// (G)MCH registers needs to use different ones on PCH based platforms
111// (Ironlake, SandyBridge, IvyBridge, Some Haswell).
112#define PCH_NORTH_SHARED_REGISTER_BASE					0x40000
113#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE			0x60000
114#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE			0x70000
115#define PCH_SOUTH_SHARED_REGISTER_BASE					0xc0000
116#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE		0xe0000
117
118
119struct DeviceType {
120	uint32			type;
121
122	DeviceType(int t)
123	{
124		type = t;
125	}
126
127	DeviceType& operator=(int t)
128	{
129		type = t;
130		return *this;
131	}
132
133	bool InFamily(uint32 family) const
134	{
135		return (type & INTEL_FAMILY_MASK) == family;
136	}
137
138	bool InGroup(uint32 group) const
139	{
140		return (type & INTEL_GROUP_MASK) == group;
141	}
142
143	bool IsModel(uint32 model) const
144	{
145		return (type & INTEL_MODEL_MASK) == model;
146	}
147
148	bool IsMobile() const
149	{
150		return (type & INTEL_MODEL_MASK) == INTEL_TYPE_MOBILE;
151	}
152
153	bool SupportsHDMI() const
154	{
155		return InGroup(INTEL_GROUP_G4x) || InGroup(INTEL_GROUP_ILK)
156			|| InFamily(INTEL_FAMILY_SER5) || InFamily(INTEL_FAMILY_SOC0);
157	}
158
159	bool HasPlatformControlHub() const
160	{
161		return InGroup(INTEL_GROUP_ILK) || InGroup(INTEL_GROUP_SNB)
162			|| InGroup(INTEL_GROUP_IVB) || InGroup(INTEL_GROUP_HAS);
163	}
164};
165
166// info about PLL on graphics card
167struct pll_info {
168	uint32			reference_frequency;
169	uint32			max_frequency;
170	uint32			min_frequency;
171	uint32			divisor_register;
172};
173
174struct ring_buffer {
175	struct lock		lock;
176	uint32			register_base;
177	uint32			offset;
178	uint32			size;
179	uint32			position;
180	uint32			space_left;
181	uint8*			base;
182};
183
184struct overlay_registers;
185
186struct intel_shared_info {
187	area_id			mode_list_area;		// area containing display mode list
188	uint32			mode_count;
189
190	display_mode	current_mode;
191	uint32			bytes_per_row;
192	uint32			bits_per_pixel;
193	uint32			dpms_mode;
194
195	area_id			registers_area;			// area of memory mapped registers
196	uint32			register_blocks[REGISTER_BLOCK_COUNT];
197
198	uint8*			status_page;
199	phys_addr_t		physical_status_page;
200	uint8*			graphics_memory;
201	phys_addr_t		physical_graphics_memory;
202	uint32			graphics_memory_size;
203
204	addr_t			frame_buffer;
205	uint32			frame_buffer_offset;
206
207	bool			got_vbt;
208	bool			single_head_locked;
209
210	struct lock		accelerant_lock;
211	struct lock		engine_lock;
212
213	ring_buffer		primary_ring_buffer;
214
215	int32			overlay_channel_used;
216	bool			overlay_active;
217	uintptr_t		overlay_token;
218	phys_addr_t		physical_overlay_registers;
219	uint32			overlay_offset;
220
221	bool			hardware_cursor_enabled;
222	sem_id			vblank_sem;
223
224	uint8*			cursor_memory;
225	phys_addr_t		physical_cursor_memory;
226	uint32			cursor_buffer_offset;
227	uint32			cursor_format;
228	bool			cursor_visible;
229	uint16			cursor_hot_x;
230	uint16			cursor_hot_y;
231
232	DeviceType		device_type;
233	char			device_identifier[32];
234	struct pll_info	pll_info;
235
236	edid1_info		vesa_edid_info;
237	bool			has_vesa_edid_info;
238};
239
240//----------------- ioctl() interface ----------------
241
242// magic code for ioctls
243#define INTEL_PRIVATE_DATA_MAGIC		'itic'
244
245// list ioctls
246enum {
247	INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
248
249	INTEL_GET_DEVICE_NAME,
250	INTEL_ALLOCATE_GRAPHICS_MEMORY,
251	INTEL_FREE_GRAPHICS_MEMORY
252};
253
254// retrieve the area_id of the kernel/accelerant shared info
255struct intel_get_private_data {
256	uint32	magic;				// magic number
257	area_id	shared_info_area;
258};
259
260// allocate graphics memory
261struct intel_allocate_graphics_memory {
262	uint32	magic;
263	uint32	size;
264	uint32	alignment;
265	uint32	flags;
266	addr_t	buffer_base;
267};
268
269// free graphics memory
270struct intel_free_graphics_memory {
271	uint32 	magic;
272	addr_t	buffer_base;
273};
274
275//----------------------------------------------------------
276// Register definitions, taken from X driver
277
278// PCI bridge memory management
279#define INTEL_GRAPHICS_MEMORY_CONTROL	0x52
280	// GGC - (G)MCH Graphics Control Register
281#define MEMORY_CONTROL_ENABLED			0x0004
282#define MEMORY_MASK						0x0001
283#define STOLEN_MEMORY_MASK				0x00f0
284#define i965_GTT_MASK					0x000e
285#define G33_GTT_MASK					0x0300
286#define G4X_GTT_MASK					0x0f00	// GGMS (GSM Memory Size) mask
287
288// models i830 and up
289#define i830_LOCAL_MEMORY_ONLY			0x10
290#define i830_STOLEN_512K				0x20
291#define i830_STOLEN_1M					0x30
292#define i830_STOLEN_8M					0x40
293#define i830_FRAME_BUFFER_64M			0x01
294#define i830_FRAME_BUFFER_128M			0x00
295
296// models i855 and up
297#define i855_STOLEN_MEMORY_1M			0x10
298#define i855_STOLEN_MEMORY_4M			0x20
299#define i855_STOLEN_MEMORY_8M			0x30
300#define i855_STOLEN_MEMORY_16M			0x40
301#define i855_STOLEN_MEMORY_32M			0x50
302#define i855_STOLEN_MEMORY_48M			0x60
303#define i855_STOLEN_MEMORY_64M			0x70
304#define i855_STOLEN_MEMORY_128M			0x80
305#define i855_STOLEN_MEMORY_256M			0x90
306
307#define G4X_STOLEN_MEMORY_96MB			0xa0	// GMS - Graphics Mode Select
308#define G4X_STOLEN_MEMORY_160MB			0xb0
309#define G4X_STOLEN_MEMORY_224MB			0xc0
310#define G4X_STOLEN_MEMORY_352MB			0xd0
311
312// SandyBridge (SNB)
313#define SNB_GRAPHICS_MEMORY_CONTROL		0x50
314
315#define SNB_STOLEN_MEMORY_MASK			0xf8
316#define SNB_STOLEN_MEMORY_32MB			(1 << 3)
317#define SNB_STOLEN_MEMORY_64MB			(2 << 3)
318#define SNB_STOLEN_MEMORY_96MB			(3 << 3)
319#define SNB_STOLEN_MEMORY_128MB			(4 << 3)
320#define SNB_STOLEN_MEMORY_160MB			(5 << 3)
321#define SNB_STOLEN_MEMORY_192MB			(6 << 3)
322#define SNB_STOLEN_MEMORY_224MB			(7 << 3)
323#define SNB_STOLEN_MEMORY_256MB			(8 << 3)
324#define SNB_STOLEN_MEMORY_288MB			(9 << 3)
325#define SNB_STOLEN_MEMORY_320MB			(10 << 3)
326#define SNB_STOLEN_MEMORY_352MB			(11 << 3)
327#define SNB_STOLEN_MEMORY_384MB			(12 << 3)
328#define SNB_STOLEN_MEMORY_416MB			(13 << 3)
329#define SNB_STOLEN_MEMORY_448MB			(14 << 3)
330#define SNB_STOLEN_MEMORY_480MB			(15 << 3)
331#define SNB_STOLEN_MEMORY_512MB			(16 << 3)
332
333#define SNB_GTT_SIZE_MASK				(3 << 8)
334#define SNB_GTT_SIZE_NONE				(0 << 8)
335#define SNB_GTT_SIZE_1MB				(1 << 8)
336#define SNB_GTT_SIZE_2MB				(2 << 8)
337
338// graphics page translation table
339#define INTEL_PAGE_TABLE_CONTROL		0x02020
340#define PAGE_TABLE_ENABLED				0x00000001
341#define INTEL_PAGE_TABLE_ERROR			0x02024
342#define INTEL_HARDWARE_STATUS_PAGE		0x02080
343#define i915_GTT_BASE					0x1c
344#define i830_GTT_BASE					0x10000	// (- 0x2ffff)
345#define i830_GTT_SIZE					0x20000
346#define i965_GTT_BASE					0x80000	// (- 0xfffff)
347#define i965_GTT_SIZE					0x80000
348#define i965_GTT_128K					(2 << 1)
349#define i965_GTT_256K					(1 << 1)
350#define i965_GTT_512K					(0 << 1)
351#define G33_GTT_1M						(1 << 8)
352#define G33_GTT_2M						(2 << 8)
353#define G4X_GTT_NONE					0x000	// GGMS - GSM Memory Size
354#define G4X_GTT_1M_NO_IVT				0x100	// no Intel Virtualization Tech.
355#define G4X_GTT_2M_NO_IVT				0x300
356#define G4X_GTT_2M_IVT					0x900	// with Intel Virt. Tech.
357#define G4X_GTT_3M_IVT					0xa00
358#define G4X_GTT_4M_IVT					0xb00
359
360
361#define GTT_ENTRY_VALID					0x01
362#define GTT_ENTRY_LOCAL_MEMORY			0x02
363#define GTT_PAGE_SHIFT					12
364
365
366// ring buffer
367#define INTEL_PRIMARY_RING_BUFFER		0x02030
368#define INTEL_SECONDARY_RING_BUFFER_0	0x02100
369#define INTEL_SECONDARY_RING_BUFFER_1	0x02110
370// offsets for the ring buffer base registers above
371#define RING_BUFFER_TAIL				0x0
372#define RING_BUFFER_HEAD				0x4
373#define RING_BUFFER_START				0x8
374#define RING_BUFFER_CONTROL				0xc
375#define INTEL_RING_BUFFER_SIZE_MASK		0x001ff000
376#define INTEL_RING_BUFFER_HEAD_MASK		0x001ffffc
377#define INTEL_RING_BUFFER_ENABLED		1
378
379// interrupts
380#define INTEL_INTERRUPT_ENABLED			0x020a0
381#define INTEL_INTERRUPT_IDENTITY		0x020a4
382#define INTEL_INTERRUPT_MASK			0x020a8
383#define INTEL_INTERRUPT_STATUS			0x020ac
384#define INTERRUPT_VBLANK_PIPEA			(1 << 7)
385#define INTERRUPT_VBLANK_PIPEB			(1 << 5)
386
387// PCH interrupts
388#define PCH_INTERRUPT_STATUS			0x44000
389#define PCH_INTERRUPT_MASK				0x44004
390#define PCH_INTERRUPT_IDENTITY			0x44008
391#define PCH_INTERRUPT_ENABLED			0x4400c
392#define PCH_INTERRUPT_VBLANK_PIPEA		(1 << 0)
393#define PCH_INTERRUPT_VBLANK_PIPEB		(1 << 5)
394#define PCH_INTERRUPT_VBLANK_PIPEC		(1 << 10)
395
396#define PCH_INTERRUPT_VBLANK_PIPEA_SNB		(1 << 7)
397#define PCH_INTERRUPT_VBLANK_PIPEB_SNB		(1 << 15)
398
399// display ports
400#define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
401#define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
402#define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
403#define DISPLAY_MONITOR_MODE_MASK		(3UL << 10)
404#define DISPLAY_MONITOR_ON				0
405#define DISPLAY_MONITOR_SUSPEND			(1UL << 10)
406#define DISPLAY_MONITOR_STAND_BY		(2UL << 10)
407#define DISPLAY_MONITOR_OFF				(3UL << 10)
408#define DISPLAY_MONITOR_POLARITY_MASK	(3UL << 3)
409#define DISPLAY_MONITOR_POSITIVE_HSYNC	(1UL << 3)
410#define DISPLAY_MONITOR_POSITIVE_VSYNC	(2UL << 3)
411#define LVDS_POST2_RATE_SLOW			14 // PLL Divisors
412#define LVDS_POST2_RATE_FAST			7
413#define LVDS_CLKB_POWER_MASK			(3 << 4)
414#define LVDS_CLKB_POWER_UP				(3 << 4)
415#define LVDS_PORT_EN					(1 << 31)
416#define LVDS_A0A2_CLKA_POWER_UP			(3 << 8)
417#define LVDS_PIPEB_SELECT				(1 << 30)
418#define LVDS_B0B3PAIRS_POWER_UP			(3 << 2)
419#define LVDS_PLL_MODE_LVDS				(2 << 26)
420#define LVDS_18BIT_DITHER				(1 << 25)
421
422// PLL flags
423#define DISPLAY_PLL_ENABLED				(1UL << 31)
424#define DISPLAY_PLL_2X_CLOCK			(1UL << 30)
425#define DISPLAY_PLL_SYNC_LOCK_ENABLED	(1UL << 29)
426#define DISPLAY_PLL_NO_VGA_CONTROL		(1UL << 28)
427#define DISPLAY_PLL_MODE_ANALOG			(1UL << 26)
428#define DISPLAY_PLL_DIVIDE_HIGH			(1UL << 24)
429#define DISPLAY_PLL_DIVIDE_4X			(1UL << 23)
430#define DISPLAY_PLL_POST1_DIVIDE_2		(1UL << 21)
431#define DISPLAY_PLL_POST1_DIVISOR_MASK	0x001f0000
432#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK	0x00ff0000
433#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK  0x00ff8000
434#define DISPLAY_PLL_POST1_DIVISOR_SHIFT	16
435#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT	15
436#define DISPLAY_PLL_DIVISOR_1			(1UL << 8)
437#define DISPLAY_PLL_N_DIVISOR_MASK		0x001f0000
438#define DISPLAY_PLL_IGD_N_DIVISOR_MASK	0x00ff0000
439#define DISPLAY_PLL_M1_DIVISOR_MASK		0x00001f00
440#define DISPLAY_PLL_M2_DIVISOR_MASK		0x0000001f
441#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK	0x000000ff
442#define DISPLAY_PLL_N_DIVISOR_SHIFT		16
443#define DISPLAY_PLL_M1_DIVISOR_SHIFT	8
444#define DISPLAY_PLL_M2_DIVISOR_SHIFT	0
445#define DISPLAY_PLL_PULSE_PHASE_SHIFT	9
446
447// display
448#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_SOUTH_TRANSCODER_PORT)
449#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_SOUTH_TRANSCODER_PORT)
450#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_SOUTH_TRANSCODER_PORT)
451#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_SOUTH_TRANSCODER_PORT)
452#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_SOUTH_TRANSCODER_PORT)
453#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_SOUTH_TRANSCODER_PORT)
454#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_SOUTH_TRANSCODER_PORT)
455#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_SOUTH_TRANSCODER_PORT)
456#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_SOUTH_TRANSCODER_PORT)
457#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_SOUTH_TRANSCODER_PORT)
458#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_SOUTH_TRANSCODER_PORT)
459#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_SOUTH_TRANSCODER_PORT)
460
461#define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
462#define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)
463
464#define INTEL_ANALOG_PORT				(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
465#define INTEL_DIGITAL_PORT_A			(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
466#define INTEL_DIGITAL_PORT_B			(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
467#define INTEL_DIGITAL_PORT_C			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
468#define INTEL_DIGITAL_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
469
470#define INTEL_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
471#define INTEL_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
472
473#define PCH_HDMI_PORT_B					(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
474#define PCH_HDMI_PORT_C					(0x1150 | REGS_SOUTH_TRANSCODER_PORT)
475#define PCH_HDMI_PORT_D					(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
476
477#define GEN4_HDMI_PORT_B				(0x1140 | REGS_NORTH_PIPE_AND_PORT)
478#define GEN4_HDMI_PORT_C				(0x1160 | REGS_NORTH_PIPE_AND_PORT)
479#define CHV_HDMI_PORT_D					(0x116C | REGS_NORTH_PIPE_AND_PORT)
480
481#define INTEL_DISPLAY_PORT_A			(0x4000 | REGS_NORTH_PIPE_AND_PORT)
482#define INTEL_DISPLAY_PORT_B			(0x4100 | REGS_NORTH_PIPE_AND_PORT)
483#define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_NORTH_PIPE_AND_PORT)
484#define INTEL_DISPLAY_PORT_D			(0x4300 | REGS_NORTH_PIPE_AND_PORT)
485
486// valid for both DVI/HDMI and DisplayPort
487#define PORT_DETECTED					(1 << 2)
488
489// planes
490#define INTEL_PIPE_BASE_REGISTER		(0x0000 | REGS_NORTH_PLANE_CONTROL)
491#define INTEL_PIPE_ENABLED				(1UL << 31)
492#define INTEL_PIPE_CONTROL				0x0008
493#define INTEL_PIPE_STATUS				0x0024
494#define INTEL_PIPE_OFFSET				0x1000
495#define INTEL_DISPLAY_A_PIPE_CONTROL	(0x0008	| REGS_NORTH_PLANE_CONTROL)
496#define INTEL_DISPLAY_B_PIPE_CONTROL	(0x1008 | REGS_NORTH_PLANE_CONTROL)
497#define INTEL_DISPLAY_A_PIPE_STATUS		(0x0024 | REGS_NORTH_PLANE_CONTROL)
498#define INTEL_DISPLAY_B_PIPE_STATUS		(0x1024 | REGS_NORTH_PLANE_CONTROL)
499
500#define DISPLAY_PIPE_VBLANK_ENABLED		(1UL << 17)
501#define DISPLAY_PIPE_VBLANK_STATUS		(1UL << 1)
502
503#define INTEL_DISPLAY_A_CONTROL			(0x0180 | REGS_NORTH_PLANE_CONTROL)
504#define INTEL_DISPLAY_A_BASE			(0x0184 | REGS_NORTH_PLANE_CONTROL)
505#define INTEL_DISPLAY_A_BYTES_PER_ROW	(0x0188 | REGS_NORTH_PLANE_CONTROL)
506#define INTEL_DISPLAY_A_POS				(0x018c | REGS_NORTH_PLANE_CONTROL)
507	// reserved on A
508#define INTEL_DISPLAY_A_PIPE_SIZE		(0x0190 | REGS_NORTH_PLANE_CONTROL)
509#define INTEL_DISPLAY_A_SURFACE			(0x019c | REGS_NORTH_PLANE_CONTROL)
510	// i965 and up only
511
512#define INTEL_DISPLAY_B_CONTROL			(0x1180 | REGS_NORTH_PLANE_CONTROL)
513#define INTEL_DISPLAY_B_BASE			(0x1184 | REGS_NORTH_PLANE_CONTROL)
514#define INTEL_DISPLAY_B_BYTES_PER_ROW	(0x1188 | REGS_NORTH_PLANE_CONTROL)
515#define INTEL_DISPLAY_B_POS				(0x118c | REGS_NORTH_PLANE_CONTROL)
516#define INTEL_DISPLAY_B_PIPE_SIZE		(0x1190 | REGS_NORTH_PLANE_CONTROL)
517#define INTEL_DISPLAY_B_SURFACE			(0x119c | REGS_NORTH_PLANE_CONTROL)
518	// i965 and up only
519
520#define DISPLAY_CONTROL_ENABLED			(1UL << 31)
521#define DISPLAY_CONTROL_GAMMA			(1UL << 30)
522#define DISPLAY_CONTROL_COLOR_MASK		(0x0fUL << 26)
523#define DISPLAY_CONTROL_CMAP8			(2UL << 26)
524#define DISPLAY_CONTROL_RGB15			(4UL << 26)
525#define DISPLAY_CONTROL_RGB16			(5UL << 26)
526#define DISPLAY_CONTROL_RGB32			(6UL << 26)
527
528// cursors
529#define INTEL_CURSOR_CONTROL			(0x0080 | REGS_NORTH_PLANE_CONTROL)
530#define INTEL_CURSOR_BASE				(0x0084 | REGS_NORTH_PLANE_CONTROL)
531#define INTEL_CURSOR_POSITION			(0x0088 | REGS_NORTH_PLANE_CONTROL)
532#define INTEL_CURSOR_PALETTE			(0x0090 | REGS_NORTH_PLANE_CONTROL)
533	// (- 0x009f)
534#define INTEL_CURSOR_SIZE				(0x00a0 | REGS_NORTH_PLANE_CONTROL)
535#define CURSOR_ENABLED					(1UL << 31)
536#define CURSOR_FORMAT_2_COLORS			(0UL << 24)
537#define CURSOR_FORMAT_3_COLORS			(1UL << 24)
538#define CURSOR_FORMAT_4_COLORS			(2UL << 24)
539#define CURSOR_FORMAT_ARGB				(4UL << 24)
540#define CURSOR_FORMAT_XRGB				(5UL << 24)
541#define CURSOR_POSITION_NEGATIVE		0x8000
542#define CURSOR_POSITION_MASK			0x3fff
543
544// palette registers
545#define INTEL_DISPLAY_A_PALETTE			(0xa000 | REGS_NORTH_SHARED)
546#define INTEL_DISPLAY_B_PALETTE			(0xa800 | REGS_NORTH_SHARED)
547
548// PLL registers
549#define INTEL_DISPLAY_A_PLL				(0x6014 | REGS_SOUTH_SHARED)
550#define INTEL_DISPLAY_B_PLL				(0x6018 | REGS_SOUTH_SHARED)
551#define CHV_DISPLAY_C_PLL				(0x6030 | REGS_SOUTH_SHARED)
552
553#define INTEL_DISPLAY_A_PLL_MULTIPLIER_DIVISOR	(INTEL_DISPLAY_A_PLL + 0x8)
554#define INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR	(INTEL_DISPLAY_B_PLL + 0x8)
555#define CHV_DISPLAY_C_PLL_MULTIPLIER_DIVISOR	(CHV_DISPLAY_C_PLL + 0xc)
556
557#define INTEL_DISPLAY_A_PLL_DIVISOR_0	(0x6040 | REGS_SOUTH_SHARED)
558#define INTEL_DISPLAY_A_PLL_DIVISOR_1	(0x6044 | REGS_SOUTH_SHARED)
559#define INTEL_DISPLAY_B_PLL_DIVISOR_0	(0x6048 | REGS_SOUTH_SHARED)
560#define INTEL_DISPLAY_B_PLL_DIVISOR_1	(0x604c | REGS_SOUTH_SHARED)
561
562// i2c
563#define INTEL_I2C_IO_A					(0x5010 | REGS_SOUTH_SHARED)
564#define INTEL_I2C_IO_B					(0x5014 | REGS_SOUTH_SHARED)
565#define INTEL_I2C_IO_C					(0x5018 | REGS_SOUTH_SHARED)
566#define INTEL_I2C_IO_D					(0x501c | REGS_SOUTH_SHARED)
567#define INTEL_I2C_IO_E					(0x5020 | REGS_SOUTH_SHARED)
568#define INTEL_I2C_IO_F					(0x5024 | REGS_SOUTH_SHARED)
569#define INTEL_I2C_IO_G					(0x5028 | REGS_SOUTH_SHARED)
570#define INTEL_I2C_IO_H					(0x502c | REGS_SOUTH_SHARED)
571
572#define I2C_CLOCK_DIRECTION_MASK		(1 << 0)
573#define I2C_CLOCK_DIRECTION_OUT			(1 << 1)
574#define I2C_CLOCK_VALUE_MASK			(1 << 2)
575#define I2C_CLOCK_VALUE_OUT				(1 << 3)
576#define I2C_CLOCK_VALUE_IN				(1 << 4)
577#define I2C_DATA_DIRECTION_MASK			(1 << 8)
578#define I2C_DATA_DIRECTION_OUT			(1 << 9)
579#define I2C_DATA_VALUE_MASK				(1 << 10)
580#define I2C_DATA_VALUE_OUT				(1 << 11)
581#define I2C_DATA_VALUE_IN				(1 << 12)
582#define I2C_RESERVED					((1 << 13) | (1 << 5))
583
584// TODO: on IronLake this is in the north shared block at 0x41000
585#define INTEL_VGA_DISPLAY_CONTROL		(0x1400 | REGS_NORTH_PLANE_CONTROL)
586#define VGA_DISPLAY_DISABLED			(1UL << 31)
587
588// LVDS panel
589#define INTEL_PANEL_STATUS				0x61200
590#define PANEL_STATUS_POWER_ON			(1UL << 31)
591#define INTEL_PANEL_CONTROL				0x61204
592#define PANEL_CONTROL_POWER_TARGET_ON	(1UL << 0)
593#define INTEL_PANEL_FIT_CONTROL			0x61230
594#define INTEL_PANEL_FIT_RATIOS			0x61234
595
596// LVDS on IronLake and up
597#define PCH_PANEL_CONTROL				0xc7200
598#define PCH_PANEL_STATUS				0xc7204
599#define PANEL_REGISTER_UNLOCK			(0xabcd << 16)
600#define PCH_LVDS_DETECTED				(1 << 1)
601
602// ring buffer commands
603
604#define COMMAND_NOOP					0x00
605#define COMMAND_WAIT_FOR_EVENT			(0x03 << 23)
606#define COMMAND_WAIT_FOR_OVERLAY_FLIP	(1 << 16)
607
608#define COMMAND_FLUSH					(0x04 << 23)
609
610// overlay flip
611#define COMMAND_OVERLAY_FLIP			(0x11 << 23)
612#define COMMAND_OVERLAY_CONTINUE		(0 << 21)
613#define COMMAND_OVERLAY_ON				(1 << 21)
614#define COMMAND_OVERLAY_OFF				(2 << 21)
615#define OVERLAY_UPDATE_COEFFICIENTS		0x1
616
617// 2D acceleration
618#define XY_COMMAND_SOURCE_BLIT			0x54c00006
619#define XY_COMMAND_COLOR_BLIT			0x54000004
620#define XY_COMMAND_SETUP_MONO_PATTERN	0x44400007
621#define XY_COMMAND_SCANLINE_BLIT		0x49400001
622#define COMMAND_COLOR_BLIT				0x50000003
623#define COMMAND_BLIT_RGBA				0x00300000
624
625#define COMMAND_MODE_SOLID_PATTERN		0x80
626#define COMMAND_MODE_CMAP8				0x00
627#define COMMAND_MODE_RGB15				0x02
628#define COMMAND_MODE_RGB16				0x01
629#define COMMAND_MODE_RGB32				0x03
630
631// overlay
632#define INTEL_OVERLAY_UPDATE			0x30000
633#define INTEL_OVERLAY_TEST				0x30004
634#define INTEL_OVERLAY_STATUS			0x30008
635#define INTEL_OVERLAY_EXTENDED_STATUS	0x3000c
636#define INTEL_OVERLAY_GAMMA_5			0x30010
637#define INTEL_OVERLAY_GAMMA_4			0x30014
638#define INTEL_OVERLAY_GAMMA_3			0x30018
639#define INTEL_OVERLAY_GAMMA_2			0x3001c
640#define INTEL_OVERLAY_GAMMA_1			0x30020
641#define INTEL_OVERLAY_GAMMA_0			0x30024
642
643// FDI - Flexible Display Interface, the interface between the (CPU-internal)
644// GPU and the PCH display outputs. Proprietary interface, based on DisplayPort
645// though, so similar link training and all...
646// There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the
647// PCH for each display pipe.
648// FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to
649// transcoder B, so we have the same mapping as with the display pipes.
650#define PCH_FDI_RX_BASE_REGISTER		0xf0000
651#define PCH_FDI_RX_PIPE_OFFSET			0x01000
652
653#define PCH_FDI_RX_CONTROL				0x0c
654#define FDI_RX_CLOCK_MASK				(1 << 4)
655#define FDI_RX_CLOCK_RAW				(0 << 4)
656#define FDI_RX_CLOCK_PCD				(1 << 4)
657
658#define PCH_FDI_RX_TRANS_UNIT_SIZE_1	0x30
659#define PCH_FDI_RX_TRANS_UNIT_SIZE_2	0x38
660#define FDI_RX_TRANS_UNIT_SIZE(x)		((x - 1) << 25)
661#define FDI_RX_TRANS_UNIT_MASK			0x7e000000
662	// Transfer unit size 1 is the primary and fixed transfer unit size,
663	// TU size 2 is the lower power state transfer unit size when using dynamic
664	// refresh rates (we don't do that though).
665
666// CPU Panel Fitters - These are for IronLake and up and are the CPU internal
667// panel fitters.
668#define PCH_PANEL_FITTER_BASE_REGISTER	0x68000
669#define PCH_PANEL_FITTER_PIPE_OFFSET	0x00800
670
671#define PCH_PANEL_FITTER_WINDOW_POS		0x70
672#define PCH_PANEL_FITTER_WINDOW_SIZE	0x74
673#define PCH_PANEL_FITTER_CONTROL		0x80
674#define PCH_PANEL_FITTER_V_SCALE		0x84
675#define PCH_PANEL_FITTER_H_SCALE		0x90
676
677#define PANEL_FITTER_ENABLED			(1 << 31)
678#define PANEL_FITTER_FILTER_MASK		(3 << 23)
679
680struct overlay_scale {
681	uint32 _reserved0 : 3;
682	uint32 horizontal_scale_fraction : 12;
683	uint32 _reserved1 : 1;
684	uint32 horizontal_downscale_factor : 3;
685	uint32 _reserved2 : 1;
686	uint32 vertical_scale_fraction : 12;
687};
688
689#define OVERLAY_FORMAT_RGB15			0x2
690#define OVERLAY_FORMAT_RGB16			0x3
691#define OVERLAY_FORMAT_RGB32			0x1
692#define OVERLAY_FORMAT_YCbCr422			0x8
693#define OVERLAY_FORMAT_YCbCr411			0x9
694#define OVERLAY_FORMAT_YCbCr420			0xc
695
696#define OVERLAY_MIRROR_NORMAL			0x0
697#define OVERLAY_MIRROR_HORIZONTAL		0x1
698#define OVERLAY_MIRROR_VERTICAL			0x2
699
700// The real overlay registers are written to using an update buffer
701
702struct overlay_registers {
703	uint32 buffer_rgb0;
704	uint32 buffer_rgb1;
705	uint32 buffer_u0;
706	uint32 buffer_v0;
707	uint32 buffer_u1;
708	uint32 buffer_v1;
709	// (0x18) OSTRIDE - overlay stride
710	uint16 stride_rgb;
711	uint16 stride_uv;
712	// (0x1c) YRGB_VPH - Y/RGB vertical phase
713	uint16 vertical_phase0_rgb;
714	uint16 vertical_phase1_rgb;
715	// (0x20) UV_VPH - UV vertical phase
716	uint16 vertical_phase0_uv;
717	uint16 vertical_phase1_uv;
718	// (0x24) HORZ_PH - horizontal phase
719	uint16 horizontal_phase_rgb;
720	uint16 horizontal_phase_uv;
721	// (0x28) INIT_PHS - initial phase shift
722	uint32 initial_vertical_phase0_shift_rgb0 : 4;
723	uint32 initial_vertical_phase1_shift_rgb0 : 4;
724	uint32 initial_horizontal_phase_shift_rgb0 : 4;
725	uint32 initial_vertical_phase0_shift_uv : 4;
726	uint32 initial_vertical_phase1_shift_uv : 4;
727	uint32 initial_horizontal_phase_shift_uv : 4;
728	uint32 _reserved0 : 8;
729	// (0x2c) DWINPOS - destination window position
730	uint16 window_left;
731	uint16 window_top;
732	// (0x30) DWINSZ - destination window size
733	uint16 window_width;
734	uint16 window_height;
735	// (0x34) SWIDTH - source width
736	uint16 source_width_rgb;
737	uint16 source_width_uv;
738	// (0x38) SWITDHSW - source width in 8 byte steps
739	uint16 source_bytes_per_row_rgb;
740	uint16 source_bytes_per_row_uv;
741	uint16 source_height_rgb;
742	uint16 source_height_uv;
743	overlay_scale scale_rgb;
744	overlay_scale scale_uv;
745	// (0x48) OCLRC0 - overlay color correction 0
746	uint32 brightness_correction : 8;		// signed, -128 to 127
747	uint32 _reserved1 : 10;
748	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
749	uint32 _reserved2 : 5;
750	// (0x4c) OCLRC1 - overlay color correction 1
751	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
752	uint32 _reserved3 : 6;
753	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
754	uint32 _reserved4 : 5;
755	// (0x50) DCLRKV - destination color key value
756	uint32 color_key_blue : 8;
757	uint32 color_key_green : 8;
758	uint32 color_key_red : 8;
759	uint32 _reserved5 : 8;
760	// (0x54) DCLRKM - destination color key mask
761	uint32 color_key_mask_blue : 8;
762	uint32 color_key_mask_green : 8;
763	uint32 color_key_mask_red : 8;
764	uint32 _reserved6 : 7;
765	uint32 color_key_enabled : 1;
766	// (0x58) SCHRKVH - source chroma key high value
767	uint32 source_chroma_key_high_red : 8;
768	uint32 source_chroma_key_high_blue : 8;
769	uint32 source_chroma_key_high_green : 8;
770	uint32 _reserved7 : 8;
771	// (0x5c) SCHRKVL - source chroma key low value
772	uint32 source_chroma_key_low_red : 8;
773	uint32 source_chroma_key_low_blue : 8;
774	uint32 source_chroma_key_low_green : 8;
775	uint32 _reserved8 : 8;
776	// (0x60) SCHRKEN - source chroma key enable
777	uint32 _reserved9 : 24;
778	uint32 source_chroma_key_red_enabled : 1;
779	uint32 source_chroma_key_blue_enabled : 1;
780	uint32 source_chroma_key_green_enabled : 1;
781	uint32 _reserved10 : 5;
782	// (0x64) OCONFIG - overlay configuration
783	uint32 _reserved11 : 3;
784	uint32 color_control_output_mode : 1;
785	uint32 yuv_to_rgb_bypass : 1;
786	uint32 _reserved12 : 11;
787	uint32 gamma2_enabled : 1;
788	uint32 _reserved13 : 1;
789	uint32 select_pipe : 1;
790	uint32 slot_time : 8;
791	uint32 _reserved14 : 5;
792	// (0x68) OCOMD - overlay command
793	uint32 overlay_enabled : 1;
794	uint32 active_field : 1;
795	uint32 active_buffer : 2;
796	uint32 test_mode : 1;
797	uint32 buffer_field_mode : 1;
798	uint32 _reserved15 : 1;
799	uint32 tv_flip_field_enabled : 1;
800	uint32 _reserved16 : 1;
801	uint32 tv_flip_field_parity : 1;
802	uint32 source_format : 4;
803	uint32 ycbcr422_order : 2;
804	uint32 _reserved18 : 1;
805	uint32 mirroring_mode : 2;
806	uint32 _reserved19 : 13;
807
808	uint32 _reserved20;
809
810	uint32 start_0y;
811	uint32 start_1y;
812	uint32 start_0u;
813	uint32 start_0v;
814	uint32 start_1u;
815	uint32 start_1v;
816	uint32 _reserved21[6];
817#if 0
818	// (0x70) AWINPOS - alpha blend window position
819	uint32 awinpos;
820	// (0x74) AWINSZ - alpha blend window size
821	uint32 awinsz;
822
823	uint32 _reserved21[10];
824#endif
825
826	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
827	// the next two registers switch the usual Y/RGB vs. UV order)
828	uint16 horizontal_scale_uv;
829	uint16 horizontal_scale_rgb;
830	// (0xa4) UVSCALEV - vertical downscale
831	uint16 vertical_scale_uv;
832	uint16 vertical_scale_rgb;
833
834	uint32 _reserved22[86];
835
836	// (0x200) polyphase filter coefficients
837	uint16 vertical_coefficients_rgb[128];
838	uint16 horizontal_coefficients_rgb[128];
839
840	uint32	_reserved23[64];
841
842	// (0x500)
843	uint16 vertical_coefficients_uv[128];
844	uint16 horizontal_coefficients_uv[128];
845};
846
847// i965 overlay support is currently realized using its 3D hardware
848#define INTEL_i965_OVERLAY_STATE_SIZE	36864
849#define INTEL_i965_3D_CONTEXT_SIZE		32768
850
851inline bool
852intel_uses_physical_overlay(intel_shared_info &info)
853{
854	return !info.device_type.InGroup(INTEL_GROUP_Gxx);
855}
856
857
858struct hardware_status {
859	uint32	interrupt_status_register;
860	uint32	_reserved0[3];
861	void*	primary_ring_head_storage;
862	uint32	_reserved1[3];
863	void*	secondary_ring_0_head_storage;
864	void*	secondary_ring_1_head_storage;
865	uint32	_reserved2[2];
866	void*	binning_head_storage;
867	uint32	_reserved3[3];
868	uint32	store[1008];
869};
870
871#endif	/* INTEL_EXTREME_H */
872