intel_extreme.h revision 61fbdb06
1/*
2 * Copyright 2006-2015, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 *		Alexander von Gluck, kallisti5@unixzen.com
8 */
9#ifndef INTEL_EXTREME_H
10#define INTEL_EXTREME_H
11
12
13#include "lock.h"
14
15#include <Accelerant.h>
16#include <Drivers.h>
17#include <PCI.h>
18
19#include <edid.h>
20
21
22#define VENDOR_ID_INTEL			0x8086
23
24#define INTEL_FAMILY_MASK	0x00ff0000
25#define INTEL_GROUP_MASK	0x00fffff0
26#define INTEL_MODEL_MASK	0x00ffffff
27#define INTEL_TYPE_MASK		0x0000000f
28// families
29#define INTEL_FAMILY_7xx	0x00010000	// First Gen
30#define INTEL_FAMILY_8xx	0x00020000	// Second Gen
31#define INTEL_FAMILY_9xx	0x00040000	// Third Gen +
32#define INTEL_FAMILY_SER5	0x00080000	// Intel5 Series
33#define INTEL_FAMILY_POVR	0x00100000	// PowerVR (uugh)
34#define INTEL_FAMILY_SOC0	0x00200000  // Atom SOC
35// groups
36#define INTEL_GROUP_83x		(INTEL_FAMILY_8xx  | 0x0010)
37#define INTEL_GROUP_85x		(INTEL_FAMILY_8xx  | 0x0020)
38#define INTEL_GROUP_91x		(INTEL_FAMILY_9xx  | 0x0010)
39#define INTEL_GROUP_94x		(INTEL_FAMILY_9xx  | 0x0020)
40#define INTEL_GROUP_96x		(INTEL_FAMILY_9xx  | 0x0040)
41#define INTEL_GROUP_Gxx		(INTEL_FAMILY_9xx  | 0x0080)
42#define INTEL_GROUP_G4x		(INTEL_FAMILY_9xx  | 0x0100)
43#define INTEL_GROUP_IGD		(INTEL_FAMILY_9xx  | 0x0200)
44#define INTEL_GROUP_ILK		(INTEL_FAMILY_SER5 | 0x0010)  // IronLake
45#define INTEL_GROUP_SNB		(INTEL_FAMILY_SER5 | 0x0020)  // SandyBridge
46#define INTEL_GROUP_IVB		(INTEL_FAMILY_SER5 | 0x0040)  // IvyBridge
47#define INTEL_GROUP_HAS		(INTEL_FAMILY_SER5 | 0x0080)  // Haswell
48#define INTEL_GROUP_SLT		(INTEL_FAMILY_POVR | 0x0010)  // Saltwell
49#define INTEL_GROUP_FSM		(INTEL_FAMILY_POVR | 0x0020)  // Fu.Silvermont
50#define INTEL_GROUP_VLV		(INTEL_FAMILY_SOC0 | 0x0010)  // ValleyView
51#define INTEL_GROUP_CHV		(INTEL_FAMILY_SOC0 | 0x0020)  // CherryView
52#define INTEL_GROUP_BXT		(INTEL_FAMILY_SOC0 | 0x0040)  // Broxton
53// models
54#define INTEL_TYPE_SERVER	0x0004
55#define INTEL_TYPE_MOBILE	0x0008
56#define INTEL_MODEL_915		(INTEL_GROUP_91x)
57#define INTEL_MODEL_915M	(INTEL_GROUP_91x | INTEL_TYPE_MOBILE)
58#define INTEL_MODEL_945		(INTEL_GROUP_94x)
59#define INTEL_MODEL_945M	(INTEL_GROUP_94x | INTEL_TYPE_MOBILE)
60#define INTEL_MODEL_965		(INTEL_GROUP_96x)
61#define INTEL_MODEL_965M	(INTEL_GROUP_96x | INTEL_TYPE_MOBILE)
62#define INTEL_MODEL_G33		(INTEL_GROUP_Gxx)
63#define INTEL_MODEL_G45		(INTEL_GROUP_G4x)
64#define INTEL_MODEL_GM45	(INTEL_GROUP_G4x | INTEL_TYPE_MOBILE)
65#define INTEL_MODEL_IGDG	(INTEL_GROUP_IGD)
66#define INTEL_MODEL_IGDGM	(INTEL_GROUP_IGD | INTEL_TYPE_MOBILE)
67#define INTEL_MODEL_ILKG	(INTEL_GROUP_ILK)
68#define INTEL_MODEL_ILKGM	(INTEL_GROUP_ILK | INTEL_TYPE_MOBILE)
69#define INTEL_MODEL_SNBG	(INTEL_GROUP_SNB)
70#define INTEL_MODEL_SNBGM	(INTEL_GROUP_SNB | INTEL_TYPE_MOBILE)
71#define INTEL_MODEL_SNBGS	(INTEL_GROUP_SNB | INTEL_TYPE_SERVER)
72#define INTEL_MODEL_IVBG	(INTEL_GROUP_IVB)
73#define INTEL_MODEL_IVBGM	(INTEL_GROUP_IVB | INTEL_TYPE_MOBILE)
74#define INTEL_MODEL_IVBGS	(INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
75#define INTEL_MODEL_HAS		(INTEL_GROUP_HAS)
76#define INTEL_MODEL_HASM	(INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
77#define INTEL_MODEL_VLV		(INTEL_GROUP_VLV)
78#define INTEL_MODEL_VLVM	(INTEL_GROUP_VLV | INTEL_TYPE_MOBILE)
79
80// ValleyView MMIO offset
81#define VLV_DISPLAY_BASE		0x180000
82
83#define DEVICE_NAME				"intel_extreme"
84#define INTEL_ACCELERANT_NAME	"intel_extreme.accelerant"
85
86// We encode the register block into the value and extract/translate it when
87// actually accessing.
88#define REGISTER_BLOCK_COUNT				6
89#define REGISTER_BLOCK_SHIFT				24
90#define REGISTER_BLOCK_MASK					0xff000000
91#define REGISTER_REGISTER_MASK				0x00ffffff
92#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
93#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
94
95#define REGS_FLAT							(0 << REGISTER_BLOCK_SHIFT)
96#define REGS_NORTH_SHARED					(1 << REGISTER_BLOCK_SHIFT)
97#define REGS_NORTH_PIPE_AND_PORT			(2 << REGISTER_BLOCK_SHIFT)
98#define REGS_NORTH_PLANE_CONTROL			(3 << REGISTER_BLOCK_SHIFT)
99#define REGS_SOUTH_SHARED					(4 << REGISTER_BLOCK_SHIFT)
100#define REGS_SOUTH_TRANSCODER_PORT			(5 << REGISTER_BLOCK_SHIFT)
101
102// register blocks for (G)MCH/ICH based platforms
103#define MCH_SHARED_REGISTER_BASE						0x00000
104#define MCH_PIPE_AND_PORT_REGISTER_BASE					0x60000
105#define MCH_PLANE_CONTROL_REGISTER_BASE					0x70000
106#define ICH_SHARED_REGISTER_BASE						0x00000
107#define ICH_PORT_REGISTER_BASE							0x60000
108
109// PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based
110// setup to a PCH based one, that means anything that used to communicate via
111// (G)MCH registers needs to use different ones on PCH based platforms
112// (Ironlake, SandyBridge, IvyBridge, Some Haswell).
113#define PCH_NORTH_SHARED_REGISTER_BASE					0x40000
114#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE			0x60000
115#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE			0x70000
116#define PCH_SOUTH_SHARED_REGISTER_BASE					0xc0000
117#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE		0xe0000
118
119
120struct DeviceType {
121	uint32			type;
122
123	DeviceType(int t)
124	{
125		type = t;
126	}
127
128	DeviceType& operator=(int t)
129	{
130		type = t;
131		return *this;
132	}
133
134	bool InFamily(uint32 family) const
135	{
136		return (type & INTEL_FAMILY_MASK) == family;
137	}
138
139	bool InGroup(uint32 group) const
140	{
141		return (type & INTEL_GROUP_MASK) == group;
142	}
143
144	bool IsModel(uint32 model) const
145	{
146		return (type & INTEL_MODEL_MASK) == model;
147	}
148
149	bool IsMobile() const
150	{
151		return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE;
152	}
153
154	bool SupportsHDMI() const
155	{
156		return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5)
157			|| InFamily(INTEL_FAMILY_SOC0);
158	}
159
160	bool HasPlatformControlHub() const
161	{
162		return InFamily(INTEL_FAMILY_SER5);
163	}
164
165	int Generation() const
166	{
167		if (InFamily(INTEL_FAMILY_7xx))
168			return 1;
169		if (InFamily(INTEL_FAMILY_8xx))
170			return 2;
171		if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
172				|| IsModel(INTEL_MODEL_G33))
173			return 3;
174		if (InFamily(INTEL_FAMILY_9xx))
175			return 4;
176		if (InGroup(INTEL_GROUP_ILK))
177			return 5;
178		if (InGroup(INTEL_GROUP_SNB))
179			return 6;
180		if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV))
181			return 7;
182		if (InGroup(INTEL_GROUP_CHV))
183			return 8;
184		if (InGroup(INTEL_GROUP_BXT))
185			return 9;
186
187		// Generation 0 means somethins is wrong :-)
188		return 0;
189	}
190};
191
192// info about PLL on graphics card
193struct pll_info {
194	uint32			reference_frequency;
195	uint32			max_frequency;
196	uint32			min_frequency;
197	uint32			divisor_register;
198};
199
200struct ring_buffer {
201	struct lock		lock;
202	uint32			register_base;
203	uint32			offset;
204	uint32			size;
205	uint32			position;
206	uint32			space_left;
207	uint8*			base;
208};
209
210struct overlay_registers;
211
212struct intel_shared_info {
213	area_id			mode_list_area;		// area containing display mode list
214	uint32			mode_count;
215
216	display_mode	current_mode;
217	uint32			bytes_per_row;
218	uint32			bits_per_pixel;
219	uint32			dpms_mode;
220
221	area_id			registers_area;			// area of memory mapped registers
222	uint32			register_blocks[REGISTER_BLOCK_COUNT];
223
224	uint8*			status_page;
225	phys_addr_t		physical_status_page;
226	uint8*			graphics_memory;
227	phys_addr_t		physical_graphics_memory;
228	uint32			graphics_memory_size;
229
230	addr_t			frame_buffer;
231	uint32			frame_buffer_offset;
232
233	bool			got_vbt;
234	bool			single_head_locked;
235
236	struct lock		accelerant_lock;
237	struct lock		engine_lock;
238
239	ring_buffer		primary_ring_buffer;
240
241	int32			overlay_channel_used;
242	bool			overlay_active;
243	uintptr_t		overlay_token;
244	phys_addr_t		physical_overlay_registers;
245	uint32			overlay_offset;
246
247	bool			hardware_cursor_enabled;
248	sem_id			vblank_sem;
249
250	uint8*			cursor_memory;
251	phys_addr_t		physical_cursor_memory;
252	uint32			cursor_buffer_offset;
253	uint32			cursor_format;
254	bool			cursor_visible;
255	uint16			cursor_hot_x;
256	uint16			cursor_hot_y;
257
258	DeviceType		device_type;
259	char			device_identifier[32];
260	struct pll_info	pll_info;
261
262	edid1_info		vesa_edid_info;
263	bool			has_vesa_edid_info;
264};
265
266//----------------- ioctl() interface ----------------
267
268// magic code for ioctls
269#define INTEL_PRIVATE_DATA_MAGIC		'itic'
270
271// list ioctls
272enum {
273	INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
274
275	INTEL_GET_DEVICE_NAME,
276	INTEL_ALLOCATE_GRAPHICS_MEMORY,
277	INTEL_FREE_GRAPHICS_MEMORY
278};
279
280// retrieve the area_id of the kernel/accelerant shared info
281struct intel_get_private_data {
282	uint32	magic;				// magic number
283	area_id	shared_info_area;
284};
285
286// allocate graphics memory
287struct intel_allocate_graphics_memory {
288	uint32	magic;
289	uint32	size;
290	uint32	alignment;
291	uint32	flags;
292	addr_t	buffer_base;
293};
294
295// free graphics memory
296struct intel_free_graphics_memory {
297	uint32 	magic;
298	addr_t	buffer_base;
299};
300
301//----------------------------------------------------------
302// Register definitions, taken from X driver
303
304// PCI bridge memory management
305#define INTEL_GRAPHICS_MEMORY_CONTROL	0x52		// i830+
306
307	// GGC - (G)MCH Graphics Control Register
308#define MEMORY_CONTROL_ENABLED			0x0004
309#define MEMORY_MASK						0x0001
310#define STOLEN_MEMORY_MASK				0x00f0
311#define i965_GTT_MASK					0x000e
312#define G33_GTT_MASK					0x0300
313#define G4X_GTT_MASK					0x0f00	// GGMS (GSM Memory Size) mask
314
315// models i830 and up
316#define i830_LOCAL_MEMORY_ONLY			0x10
317#define i830_STOLEN_512K				0x20
318#define i830_STOLEN_1M					0x30
319#define i830_STOLEN_8M					0x40
320#define i830_FRAME_BUFFER_64M			0x01
321#define i830_FRAME_BUFFER_128M			0x00
322
323// models i855 and up
324#define i855_STOLEN_MEMORY_1M			0x10
325#define i855_STOLEN_MEMORY_4M			0x20
326#define i855_STOLEN_MEMORY_8M			0x30
327#define i855_STOLEN_MEMORY_16M			0x40
328#define i855_STOLEN_MEMORY_32M			0x50
329#define i855_STOLEN_MEMORY_48M			0x60
330#define i855_STOLEN_MEMORY_64M			0x70
331#define i855_STOLEN_MEMORY_128M			0x80
332#define i855_STOLEN_MEMORY_256M			0x90
333
334#define G4X_STOLEN_MEMORY_96MB			0xa0	// GMS - Graphics Mode Select
335#define G4X_STOLEN_MEMORY_160MB			0xb0
336#define G4X_STOLEN_MEMORY_224MB			0xc0
337#define G4X_STOLEN_MEMORY_352MB			0xd0
338
339// SandyBridge (SNB)
340
341#define SNB_GRAPHICS_MEMORY_CONTROL		0x50
342
343#define SNB_STOLEN_MEMORY_MASK			0xf8
344#define SNB_STOLEN_MEMORY_32MB			(1 << 3)
345#define SNB_STOLEN_MEMORY_64MB			(2 << 3)
346#define SNB_STOLEN_MEMORY_96MB			(3 << 3)
347#define SNB_STOLEN_MEMORY_128MB			(4 << 3)
348#define SNB_STOLEN_MEMORY_160MB			(5 << 3)
349#define SNB_STOLEN_MEMORY_192MB			(6 << 3)
350#define SNB_STOLEN_MEMORY_224MB			(7 << 3)
351#define SNB_STOLEN_MEMORY_256MB			(8 << 3)
352#define SNB_STOLEN_MEMORY_288MB			(9 << 3)
353#define SNB_STOLEN_MEMORY_320MB			(10 << 3)
354#define SNB_STOLEN_MEMORY_352MB			(11 << 3)
355#define SNB_STOLEN_MEMORY_384MB			(12 << 3)
356#define SNB_STOLEN_MEMORY_416MB			(13 << 3)
357#define SNB_STOLEN_MEMORY_448MB			(14 << 3)
358#define SNB_STOLEN_MEMORY_480MB			(15 << 3)
359#define SNB_STOLEN_MEMORY_512MB			(16 << 3)
360
361#define SNB_GTT_SIZE_MASK				(3 << 8)
362#define SNB_GTT_SIZE_NONE				(0 << 8)
363#define SNB_GTT_SIZE_1MB				(1 << 8)
364#define SNB_GTT_SIZE_2MB				(2 << 8)
365
366// graphics page translation table
367#define INTEL_PAGE_TABLE_CONTROL		0x02020
368#define PAGE_TABLE_ENABLED				0x00000001
369#define INTEL_PAGE_TABLE_ERROR			0x02024
370#define INTEL_HARDWARE_STATUS_PAGE		0x02080
371#define i915_GTT_BASE					0x1c
372#define i830_GTT_BASE					0x10000	// (- 0x2ffff)
373#define i830_GTT_SIZE					0x20000
374#define i965_GTT_BASE					0x80000	// (- 0xfffff)
375#define i965_GTT_SIZE					0x80000
376#define i965_GTT_128K					(2 << 1)
377#define i965_GTT_256K					(1 << 1)
378#define i965_GTT_512K					(0 << 1)
379#define G33_GTT_1M						(1 << 8)
380#define G33_GTT_2M						(2 << 8)
381#define G4X_GTT_NONE					0x000	// GGMS - GSM Memory Size
382#define G4X_GTT_1M_NO_IVT				0x100	// no Intel Virtualization Tech.
383#define G4X_GTT_2M_NO_IVT				0x300
384#define G4X_GTT_2M_IVT					0x900	// with Intel Virt. Tech.
385#define G4X_GTT_3M_IVT					0xa00
386#define G4X_GTT_4M_IVT					0xb00
387
388
389#define GTT_ENTRY_VALID					0x01
390#define GTT_ENTRY_LOCAL_MEMORY			0x02
391#define GTT_PAGE_SHIFT					12
392
393
394// ring buffer
395#define INTEL_PRIMARY_RING_BUFFER		0x02030
396#define INTEL_SECONDARY_RING_BUFFER_0	0x02100
397#define INTEL_SECONDARY_RING_BUFFER_1	0x02110
398// offsets for the ring buffer base registers above
399#define RING_BUFFER_TAIL				0x0
400#define RING_BUFFER_HEAD				0x4
401#define RING_BUFFER_START				0x8
402#define RING_BUFFER_CONTROL				0xc
403#define INTEL_RING_BUFFER_SIZE_MASK		0x001ff000
404#define INTEL_RING_BUFFER_HEAD_MASK		0x001ffffc
405#define INTEL_RING_BUFFER_ENABLED		1
406
407// interrupts
408#define INTEL_INTERRUPT_ENABLED			0x020a0
409#define INTEL_INTERRUPT_IDENTITY		0x020a4
410#define INTEL_INTERRUPT_MASK			0x020a8
411#define INTEL_INTERRUPT_STATUS			0x020ac
412#define INTERRUPT_VBLANK_PIPEA			(1 << 7)
413#define INTERRUPT_VBLANK_PIPEB			(1 << 5)
414
415// PCH interrupts
416#define PCH_INTERRUPT_STATUS			0x44000
417#define PCH_INTERRUPT_MASK				0x44004
418#define PCH_INTERRUPT_IDENTITY			0x44008
419#define PCH_INTERRUPT_ENABLED			0x4400c
420#define PCH_INTERRUPT_VBLANK_PIPEA		(1 << 0)
421#define PCH_INTERRUPT_VBLANK_PIPEB		(1 << 5)
422#define PCH_INTERRUPT_VBLANK_PIPEC		(1 << 10)
423
424#define PCH_INTERRUPT_VBLANK_PIPEA_SNB		(1 << 7)
425#define PCH_INTERRUPT_VBLANK_PIPEB_SNB		(1 << 15)
426
427// graphics port control
428#define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
429#define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
430#define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
431#define DISPLAY_MONITOR_MODE_MASK		(3UL << 10)
432#define DISPLAY_MONITOR_ON				0
433#define DISPLAY_MONITOR_SUSPEND			(1UL << 10)
434#define DISPLAY_MONITOR_STAND_BY		(2UL << 10)
435#define DISPLAY_MONITOR_OFF				(3UL << 10)
436#define DISPLAY_MONITOR_POLARITY_MASK	(3UL << 3)
437#define DISPLAY_MONITOR_POSITIVE_HSYNC	(1UL << 3)
438#define DISPLAY_MONITOR_POSITIVE_VSYNC	(2UL << 3)
439#define DISPLAY_MONITOR_PORT_DETECTED	(1UL << 2) // TMDS/DisplayPort only
440
441#define LVDS_POST2_RATE_SLOW			14 // PLL Divisors
442#define LVDS_POST2_RATE_FAST			7
443#define LVDS_CLKB_POWER_MASK			(3 << 4)
444#define LVDS_CLKB_POWER_UP				(3 << 4)
445#define LVDS_PORT_EN					(1 << 31)
446#define LVDS_A0A2_CLKA_POWER_UP			(3 << 8)
447#define LVDS_B0B3PAIRS_POWER_UP			(3 << 2)
448#define LVDS_18BIT_DITHER				(1 << 25)
449
450// PLL flags
451#define DISPLAY_PLL_ENABLED				(1UL << 31)
452#define DISPLAY_PLL_2X_CLOCK			(1UL << 30)
453#define DISPLAY_PLL_SYNC_LOCK_ENABLED	(1UL << 29)
454#define DISPLAY_PLL_NO_VGA_CONTROL		(1UL << 28)
455#define DISPLAY_PLL_MODE_ANALOG			(1UL << 26)
456#define DISPLAY_PLL_MODE_LVDS			(2UL << 26)
457#define DISPLAY_PLL_DIVIDE_HIGH			(1UL << 24)
458#define DISPLAY_PLL_DIVIDE_4X			(1UL << 23)
459#define DISPLAY_PLL_POST1_DIVIDE_2		(1UL << 21)
460#define DISPLAY_PLL_POST1_DIVISOR_MASK	0x001f0000
461#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK	0x00ff0000
462#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK  0x00ff8000
463#define DISPLAY_PLL_POST1_DIVISOR_SHIFT	16
464#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT	15
465#define DISPLAY_PLL_DIVISOR_1			(1UL << 8)
466#define DISPLAY_PLL_N_DIVISOR_MASK		0x001f0000
467#define DISPLAY_PLL_IGD_N_DIVISOR_MASK	0x00ff0000
468#define DISPLAY_PLL_M1_DIVISOR_MASK		0x00001f00
469#define DISPLAY_PLL_M2_DIVISOR_MASK		0x0000001f
470#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK	0x000000ff
471#define DISPLAY_PLL_N_DIVISOR_SHIFT		16
472#define DISPLAY_PLL_M1_DIVISOR_SHIFT	8
473#define DISPLAY_PLL_M2_DIVISOR_SHIFT	0
474#define DISPLAY_PLL_PULSE_PHASE_SHIFT	9
475
476// display
477
478#define INTEL_DISPLAY_OFFSET			0x1000
479
480#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_NORTH_PIPE_AND_PORT)
481#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_NORTH_PIPE_AND_PORT)
482#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_NORTH_PIPE_AND_PORT)
483#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_NORTH_PIPE_AND_PORT)
484#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_NORTH_PIPE_AND_PORT)
485#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_NORTH_PIPE_AND_PORT)
486#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_NORTH_PIPE_AND_PORT)
487#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_NORTH_PIPE_AND_PORT)
488#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_NORTH_PIPE_AND_PORT)
489#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_NORTH_PIPE_AND_PORT)
490#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_NORTH_PIPE_AND_PORT)
491#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_NORTH_PIPE_AND_PORT)
492
493#define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
494#define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)
495
496#define INTEL_ANALOG_PORT				(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
497#define INTEL_DIGITAL_PORT_A			(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
498#define INTEL_DIGITAL_PORT_B			(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
499#define INTEL_DIGITAL_PORT_C			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
500#define INTEL_DIGITAL_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
501
502#define INTEL_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
503#define INTEL_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
504
505#define PCH_HDMI_PORT_B					(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
506#define PCH_HDMI_PORT_C					(0x1150 | REGS_SOUTH_TRANSCODER_PORT)
507#define PCH_HDMI_PORT_D					(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
508
509#define GEN4_HDMI_PORT_B				(0x1140 | REGS_NORTH_PIPE_AND_PORT)
510#define GEN4_HDMI_PORT_C				(0x1160 | REGS_NORTH_PIPE_AND_PORT)
511#define CHV_HDMI_PORT_D					(0x116C | REGS_NORTH_PIPE_AND_PORT)
512
513#define INTEL_DISPLAY_PORT_A			(0x4000 | REGS_NORTH_PIPE_AND_PORT)
514#define INTEL_DISPLAY_PORT_B			(0x4100 | REGS_NORTH_PIPE_AND_PORT)
515#define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_NORTH_PIPE_AND_PORT)
516#define INTEL_DISPLAY_PORT_D			(0x4300 | REGS_NORTH_PIPE_AND_PORT)
517
518// planes
519#define INTEL_PIPE_ENABLED				(1UL << 31)
520#define INTEL_PIPE_CONTROL				0x0008
521#define INTEL_PIPE_STATUS				0x0024
522
523#define INTEL_PLANE_OFFSET				0x1000
524
525#define INTEL_DISPLAY_A_PIPE_CONTROL	(0x0008	| REGS_NORTH_PLANE_CONTROL)
526#define INTEL_DISPLAY_B_PIPE_CONTROL	(0x1008 | REGS_NORTH_PLANE_CONTROL)
527#define INTEL_DISPLAY_A_PIPE_STATUS		(0x0024 | REGS_NORTH_PLANE_CONTROL)
528#define INTEL_DISPLAY_B_PIPE_STATUS		(0x1024 | REGS_NORTH_PLANE_CONTROL)
529
530#define DISPLAY_PIPE_VBLANK_ENABLED		(1UL << 17)
531#define DISPLAY_PIPE_VBLANK_STATUS		(1UL << 1)
532
533#define INTEL_DISPLAY_A_CONTROL			(0x0180 | REGS_NORTH_PLANE_CONTROL)
534#define INTEL_DISPLAY_A_BASE			(0x0184 | REGS_NORTH_PLANE_CONTROL)
535#define INTEL_DISPLAY_A_BYTES_PER_ROW	(0x0188 | REGS_NORTH_PLANE_CONTROL)
536#define INTEL_DISPLAY_A_POS				(0x018c | REGS_NORTH_PLANE_CONTROL)
537	// reserved on A
538#define INTEL_DISPLAY_A_PIPE_SIZE		(0x0190 | REGS_NORTH_PLANE_CONTROL)
539#define INTEL_DISPLAY_A_SURFACE			(0x019c | REGS_NORTH_PLANE_CONTROL)
540	// i965 and up only
541
542#define INTEL_DISPLAY_B_CONTROL			(0x1180 | REGS_NORTH_PLANE_CONTROL)
543#define INTEL_DISPLAY_B_BASE			(0x1184 | REGS_NORTH_PLANE_CONTROL)
544#define INTEL_DISPLAY_B_BYTES_PER_ROW	(0x1188 | REGS_NORTH_PLANE_CONTROL)
545#define INTEL_DISPLAY_B_POS				(0x118c | REGS_NORTH_PLANE_CONTROL)
546#define INTEL_DISPLAY_B_PIPE_SIZE		(0x1190 | REGS_NORTH_PLANE_CONTROL)
547#define INTEL_DISPLAY_B_SURFACE			(0x119c | REGS_NORTH_PLANE_CONTROL)
548	// i965 and up only
549
550#define DISPLAY_CONTROL_ENABLED			(1UL << 31)
551#define DISPLAY_CONTROL_GAMMA			(1UL << 30)
552#define DISPLAY_CONTROL_COLOR_MASK		(0x0fUL << 26)
553#define DISPLAY_CONTROL_CMAP8			(2UL << 26)
554#define DISPLAY_CONTROL_RGB15			(4UL << 26)
555#define DISPLAY_CONTROL_RGB16			(5UL << 26)
556#define DISPLAY_CONTROL_RGB32			(6UL << 26)
557
558// cursors
559#define INTEL_CURSOR_CONTROL			(0x0080 | REGS_NORTH_PLANE_CONTROL)
560#define INTEL_CURSOR_BASE				(0x0084 | REGS_NORTH_PLANE_CONTROL)
561#define INTEL_CURSOR_POSITION			(0x0088 | REGS_NORTH_PLANE_CONTROL)
562#define INTEL_CURSOR_PALETTE			(0x0090 | REGS_NORTH_PLANE_CONTROL)
563	// (- 0x009f)
564#define INTEL_CURSOR_SIZE				(0x00a0 | REGS_NORTH_PLANE_CONTROL)
565#define CURSOR_ENABLED					(1UL << 31)
566#define CURSOR_FORMAT_2_COLORS			(0UL << 24)
567#define CURSOR_FORMAT_3_COLORS			(1UL << 24)
568#define CURSOR_FORMAT_4_COLORS			(2UL << 24)
569#define CURSOR_FORMAT_ARGB				(4UL << 24)
570#define CURSOR_FORMAT_XRGB				(5UL << 24)
571#define CURSOR_POSITION_NEGATIVE		0x8000
572#define CURSOR_POSITION_MASK			0x3fff
573
574// palette registers
575#define INTEL_DISPLAY_A_PALETTE			(0xa000 | REGS_NORTH_SHARED)
576#define INTEL_DISPLAY_B_PALETTE			(0xa800 | REGS_NORTH_SHARED)
577
578// PLL registers
579#define INTEL_DISPLAY_A_PLL				(0x6014 | REGS_SOUTH_SHARED)
580#define INTEL_DISPLAY_B_PLL				(0x6018 | REGS_SOUTH_SHARED)
581#define CHV_DISPLAY_C_PLL				(0x6030 | REGS_SOUTH_SHARED)
582
583//  Multiplier Divisor
584#define INTEL_DISPLAY_A_PLL_MD			(0x601C | REGS_SOUTH_SHARED)
585#define INTEL_DISPLAY_B_PLL_MD			(0x6020 | REGS_SOUTH_SHARED)
586#define CHV_DISPLAY_B_PLL_MD			(0x603C | REGS_SOUTH_SHARED)
587
588#define INTEL_DISPLAY_A_PLL_DIVISOR_0	(0x6040 | REGS_SOUTH_SHARED)
589#define INTEL_DISPLAY_A_PLL_DIVISOR_1	(0x6044 | REGS_SOUTH_SHARED)
590#define INTEL_DISPLAY_B_PLL_DIVISOR_0	(0x6048 | REGS_SOUTH_SHARED)
591#define INTEL_DISPLAY_B_PLL_DIVISOR_1	(0x604c | REGS_SOUTH_SHARED)
592
593// i2c
594#define INTEL_I2C_IO_A					(0x5010 | REGS_SOUTH_SHARED)
595#define INTEL_I2C_IO_B					(0x5014 | REGS_SOUTH_SHARED)
596#define INTEL_I2C_IO_C					(0x5018 | REGS_SOUTH_SHARED)
597#define INTEL_I2C_IO_D					(0x501c | REGS_SOUTH_SHARED)
598#define INTEL_I2C_IO_E					(0x5020 | REGS_SOUTH_SHARED)
599#define INTEL_I2C_IO_F					(0x5024 | REGS_SOUTH_SHARED)
600#define INTEL_I2C_IO_G					(0x5028 | REGS_SOUTH_SHARED)
601#define INTEL_I2C_IO_H					(0x502c | REGS_SOUTH_SHARED)
602
603#define I2C_CLOCK_DIRECTION_MASK		(1 << 0)
604#define I2C_CLOCK_DIRECTION_OUT			(1 << 1)
605#define I2C_CLOCK_VALUE_MASK			(1 << 2)
606#define I2C_CLOCK_VALUE_OUT				(1 << 3)
607#define I2C_CLOCK_VALUE_IN				(1 << 4)
608#define I2C_DATA_DIRECTION_MASK			(1 << 8)
609#define I2C_DATA_DIRECTION_OUT			(1 << 9)
610#define I2C_DATA_VALUE_MASK				(1 << 10)
611#define I2C_DATA_VALUE_OUT				(1 << 11)
612#define I2C_DATA_VALUE_IN				(1 << 12)
613#define I2C_RESERVED					((1 << 13) | (1 << 5))
614
615// TODO: on IronLake this is in the north shared block at 0x41000
616#define INTEL_VGA_DISPLAY_CONTROL		(0x1400 | REGS_NORTH_PLANE_CONTROL)
617#define VGA_DISPLAY_DISABLED			(1UL << 31)
618
619// LVDS panel
620#define INTEL_PANEL_STATUS				(0x1200 | REGS_NORTH_PIPE_AND_PORT)
621#define INTEL_PANEL_CONTROL				(0x1204 | REGS_NORTH_PIPE_AND_PORT)
622#define INTEL_PANEL_FIT_CONTROL			(0x1230 | REGS_NORTH_PIPE_AND_PORT)
623#define INTEL_PANEL_FIT_RATIOS			(0x1234 | REGS_NORTH_PIPE_AND_PORT)
624
625// LVDS on IronLake and up
626#define PCH_PANEL_STATUS				(0x7200 | REGS_SOUTH_SHARED)
627#define PCH_PANEL_CONTROL				(0x7204 | REGS_SOUTH_SHARED)
628#define PCH_PANEL_ON_DELAYS				(0x7208 | REGS_SOUTH_SHARED)
629#define PCH_PANEL_OFF_DELAYS			(0x720c | REGS_SOUTH_SHARED)
630#define PCH_PANEL_DIVISOR				(0x7210 | REGS_SOUTH_SHARED)
631#define PCH_LVDS_DETECTED				(1 << 1)
632
633#define PANEL_STATUS_POWER_ON			(1UL << 31)
634#define PANEL_CONTROL_POWER_TARGET_OFF	(0UL << 0)
635#define PANEL_CONTROL_POWER_TARGET_ON	(1UL << 0)
636#define PANEL_CONTROL_POWER_TARGET_RST	(1UL << 1)
637#define PANEL_REGISTER_UNLOCK			(0xabcd << 16)
638
639// PCH_PANEL_ON_DELAYS
640#define PANEL_DELAY_PORT_SELECT_MASK	(3 << 30)
641#define PANEL_DELAY_PORT_SELECT_LVDS	(0 << 30)
642#define PANEL_DELAY_PORT_SELECT_DPA		(1 << 30)
643#define PANEL_DELAY_PORT_SELECT_DPC		(2 << 30)
644#define PANEL_DELAY_PORT_SELECT_DPD		(3 << 30)
645
646// PCH_PANEL_DIVISOR
647#define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00
648#define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8
649#define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f
650#define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f
651
652// ring buffer commands
653
654#define COMMAND_NOOP					0x00
655#define COMMAND_WAIT_FOR_EVENT			(0x03 << 23)
656#define COMMAND_WAIT_FOR_OVERLAY_FLIP	(1 << 16)
657
658#define COMMAND_FLUSH					(0x04 << 23)
659
660// overlay flip
661#define COMMAND_OVERLAY_FLIP			(0x11 << 23)
662#define COMMAND_OVERLAY_CONTINUE		(0 << 21)
663#define COMMAND_OVERLAY_ON				(1 << 21)
664#define COMMAND_OVERLAY_OFF				(2 << 21)
665#define OVERLAY_UPDATE_COEFFICIENTS		0x1
666
667// 2D acceleration
668#define XY_COMMAND_SOURCE_BLIT			0x54c00006
669#define XY_COMMAND_COLOR_BLIT			0x54000004
670#define XY_COMMAND_SETUP_MONO_PATTERN	0x44400007
671#define XY_COMMAND_SCANLINE_BLIT		0x49400001
672#define COMMAND_COLOR_BLIT				0x50000003
673#define COMMAND_BLIT_RGBA				0x00300000
674
675#define COMMAND_MODE_SOLID_PATTERN		0x80
676#define COMMAND_MODE_CMAP8				0x00
677#define COMMAND_MODE_RGB15				0x02
678#define COMMAND_MODE_RGB16				0x01
679#define COMMAND_MODE_RGB32				0x03
680
681// overlay
682#define INTEL_OVERLAY_UPDATE			0x30000
683#define INTEL_OVERLAY_TEST				0x30004
684#define INTEL_OVERLAY_STATUS			0x30008
685#define INTEL_OVERLAY_EXTENDED_STATUS	0x3000c
686#define INTEL_OVERLAY_GAMMA_5			0x30010
687#define INTEL_OVERLAY_GAMMA_4			0x30014
688#define INTEL_OVERLAY_GAMMA_3			0x30018
689#define INTEL_OVERLAY_GAMMA_2			0x3001c
690#define INTEL_OVERLAY_GAMMA_1			0x30020
691#define INTEL_OVERLAY_GAMMA_0			0x30024
692
693// FDI - Flexible Display Interface, the interface between the (CPU-internal)
694// GPU and the PCH display outputs. Proprietary interface, based on DisplayPort
695// though, so similar link training and all...
696// There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the
697// PCH for each display pipe.
698// FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to
699// transcoder B, so we have the same mapping as with the display pipes.
700#define PCH_FDI_RX_BASE_REGISTER		0xf0000
701#define PCH_FDI_RX_PIPE_OFFSET			0x01000
702
703#define PCH_FDI_RX_CONTROL				0x0c
704#define FDI_RX_CLOCK_MASK				(1 << 4)
705#define FDI_RX_CLOCK_RAW				(0 << 4)
706#define FDI_RX_CLOCK_PCD				(1 << 4)
707
708#define PCH_FDI_RX_TRANS_UNIT_SIZE_1	0x30
709#define PCH_FDI_RX_TRANS_UNIT_SIZE_2	0x38
710#define FDI_RX_TRANS_UNIT_SIZE(x)		((x - 1) << 25)
711#define FDI_RX_TRANS_UNIT_MASK			0x7e000000
712	// Transfer unit size 1 is the primary and fixed transfer unit size,
713	// TU size 2 is the lower power state transfer unit size when using dynamic
714	// refresh rates (we don't do that though).
715
716// CPU Panel Fitters - These are for IronLake and up and are the CPU internal
717// panel fitters.
718#define PCH_PANEL_FITTER_BASE_REGISTER	0x68000
719#define PCH_PANEL_FITTER_PIPE_OFFSET	0x00800
720
721#define PCH_PANEL_FITTER_WINDOW_POS		0x70
722#define PCH_PANEL_FITTER_WINDOW_SIZE	0x74
723#define PCH_PANEL_FITTER_CONTROL		0x80
724#define PCH_PANEL_FITTER_V_SCALE		0x84
725#define PCH_PANEL_FITTER_H_SCALE		0x90
726
727#define PANEL_FITTER_ENABLED			(1 << 31)
728#define PANEL_FITTER_FILTER_MASK		(3 << 23)
729
730struct overlay_scale {
731	uint32 _reserved0 : 3;
732	uint32 horizontal_scale_fraction : 12;
733	uint32 _reserved1 : 1;
734	uint32 horizontal_downscale_factor : 3;
735	uint32 _reserved2 : 1;
736	uint32 vertical_scale_fraction : 12;
737};
738
739#define OVERLAY_FORMAT_RGB15			0x2
740#define OVERLAY_FORMAT_RGB16			0x3
741#define OVERLAY_FORMAT_RGB32			0x1
742#define OVERLAY_FORMAT_YCbCr422			0x8
743#define OVERLAY_FORMAT_YCbCr411			0x9
744#define OVERLAY_FORMAT_YCbCr420			0xc
745
746#define OVERLAY_MIRROR_NORMAL			0x0
747#define OVERLAY_MIRROR_HORIZONTAL		0x1
748#define OVERLAY_MIRROR_VERTICAL			0x2
749
750// The real overlay registers are written to using an update buffer
751
752struct overlay_registers {
753	uint32 buffer_rgb0;
754	uint32 buffer_rgb1;
755	uint32 buffer_u0;
756	uint32 buffer_v0;
757	uint32 buffer_u1;
758	uint32 buffer_v1;
759	// (0x18) OSTRIDE - overlay stride
760	uint16 stride_rgb;
761	uint16 stride_uv;
762	// (0x1c) YRGB_VPH - Y/RGB vertical phase
763	uint16 vertical_phase0_rgb;
764	uint16 vertical_phase1_rgb;
765	// (0x20) UV_VPH - UV vertical phase
766	uint16 vertical_phase0_uv;
767	uint16 vertical_phase1_uv;
768	// (0x24) HORZ_PH - horizontal phase
769	uint16 horizontal_phase_rgb;
770	uint16 horizontal_phase_uv;
771	// (0x28) INIT_PHS - initial phase shift
772	uint32 initial_vertical_phase0_shift_rgb0 : 4;
773	uint32 initial_vertical_phase1_shift_rgb0 : 4;
774	uint32 initial_horizontal_phase_shift_rgb0 : 4;
775	uint32 initial_vertical_phase0_shift_uv : 4;
776	uint32 initial_vertical_phase1_shift_uv : 4;
777	uint32 initial_horizontal_phase_shift_uv : 4;
778	uint32 _reserved0 : 8;
779	// (0x2c) DWINPOS - destination window position
780	uint16 window_left;
781	uint16 window_top;
782	// (0x30) DWINSZ - destination window size
783	uint16 window_width;
784	uint16 window_height;
785	// (0x34) SWIDTH - source width
786	uint16 source_width_rgb;
787	uint16 source_width_uv;
788	// (0x38) SWITDHSW - source width in 8 byte steps
789	uint16 source_bytes_per_row_rgb;
790	uint16 source_bytes_per_row_uv;
791	uint16 source_height_rgb;
792	uint16 source_height_uv;
793	overlay_scale scale_rgb;
794	overlay_scale scale_uv;
795	// (0x48) OCLRC0 - overlay color correction 0
796	uint32 brightness_correction : 8;		// signed, -128 to 127
797	uint32 _reserved1 : 10;
798	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
799	uint32 _reserved2 : 5;
800	// (0x4c) OCLRC1 - overlay color correction 1
801	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
802	uint32 _reserved3 : 6;
803	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
804	uint32 _reserved4 : 5;
805	// (0x50) DCLRKV - destination color key value
806	uint32 color_key_blue : 8;
807	uint32 color_key_green : 8;
808	uint32 color_key_red : 8;
809	uint32 _reserved5 : 8;
810	// (0x54) DCLRKM - destination color key mask
811	uint32 color_key_mask_blue : 8;
812	uint32 color_key_mask_green : 8;
813	uint32 color_key_mask_red : 8;
814	uint32 _reserved6 : 7;
815	uint32 color_key_enabled : 1;
816	// (0x58) SCHRKVH - source chroma key high value
817	uint32 source_chroma_key_high_red : 8;
818	uint32 source_chroma_key_high_blue : 8;
819	uint32 source_chroma_key_high_green : 8;
820	uint32 _reserved7 : 8;
821	// (0x5c) SCHRKVL - source chroma key low value
822	uint32 source_chroma_key_low_red : 8;
823	uint32 source_chroma_key_low_blue : 8;
824	uint32 source_chroma_key_low_green : 8;
825	uint32 _reserved8 : 8;
826	// (0x60) SCHRKEN - source chroma key enable
827	uint32 _reserved9 : 24;
828	uint32 source_chroma_key_red_enabled : 1;
829	uint32 source_chroma_key_blue_enabled : 1;
830	uint32 source_chroma_key_green_enabled : 1;
831	uint32 _reserved10 : 5;
832	// (0x64) OCONFIG - overlay configuration
833	uint32 _reserved11 : 3;
834	uint32 color_control_output_mode : 1;
835	uint32 yuv_to_rgb_bypass : 1;
836	uint32 _reserved12 : 11;
837	uint32 gamma2_enabled : 1;
838	uint32 _reserved13 : 1;
839	uint32 select_pipe : 1;
840	uint32 slot_time : 8;
841	uint32 _reserved14 : 5;
842	// (0x68) OCOMD - overlay command
843	uint32 overlay_enabled : 1;
844	uint32 active_field : 1;
845	uint32 active_buffer : 2;
846	uint32 test_mode : 1;
847	uint32 buffer_field_mode : 1;
848	uint32 _reserved15 : 1;
849	uint32 tv_flip_field_enabled : 1;
850	uint32 _reserved16 : 1;
851	uint32 tv_flip_field_parity : 1;
852	uint32 source_format : 4;
853	uint32 ycbcr422_order : 2;
854	uint32 _reserved18 : 1;
855	uint32 mirroring_mode : 2;
856	uint32 _reserved19 : 13;
857
858	uint32 _reserved20;
859
860	uint32 start_0y;
861	uint32 start_1y;
862	uint32 start_0u;
863	uint32 start_0v;
864	uint32 start_1u;
865	uint32 start_1v;
866	uint32 _reserved21[6];
867#if 0
868	// (0x70) AWINPOS - alpha blend window position
869	uint32 awinpos;
870	// (0x74) AWINSZ - alpha blend window size
871	uint32 awinsz;
872
873	uint32 _reserved21[10];
874#endif
875
876	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
877	// the next two registers switch the usual Y/RGB vs. UV order)
878	uint16 horizontal_scale_uv;
879	uint16 horizontal_scale_rgb;
880	// (0xa4) UVSCALEV - vertical downscale
881	uint16 vertical_scale_uv;
882	uint16 vertical_scale_rgb;
883
884	uint32 _reserved22[86];
885
886	// (0x200) polyphase filter coefficients
887	uint16 vertical_coefficients_rgb[128];
888	uint16 horizontal_coefficients_rgb[128];
889
890	uint32	_reserved23[64];
891
892	// (0x500)
893	uint16 vertical_coefficients_uv[128];
894	uint16 horizontal_coefficients_uv[128];
895};
896
897// i965 overlay support is currently realized using its 3D hardware
898#define INTEL_i965_OVERLAY_STATE_SIZE	36864
899#define INTEL_i965_3D_CONTEXT_SIZE		32768
900
901inline bool
902intel_uses_physical_overlay(intel_shared_info &info)
903{
904	return !info.device_type.InGroup(INTEL_GROUP_Gxx);
905}
906
907
908struct hardware_status {
909	uint32	interrupt_status_register;
910	uint32	_reserved0[3];
911	void*	primary_ring_head_storage;
912	uint32	_reserved1[3];
913	void*	secondary_ring_0_head_storage;
914	void*	secondary_ring_1_head_storage;
915	uint32	_reserved2[2];
916	void*	binning_head_storage;
917	uint32	_reserved3[3];
918	uint32	store[1008];
919};
920
921#endif	/* INTEL_EXTREME_H */
922