intel_extreme.h revision 50f0b3fe
1/*
2 * Copyright 2006-2014, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 */
8#ifndef INTEL_EXTREME_H
9#define INTEL_EXTREME_H
10
11
12#include "lock.h"
13
14#include <Accelerant.h>
15#include <Drivers.h>
16#include <PCI.h>
17
18#include <edid.h>
19
20
21#define VENDOR_ID_INTEL			0x8086
22
23#define INTEL_TYPE_FAMILY_MASK	0x000f0000
24#define INTEL_TYPE_GROUP_MASK	0x000ffff0
25#define INTEL_TYPE_MODEL_MASK	0x000fffff
26// families
27#define INTEL_TYPE_7xx			0x00010000
28#define INTEL_TYPE_8xx			0x00020000
29#define INTEL_TYPE_9xx			0x00040000
30// groups
31#define INTEL_TYPE_83x			(INTEL_TYPE_8xx | 0x0010)
32#define INTEL_TYPE_85x			(INTEL_TYPE_8xx | 0x0020)
33#define INTEL_TYPE_91x			(INTEL_TYPE_9xx | 0x0040)
34#define INTEL_TYPE_94x			(INTEL_TYPE_9xx | 0x0080)
35#define INTEL_TYPE_96x			(INTEL_TYPE_9xx | 0x0100)
36#define INTEL_TYPE_Gxx			(INTEL_TYPE_9xx | 0x0200)
37#define INTEL_TYPE_G4x			(INTEL_TYPE_9xx | 0x0400)
38#define INTEL_TYPE_IGD			(INTEL_TYPE_9xx | 0x0800)
39#define INTEL_TYPE_ILK			(INTEL_TYPE_9xx | 0x1000)
40#define INTEL_TYPE_SNB			(INTEL_TYPE_9xx | 0x2000)
41#define INTEL_TYPE_IVB			(INTEL_TYPE_9xx | 0x4000)
42#define INTEL_TYPE_VLV			(INTEL_TYPE_9xx | 0x8000)
43// models
44#define INTEL_TYPE_SERVER		0x0004
45#define INTEL_TYPE_MOBILE		0x0008
46#define INTEL_TYPE_915			(INTEL_TYPE_91x)
47#define INTEL_TYPE_915M			(INTEL_TYPE_91x | INTEL_TYPE_MOBILE)
48#define INTEL_TYPE_945			(INTEL_TYPE_94x)
49#define INTEL_TYPE_945M			(INTEL_TYPE_94x | INTEL_TYPE_MOBILE)
50#define INTEL_TYPE_965			(INTEL_TYPE_96x)
51#define INTEL_TYPE_965M			(INTEL_TYPE_96x | INTEL_TYPE_MOBILE)
52#define INTEL_TYPE_G33			(INTEL_TYPE_Gxx)
53#define INTEL_TYPE_G45			(INTEL_TYPE_G4x)
54#define INTEL_TYPE_GM45			(INTEL_TYPE_G4x | INTEL_TYPE_MOBILE)
55#define INTEL_TYPE_IGDG			(INTEL_TYPE_IGD)
56#define INTEL_TYPE_IGDGM		(INTEL_TYPE_IGD | INTEL_TYPE_MOBILE)
57#define INTEL_TYPE_ILKG			(INTEL_TYPE_ILK)
58#define INTEL_TYPE_ILKGM		(INTEL_TYPE_ILK | INTEL_TYPE_MOBILE)
59#define INTEL_TYPE_SNBG			(INTEL_TYPE_SNB)
60#define INTEL_TYPE_SNBGM		(INTEL_TYPE_SNB | INTEL_TYPE_MOBILE)
61#define INTEL_TYPE_SNBGS		(INTEL_TYPE_SNB | INTEL_TYPE_SERVER)
62#define INTEL_TYPE_IVBG			(INTEL_TYPE_IVB)
63#define INTEL_TYPE_IVBGM		(INTEL_TYPE_IVB | INTEL_TYPE_MOBILE)
64#define INTEL_TYPE_IVBGS		(INTEL_TYPE_IVB | INTEL_TYPE_SERVER)
65#define INTEL_TYPE_VLVG			(INTEL_TYPE_VLV)
66#define INTEL_TYPE_VLVGM		(INTEL_TYPE_VLV | INTEL_TYPE_MOBILE)
67
68// ValleyView MMIO offset
69#define VLV_DISPLAY_BASE		0x180000
70
71#define DEVICE_NAME				"intel_extreme"
72#define INTEL_ACCELERANT_NAME	"intel_extreme.accelerant"
73
74// We encode the register block into the value and extract/translate it when
75// actually accessing.
76#define REGISTER_BLOCK_COUNT				6
77#define REGISTER_BLOCK_SHIFT				24
78#define REGISTER_BLOCK_MASK					0xff000000
79#define REGISTER_REGISTER_MASK				0x00ffffff
80#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
81#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
82
83#define REGS_FLAT							(0 << REGISTER_BLOCK_SHIFT)
84#define REGS_NORTH_SHARED					(1 << REGISTER_BLOCK_SHIFT)
85#define REGS_NORTH_PIPE_AND_PORT			(2 << REGISTER_BLOCK_SHIFT)
86#define REGS_NORTH_PLANE_CONTROL			(3 << REGISTER_BLOCK_SHIFT)
87#define REGS_SOUTH_SHARED					(4 << REGISTER_BLOCK_SHIFT)
88#define REGS_SOUTH_TRANSCODER_PORT			(5 << REGISTER_BLOCK_SHIFT)
89
90// register blocks for (G)MCH/ICH based platforms
91#define MCH_SHARED_REGISTER_BASE						0x00000
92#define MCH_PIPE_AND_PORT_REGISTER_BASE					0x60000
93#define MCH_PLANE_CONTROL_REGISTER_BASE					0x70000
94#define ICH_SHARED_REGISTER_BASE						0x00000
95#define ICH_PORT_REGISTER_BASE							0x60000
96
97// PCH - Platform Control Hub - Newer hardware moves from a MCH/ICH based setup
98// to a PCH based one, that means anything that used to communicate via (G)MCH
99// registers needs to use different ones on PCH based platforms (Ironlake and
100// up, SandyBridge, etc.).
101#define PCH_NORTH_SHARED_REGISTER_BASE					0x40000
102#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE			0x60000
103#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE			0x70000
104#define PCH_SOUTH_SHARED_REGISTER_BASE					0xc0000
105#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE		0xe0000
106
107
108struct DeviceType {
109	uint32			type;
110
111	DeviceType(int t)
112	{
113		type = t;
114	}
115
116	DeviceType& operator=(int t)
117	{
118		type = t;
119		return *this;
120	}
121
122	bool InFamily(uint32 family) const
123	{
124		return (type & INTEL_TYPE_FAMILY_MASK) == family;
125	}
126
127	bool InGroup(uint32 group) const
128	{
129		return (type & INTEL_TYPE_GROUP_MASK) == group;
130	}
131
132	bool IsModel(uint32 model) const
133	{
134		return (type & INTEL_TYPE_MODEL_MASK) == model;
135	}
136
137	bool IsMobile() const
138	{
139		return (type & INTEL_TYPE_MODEL_MASK) == INTEL_TYPE_MOBILE;
140	}
141
142	bool SupportsHDMI() const
143	{
144		switch (type & INTEL_TYPE_GROUP_MASK) {
145			case INTEL_TYPE_G4x:
146			case INTEL_TYPE_ILK:
147			case INTEL_TYPE_SNB:
148			case INTEL_TYPE_IVBG:
149			case INTEL_TYPE_VLV:
150				return true;
151		}
152		return false;
153	}
154
155	bool HasPlatformControlHub() const
156	{
157		return InGroup(INTEL_TYPE_ILK) || InGroup(INTEL_TYPE_SNB)
158			|| InGroup(INTEL_TYPE_IVB) || InGroup(INTEL_TYPE_VLV);
159	}
160};
161
162// info about PLL on graphics card
163struct pll_info {
164	uint32			reference_frequency;
165	uint32			max_frequency;
166	uint32			min_frequency;
167	uint32			divisor_register;
168};
169
170struct ring_buffer {
171	struct lock		lock;
172	uint32			register_base;
173	uint32			offset;
174	uint32			size;
175	uint32			position;
176	uint32			space_left;
177	uint8*			base;
178};
179
180struct overlay_registers;
181
182struct intel_shared_info {
183	area_id			mode_list_area;		// area containing display mode list
184	uint32			mode_count;
185
186	display_mode	current_mode;
187	uint32			bytes_per_row;
188	uint32			bits_per_pixel;
189	uint32			dpms_mode;
190
191	area_id			registers_area;			// area of memory mapped registers
192	uint32			register_blocks[REGISTER_BLOCK_COUNT];
193
194	uint8*			status_page;
195	phys_addr_t		physical_status_page;
196	uint8*			graphics_memory;
197	phys_addr_t		physical_graphics_memory;
198	uint32			graphics_memory_size;
199
200	addr_t			frame_buffer;
201	uint32			frame_buffer_offset;
202
203	bool			got_vbt;
204	bool			single_head_locked;
205
206	struct lock		accelerant_lock;
207	struct lock		engine_lock;
208
209	ring_buffer		primary_ring_buffer;
210
211	int32			overlay_channel_used;
212	bool			overlay_active;
213	uintptr_t		overlay_token;
214	phys_addr_t		physical_overlay_registers;
215	uint32			overlay_offset;
216
217	bool			hardware_cursor_enabled;
218	sem_id			vblank_sem;
219
220	uint8*			cursor_memory;
221	phys_addr_t		physical_cursor_memory;
222	uint32			cursor_buffer_offset;
223	uint32			cursor_format;
224	bool			cursor_visible;
225	uint16			cursor_hot_x;
226	uint16			cursor_hot_y;
227
228	DeviceType		device_type;
229	char			device_identifier[32];
230	struct pll_info	pll_info;
231
232	edid1_info		vesa_edid_info;
233	bool			has_vesa_edid_info;
234};
235
236//----------------- ioctl() interface ----------------
237
238// magic code for ioctls
239#define INTEL_PRIVATE_DATA_MAGIC		'itic'
240
241// list ioctls
242enum {
243	INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
244
245	INTEL_GET_DEVICE_NAME,
246	INTEL_ALLOCATE_GRAPHICS_MEMORY,
247	INTEL_FREE_GRAPHICS_MEMORY
248};
249
250// retrieve the area_id of the kernel/accelerant shared info
251struct intel_get_private_data {
252	uint32	magic;				// magic number
253	area_id	shared_info_area;
254};
255
256// allocate graphics memory
257struct intel_allocate_graphics_memory {
258	uint32	magic;
259	uint32	size;
260	uint32	alignment;
261	uint32	flags;
262	addr_t	buffer_base;
263};
264
265// free graphics memory
266struct intel_free_graphics_memory {
267	uint32 	magic;
268	addr_t	buffer_base;
269};
270
271//----------------------------------------------------------
272// Register definitions, taken from X driver
273
274// PCI bridge memory management
275#define INTEL_GRAPHICS_MEMORY_CONTROL	0x52
276	// GGC - (G)MCH Graphics Control Register
277#define MEMORY_CONTROL_ENABLED			0x0004
278#define MEMORY_MASK						0x0001
279#define STOLEN_MEMORY_MASK				0x00f0
280#define i965_GTT_MASK					0x000e
281#define G33_GTT_MASK					0x0300
282#define G4X_GTT_MASK					0x0f00	// GGMS (GSM Memory Size) mask
283
284// models i830 and up
285#define i830_LOCAL_MEMORY_ONLY			0x10
286#define i830_STOLEN_512K				0x20
287#define i830_STOLEN_1M					0x30
288#define i830_STOLEN_8M					0x40
289#define i830_FRAME_BUFFER_64M			0x01
290#define i830_FRAME_BUFFER_128M			0x00
291
292// models i855 and up
293#define i855_STOLEN_MEMORY_1M			0x10
294#define i855_STOLEN_MEMORY_4M			0x20
295#define i855_STOLEN_MEMORY_8M			0x30
296#define i855_STOLEN_MEMORY_16M			0x40
297#define i855_STOLEN_MEMORY_32M			0x50
298#define i855_STOLEN_MEMORY_48M			0x60
299#define i855_STOLEN_MEMORY_64M			0x70
300#define i855_STOLEN_MEMORY_128M			0x80
301#define i855_STOLEN_MEMORY_256M			0x90
302
303#define G4X_STOLEN_MEMORY_96MB			0xa0	// GMS - Graphics Mode Select
304#define G4X_STOLEN_MEMORY_160MB			0xb0
305#define G4X_STOLEN_MEMORY_224MB			0xc0
306#define G4X_STOLEN_MEMORY_352MB			0xd0
307
308// SandyBridge (SNB)
309#define SNB_GRAPHICS_MEMORY_CONTROL		0x50
310
311#define SNB_STOLEN_MEMORY_MASK			0xf8
312#define SNB_STOLEN_MEMORY_32MB			(1 << 3)
313#define SNB_STOLEN_MEMORY_64MB			(2 << 3)
314#define SNB_STOLEN_MEMORY_96MB			(3 << 3)
315#define SNB_STOLEN_MEMORY_128MB			(4 << 3)
316#define SNB_STOLEN_MEMORY_160MB			(5 << 3)
317#define SNB_STOLEN_MEMORY_192MB			(6 << 3)
318#define SNB_STOLEN_MEMORY_224MB			(7 << 3)
319#define SNB_STOLEN_MEMORY_256MB			(8 << 3)
320#define SNB_STOLEN_MEMORY_288MB			(9 << 3)
321#define SNB_STOLEN_MEMORY_320MB			(10 << 3)
322#define SNB_STOLEN_MEMORY_352MB			(11 << 3)
323#define SNB_STOLEN_MEMORY_384MB			(12 << 3)
324#define SNB_STOLEN_MEMORY_416MB			(13 << 3)
325#define SNB_STOLEN_MEMORY_448MB			(14 << 3)
326#define SNB_STOLEN_MEMORY_480MB			(15 << 3)
327#define SNB_STOLEN_MEMORY_512MB			(16 << 3)
328
329#define SNB_GTT_SIZE_MASK				(3 << 8)
330#define SNB_GTT_SIZE_NONE				(0 << 8)
331#define SNB_GTT_SIZE_1MB				(1 << 8)
332#define SNB_GTT_SIZE_2MB				(2 << 8)
333
334// graphics page translation table
335#define INTEL_PAGE_TABLE_CONTROL		0x02020
336#define PAGE_TABLE_ENABLED				0x00000001
337#define INTEL_PAGE_TABLE_ERROR			0x02024
338#define INTEL_HARDWARE_STATUS_PAGE		0x02080
339#define i915_GTT_BASE					0x1c
340#define i830_GTT_BASE					0x10000	// (- 0x2ffff)
341#define i830_GTT_SIZE					0x20000
342#define i965_GTT_BASE					0x80000	// (- 0xfffff)
343#define i965_GTT_SIZE					0x80000
344#define i965_GTT_128K					(2 << 1)
345#define i965_GTT_256K					(1 << 1)
346#define i965_GTT_512K					(0 << 1)
347#define G33_GTT_1M						(1 << 8)
348#define G33_GTT_2M						(2 << 8)
349#define G4X_GTT_NONE					0x000	// GGMS - GSM Memory Size
350#define G4X_GTT_1M_NO_IVT				0x100	// no Intel Virtualization Tech.
351#define G4X_GTT_2M_NO_IVT				0x300
352#define G4X_GTT_2M_IVT					0x900	// with Intel Virt. Tech.
353#define G4X_GTT_3M_IVT					0xa00
354#define G4X_GTT_4M_IVT					0xb00
355
356
357#define GTT_ENTRY_VALID					0x01
358#define GTT_ENTRY_LOCAL_MEMORY			0x02
359#define GTT_PAGE_SHIFT					12
360
361
362// ring buffer
363#define INTEL_PRIMARY_RING_BUFFER		0x02030
364#define INTEL_SECONDARY_RING_BUFFER_0	0x02100
365#define INTEL_SECONDARY_RING_BUFFER_1	0x02110
366// offsets for the ring buffer base registers above
367#define RING_BUFFER_TAIL				0x0
368#define RING_BUFFER_HEAD				0x4
369#define RING_BUFFER_START				0x8
370#define RING_BUFFER_CONTROL				0xc
371#define INTEL_RING_BUFFER_SIZE_MASK		0x001ff000
372#define INTEL_RING_BUFFER_HEAD_MASK		0x001ffffc
373#define INTEL_RING_BUFFER_ENABLED		1
374
375// interrupts
376#define INTEL_INTERRUPT_ENABLED			0x020a0
377#define INTEL_INTERRUPT_IDENTITY		0x020a4
378#define INTEL_INTERRUPT_MASK			0x020a8
379#define INTEL_INTERRUPT_STATUS			0x020ac
380#define INTERRUPT_VBLANK_PIPEA			(1 << 7)
381#define INTERRUPT_VBLANK_PIPEB			(1 << 5)
382
383// PCH interrupts
384#define PCH_INTERRUPT_STATUS			0x44000
385#define PCH_INTERRUPT_MASK				0x44004
386#define PCH_INTERRUPT_IDENTITY			0x44008
387#define PCH_INTERRUPT_ENABLED			0x4400c
388#define PCH_INTERRUPT_VBLANK_PIPEA		(1 << 0)
389#define PCH_INTERRUPT_VBLANK_PIPEB		(1 << 5)
390#define PCH_INTERRUPT_VBLANK_PIPEC		(1 << 10)
391
392#define PCH_INTERRUPT_VBLANK_PIPEA_SNB		(1 << 7)
393#define PCH_INTERRUPT_VBLANK_PIPEB_SNB		(1 << 15)
394
395// display ports
396#define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
397#define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
398#define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
399#define DISPLAY_MONITOR_MODE_MASK		(3UL << 10)
400#define DISPLAY_MONITOR_ON				0
401#define DISPLAY_MONITOR_SUSPEND			(1UL << 10)
402#define DISPLAY_MONITOR_STAND_BY		(2UL << 10)
403#define DISPLAY_MONITOR_OFF				(3UL << 10)
404#define DISPLAY_MONITOR_POLARITY_MASK	(3UL << 3)
405#define DISPLAY_MONITOR_POSITIVE_HSYNC	(1UL << 3)
406#define DISPLAY_MONITOR_POSITIVE_VSYNC	(2UL << 3)
407#define LVDS_POST2_RATE_SLOW			14 // PLL Divisors
408#define LVDS_POST2_RATE_FAST			7
409#define LVDS_CLKB_POWER_MASK			(3 << 4)
410#define LVDS_CLKB_POWER_UP				(3 << 4)
411#define LVDS_PORT_EN					(1 << 31)
412#define LVDS_A0A2_CLKA_POWER_UP			(3 << 8)
413#define LVDS_PIPEB_SELECT				(1 << 30)
414#define LVDS_B0B3PAIRS_POWER_UP			(3 << 2)
415#define LVDS_PLL_MODE_LVDS				(2 << 26)
416#define LVDS_18BIT_DITHER				(1 << 25)
417
418// PLL flags
419#define DISPLAY_PLL_ENABLED				(1UL << 31)
420#define DISPLAY_PLL_2X_CLOCK			(1UL << 30)
421#define DISPLAY_PLL_SYNC_LOCK_ENABLED	(1UL << 29)
422#define DISPLAY_PLL_NO_VGA_CONTROL		(1UL << 28)
423#define DISPLAY_PLL_MODE_ANALOG			(1UL << 26)
424#define DISPLAY_PLL_DIVIDE_HIGH			(1UL << 24)
425#define DISPLAY_PLL_DIVIDE_4X			(1UL << 23)
426#define DISPLAY_PLL_POST1_DIVIDE_2		(1UL << 21)
427#define DISPLAY_PLL_POST1_DIVISOR_MASK	0x001f0000
428#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK	0x00ff0000
429#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK  0x00ff8000
430#define DISPLAY_PLL_POST1_DIVISOR_SHIFT	16
431#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT	15
432#define DISPLAY_PLL_DIVISOR_1			(1UL << 8)
433#define DISPLAY_PLL_N_DIVISOR_MASK		0x001f0000
434#define DISPLAY_PLL_IGD_N_DIVISOR_MASK	0x00ff0000
435#define DISPLAY_PLL_M1_DIVISOR_MASK		0x00001f00
436#define DISPLAY_PLL_M2_DIVISOR_MASK		0x0000001f
437#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK	0x000000ff
438#define DISPLAY_PLL_N_DIVISOR_SHIFT		16
439#define DISPLAY_PLL_M1_DIVISOR_SHIFT	8
440#define DISPLAY_PLL_M2_DIVISOR_SHIFT	0
441#define DISPLAY_PLL_PULSE_PHASE_SHIFT	9
442
443// display
444#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_SOUTH_TRANSCODER_PORT)
445#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_SOUTH_TRANSCODER_PORT)
446#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_SOUTH_TRANSCODER_PORT)
447#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_SOUTH_TRANSCODER_PORT)
448#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_SOUTH_TRANSCODER_PORT)
449#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_SOUTH_TRANSCODER_PORT)
450#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_SOUTH_TRANSCODER_PORT)
451#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_SOUTH_TRANSCODER_PORT)
452#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_SOUTH_TRANSCODER_PORT)
453#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_SOUTH_TRANSCODER_PORT)
454#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_SOUTH_TRANSCODER_PORT)
455#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_SOUTH_TRANSCODER_PORT)
456
457#define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
458#define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)
459
460#define INTEL_ANALOG_PORT				(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
461#define INTEL_DIGITAL_PORT_A			(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
462#define INTEL_DIGITAL_PORT_B			(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
463#define INTEL_DIGITAL_PORT_C			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
464#define INTEL_DIGITAL_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
465
466#define INTEL_HDMI_PORT_B				(0x1140 | REGS_NORTH_PIPE_AND_PORT)
467#define INTEL_HDMI_PORT_C				(0x1160 | REGS_NORTH_PIPE_AND_PORT)
468
469#define PCH_HDMI_PORT_B					(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
470#define PCH_HDMI_PORT_C					(0x1150 | REGS_SOUTH_TRANSCODER_PORT)
471#define PCH_HDMI_PORT_D					(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
472
473#define INTEL_DISPLAY_PORT_A			(0x4000 | REGS_NORTH_PIPE_AND_PORT)
474#define INTEL_DISPLAY_PORT_B			(0x4100 | REGS_NORTH_PIPE_AND_PORT)
475#define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_NORTH_PIPE_AND_PORT)
476#define INTEL_DISPLAY_PORT_D			(0x4300 | REGS_NORTH_PIPE_AND_PORT)
477
478// valid for both DVI/HDMI and DisplayPort
479#define PORT_DETECTED					(1 << 2)
480
481// planes
482#define INTEL_PIPE_ENABLED				(1UL << 31)
483#define INTEL_PIPE_CONTROL				0x08
484#define INTEL_PIPE_STATUS				0x24
485#define INTEL_PIPE_OFFSET				0x1000
486#define INTEL_DISPLAY_A_PIPE_CONTROL	(0x0008	| REGS_NORTH_PLANE_CONTROL)
487#define INTEL_DISPLAY_B_PIPE_CONTROL	(0x1008 | REGS_NORTH_PLANE_CONTROL)
488#define INTEL_DISPLAY_A_PIPE_STATUS		(0x0024 | REGS_NORTH_PLANE_CONTROL)
489#define INTEL_DISPLAY_B_PIPE_STATUS		(0x1024 | REGS_NORTH_PLANE_CONTROL)
490
491#define DISPLAY_PIPE_VBLANK_ENABLED		(1UL << 17)
492#define DISPLAY_PIPE_VBLANK_STATUS		(1UL << 1)
493
494#define INTEL_DISPLAY_A_CONTROL			(0x0180 | REGS_NORTH_PLANE_CONTROL)
495#define INTEL_DISPLAY_A_BASE			(0x0184 | REGS_NORTH_PLANE_CONTROL)
496#define INTEL_DISPLAY_A_BYTES_PER_ROW	(0x0188 | REGS_NORTH_PLANE_CONTROL)
497#define INTEL_DISPLAY_A_POS				(0x018c | REGS_NORTH_PLANE_CONTROL)
498	// reserved on A
499#define INTEL_DISPLAY_A_PIPE_SIZE		(0x0190 | REGS_NORTH_PLANE_CONTROL)
500#define INTEL_DISPLAY_A_SURFACE			(0x019c | REGS_NORTH_PLANE_CONTROL)
501	// i965 and up only
502
503#define INTEL_DISPLAY_B_CONTROL			(0x1180 | REGS_NORTH_PLANE_CONTROL)
504#define INTEL_DISPLAY_B_BASE			(0x1184 | REGS_NORTH_PLANE_CONTROL)
505#define INTEL_DISPLAY_B_BYTES_PER_ROW	(0x1188 | REGS_NORTH_PLANE_CONTROL)
506#define INTEL_DISPLAY_B_POS				(0x118c | REGS_NORTH_PLANE_CONTROL)
507#define INTEL_DISPLAY_B_PIPE_SIZE		(0x1190 | REGS_NORTH_PLANE_CONTROL)
508#define INTEL_DISPLAY_B_SURFACE			(0x119c | REGS_NORTH_PLANE_CONTROL)
509	// i965 and up only
510
511#define DISPLAY_CONTROL_ENABLED			(1UL << 31)
512#define DISPLAY_CONTROL_GAMMA			(1UL << 30)
513#define DISPLAY_CONTROL_COLOR_MASK		(0x0fUL << 26)
514#define DISPLAY_CONTROL_CMAP8			(2UL << 26)
515#define DISPLAY_CONTROL_RGB15			(4UL << 26)
516#define DISPLAY_CONTROL_RGB16			(5UL << 26)
517#define DISPLAY_CONTROL_RGB32			(6UL << 26)
518
519// cursors
520#define INTEL_CURSOR_CONTROL			(0x0080 | REGS_NORTH_PLANE_CONTROL)
521#define INTEL_CURSOR_BASE				(0x0084 | REGS_NORTH_PLANE_CONTROL)
522#define INTEL_CURSOR_POSITION			(0x0088 | REGS_NORTH_PLANE_CONTROL)
523#define INTEL_CURSOR_PALETTE			(0x0090 | REGS_NORTH_PLANE_CONTROL)
524	// (- 0x009f)
525#define INTEL_CURSOR_SIZE				(0x00a0 | REGS_NORTH_PLANE_CONTROL)
526#define CURSOR_ENABLED					(1UL << 31)
527#define CURSOR_FORMAT_2_COLORS			(0UL << 24)
528#define CURSOR_FORMAT_3_COLORS			(1UL << 24)
529#define CURSOR_FORMAT_4_COLORS			(2UL << 24)
530#define CURSOR_FORMAT_ARGB				(4UL << 24)
531#define CURSOR_FORMAT_XRGB				(5UL << 24)
532#define CURSOR_POSITION_NEGATIVE		0x8000
533#define CURSOR_POSITION_MASK			0x3fff
534
535// palette registers
536#define INTEL_DISPLAY_A_PALETTE			(0xa000 | REGS_NORTH_SHARED)
537#define INTEL_DISPLAY_B_PALETTE			(0xa800 | REGS_NORTH_SHARED)
538
539// PLL registers
540#define INTEL_DISPLAY_A_PLL				(0x6014 | REGS_SOUTH_SHARED)
541#define INTEL_DISPLAY_B_PLL				(0x6018 | REGS_SOUTH_SHARED)
542#define INTEL_DISPLAY_A_PLL_MULTIPLIER_DIVISOR \
543										(0x601c | REGS_SOUTH_SHARED)
544#define INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR \
545										(0x6020 | REGS_SOUTH_SHARED)
546#define INTEL_DISPLAY_A_PLL_DIVISOR_0	(0x6040 | REGS_SOUTH_SHARED)
547#define INTEL_DISPLAY_A_PLL_DIVISOR_1	(0x6044 | REGS_SOUTH_SHARED)
548#define INTEL_DISPLAY_B_PLL_DIVISOR_0	(0x6048 | REGS_SOUTH_SHARED)
549#define INTEL_DISPLAY_B_PLL_DIVISOR_1	(0x604c | REGS_SOUTH_SHARED)
550
551// i2c
552#define INTEL_I2C_IO_A					(0x5010 | REGS_SOUTH_SHARED)
553#define INTEL_I2C_IO_B					(0x5014 | REGS_SOUTH_SHARED)
554#define INTEL_I2C_IO_C					(0x5018 | REGS_SOUTH_SHARED)
555#define INTEL_I2C_IO_D					(0x501c | REGS_SOUTH_SHARED)
556#define INTEL_I2C_IO_E					(0x5020 | REGS_SOUTH_SHARED)
557#define INTEL_I2C_IO_F					(0x5024 | REGS_SOUTH_SHARED)
558#define INTEL_I2C_IO_G					(0x5028 | REGS_SOUTH_SHARED)
559#define INTEL_I2C_IO_H					(0x502c | REGS_SOUTH_SHARED)
560
561#define I2C_CLOCK_DIRECTION_MASK		(1 << 0)
562#define I2C_CLOCK_DIRECTION_OUT			(1 << 1)
563#define I2C_CLOCK_VALUE_MASK			(1 << 2)
564#define I2C_CLOCK_VALUE_OUT				(1 << 3)
565#define I2C_CLOCK_VALUE_IN				(1 << 4)
566#define I2C_DATA_DIRECTION_MASK			(1 << 8)
567#define I2C_DATA_DIRECTION_OUT			(1 << 9)
568#define I2C_DATA_VALUE_MASK				(1 << 10)
569#define I2C_DATA_VALUE_OUT				(1 << 11)
570#define I2C_DATA_VALUE_IN				(1 << 12)
571#define I2C_RESERVED					((1 << 13) | (1 << 5))
572
573// TODO: on IronLake this is in the north shared block at 0x41000
574#define INTEL_VGA_DISPLAY_CONTROL		0x71400
575#define VGA_DISPLAY_DISABLED			(1UL << 31)
576
577// LVDS panel
578#define INTEL_PANEL_STATUS				0x61200
579#define PANEL_STATUS_POWER_ON			(1UL << 31)
580#define INTEL_PANEL_CONTROL				0x61204
581#define PANEL_CONTROL_POWER_TARGET_ON	(1UL << 0)
582#define INTEL_PANEL_FIT_CONTROL			0x61230
583#define INTEL_PANEL_FIT_RATIOS			0x61234
584
585// LVDS on IronLake and up
586#define PCH_PANEL_CONTROL				0xc7200
587#define PCH_PANEL_STATUS				0xc7204
588#define PANEL_REGISTER_UNLOCK			(0xabcd << 16)
589#define PCH_LVDS_DETECTED				(1 << 1)
590
591
592// ring buffer commands
593
594#define COMMAND_NOOP					0x00
595#define COMMAND_WAIT_FOR_EVENT			(0x03 << 23)
596#define COMMAND_WAIT_FOR_OVERLAY_FLIP	(1 << 16)
597
598#define COMMAND_FLUSH					(0x04 << 23)
599
600// overlay flip
601#define COMMAND_OVERLAY_FLIP			(0x11 << 23)
602#define COMMAND_OVERLAY_CONTINUE		(0 << 21)
603#define COMMAND_OVERLAY_ON				(1 << 21)
604#define COMMAND_OVERLAY_OFF				(2 << 21)
605#define OVERLAY_UPDATE_COEFFICIENTS		0x1
606
607// 2D acceleration
608#define XY_COMMAND_SOURCE_BLIT			0x54c00006
609#define XY_COMMAND_COLOR_BLIT			0x54000004
610#define XY_COMMAND_SETUP_MONO_PATTERN	0x44400007
611#define XY_COMMAND_SCANLINE_BLIT		0x49400001
612#define COMMAND_COLOR_BLIT				0x50000003
613#define COMMAND_BLIT_RGBA				0x00300000
614
615#define COMMAND_MODE_SOLID_PATTERN		0x80
616#define COMMAND_MODE_CMAP8				0x00
617#define COMMAND_MODE_RGB15				0x02
618#define COMMAND_MODE_RGB16				0x01
619#define COMMAND_MODE_RGB32				0x03
620
621// overlay
622#define INTEL_OVERLAY_UPDATE			0x30000
623#define INTEL_OVERLAY_TEST				0x30004
624#define INTEL_OVERLAY_STATUS			0x30008
625#define INTEL_OVERLAY_EXTENDED_STATUS	0x3000c
626#define INTEL_OVERLAY_GAMMA_5			0x30010
627#define INTEL_OVERLAY_GAMMA_4			0x30014
628#define INTEL_OVERLAY_GAMMA_3			0x30018
629#define INTEL_OVERLAY_GAMMA_2			0x3001c
630#define INTEL_OVERLAY_GAMMA_1			0x30020
631#define INTEL_OVERLAY_GAMMA_0			0x30024
632
633// FDI - Flexible Display Interface, the interface between the (CPU-internal)
634// GPU and the PCH display outputs. Proprietary interface, based on DisplayPort
635// though, so similar link training and all...
636// There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the
637// PCH for each display pipe.
638// FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to
639// transcoder B, so we have the same mapping as with the display pipes.
640#define PCH_FDI_RX_BASE_REGISTER		0xf0000
641#define PCH_FDI_RX_PIPE_OFFSET			0x01000
642
643#define PCH_FDI_RX_CONTROL				0x0c
644#define FDI_RX_CLOCK_MASK				(1 << 4)
645#define FDI_RX_CLOCK_RAW				(0 << 4)
646#define FDI_RX_CLOCK_PCD				(1 << 4)
647
648#define PCH_FDI_RX_TRANS_UNIT_SIZE_1	0x30
649#define PCH_FDI_RX_TRANS_UNIT_SIZE_2	0x38
650#define FDI_RX_TRANS_UNIT_SIZE(x)		((x - 1) << 25)
651#define FDI_RX_TRANS_UNIT_MASK			0x7e000000
652	// Transfer unit size 1 is the primary and fixed transfer unit size,
653	// TU size 2 is the lower power state transfer unit size when using dynamic
654	// refresh rates (we don't do that though).
655
656// CPU Panel Fitters - These are for IronLake and up and are the CPU internal
657// panel fitters.
658#define PCH_PANEL_FITTER_BASE_REGISTER	0x68000
659#define PCH_PANEL_FITTER_PIPE_OFFSET	0x00800
660
661#define PCH_PANEL_FITTER_WINDOW_POS		0x70
662#define PCH_PANEL_FITTER_WINDOW_SIZE	0x74
663#define PCH_PANEL_FITTER_CONTROL		0x80
664#define PCH_PANEL_FITTER_V_SCALE		0x84
665#define PCH_PANEL_FITTER_H_SCALE		0x90
666
667#define PANEL_FITTER_ENABLED			(1 << 31)
668#define PANEL_FITTER_FILTER_MASK		(3 << 23)
669
670struct overlay_scale {
671	uint32 _reserved0 : 3;
672	uint32 horizontal_scale_fraction : 12;
673	uint32 _reserved1 : 1;
674	uint32 horizontal_downscale_factor : 3;
675	uint32 _reserved2 : 1;
676	uint32 vertical_scale_fraction : 12;
677};
678
679#define OVERLAY_FORMAT_RGB15			0x2
680#define OVERLAY_FORMAT_RGB16			0x3
681#define OVERLAY_FORMAT_RGB32			0x1
682#define OVERLAY_FORMAT_YCbCr422			0x8
683#define OVERLAY_FORMAT_YCbCr411			0x9
684#define OVERLAY_FORMAT_YCbCr420			0xc
685
686#define OVERLAY_MIRROR_NORMAL			0x0
687#define OVERLAY_MIRROR_HORIZONTAL		0x1
688#define OVERLAY_MIRROR_VERTICAL			0x2
689
690// The real overlay registers are written to using an update buffer
691
692struct overlay_registers {
693	uint32 buffer_rgb0;
694	uint32 buffer_rgb1;
695	uint32 buffer_u0;
696	uint32 buffer_v0;
697	uint32 buffer_u1;
698	uint32 buffer_v1;
699	// (0x18) OSTRIDE - overlay stride
700	uint16 stride_rgb;
701	uint16 stride_uv;
702	// (0x1c) YRGB_VPH - Y/RGB vertical phase
703	uint16 vertical_phase0_rgb;
704	uint16 vertical_phase1_rgb;
705	// (0x20) UV_VPH - UV vertical phase
706	uint16 vertical_phase0_uv;
707	uint16 vertical_phase1_uv;
708	// (0x24) HORZ_PH - horizontal phase
709	uint16 horizontal_phase_rgb;
710	uint16 horizontal_phase_uv;
711	// (0x28) INIT_PHS - initial phase shift
712	uint32 initial_vertical_phase0_shift_rgb0 : 4;
713	uint32 initial_vertical_phase1_shift_rgb0 : 4;
714	uint32 initial_horizontal_phase_shift_rgb0 : 4;
715	uint32 initial_vertical_phase0_shift_uv : 4;
716	uint32 initial_vertical_phase1_shift_uv : 4;
717	uint32 initial_horizontal_phase_shift_uv : 4;
718	uint32 _reserved0 : 8;
719	// (0x2c) DWINPOS - destination window position
720	uint16 window_left;
721	uint16 window_top;
722	// (0x30) DWINSZ - destination window size
723	uint16 window_width;
724	uint16 window_height;
725	// (0x34) SWIDTH - source width
726	uint16 source_width_rgb;
727	uint16 source_width_uv;
728	// (0x38) SWITDHSW - source width in 8 byte steps
729	uint16 source_bytes_per_row_rgb;
730	uint16 source_bytes_per_row_uv;
731	uint16 source_height_rgb;
732	uint16 source_height_uv;
733	overlay_scale scale_rgb;
734	overlay_scale scale_uv;
735	// (0x48) OCLRC0 - overlay color correction 0
736	uint32 brightness_correction : 8;		// signed, -128 to 127
737	uint32 _reserved1 : 10;
738	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
739	uint32 _reserved2 : 5;
740	// (0x4c) OCLRC1 - overlay color correction 1
741	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
742	uint32 _reserved3 : 6;
743	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
744	uint32 _reserved4 : 5;
745	// (0x50) DCLRKV - destination color key value
746	uint32 color_key_blue : 8;
747	uint32 color_key_green : 8;
748	uint32 color_key_red : 8;
749	uint32 _reserved5 : 8;
750	// (0x54) DCLRKM - destination color key mask
751	uint32 color_key_mask_blue : 8;
752	uint32 color_key_mask_green : 8;
753	uint32 color_key_mask_red : 8;
754	uint32 _reserved6 : 7;
755	uint32 color_key_enabled : 1;
756	// (0x58) SCHRKVH - source chroma key high value
757	uint32 source_chroma_key_high_red : 8;
758	uint32 source_chroma_key_high_blue : 8;
759	uint32 source_chroma_key_high_green : 8;
760	uint32 _reserved7 : 8;
761	// (0x5c) SCHRKVL - source chroma key low value
762	uint32 source_chroma_key_low_red : 8;
763	uint32 source_chroma_key_low_blue : 8;
764	uint32 source_chroma_key_low_green : 8;
765	uint32 _reserved8 : 8;
766	// (0x60) SCHRKEN - source chroma key enable
767	uint32 _reserved9 : 24;
768	uint32 source_chroma_key_red_enabled : 1;
769	uint32 source_chroma_key_blue_enabled : 1;
770	uint32 source_chroma_key_green_enabled : 1;
771	uint32 _reserved10 : 5;
772	// (0x64) OCONFIG - overlay configuration
773	uint32 _reserved11 : 3;
774	uint32 color_control_output_mode : 1;
775	uint32 yuv_to_rgb_bypass : 1;
776	uint32 _reserved12 : 11;
777	uint32 gamma2_enabled : 1;
778	uint32 _reserved13 : 1;
779	uint32 select_pipe : 1;
780	uint32 slot_time : 8;
781	uint32 _reserved14 : 5;
782	// (0x68) OCOMD - overlay command
783	uint32 overlay_enabled : 1;
784	uint32 active_field : 1;
785	uint32 active_buffer : 2;
786	uint32 test_mode : 1;
787	uint32 buffer_field_mode : 1;
788	uint32 _reserved15 : 1;
789	uint32 tv_flip_field_enabled : 1;
790	uint32 _reserved16 : 1;
791	uint32 tv_flip_field_parity : 1;
792	uint32 source_format : 4;
793	uint32 ycbcr422_order : 2;
794	uint32 _reserved18 : 1;
795	uint32 mirroring_mode : 2;
796	uint32 _reserved19 : 13;
797
798	uint32 _reserved20;
799
800	uint32 start_0y;
801	uint32 start_1y;
802	uint32 start_0u;
803	uint32 start_0v;
804	uint32 start_1u;
805	uint32 start_1v;
806	uint32 _reserved21[6];
807#if 0
808	// (0x70) AWINPOS - alpha blend window position
809	uint32 awinpos;
810	// (0x74) AWINSZ - alpha blend window size
811	uint32 awinsz;
812
813	uint32 _reserved21[10];
814#endif
815
816	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
817	// the next two registers switch the usual Y/RGB vs. UV order)
818	uint16 horizontal_scale_uv;
819	uint16 horizontal_scale_rgb;
820	// (0xa4) UVSCALEV - vertical downscale
821	uint16 vertical_scale_uv;
822	uint16 vertical_scale_rgb;
823
824	uint32 _reserved22[86];
825
826	// (0x200) polyphase filter coefficients
827	uint16 vertical_coefficients_rgb[128];
828	uint16 horizontal_coefficients_rgb[128];
829
830	uint32	_reserved23[64];
831
832	// (0x500)
833	uint16 vertical_coefficients_uv[128];
834	uint16 horizontal_coefficients_uv[128];
835};
836
837// i965 overlay support is currently realized using its 3D hardware
838#define INTEL_i965_OVERLAY_STATE_SIZE	36864
839#define INTEL_i965_3D_CONTEXT_SIZE		32768
840
841inline bool
842intel_uses_physical_overlay(intel_shared_info &info)
843{
844	return !info.device_type.InGroup(INTEL_TYPE_Gxx);
845}
846
847
848struct hardware_status {
849	uint32	interrupt_status_register;
850	uint32	_reserved0[3];
851	void*	primary_ring_head_storage;
852	uint32	_reserved1[3];
853	void*	secondary_ring_0_head_storage;
854	void*	secondary_ring_1_head_storage;
855	uint32	_reserved2[2];
856	void*	binning_head_storage;
857	uint32	_reserved3[3];
858	uint32	store[1008];
859};
860
861#endif	/* INTEL_EXTREME_H */
862