1e404297eSAxel Dörfler/*
299756206SAlexander von Gluck IV * Copyright 2006-2016, Haiku, Inc. All Rights Reserved.
3e404297eSAxel Dörfler * Distributed under the terms of the MIT License.
4e404297eSAxel Dörfler *
5e404297eSAxel Dörfler * Authors:
6e404297eSAxel Dörfler *		Axel D��rfler, axeld@pinc-software.de
784b7116dSAlexander von Gluck IV *		Alexander von Gluck, kallisti5@unixzen.com
8e404297eSAxel Dörfler */
9e404297eSAxel Dörfler#ifndef INTEL_EXTREME_H
10e404297eSAxel Dörfler#define INTEL_EXTREME_H
11e404297eSAxel Dörfler
12e404297eSAxel Dörfler
137740a4c1SAxel Dörfler#include "lock.h"
147740a4c1SAxel Dörfler
15e404297eSAxel Dörfler#include <Accelerant.h>
16e404297eSAxel Dörfler#include <Drivers.h>
17e404297eSAxel Dörfler#include <PCI.h>
18e404297eSAxel Dörfler
19c1400fb6SAxel Dörfler#include <edid.h>
20c1400fb6SAxel Dörfler
21e404297eSAxel Dörfler
22020c1aa8SAxel Dörfler#define VENDOR_ID_INTEL			0x8086
23020c1aa8SAxel Dörfler
2484b7116dSAlexander von Gluck IV#define INTEL_FAMILY_MASK	0x00ff0000
2584b7116dSAlexander von Gluck IV#define INTEL_GROUP_MASK	0x00fffff0
2684b7116dSAlexander von Gluck IV#define INTEL_MODEL_MASK	0x00ffffff
2747fba246SAlexander von Gluck IV#define INTEL_TYPE_MASK		0x0000000f
2823843356SAxel Dörfler// families
2984b7116dSAlexander von Gluck IV#define INTEL_FAMILY_7xx	0x00010000	// First Gen
3084b7116dSAlexander von Gluck IV#define INTEL_FAMILY_8xx	0x00020000	// Second Gen
3184b7116dSAlexander von Gluck IV#define INTEL_FAMILY_9xx	0x00040000	// Third Gen +
3284b7116dSAlexander von Gluck IV#define INTEL_FAMILY_SER5	0x00080000	// Intel5 Series
3384b7116dSAlexander von Gluck IV#define INTEL_FAMILY_POVR	0x00100000	// PowerVR (uugh)
3484b7116dSAlexander von Gluck IV#define INTEL_FAMILY_SOC0	0x00200000  // Atom SOC
358d1cb54aSAlexander von Gluck IV#define INTEL_FAMILY_LAKE	0x00400000	// Intel Lakes
3623843356SAxel Dörfler// groups
3784b7116dSAlexander von Gluck IV#define INTEL_GROUP_83x		(INTEL_FAMILY_8xx  | 0x0010)
3884b7116dSAlexander von Gluck IV#define INTEL_GROUP_85x		(INTEL_FAMILY_8xx  | 0x0020)
3984b7116dSAlexander von Gluck IV#define INTEL_GROUP_91x		(INTEL_FAMILY_9xx  | 0x0010)
4084b7116dSAlexander von Gluck IV#define INTEL_GROUP_94x		(INTEL_FAMILY_9xx  | 0x0020)
4184b7116dSAlexander von Gluck IV#define INTEL_GROUP_96x		(INTEL_FAMILY_9xx  | 0x0040)
4284b7116dSAlexander von Gluck IV#define INTEL_GROUP_Gxx		(INTEL_FAMILY_9xx  | 0x0080)
4384b7116dSAlexander von Gluck IV#define INTEL_GROUP_G4x		(INTEL_FAMILY_9xx  | 0x0100)
443cfe2997SAlexander von Gluck IV#define INTEL_GROUP_PIN		(INTEL_FAMILY_9xx  | 0x0200)  // PineView
4553f5bffeSAlexander von Gluck IV#define INTEL_GROUP_ILK		(INTEL_FAMILY_SER5 | 0x0010)  // IronLake
4653f5bffeSAlexander von Gluck IV#define INTEL_GROUP_SNB		(INTEL_FAMILY_SER5 | 0x0020)  // SandyBridge
4753f5bffeSAlexander von Gluck IV#define INTEL_GROUP_IVB		(INTEL_FAMILY_SER5 | 0x0040)  // IvyBridge
4853f5bffeSAlexander von Gluck IV#define INTEL_GROUP_HAS		(INTEL_FAMILY_SER5 | 0x0080)  // Haswell
4984b7116dSAlexander von Gluck IV#define INTEL_GROUP_SLT		(INTEL_FAMILY_POVR | 0x0010)  // Saltwell
5084b7116dSAlexander von Gluck IV#define INTEL_GROUP_FSM		(INTEL_FAMILY_POVR | 0x0020)  // Fu.Silvermont
51fb255821SAlexander von Gluck IV#define INTEL_GROUP_VLV		(INTEL_FAMILY_SOC0 | 0x0010)  // ValleyView
52fb255821SAlexander von Gluck IV#define INTEL_GROUP_CHV		(INTEL_FAMILY_SOC0 | 0x0020)  // CherryView
5352d1e933SAugustin Cavalier#define INTEL_GROUP_BDW		(INTEL_FAMILY_SOC0 | 0x0040)  // Broadwell
548d1cb54aSAlexander von Gluck IV#define INTEL_GROUP_SKY		(INTEL_FAMILY_LAKE | 0x0010)  // SkyLake
558d1cb54aSAlexander von Gluck IV#define INTEL_GROUP_KBY		(INTEL_FAMILY_LAKE | 0x0020)  // KabyLake
5623843356SAxel Dörfler// models
5784b7116dSAlexander von Gluck IV#define INTEL_TYPE_SERVER	0x0004
5884b7116dSAlexander von Gluck IV#define INTEL_TYPE_MOBILE	0x0008
5984b7116dSAlexander von Gluck IV#define INTEL_MODEL_915		(INTEL_GROUP_91x)
6084b7116dSAlexander von Gluck IV#define INTEL_MODEL_915M	(INTEL_GROUP_91x | INTEL_TYPE_MOBILE)
6184b7116dSAlexander von Gluck IV#define INTEL_MODEL_945		(INTEL_GROUP_94x)
6284b7116dSAlexander von Gluck IV#define INTEL_MODEL_945M	(INTEL_GROUP_94x | INTEL_TYPE_MOBILE)
6384b7116dSAlexander von Gluck IV#define INTEL_MODEL_965		(INTEL_GROUP_96x)
6484b7116dSAlexander von Gluck IV#define INTEL_MODEL_965M	(INTEL_GROUP_96x | INTEL_TYPE_MOBILE)
6584b7116dSAlexander von Gluck IV#define INTEL_MODEL_G33		(INTEL_GROUP_Gxx)
6684b7116dSAlexander von Gluck IV#define INTEL_MODEL_G45		(INTEL_GROUP_G4x)
6784b7116dSAlexander von Gluck IV#define INTEL_MODEL_GM45	(INTEL_GROUP_G4x | INTEL_TYPE_MOBILE)
683cfe2997SAlexander von Gluck IV#define INTEL_MODEL_PINE	(INTEL_GROUP_PIN)
693cfe2997SAlexander von Gluck IV#define INTEL_MODEL_PINEM	(INTEL_GROUP_PIN | INTEL_TYPE_MOBILE)
7084b7116dSAlexander von Gluck IV#define INTEL_MODEL_ILKG	(INTEL_GROUP_ILK)
7184b7116dSAlexander von Gluck IV#define INTEL_MODEL_ILKGM	(INTEL_GROUP_ILK | INTEL_TYPE_MOBILE)
7284b7116dSAlexander von Gluck IV#define INTEL_MODEL_SNBG	(INTEL_GROUP_SNB)
7384b7116dSAlexander von Gluck IV#define INTEL_MODEL_SNBGM	(INTEL_GROUP_SNB | INTEL_TYPE_MOBILE)
7484b7116dSAlexander von Gluck IV#define INTEL_MODEL_SNBGS	(INTEL_GROUP_SNB | INTEL_TYPE_SERVER)
7584b7116dSAlexander von Gluck IV#define INTEL_MODEL_IVBG	(INTEL_GROUP_IVB)
7684b7116dSAlexander von Gluck IV#define INTEL_MODEL_IVBGM	(INTEL_GROUP_IVB | INTEL_TYPE_MOBILE)
7784b7116dSAlexander von Gluck IV#define INTEL_MODEL_IVBGS	(INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
7884b7116dSAlexander von Gluck IV#define INTEL_MODEL_HAS		(INTEL_GROUP_HAS)
7984b7116dSAlexander von Gluck IV#define INTEL_MODEL_HASM	(INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
804f059c1fSAugustin Cavalier#define INTEL_MODEL_VLV		(INTEL_GROUP_VLV)
814f059c1fSAugustin Cavalier#define INTEL_MODEL_VLVM	(INTEL_GROUP_VLV | INTEL_TYPE_MOBILE)
8252d1e933SAugustin Cavalier#define INTEL_MODEL_BDW		(INTEL_GROUP_BDW)
8352d1e933SAugustin Cavalier#define INTEL_MODEL_BDWM	(INTEL_GROUP_BDW | INTEL_TYPE_MOBILE)
848d1cb54aSAlexander von Gluck IV#define INTEL_MODEL_SKY		(INTEL_GROUP_SKY)
858d1cb54aSAlexander von Gluck IV#define INTEL_MODEL_SKYM	(INTEL_GROUP_SKY | INTEL_TYPE_MOBILE)
868d1cb54aSAlexander von Gluck IV#define INTEL_MODEL_SKYS	(INTEL_GROUP_SKY | INTEL_TYPE_SERVER)
8797aa078eSAlexander von Gluck IV
887d95ab67SAlexander von Gluck IV#define INTEL_PCH_DEVICE_ID_MASK	0xff80
8992e254d0SAlexander von Gluck IV#define INTEL_PCH_IBX_DEVICE_ID		0x3b00
9092e254d0SAlexander von Gluck IV#define INTEL_PCH_CPT_DEVICE_ID		0x1c00
9192e254d0SAlexander von Gluck IV#define INTEL_PCH_PPT_DEVICE_ID		0x1e00
9292e254d0SAlexander von Gluck IV#define INTEL_PCH_LPT_DEVICE_ID		0x8c00
9387628f17SAlexander von Gluck IV#define INTEL_PCH_LPT_LP_DEVICE_ID	0x9c00
9487628f17SAlexander von Gluck IV#define INTEL_PCH_WPT_DEVICE_ID		0x8c80
9587628f17SAlexander von Gluck IV#define INTEL_PCH_WPT_LP_DEVICE_ID	0x9c80
96c0d4def4SAlexander von Gluck IV#define INTEL_PCH_SPT_DEVICE_ID		0xa100
97c0d4def4SAlexander von Gluck IV#define INTEL_PCH_SPT_LP_DEVICE_ID	0x9d00
9887628f17SAlexander von Gluck IV#define INTEL_PCH_KBP_DEVICE_ID		0xa280
9987628f17SAlexander von Gluck IV#define INTEL_PCH_CNP_DEVICE_ID		0xa300
10087628f17SAlexander von Gluck IV#define INTEL_PCH_CNP_LP_DEVICE_ID	0x9d80
10187628f17SAlexander von Gluck IV#define INTEL_PCH_ICP_DEVICE_ID		0x3480
10292e254d0SAlexander von Gluck IV#define INTEL_PCH_P2X_DEVICE_ID		0x7100
10392e254d0SAlexander von Gluck IV#define INTEL_PCH_P3X_DEVICE_ID		0x7000
10492e254d0SAlexander von Gluck IV
10597aa078eSAlexander von Gluck IV// ValleyView MMIO offset
10697aa078eSAlexander von Gluck IV#define VLV_DISPLAY_BASE		0x180000
107e404297eSAxel Dörfler
108e404297eSAxel Dörfler#define DEVICE_NAME				"intel_extreme"
109e404297eSAxel Dörfler#define INTEL_ACCELERANT_NAME	"intel_extreme.accelerant"
110e404297eSAxel Dörfler
111f0468be3SMichael Lotz// We encode the register block into the value and extract/translate it when
112f0468be3SMichael Lotz// actually accessing.
1131f75663cSMichael Lotz#define REGISTER_BLOCK_COUNT				6
114f0468be3SMichael Lotz#define REGISTER_BLOCK_SHIFT				24
115f0468be3SMichael Lotz#define REGISTER_BLOCK_MASK					0xff000000
116f0468be3SMichael Lotz#define REGISTER_REGISTER_MASK				0x00ffffff
117f0468be3SMichael Lotz#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
118f0468be3SMichael Lotz#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
119f0468be3SMichael Lotz
120f0468be3SMichael Lotz#define REGS_FLAT							(0 << REGISTER_BLOCK_SHIFT)
1211f75663cSMichael Lotz#define REGS_NORTH_SHARED					(1 << REGISTER_BLOCK_SHIFT)
1221f75663cSMichael Lotz#define REGS_NORTH_PIPE_AND_PORT			(2 << REGISTER_BLOCK_SHIFT)
1231f75663cSMichael Lotz#define REGS_NORTH_PLANE_CONTROL			(3 << REGISTER_BLOCK_SHIFT)
1241f75663cSMichael Lotz#define REGS_SOUTH_SHARED					(4 << REGISTER_BLOCK_SHIFT)
1251f75663cSMichael Lotz#define REGS_SOUTH_TRANSCODER_PORT			(5 << REGISTER_BLOCK_SHIFT)
126f0468be3SMichael Lotz
127f0468be3SMichael Lotz// register blocks for (G)MCH/ICH based platforms
128f0468be3SMichael Lotz#define MCH_SHARED_REGISTER_BASE						0x00000
129f0468be3SMichael Lotz#define MCH_PIPE_AND_PORT_REGISTER_BASE					0x60000
130f0468be3SMichael Lotz#define MCH_PLANE_CONTROL_REGISTER_BASE					0x70000
131adc0f76eSAdrien Destugues
132f0468be3SMichael Lotz#define ICH_SHARED_REGISTER_BASE						0x00000
133f0468be3SMichael Lotz#define ICH_PORT_REGISTER_BASE							0x60000
134f0468be3SMichael Lotz
135e747cbe1SAlexander von Gluck IV// PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based
136e747cbe1SAlexander von Gluck IV// setup to a PCH based one, that means anything that used to communicate via
137e747cbe1SAlexander von Gluck IV// (G)MCH registers needs to use different ones on PCH based platforms
138e747cbe1SAlexander von Gluck IV// (Ironlake, SandyBridge, IvyBridge, Some Haswell).
139f0468be3SMichael Lotz#define PCH_NORTH_SHARED_REGISTER_BASE					0x40000
140f0468be3SMichael Lotz#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE			0x60000
141f0468be3SMichael Lotz#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE			0x70000
142f0468be3SMichael Lotz#define PCH_SOUTH_SHARED_REGISTER_BASE					0xc0000
143f0468be3SMichael Lotz#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE		0xe0000
144f0468be3SMichael Lotz
145f0468be3SMichael Lotz
14623843356SAxel Dörflerstruct DeviceType {
14723843356SAxel Dörfler	uint32			type;
14823843356SAxel Dörfler
14923843356SAxel Dörfler	DeviceType(int t)
15023843356SAxel Dörfler	{
15123843356SAxel Dörfler		type = t;
15223843356SAxel Dörfler	}
15323843356SAxel Dörfler
15423843356SAxel Dörfler	DeviceType& operator=(int t)
15523843356SAxel Dörfler	{
15623843356SAxel Dörfler		type = t;
15723843356SAxel Dörfler		return *this;
15823843356SAxel Dörfler	}
15923843356SAxel Dörfler
16023843356SAxel Dörfler	bool InFamily(uint32 family) const
16123843356SAxel Dörfler	{
16284b7116dSAlexander von Gluck IV		return (type & INTEL_FAMILY_MASK) == family;
16323843356SAxel Dörfler	}
16423843356SAxel Dörfler
16523843356SAxel Dörfler	bool InGroup(uint32 group) const
16623843356SAxel Dörfler	{
16784b7116dSAlexander von Gluck IV		return (type & INTEL_GROUP_MASK) == group;
16823843356SAxel Dörfler	}
16923843356SAxel Dörfler
17023843356SAxel Dörfler	bool IsModel(uint32 model) const
17123843356SAxel Dörfler	{
17284b7116dSAlexander von Gluck IV		return (type & INTEL_MODEL_MASK) == model;
17323843356SAxel Dörfler	}
1749e2e0d8dSMichael Lotz
17550f0b3feSAlexander von Gluck IV	bool IsMobile() const
17650f0b3feSAlexander von Gluck IV	{
17747fba246SAlexander von Gluck IV		return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE;
17850f0b3feSAlexander von Gluck IV	}
17950f0b3feSAlexander von Gluck IV
18050f0b3feSAlexander von Gluck IV	bool SupportsHDMI() const
18150f0b3feSAlexander von Gluck IV	{
18253f5bffeSAlexander von Gluck IV		return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5)
18353f5bffeSAlexander von Gluck IV			|| InFamily(INTEL_FAMILY_SOC0);
18450f0b3feSAlexander von Gluck IV	}
18550f0b3feSAlexander von Gluck IV
186ca95e9daSAlexander von Gluck IV	bool HasDDI() const
187ca95e9daSAlexander von Gluck IV	{
188ca95e9daSAlexander von Gluck IV		// Intel Digital Display Interface
189ca95e9daSAlexander von Gluck IV		return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8);
190ca95e9daSAlexander von Gluck IV	}
191ca95e9daSAlexander von Gluck IV
192e2e5daf2SAlexander von Gluck IV	int Generation() const
193e2e5daf2SAlexander von Gluck IV	{
194e2e5daf2SAlexander von Gluck IV		if (InFamily(INTEL_FAMILY_7xx))
195e2e5daf2SAlexander von Gluck IV			return 1;
196e2e5daf2SAlexander von Gluck IV		if (InFamily(INTEL_FAMILY_8xx))
197e2e5daf2SAlexander von Gluck IV			return 2;
198e2e5daf2SAlexander von Gluck IV		if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
1993cfe2997SAlexander von Gluck IV				|| IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN))
200e2e5daf2SAlexander von Gluck IV			return 3;
201e2e5daf2SAlexander von Gluck IV		if (InFamily(INTEL_FAMILY_9xx))
202e2e5daf2SAlexander von Gluck IV			return 4;
203e2e5daf2SAlexander von Gluck IV		if (InGroup(INTEL_GROUP_ILK))
204e2e5daf2SAlexander von Gluck IV			return 5;
205e2e5daf2SAlexander von Gluck IV		if (InGroup(INTEL_GROUP_SNB))
206e2e5daf2SAlexander von Gluck IV			return 6;
207fb255821SAlexander von Gluck IV		if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV))
208e2e5daf2SAlexander von Gluck IV			return 7;
20952d1e933SAugustin Cavalier		if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW))
210e2e5daf2SAlexander von Gluck IV			return 8;
211164e4f8dSAugustin Cavalier		if (InFamily(INTEL_FAMILY_LAKE))
212fb255821SAlexander von Gluck IV			return 9;
213e2e5daf2SAlexander von Gluck IV
214e2e5daf2SAlexander von Gluck IV		// Generation 0 means somethins is wrong :-)
215e2e5daf2SAlexander von Gluck IV		return 0;
216e2e5daf2SAlexander von Gluck IV	}
21723843356SAxel Dörfler};
21823843356SAxel Dörfler
21992e254d0SAlexander von Gluck IVenum pch_info {
22092e254d0SAlexander von Gluck IV	INTEL_PCH_NONE = 0,		// No PCH present
22192e254d0SAlexander von Gluck IV	INTEL_PCH_IBX,			// Ibexpeak
22292e254d0SAlexander von Gluck IV	INTEL_PCH_CPT,			// Cougarpoint
22392e254d0SAlexander von Gluck IV	INTEL_PCH_LPT,			// Lynxpoint
22487628f17SAlexander von Gluck IV	INTEL_PCH_SPT,			// SunrisePoint
22587628f17SAlexander von Gluck IV	INTEL_PCH_KBP,			// KabyLake
22687628f17SAlexander von Gluck IV	INTEL_PCH_CNP,			// CannonLake
22787628f17SAlexander von Gluck IV	INTEL_PCH_ICP,			// IceLake
22892e254d0SAlexander von Gluck IV	INTEL_PCH_NOP
22992e254d0SAlexander von Gluck IV};
23092e254d0SAlexander von Gluck IV
231e404297eSAxel Dörfler// info about PLL on graphics card
232e404297eSAxel Dörflerstruct pll_info {
23308ef16abSAxel Dörfler	uint32			reference_frequency;
23408ef16abSAxel Dörfler	uint32			max_frequency;
23508ef16abSAxel Dörfler	uint32			min_frequency;
23608ef16abSAxel Dörfler	uint32			divisor_register;
237e404297eSAxel Dörfler};
238e404297eSAxel Dörfler
2397740a4c1SAxel Dörflerstruct ring_buffer {
24008ef16abSAxel Dörfler	struct lock		lock;
24108ef16abSAxel Dörfler	uint32			register_base;
24208ef16abSAxel Dörfler	uint32			offset;
24308ef16abSAxel Dörfler	uint32			size;
24408ef16abSAxel Dörfler	uint32			position;
2458818c505SAxel Dörfler	uint32			space_left;
24623843356SAxel Dörfler	uint8*			base;
2477740a4c1SAxel Dörfler};
2487740a4c1SAxel Dörfler
24922d4db92SAxel Dörflerstruct overlay_registers;
25022d4db92SAxel Dörfler
251e404297eSAxel Dörflerstruct intel_shared_info {
252e404297eSAxel Dörfler	area_id			mode_list_area;		// area containing display mode list
253e404297eSAxel Dörfler	uint32			mode_count;
254e404297eSAxel Dörfler
2553d1bd895SAlexander von Gluck IV	display_mode	panel_mode;			// VBIOS VBT panel mode
256e404297eSAxel Dörfler	uint32			bytes_per_row;
2572ace35edSAxel Dörfler	uint32			bits_per_pixel;
258e404297eSAxel Dörfler	uint32			dpms_mode;
259e404297eSAxel Dörfler
2603d1bd895SAlexander von Gluck IV	area_id			registers_area;		// area of memory mapped registers
261f0468be3SMichael Lotz	uint32			register_blocks[REGISTER_BLOCK_COUNT];
26297aa078eSAlexander von Gluck IV
26323843356SAxel Dörfler	uint8*			status_page;
264cdfd124bSAxel Dörfler	phys_addr_t		physical_status_page;
26523843356SAxel Dörfler	uint8*			graphics_memory;
266cdfd124bSAxel Dörfler	phys_addr_t		physical_graphics_memory;
267e404297eSAxel Dörfler	uint32			graphics_memory_size;
268020c1aa8SAxel Dörfler
2691c34b9b1SAxel Dörfler	addr_t			frame_buffer;
2705da6291bSAxel Dörfler	uint32			frame_buffer_offset;
2715da6291bSAxel Dörfler
272e6fefa6cSAlexander von Gluck IV	uint32			fdi_link_frequency;	// In Mhz
273e6fefa6cSAlexander von Gluck IV
274ef726c68SAdrien Destugues	bool			got_vbt;
275ef726c68SAdrien Destugues	bool			single_head_locked;
276ef726c68SAdrien Destugues
277973d499eSAxel Dörfler	struct lock		accelerant_lock;
278973d499eSAxel Dörfler	struct lock		engine_lock;
279973d499eSAxel Dörfler
2807740a4c1SAxel Dörfler	ring_buffer		primary_ring_buffer;
2817740a4c1SAxel Dörfler
282b907a5acSAxel Dörfler	int32			overlay_channel_used;
283f4c4106aSAxel Dörfler	bool			overlay_active;
28413af65c4SAdrien Destugues	uintptr_t		overlay_token;
285cdfd124bSAxel Dörfler	phys_addr_t		physical_overlay_registers;
286c88e5e41SAxel Dörfler	uint32			overlay_offset;
287b907a5acSAxel Dörfler
2887902c46cSAxel Dörfler	bool			hardware_cursor_enabled;
2895af5259cSAxel Dörfler	sem_id			vblank_sem;
2905af5259cSAxel Dörfler
29123843356SAxel Dörfler	uint8*			cursor_memory;
292cdfd124bSAxel Dörfler	phys_addr_t		physical_cursor_memory;
2937d5957dfSAxel Dörfler	uint32			cursor_buffer_offset;
2947d5957dfSAxel Dörfler	uint32			cursor_format;
2957d5957dfSAxel Dörfler	bool			cursor_visible;
2967d5957dfSAxel Dörfler	uint16			cursor_hot_x;
2977d5957dfSAxel Dörfler	uint16			cursor_hot_y;
2987d5957dfSAxel Dörfler
29923843356SAxel Dörfler	DeviceType		device_type;
300020c1aa8SAxel Dörfler	char			device_identifier[32];
301e404297eSAxel Dörfler	struct pll_info	pll_info;
302c1400fb6SAxel Dörfler
30392e254d0SAlexander von Gluck IV	enum pch_info	pch_info;
30492e254d0SAlexander von Gluck IV
305c1400fb6SAxel Dörfler	edid1_info		vesa_edid_info;
306c1400fb6SAxel Dörfler	bool			has_vesa_edid_info;
307e404297eSAxel Dörfler};
308e404297eSAxel Dörfler
30900e0982fSAlexander von Gluck IVenum pipe_index {
31000e0982fSAlexander von Gluck IV    INTEL_PIPE_ANY,
31100e0982fSAlexander von Gluck IV    INTEL_PIPE_A,
31200e0982fSAlexander von Gluck IV    INTEL_PIPE_B
31300e0982fSAlexander von Gluck IV};
31400e0982fSAlexander von Gluck IV
315e404297eSAxel Dörfler//----------------- ioctl() interface ----------------
316e404297eSAxel Dörfler
317e404297eSAxel Dörfler// magic code for ioctls
318e404297eSAxel Dörfler#define INTEL_PRIVATE_DATA_MAGIC		'itic'
319e404297eSAxel Dörfler
320e404297eSAxel Dörfler// list ioctls
321e404297eSAxel Dörflerenum {
322e404297eSAxel Dörfler	INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
323e404297eSAxel Dörfler
324e404297eSAxel Dörfler	INTEL_GET_DEVICE_NAME,
3255da6291bSAxel Dörfler	INTEL_ALLOCATE_GRAPHICS_MEMORY,
3265da6291bSAxel Dörfler	INTEL_FREE_GRAPHICS_MEMORY
327e404297eSAxel Dörfler};
328e404297eSAxel Dörfler
329e404297eSAxel Dörfler// retrieve the area_id of the kernel/accelerant shared info
330e404297eSAxel Dörflerstruct intel_get_private_data {
331e404297eSAxel Dörfler	uint32	magic;				// magic number
332e404297eSAxel Dörfler	area_id	shared_info_area;
333e404297eSAxel Dörfler};
334e404297eSAxel Dörfler
335e404297eSAxel Dörfler// allocate graphics memory
336e404297eSAxel Dörflerstruct intel_allocate_graphics_memory {
337e404297eSAxel Dörfler	uint32	magic;
338e404297eSAxel Dörfler	uint32	size;
3391c34b9b1SAxel Dörfler	uint32	alignment;
3401c34b9b1SAxel Dörfler	uint32	flags;
341c162f52eSJérôme Duval	addr_t	buffer_base;
342e404297eSAxel Dörfler};
343e404297eSAxel Dörfler
344e404297eSAxel Dörfler// free graphics memory
345e404297eSAxel Dörflerstruct intel_free_graphics_memory {
346e404297eSAxel Dörfler	uint32 	magic;
347c162f52eSJérôme Duval	addr_t	buffer_base;
348e404297eSAxel Dörfler};
349e404297eSAxel Dörfler
350e404297eSAxel Dörfler//----------------------------------------------------------
351e404297eSAxel Dörfler// Register definitions, taken from X driver
352e404297eSAxel Dörfler
353f1973028SAxel Dörfler// PCI bridge memory management
354fa1d5933SAlexander von Gluck IV#define INTEL_GRAPHICS_MEMORY_CONTROL	0x52		// i830+
355fa1d5933SAlexander von Gluck IV
356c788baedSMichael Lotz	// GGC - (G)MCH Graphics Control Register
357d75c8820SAxel Dörfler#define MEMORY_CONTROL_ENABLED			0x0004
358d75c8820SAxel Dörfler#define MEMORY_MASK						0x0001
3598b20f2e4SBrecht Machiels#define STOLEN_MEMORY_MASK				0x00f0
360c88e5e41SAxel Dörfler#define i965_GTT_MASK					0x000e
361c88e5e41SAxel Dörfler#define G33_GTT_MASK					0x0300
3628b20f2e4SBrecht Machiels#define G4X_GTT_MASK					0x0f00	// GGMS (GSM Memory Size) mask
363dfdfbd3eSBrecht Machiels
364f1973028SAxel Dörfler// models i830 and up
365f1973028SAxel Dörfler#define i830_LOCAL_MEMORY_ONLY			0x10
366f1973028SAxel Dörfler#define i830_STOLEN_512K				0x20
367f1973028SAxel Dörfler#define i830_STOLEN_1M					0x30
368f1973028SAxel Dörfler#define i830_STOLEN_8M					0x40
369c88e5e41SAxel Dörfler#define i830_FRAME_BUFFER_64M			0x01
370c88e5e41SAxel Dörfler#define i830_FRAME_BUFFER_128M			0x00
371f1973028SAxel Dörfler
372f1973028SAxel Dörfler// models i855 and up
373f1973028SAxel Dörfler#define i855_STOLEN_MEMORY_1M			0x10
374f1973028SAxel Dörfler#define i855_STOLEN_MEMORY_4M			0x20
375f1973028SAxel Dörfler#define i855_STOLEN_MEMORY_8M			0x30
376f1973028SAxel Dörfler#define i855_STOLEN_MEMORY_16M			0x40
377f1973028SAxel Dörfler#define i855_STOLEN_MEMORY_32M			0x50
378f1973028SAxel Dörfler#define i855_STOLEN_MEMORY_48M			0x60
379f1973028SAxel Dörfler#define i855_STOLEN_MEMORY_64M			0x70
380c88e5e41SAxel Dörfler#define i855_STOLEN_MEMORY_128M			0x80
381c88e5e41SAxel Dörfler#define i855_STOLEN_MEMORY_256M			0x90
382f1973028SAxel Dörfler
3838b20f2e4SBrecht Machiels#define G4X_STOLEN_MEMORY_96MB			0xa0	// GMS - Graphics Mode Select
3848b20f2e4SBrecht Machiels#define G4X_STOLEN_MEMORY_160MB			0xb0
3858b20f2e4SBrecht Machiels#define G4X_STOLEN_MEMORY_224MB			0xc0
3868b20f2e4SBrecht Machiels#define G4X_STOLEN_MEMORY_352MB			0xd0
3878b20f2e4SBrecht Machiels
388e436a27eSMichael Lotz// SandyBridge (SNB)
389e436a27eSMichael Lotz
390fb255821SAlexander von Gluck IV#define SNB_GRAPHICS_MEMORY_CONTROL		0x50
391fb255821SAlexander von Gluck IV
392e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_MASK			0xf8
393e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_32MB			(1 << 3)
394e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_64MB			(2 << 3)
395e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_96MB			(3 << 3)
396e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_128MB			(4 << 3)
397e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_160MB			(5 << 3)
398e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_192MB			(6 << 3)
399e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_224MB			(7 << 3)
400e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_256MB			(8 << 3)
401e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_288MB			(9 << 3)
402e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_320MB			(10 << 3)
403e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_352MB			(11 << 3)
404e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_384MB			(12 << 3)
405e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_416MB			(13 << 3)
406e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_448MB			(14 << 3)
407e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_480MB			(15 << 3)
408e436a27eSMichael Lotz#define SNB_STOLEN_MEMORY_512MB			(16 << 3)
409e436a27eSMichael Lotz
410e436a27eSMichael Lotz#define SNB_GTT_SIZE_MASK				(3 << 8)
411e436a27eSMichael Lotz#define SNB_GTT_SIZE_NONE				(0 << 8)
412e436a27eSMichael Lotz#define SNB_GTT_SIZE_1MB				(1 << 8)
413e436a27eSMichael Lotz#define SNB_GTT_SIZE_2MB				(2 << 8)
4148b20f2e4SBrecht Machiels
4155af5259cSAxel Dörfler// graphics page translation table
4167740a4c1SAxel Dörfler#define INTEL_PAGE_TABLE_CONTROL		0x02020
417d75c8820SAxel Dörfler#define PAGE_TABLE_ENABLED				0x00000001
4187740a4c1SAxel Dörfler#define INTEL_PAGE_TABLE_ERROR			0x02024
4197740a4c1SAxel Dörfler#define INTEL_HARDWARE_STATUS_PAGE		0x02080
420d75c8820SAxel Dörfler#define i915_GTT_BASE					0x1c
421e7e32550SAxel Dörfler#define i830_GTT_BASE					0x10000	// (- 0x2ffff)
422e7e32550SAxel Dörfler#define i830_GTT_SIZE					0x20000
423e7e32550SAxel Dörfler#define i965_GTT_BASE					0x80000	// (- 0xfffff)
424e7e32550SAxel Dörfler#define i965_GTT_SIZE					0x80000
425c88e5e41SAxel Dörfler#define i965_GTT_128K					(2 << 1)
426c88e5e41SAxel Dörfler#define i965_GTT_256K					(1 << 1)
427c88e5e41SAxel Dörfler#define i965_GTT_512K					(0 << 1)
428c88e5e41SAxel Dörfler#define G33_GTT_1M						(1 << 8)
429c88e5e41SAxel Dörfler#define G33_GTT_2M						(2 << 8)
4308b20f2e4SBrecht Machiels#define G4X_GTT_NONE					0x000	// GGMS - GSM Memory Size
4318b20f2e4SBrecht Machiels#define G4X_GTT_1M_NO_IVT				0x100	// no Intel Virtualization Tech.
4328b20f2e4SBrecht Machiels#define G4X_GTT_2M_NO_IVT				0x300
4338b20f2e4SBrecht Machiels#define G4X_GTT_2M_IVT					0x900	// with Intel Virt. Tech.
4348b20f2e4SBrecht Machiels#define G4X_GTT_3M_IVT					0xa00
4358b20f2e4SBrecht Machiels#define G4X_GTT_4M_IVT					0xb00
436dfdfbd3eSBrecht Machiels
437dfdfbd3eSBrecht Machiels
438ccb666bcSAxel Dörfler#define GTT_ENTRY_VALID					0x01
439ccb666bcSAxel Dörfler#define GTT_ENTRY_LOCAL_MEMORY			0x02
4404dfa9e42SAxel Dörfler#define GTT_PAGE_SHIFT					12
4417740a4c1SAxel Dörfler
4425af5259cSAxel Dörfler
4435af5259cSAxel Dörfler// ring buffer
4447740a4c1SAxel Dörfler#define INTEL_PRIMARY_RING_BUFFER		0x02030
4457740a4c1SAxel Dörfler#define INTEL_SECONDARY_RING_BUFFER_0	0x02100
4467740a4c1SAxel Dörfler#define INTEL_SECONDARY_RING_BUFFER_1	0x02110
4477740a4c1SAxel Dörfler// offsets for the ring buffer base registers above
4487740a4c1SAxel Dörfler#define RING_BUFFER_TAIL				0x0
4497740a4c1SAxel Dörfler#define RING_BUFFER_HEAD				0x4
4507740a4c1SAxel Dörfler#define RING_BUFFER_START				0x8
4517740a4c1SAxel Dörfler#define RING_BUFFER_CONTROL				0xc
45278fa3affSAxel Dörfler#define INTEL_RING_BUFFER_SIZE_MASK		0x001ff000
4535462d440SAxel Dörfler#define INTEL_RING_BUFFER_HEAD_MASK		0x001ffffc
4547740a4c1SAxel Dörfler#define INTEL_RING_BUFFER_ENABLED		1
4557740a4c1SAxel Dörfler
456f0468be3SMichael Lotz// interrupts
4574254fc37SMichael Lotz#define INTEL_INTERRUPT_ENABLED			0x020a0
4584254fc37SMichael Lotz#define INTEL_INTERRUPT_IDENTITY		0x020a4
4594254fc37SMichael Lotz#define INTEL_INTERRUPT_MASK			0x020a8
4604254fc37SMichael Lotz#define INTEL_INTERRUPT_STATUS			0x020ac
461f0468be3SMichael Lotz#define INTERRUPT_VBLANK_PIPEA			(1 << 7)
462f0468be3SMichael Lotz#define INTERRUPT_VBLANK_PIPEB			(1 << 5)
4631f75663cSMichael Lotz
4641f75663cSMichael Lotz// PCH interrupts
4651f75663cSMichael Lotz#define PCH_INTERRUPT_STATUS			0x44000
4661f75663cSMichael Lotz#define PCH_INTERRUPT_MASK				0x44004
4671f75663cSMichael Lotz#define PCH_INTERRUPT_IDENTITY			0x44008
4681f75663cSMichael Lotz#define PCH_INTERRUPT_ENABLED			0x4400c
469187ad82aSAdrien Destugues
4700f94784aSAdrien Destugues#define PCH_INTERRUPT_VBLANK_PIPEA		(1 << 0)
4710f94784aSAdrien Destugues#define PCH_INTERRUPT_VBLANK_PIPEB		(1 << 5)
4720f94784aSAdrien Destugues#define PCH_INTERRUPT_VBLANK_PIPEC		(1 << 10)
4730f94784aSAdrien Destugues
474187ad82aSAdrien Destugues// SandyBridge had only two pipes, and things were shuffled aroud again with
475187ad82aSAdrien Destugues// the introduction of pipe C.
4760f94784aSAdrien Destugues#define PCH_INTERRUPT_VBLANK_PIPEA_SNB		(1 << 7)
4770f94784aSAdrien Destugues#define PCH_INTERRUPT_VBLANK_PIPEB_SNB		(1 << 15)
478187ad82aSAdrien Destugues#define PCH_INTERRUPT_GLOBAL_SNB			(1 << 31)
479f0468be3SMichael Lotz
48037b903fbSAlexander von Gluck IV// graphics port control
4812d5f339dSAxel Dörfler#define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
4822d5f339dSAxel Dörfler#define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
4832d5f339dSAxel Dörfler#define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
4842d5f339dSAxel Dörfler#define DISPLAY_MONITOR_MODE_MASK		(3UL << 10)
4852d5f339dSAxel Dörfler#define DISPLAY_MONITOR_ON				0
4862d5f339dSAxel Dörfler#define DISPLAY_MONITOR_SUSPEND			(1UL << 10)
4872d5f339dSAxel Dörfler#define DISPLAY_MONITOR_STAND_BY		(2UL << 10)
4882d5f339dSAxel Dörfler#define DISPLAY_MONITOR_OFF				(3UL << 10)
4892d5f339dSAxel Dörfler#define DISPLAY_MONITOR_POLARITY_MASK	(3UL << 3)
4902d5f339dSAxel Dörfler#define DISPLAY_MONITOR_POSITIVE_HSYNC	(1UL << 3)
4912d5f339dSAxel Dörfler#define DISPLAY_MONITOR_POSITIVE_VSYNC	(2UL << 3)
49237b903fbSAlexander von Gluck IV#define DISPLAY_MONITOR_PORT_DETECTED	(1UL << 2) // TMDS/DisplayPort only
49337b903fbSAlexander von Gluck IV
4942d5f339dSAxel Dörfler#define LVDS_POST2_RATE_SLOW			14 // PLL Divisors
49523843356SAxel Dörfler#define LVDS_POST2_RATE_FAST			7
496d35a52e8SAlexander von Gluck IV#define LVDS_B0B3_POWER_MASK			(3UL << 2)
497d35a52e8SAlexander von Gluck IV#define LVDS_B0B3_POWER_UP				(3UL << 2)
498d35a52e8SAlexander von Gluck IV#define LVDS_CLKB_POWER_MASK			(3UL << 4)
499d35a52e8SAlexander von Gluck IV#define LVDS_CLKB_POWER_UP				(3UL << 4)
500d35a52e8SAlexander von Gluck IV#define LVDS_A3_POWER_MASK				(3UL << 6)
501d35a52e8SAlexander von Gluck IV#define LVDS_A3_POWER_UP				(3UL << 6)
502d35a52e8SAlexander von Gluck IV#define LVDS_A0A2_CLKA_POWER_UP			(3UL << 8)
503d35a52e8SAlexander von Gluck IV#define LVDS_BORDER_ENABLE				(1UL << 15)
504d35a52e8SAlexander von Gluck IV#define LVDS_HSYNC_POLARITY				(1UL << 20)
505d35a52e8SAlexander von Gluck IV#define LVDS_VSYNC_POLARITY				(1UL << 21)
506d35a52e8SAlexander von Gluck IV#define LVDS_18BIT_DITHER				(1UL << 25)
507d35a52e8SAlexander von Gluck IV#define LVDS_PORT_EN					(1UL << 31)
508f979e62eSAlexander von Gluck IV
5092d5f339dSAxel Dörfler// PLL flags
5102d5f339dSAxel Dörfler#define DISPLAY_PLL_ENABLED				(1UL << 31)
5112d5f339dSAxel Dörfler#define DISPLAY_PLL_2X_CLOCK			(1UL << 30)
5122d5f339dSAxel Dörfler#define DISPLAY_PLL_SYNC_LOCK_ENABLED	(1UL << 29)
5132d5f339dSAxel Dörfler#define DISPLAY_PLL_NO_VGA_CONTROL		(1UL << 28)
51492bcdd79SAlexander von Gluck IV#define DISPLAY_PLL_MODE_NORMAL			(1UL << 26)
51561fbdb06SAlexander von Gluck IV#define DISPLAY_PLL_MODE_LVDS			(2UL << 26)
5162d5f339dSAxel Dörfler#define DISPLAY_PLL_DIVIDE_HIGH			(1UL << 24)
5172d5f339dSAxel Dörfler#define DISPLAY_PLL_DIVIDE_4X			(1UL << 23)
5182d5f339dSAxel Dörfler#define DISPLAY_PLL_POST1_DIVIDE_2		(1UL << 21)
5192d5f339dSAxel Dörfler#define DISPLAY_PLL_POST1_DIVISOR_MASK	0x001f0000
5202d5f339dSAxel Dörfler#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK	0x00ff0000
5212f4d9fdbSBrecht Machiels#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK  0x00ff8000
5222d5f339dSAxel Dörfler#define DISPLAY_PLL_POST1_DIVISOR_SHIFT	16
5232f4d9fdbSBrecht Machiels#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT	15
5242d5f339dSAxel Dörfler#define DISPLAY_PLL_DIVISOR_1			(1UL << 8)
5252d5f339dSAxel Dörfler#define DISPLAY_PLL_N_DIVISOR_MASK		0x001f0000
5262f4d9fdbSBrecht Machiels#define DISPLAY_PLL_IGD_N_DIVISOR_MASK	0x00ff0000
5272d5f339dSAxel Dörfler#define DISPLAY_PLL_M1_DIVISOR_MASK		0x00001f00
5282d5f339dSAxel Dörfler#define DISPLAY_PLL_M2_DIVISOR_MASK		0x0000001f
5292f4d9fdbSBrecht Machiels#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK	0x000000ff
5302d5f339dSAxel Dörfler#define DISPLAY_PLL_N_DIVISOR_SHIFT		16
5312d5f339dSAxel Dörfler#define DISPLAY_PLL_M1_DIVISOR_SHIFT	8
5322d5f339dSAxel Dörfler#define DISPLAY_PLL_M2_DIVISOR_SHIFT	0
5332d5f339dSAxel Dörfler#define DISPLAY_PLL_PULSE_PHASE_SHIFT	9
5342d5f339dSAxel Dörfler
535f0468be3SMichael Lotz// display
53661fbdb06SAlexander von Gluck IV
53761fbdb06SAlexander von Gluck IV#define INTEL_DISPLAY_OFFSET			0x1000
53861fbdb06SAlexander von Gluck IV
539adc0f76eSAdrien Destugues#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_NORTH_PIPE_AND_PORT)
540adc0f76eSAdrien Destugues#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_NORTH_PIPE_AND_PORT)
541adc0f76eSAdrien Destugues#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_NORTH_PIPE_AND_PORT)
542adc0f76eSAdrien Destugues#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_NORTH_PIPE_AND_PORT)
543adc0f76eSAdrien Destugues#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_NORTH_PIPE_AND_PORT)
544adc0f76eSAdrien Destugues#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_NORTH_PIPE_AND_PORT)
545adc0f76eSAdrien Destugues#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_NORTH_PIPE_AND_PORT)
546adc0f76eSAdrien Destugues#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_NORTH_PIPE_AND_PORT)
547adc0f76eSAdrien Destugues#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_NORTH_PIPE_AND_PORT)
548adc0f76eSAdrien Destugues#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_NORTH_PIPE_AND_PORT)
549adc0f76eSAdrien Destugues#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_NORTH_PIPE_AND_PORT)
550adc0f76eSAdrien Destugues#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_NORTH_PIPE_AND_PORT)
5512d004e3eSMichael Lotz
5522d004e3eSMichael Lotz#define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
5532d004e3eSMichael Lotz#define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)
554f0468be3SMichael Lotz
55592e254d0SAlexander von Gluck IV// Cougar Point transcoder pipe selection
55692e254d0SAlexander von Gluck IV#define  PORT_TRANS_A_SEL_CPT			0
55792e254d0SAlexander von Gluck IV#define  PORT_TRANS_B_SEL_CPT			(1<<29)
55892e254d0SAlexander von Gluck IV#define  PORT_TRANS_C_SEL_CPT			(2<<29)
55992e254d0SAlexander von Gluck IV#define  PORT_TRANS_SEL_MASK			(3<<29)
56092e254d0SAlexander von Gluck IV
561d35a52e8SAlexander von Gluck IV// on PCH we also have to set the transcoder
562c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_A_HTOTAL		(0x0000 | REGS_SOUTH_TRANSCODER_PORT)
563c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_A_HBLANK		(0x0004 | REGS_SOUTH_TRANSCODER_PORT)
564c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_A_HSYNC		(0x0008 | REGS_SOUTH_TRANSCODER_PORT)
565c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_A_VTOTAL		(0x000c | REGS_SOUTH_TRANSCODER_PORT)
566c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_A_VBLANK		(0x0010 | REGS_SOUTH_TRANSCODER_PORT)
567c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_A_VSYNC		(0x0014 | REGS_SOUTH_TRANSCODER_PORT)
568c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_B_HTOTAL		(0x1000 | REGS_SOUTH_TRANSCODER_PORT)
569c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_B_HBLANK		(0x1004 | REGS_SOUTH_TRANSCODER_PORT)
570c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_B_HSYNC		(0x1008 | REGS_SOUTH_TRANSCODER_PORT)
571c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_B_VTOTAL		(0x100c | REGS_SOUTH_TRANSCODER_PORT)
572c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_B_VBLANK		(0x1010 | REGS_SOUTH_TRANSCODER_PORT)
573c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_B_VSYNC		(0x1014 | REGS_SOUTH_TRANSCODER_PORT)
574c0d4def4SAlexander von Gluck IV
575c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_A_IMAGE_SIZE	(0x001c | REGS_SOUTH_TRANSCODER_PORT)
576c0d4def4SAlexander von Gluck IV#define INTEL_TRANSCODER_B_IMAGE_SIZE	(0x101c | REGS_SOUTH_TRANSCODER_PORT)
577d35a52e8SAlexander von Gluck IV
5788fe50548SAlexander von Gluck IV// TODO: Is there consolidation that could happen here with digital ports?
5798fe50548SAlexander von Gluck IV
58050f0b3feSAlexander von Gluck IV#define INTEL_ANALOG_PORT				(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
58150f0b3feSAlexander von Gluck IV#define INTEL_DIGITAL_PORT_A			(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
58250f0b3feSAlexander von Gluck IV#define INTEL_DIGITAL_PORT_B			(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
58350f0b3feSAlexander von Gluck IV#define INTEL_DIGITAL_PORT_C			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
58450f0b3feSAlexander von Gluck IV#define INTEL_DIGITAL_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
58550f0b3feSAlexander von Gluck IV
586e747cbe1SAlexander von Gluck IV#define INTEL_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
587e747cbe1SAlexander von Gluck IV#define INTEL_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
58850f0b3feSAlexander von Gluck IV
58950f0b3feSAlexander von Gluck IV#define PCH_HDMI_PORT_B					(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
59050f0b3feSAlexander von Gluck IV#define PCH_HDMI_PORT_C					(0x1150 | REGS_SOUTH_TRANSCODER_PORT)
59150f0b3feSAlexander von Gluck IV#define PCH_HDMI_PORT_D					(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
59250f0b3feSAlexander von Gluck IV
593202ffc8cSAlexander von Gluck IV#define GEN4_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
594202ffc8cSAlexander von Gluck IV#define GEN4_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
595202ffc8cSAlexander von Gluck IV#define CHV_HDMI_PORT_D					(0x116C | REGS_SOUTH_TRANSCODER_PORT)
596bc5cad73SAlexander von Gluck IV
597ca95e9daSAlexander von Gluck IV// DDI Buffer Control (This replaces DP on Haswell+)
598ca95e9daSAlexander von Gluck IV#define DDI_BUF_CTL_A					(0x4000 | REGS_NORTH_PIPE_AND_PORT)
599ca95e9daSAlexander von Gluck IV#define DDI_BUF_CTL_B					(0x4100 | REGS_NORTH_PIPE_AND_PORT)
6008fe50548SAlexander von Gluck IV#define DDI_BUF_CTL_C					(0x4200 | REGS_NORTH_PIPE_AND_PORT)
6018fe50548SAlexander von Gluck IV#define DDI_BUF_CTL_D					(0x4300 | REGS_NORTH_PIPE_AND_PORT)
6028fe50548SAlexander von Gluck IV#define DDI_BUF_CTL_E					(0x4400 | REGS_NORTH_PIPE_AND_PORT)
603ca95e9daSAlexander von Gluck IV#define 	DDI_BUF_CTL_ENABLE			(1 << 31)
604ca95e9daSAlexander von Gluck IV#define 	DDI_BUF_TRANS_SELECT(n)		((n) << 24)
605ca95e9daSAlexander von Gluck IV#define 	DDI_BUF_EMP_MASK			(0xf << 24)
606ca95e9daSAlexander von Gluck IV#define 	DDI_BUF_PORT_REVERSAL		(1 << 16)
607ca95e9daSAlexander von Gluck IV#define 	DDI_BUF_IS_IDLE				(1 << 7)
608ca95e9daSAlexander von Gluck IV#define 	DDI_A_4_LANES				(1 << 4)
609ca95e9daSAlexander von Gluck IV#define 	DDI_PORT_WIDTH(width)		(((width) - 1) << 1)
610ca95e9daSAlexander von Gluck IV#define 	DDI_INIT_DISPLAY_DETECTED	(1 << 0)
611ca95e9daSAlexander von Gluck IV
612d442692fSAlexander von Gluck IV// DP_A always @ 6xxxx, DP_B-DP_D move with PCH
61350f0b3feSAlexander von Gluck IV#define INTEL_DISPLAY_PORT_A			(0x4000 | REGS_NORTH_PIPE_AND_PORT)
614d442692fSAlexander von Gluck IV#define INTEL_DISPLAY_PORT_B			(0x4100 | REGS_SOUTH_TRANSCODER_PORT)
615d442692fSAlexander von Gluck IV#define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_SOUTH_TRANSCODER_PORT)
616d442692fSAlexander von Gluck IV#define INTEL_DISPLAY_PORT_D			(0x4300 | REGS_SOUTH_TRANSCODER_PORT)
61750f0b3feSAlexander von Gluck IV
618e5494f1bSAlexander von Gluck IV// Unless you're a damn Valley/CherryView unicorn :-(
619e5494f1bSAlexander von Gluck IV#define VLV_DISPLAY_PORT_B				(VLV_DISPLAY_BASE + 0x64100)
620e5494f1bSAlexander von Gluck IV#define VLV_DISPLAY_PORT_C				(VLV_DISPLAY_BASE + 0x64200)
621e5494f1bSAlexander von Gluck IV#define CHV_DISPLAY_PORT_D				(VLV_DISPLAY_BASE + 0x64300)
622e5494f1bSAlexander von Gluck IV
62399756206SAlexander von Gluck IV// DP AUX channels
624721ba9afSAlexander von Gluck IV#define INTEL_DP_AUX_CTL_A				(0x4010 | REGS_NORTH_PIPE_AND_PORT)
625721ba9afSAlexander von Gluck IV#define INTEL_DP_AUX_CTL_B				(0x4110 | REGS_SOUTH_TRANSCODER_PORT)
626721ba9afSAlexander von Gluck IV#define INTEL_DP_AUX_CTL_C				(0x4210 | REGS_SOUTH_TRANSCODER_PORT)
627721ba9afSAlexander von Gluck IV#define INTEL_DP_AUX_CTL_D				(0x4310 | REGS_SOUTH_TRANSCODER_PORT)
628721ba9afSAlexander von Gluck IV
629721ba9afSAlexander von Gluck IV#define VLV_DP_AUX_CTL_B				(VLV_DISPLAY_BASE + 0x64110)
630721ba9afSAlexander von Gluck IV#define VLV_DP_AUX_CTL_C				(VLV_DISPLAY_BASE + 0x64210)
631721ba9afSAlexander von Gluck IV#define CHV_DP_AUX_CTL_D				(VLV_DISPLAY_BASE + 0x64310)
63299756206SAlexander von Gluck IV
63399756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_BUSY			(1 << 31)
63499756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_DONE			(1 << 30)
63599756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_INTERRUPT		(1 << 29)
63699756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_TIMEOUT_ERROR	(1 << 28)
63799756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_TIMEOUT_400us	(0 << 26)
63899756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_TIMEOUT_600us	(1 << 26)
63999756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_TIMEOUT_800us	(2 << 26)
64099756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26)
64199756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_TIMEOUT_MASK	(3 << 26)
64299756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_RECEIVE_ERROR	(1 << 25)
64399756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_MSG_SIZE_MASK	(0x1f << 20)
64499756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20
64599756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
64699756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16
64799756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
64899756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0
64999756206SAlexander von Gluck IV#define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
65099756206SAlexander von Gluck IV
651f0468be3SMichael Lotz// planes
65250f0b3feSAlexander von Gluck IV#define INTEL_PIPE_ENABLED				(1UL << 31)
653163e66f7SAlexander von Gluck IV#define INTEL_PIPE_CONTROL				0x0008
654163e66f7SAlexander von Gluck IV#define INTEL_PIPE_STATUS				0x0024
65561fbdb06SAlexander von Gluck IV
65661fbdb06SAlexander von Gluck IV#define INTEL_PLANE_OFFSET				0x1000
65761fbdb06SAlexander von Gluck IV
65850f0b3feSAlexander von Gluck IV#define INTEL_DISPLAY_A_PIPE_CONTROL	(0x0008	| REGS_NORTH_PLANE_CONTROL)
659f0468be3SMichael Lotz#define INTEL_DISPLAY_B_PIPE_CONTROL	(0x1008 | REGS_NORTH_PLANE_CONTROL)
660f0468be3SMichael Lotz#define INTEL_DISPLAY_A_PIPE_STATUS		(0x0024 | REGS_NORTH_PLANE_CONTROL)
661f0468be3SMichael Lotz#define INTEL_DISPLAY_B_PIPE_STATUS		(0x1024 | REGS_NORTH_PLANE_CONTROL)
66250f0b3feSAlexander von Gluck IV
663f0468be3SMichael Lotz#define DISPLAY_PIPE_VBLANK_ENABLED		(1UL << 17)
664f0468be3SMichael Lotz#define DISPLAY_PIPE_VBLANK_STATUS		(1UL << 1)
665f0468be3SMichael Lotz
666f0468be3SMichael Lotz#define INTEL_DISPLAY_A_CONTROL			(0x0180 | REGS_NORTH_PLANE_CONTROL)
667f0468be3SMichael Lotz#define INTEL_DISPLAY_A_BASE			(0x0184 | REGS_NORTH_PLANE_CONTROL)
668f0468be3SMichael Lotz#define INTEL_DISPLAY_A_BYTES_PER_ROW	(0x0188 | REGS_NORTH_PLANE_CONTROL)
669f0468be3SMichael Lotz#define INTEL_DISPLAY_A_POS				(0x018c | REGS_NORTH_PLANE_CONTROL)
670f0468be3SMichael Lotz	// reserved on A
671f0468be3SMichael Lotz#define INTEL_DISPLAY_A_PIPE_SIZE		(0x0190 | REGS_NORTH_PLANE_CONTROL)
672f0468be3SMichael Lotz#define INTEL_DISPLAY_A_SURFACE			(0x019c | REGS_NORTH_PLANE_CONTROL)
673f0468be3SMichael Lotz	// i965 and up only
674f0468be3SMichael Lotz
675f0468be3SMichael Lotz#define INTEL_DISPLAY_B_CONTROL			(0x1180 | REGS_NORTH_PLANE_CONTROL)
676f0468be3SMichael Lotz#define INTEL_DISPLAY_B_BASE			(0x1184 | REGS_NORTH_PLANE_CONTROL)
677f0468be3SMichael Lotz#define INTEL_DISPLAY_B_BYTES_PER_ROW	(0x1188 | REGS_NORTH_PLANE_CONTROL)
678f0468be3SMichael Lotz#define INTEL_DISPLAY_B_POS				(0x118c | REGS_NORTH_PLANE_CONTROL)
679f0468be3SMichael Lotz#define INTEL_DISPLAY_B_PIPE_SIZE		(0x1190 | REGS_NORTH_PLANE_CONTROL)
680f0468be3SMichael Lotz#define INTEL_DISPLAY_B_SURFACE			(0x119c | REGS_NORTH_PLANE_CONTROL)
681f0468be3SMichael Lotz	// i965 and up only
682f0468be3SMichael Lotz
683c9c61669SAlexander von Gluck IV// INTEL_DISPLAY_A_CONTROL source pixel format
684e404297eSAxel Dörfler#define DISPLAY_CONTROL_ENABLED			(1UL << 31)
685a0902420SAxel Dörfler#define DISPLAY_CONTROL_GAMMA			(1UL << 30)
686e404297eSAxel Dörfler#define DISPLAY_CONTROL_COLOR_MASK		(0x0fUL << 26)
687e404297eSAxel Dörfler#define DISPLAY_CONTROL_CMAP8			(2UL << 26)
688e404297eSAxel Dörfler#define DISPLAY_CONTROL_RGB15			(4UL << 26)
689e404297eSAxel Dörfler#define DISPLAY_CONTROL_RGB16			(5UL << 26)
69061291964SAxel Dörfler#define DISPLAY_CONTROL_RGB32			(6UL << 26)
691e404297eSAxel Dörfler
692c9c61669SAlexander von Gluck IV// INTEL_DISPLAY_A_PIPE_CONTROL ILK+
693c9c61669SAlexander von Gluck IV#define INTEL_PIPE_DITHER_TYPE_MASK		(0x0000000c)
694c9c61669SAlexander von Gluck IV#define INTEL_PIPE_DITHER_TYPE_SP		(0 << 2)
695c9c61669SAlexander von Gluck IV#define INTEL_PIPE_DITHER_TYPE_ST1		(1 << 2)
696c9c61669SAlexander von Gluck IV#define INTEL_PIPE_DITHER_TYPE_ST2		(2 << 2)
697c9c61669SAlexander von Gluck IV#define INTEL_PIPE_DITHER_TYPE_TEMP		(3 << 2)
698c9c61669SAlexander von Gluck IV#define INTEL_PIPE_DITHER_EN			(1 << 4)
699c9c61669SAlexander von Gluck IV#define INTEL_PIPE_8BPC					(0 << 5)
700c9c61669SAlexander von Gluck IV#define INTEL_PIPE_10BPC				(1 << 5)
701c9c61669SAlexander von Gluck IV#define INTEL_PIPE_6BPC					(2 << 5)
702c9c61669SAlexander von Gluck IV#define INTEL_PIPE_12BPC				(3 << 5)
703c9c61669SAlexander von Gluck IV#define INTEL_PIPE_PROGRESSIVE			(0 << 21)
704c9c61669SAlexander von Gluck IV
705f0468be3SMichael Lotz// cursors
706f0468be3SMichael Lotz#define INTEL_CURSOR_CONTROL			(0x0080 | REGS_NORTH_PLANE_CONTROL)
707f0468be3SMichael Lotz#define INTEL_CURSOR_BASE				(0x0084 | REGS_NORTH_PLANE_CONTROL)
708f0468be3SMichael Lotz#define INTEL_CURSOR_POSITION			(0x0088 | REGS_NORTH_PLANE_CONTROL)
709f0468be3SMichael Lotz#define INTEL_CURSOR_PALETTE			(0x0090 | REGS_NORTH_PLANE_CONTROL)
710f0468be3SMichael Lotz	// (- 0x009f)
711