1/*
2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 *		Alexander von Gluck, kallisti5@unixzen.com
8 */
9#ifndef INTEL_EXTREME_H
10#define INTEL_EXTREME_H
11
12
13#include "lock.h"
14
15#include <Accelerant.h>
16#include <Drivers.h>
17#include <PCI.h>
18
19#include <edid.h>
20
21
22#define VENDOR_ID_INTEL			0x8086
23
24#define INTEL_FAMILY_MASK	0x00ff0000
25#define INTEL_GROUP_MASK	0x00fffff0
26#define INTEL_MODEL_MASK	0x00ffffff
27#define INTEL_TYPE_MASK		0x0000000f
28// families
29#define INTEL_FAMILY_7xx	0x00010000	// First Gen
30#define INTEL_FAMILY_8xx	0x00020000	// Second Gen
31#define INTEL_FAMILY_9xx	0x00040000	// Third Gen +
32#define INTEL_FAMILY_SER5	0x00080000	// Intel5 Series
33#define INTEL_FAMILY_POVR	0x00100000	// PowerVR (uugh)
34#define INTEL_FAMILY_SOC0	0x00200000  // Atom SOC
35#define INTEL_FAMILY_LAKE	0x00400000	// Intel Lakes
36// groups
37#define INTEL_GROUP_83x		(INTEL_FAMILY_8xx  | 0x0010)
38#define INTEL_GROUP_85x		(INTEL_FAMILY_8xx  | 0x0020)
39#define INTEL_GROUP_91x		(INTEL_FAMILY_9xx  | 0x0010)
40#define INTEL_GROUP_94x		(INTEL_FAMILY_9xx  | 0x0020)
41#define INTEL_GROUP_96x		(INTEL_FAMILY_9xx  | 0x0040)
42#define INTEL_GROUP_Gxx		(INTEL_FAMILY_9xx  | 0x0080)
43#define INTEL_GROUP_G4x		(INTEL_FAMILY_9xx  | 0x0100)
44#define INTEL_GROUP_PIN		(INTEL_FAMILY_9xx  | 0x0200)  // PineView
45#define INTEL_GROUP_ILK		(INTEL_FAMILY_SER5 | 0x0010)  // IronLake
46#define INTEL_GROUP_SNB		(INTEL_FAMILY_SER5 | 0x0020)  // SandyBridge
47#define INTEL_GROUP_IVB		(INTEL_FAMILY_SER5 | 0x0040)  // IvyBridge
48#define INTEL_GROUP_HAS		(INTEL_FAMILY_SER5 | 0x0080)  // Haswell
49#define INTEL_GROUP_SLT		(INTEL_FAMILY_POVR | 0x0010)  // Saltwell
50#define INTEL_GROUP_FSM		(INTEL_FAMILY_POVR | 0x0020)  // Fu.Silvermont
51#define INTEL_GROUP_VLV		(INTEL_FAMILY_SOC0 | 0x0010)  // ValleyView
52#define INTEL_GROUP_CHV		(INTEL_FAMILY_SOC0 | 0x0020)  // CherryView
53#define INTEL_GROUP_BDW		(INTEL_FAMILY_SOC0 | 0x0040)  // Broadwell
54#define INTEL_GROUP_SKY		(INTEL_FAMILY_LAKE | 0x0010)  // SkyLake
55#define INTEL_GROUP_KBY		(INTEL_FAMILY_LAKE | 0x0020)  // KabyLake
56// models
57#define INTEL_TYPE_SERVER	0x0004
58#define INTEL_TYPE_MOBILE	0x0008
59#define INTEL_MODEL_915		(INTEL_GROUP_91x)
60#define INTEL_MODEL_915M	(INTEL_GROUP_91x | INTEL_TYPE_MOBILE)
61#define INTEL_MODEL_945		(INTEL_GROUP_94x)
62#define INTEL_MODEL_945M	(INTEL_GROUP_94x | INTEL_TYPE_MOBILE)
63#define INTEL_MODEL_965		(INTEL_GROUP_96x)
64#define INTEL_MODEL_965M	(INTEL_GROUP_96x | INTEL_TYPE_MOBILE)
65#define INTEL_MODEL_G33		(INTEL_GROUP_Gxx)
66#define INTEL_MODEL_G45		(INTEL_GROUP_G4x)
67#define INTEL_MODEL_GM45	(INTEL_GROUP_G4x | INTEL_TYPE_MOBILE)
68#define INTEL_MODEL_PINE	(INTEL_GROUP_PIN)
69#define INTEL_MODEL_PINEM	(INTEL_GROUP_PIN | INTEL_TYPE_MOBILE)
70#define INTEL_MODEL_ILKG	(INTEL_GROUP_ILK)
71#define INTEL_MODEL_ILKGM	(INTEL_GROUP_ILK | INTEL_TYPE_MOBILE)
72#define INTEL_MODEL_SNBG	(INTEL_GROUP_SNB)
73#define INTEL_MODEL_SNBGM	(INTEL_GROUP_SNB | INTEL_TYPE_MOBILE)
74#define INTEL_MODEL_SNBGS	(INTEL_GROUP_SNB | INTEL_TYPE_SERVER)
75#define INTEL_MODEL_IVBG	(INTEL_GROUP_IVB)
76#define INTEL_MODEL_IVBGM	(INTEL_GROUP_IVB | INTEL_TYPE_MOBILE)
77#define INTEL_MODEL_IVBGS	(INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
78#define INTEL_MODEL_HAS		(INTEL_GROUP_HAS)
79#define INTEL_MODEL_HASM	(INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
80#define INTEL_MODEL_VLV		(INTEL_GROUP_VLV)
81#define INTEL_MODEL_VLVM	(INTEL_GROUP_VLV | INTEL_TYPE_MOBILE)
82#define INTEL_MODEL_BDW		(INTEL_GROUP_BDW)
83#define INTEL_MODEL_BDWM	(INTEL_GROUP_BDW | INTEL_TYPE_MOBILE)
84#define INTEL_MODEL_SKY		(INTEL_GROUP_SKY)
85#define INTEL_MODEL_SKYM	(INTEL_GROUP_SKY | INTEL_TYPE_MOBILE)
86#define INTEL_MODEL_SKYS	(INTEL_GROUP_SKY | INTEL_TYPE_SERVER)
87
88#define INTEL_PCH_DEVICE_ID_MASK	0xff80
89#define INTEL_PCH_IBX_DEVICE_ID		0x3b00
90#define INTEL_PCH_CPT_DEVICE_ID		0x1c00
91#define INTEL_PCH_PPT_DEVICE_ID		0x1e00
92#define INTEL_PCH_LPT_DEVICE_ID		0x8c00
93#define INTEL_PCH_LPT_LP_DEVICE_ID	0x9c00
94#define INTEL_PCH_WPT_DEVICE_ID		0x8c80
95#define INTEL_PCH_WPT_LP_DEVICE_ID	0x9c80
96#define INTEL_PCH_SPT_DEVICE_ID		0xa100
97#define INTEL_PCH_SPT_LP_DEVICE_ID	0x9d00
98#define INTEL_PCH_KBP_DEVICE_ID		0xa280
99#define INTEL_PCH_CNP_DEVICE_ID		0xa300
100#define INTEL_PCH_CNP_LP_DEVICE_ID	0x9d80
101#define INTEL_PCH_ICP_DEVICE_ID		0x3480
102#define INTEL_PCH_P2X_DEVICE_ID		0x7100
103#define INTEL_PCH_P3X_DEVICE_ID		0x7000
104
105// ValleyView MMIO offset
106#define VLV_DISPLAY_BASE		0x180000
107
108#define DEVICE_NAME				"intel_extreme"
109#define INTEL_ACCELERANT_NAME	"intel_extreme.accelerant"
110
111// We encode the register block into the value and extract/translate it when
112// actually accessing.
113#define REGISTER_BLOCK_COUNT				6
114#define REGISTER_BLOCK_SHIFT				24
115#define REGISTER_BLOCK_MASK					0xff000000
116#define REGISTER_REGISTER_MASK				0x00ffffff
117#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
118#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
119
120#define REGS_FLAT							(0 << REGISTER_BLOCK_SHIFT)
121#define REGS_NORTH_SHARED					(1 << REGISTER_BLOCK_SHIFT)
122#define REGS_NORTH_PIPE_AND_PORT			(2 << REGISTER_BLOCK_SHIFT)
123#define REGS_NORTH_PLANE_CONTROL			(3 << REGISTER_BLOCK_SHIFT)
124#define REGS_SOUTH_SHARED					(4 << REGISTER_BLOCK_SHIFT)
125#define REGS_SOUTH_TRANSCODER_PORT			(5 << REGISTER_BLOCK_SHIFT)
126
127// register blocks for (G)MCH/ICH based platforms
128#define MCH_SHARED_REGISTER_BASE						0x00000
129#define MCH_PIPE_AND_PORT_REGISTER_BASE					0x60000
130#define MCH_PLANE_CONTROL_REGISTER_BASE					0x70000
131
132#define ICH_SHARED_REGISTER_BASE						0x00000
133#define ICH_PORT_REGISTER_BASE							0x60000
134
135// PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based
136// setup to a PCH based one, that means anything that used to communicate via
137// (G)MCH registers needs to use different ones on PCH based platforms
138// (Ironlake, SandyBridge, IvyBridge, Some Haswell).
139#define PCH_NORTH_SHARED_REGISTER_BASE					0x40000
140#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE			0x60000
141#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE			0x70000
142#define PCH_SOUTH_SHARED_REGISTER_BASE					0xc0000
143#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE		0xe0000
144
145
146struct DeviceType {
147	uint32			type;
148
149	DeviceType(int t)
150	{
151		type = t;
152	}
153
154	DeviceType& operator=(int t)
155	{
156		type = t;
157		return *this;
158	}
159
160	bool InFamily(uint32 family) const
161	{
162		return (type & INTEL_FAMILY_MASK) == family;
163	}
164
165	bool InGroup(uint32 group) const
166	{
167		return (type & INTEL_GROUP_MASK) == group;
168	}
169
170	bool IsModel(uint32 model) const
171	{
172		return (type & INTEL_MODEL_MASK) == model;
173	}
174
175	bool IsMobile() const
176	{
177		return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE;
178	}
179
180	bool SupportsHDMI() const
181	{
182		return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5)
183			|| InFamily(INTEL_FAMILY_SOC0);
184	}
185
186	bool HasDDI() const
187	{
188		// Intel Digital Display Interface
189		return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8);
190	}
191
192	int Generation() const
193	{
194		if (InFamily(INTEL_FAMILY_7xx))
195			return 1;
196		if (InFamily(INTEL_FAMILY_8xx))
197			return 2;
198		if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
199				|| IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN))
200			return 3;
201		if (InFamily(INTEL_FAMILY_9xx))
202			return 4;
203		if (InGroup(INTEL_GROUP_ILK))
204			return 5;
205		if (InGroup(INTEL_GROUP_SNB))
206			return 6;
207		if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV))
208			return 7;
209		if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW))
210			return 8;
211		if (InFamily(INTEL_FAMILY_LAKE))
212			return 9;
213
214		// Generation 0 means somethins is wrong :-)
215		return 0;
216	}
217};
218
219enum pch_info {
220	INTEL_PCH_NONE = 0,		// No PCH present
221	INTEL_PCH_IBX,			// Ibexpeak
222	INTEL_PCH_CPT,			// Cougarpoint
223	INTEL_PCH_LPT,			// Lynxpoint
224	INTEL_PCH_SPT,			// SunrisePoint
225	INTEL_PCH_KBP,			// KabyLake
226	INTEL_PCH_CNP,			// CannonLake
227	INTEL_PCH_ICP,			// IceLake
228	INTEL_PCH_NOP
229};
230
231// info about PLL on graphics card
232struct pll_info {
233	uint32			reference_frequency;
234	uint32			max_frequency;
235	uint32			min_frequency;
236	uint32			divisor_register;
237};
238
239struct ring_buffer {
240	struct lock		lock;
241	uint32			register_base;
242	uint32			offset;
243	uint32			size;
244	uint32			position;
245	uint32			space_left;
246	uint8*			base;
247};
248
249struct overlay_registers;
250
251struct intel_shared_info {
252	area_id			mode_list_area;		// area containing display mode list
253	uint32			mode_count;
254
255	display_mode	panel_mode;			// VBIOS VBT panel mode
256	uint32			bytes_per_row;
257	uint32			bits_per_pixel;
258	uint32			dpms_mode;
259
260	area_id			registers_area;		// area of memory mapped registers
261	uint32			register_blocks[REGISTER_BLOCK_COUNT];
262
263	uint8*			status_page;
264	phys_addr_t		physical_status_page;
265	uint8*			graphics_memory;
266	phys_addr_t		physical_graphics_memory;
267	uint32			graphics_memory_size;
268
269	addr_t			frame_buffer;
270	uint32			frame_buffer_offset;
271
272	uint32			fdi_link_frequency;	// In Mhz
273
274	bool			got_vbt;
275	bool			single_head_locked;
276
277	struct lock		accelerant_lock;
278	struct lock		engine_lock;
279
280	ring_buffer		primary_ring_buffer;
281
282	int32			overlay_channel_used;
283	bool			overlay_active;
284	uintptr_t		overlay_token;
285	phys_addr_t		physical_overlay_registers;
286	uint32			overlay_offset;
287
288	bool			hardware_cursor_enabled;
289	sem_id			vblank_sem;
290
291	uint8*			cursor_memory;
292	phys_addr_t		physical_cursor_memory;
293	uint32			cursor_buffer_offset;
294	uint32			cursor_format;
295	bool			cursor_visible;
296	uint16			cursor_hot_x;
297	uint16			cursor_hot_y;
298
299	DeviceType		device_type;
300	char			device_identifier[32];
301	struct pll_info	pll_info;
302
303	enum pch_info	pch_info;
304
305	edid1_info		vesa_edid_info;
306	bool			has_vesa_edid_info;
307};
308
309enum pipe_index {
310    INTEL_PIPE_ANY,
311    INTEL_PIPE_A,
312    INTEL_PIPE_B
313};
314
315//----------------- ioctl() interface ----------------
316
317// magic code for ioctls
318#define INTEL_PRIVATE_DATA_MAGIC		'itic'
319
320// list ioctls
321enum {
322	INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
323
324	INTEL_GET_DEVICE_NAME,
325	INTEL_ALLOCATE_GRAPHICS_MEMORY,
326	INTEL_FREE_GRAPHICS_MEMORY
327};
328
329// retrieve the area_id of the kernel/accelerant shared info
330struct intel_get_private_data {
331	uint32	magic;				// magic number
332	area_id	shared_info_area;
333};
334
335// allocate graphics memory
336struct intel_allocate_graphics_memory {
337	uint32	magic;
338	uint32	size;
339	uint32	alignment;
340	uint32	flags;
341	addr_t	buffer_base;
342};
343
344// free graphics memory
345struct intel_free_graphics_memory {
346	uint32 	magic;
347	addr_t	buffer_base;
348};
349
350//----------------------------------------------------------
351// Register definitions, taken from X driver
352
353// PCI bridge memory management
354#define INTEL_GRAPHICS_MEMORY_CONTROL	0x52		// i830+
355
356	// GGC - (G)MCH Graphics Control Register
357#define MEMORY_CONTROL_ENABLED			0x0004
358#define MEMORY_MASK						0x0001
359#define STOLEN_MEMORY_MASK				0x00f0
360#define i965_GTT_MASK					0x000e
361#define G33_GTT_MASK					0x0300
362#define G4X_GTT_MASK					0x0f00	// GGMS (GSM Memory Size) mask
363
364// models i830 and up
365#define i830_LOCAL_MEMORY_ONLY			0x10
366#define i830_STOLEN_512K				0x20
367#define i830_STOLEN_1M					0x30
368#define i830_STOLEN_8M					0x40
369#define i830_FRAME_BUFFER_64M			0x01
370#define i830_FRAME_BUFFER_128M			0x00
371
372// models i855 and up
373#define i855_STOLEN_MEMORY_1M			0x10
374#define i855_STOLEN_MEMORY_4M			0x20
375#define i855_STOLEN_MEMORY_8M			0x30
376#define i855_STOLEN_MEMORY_16M			0x40
377#define i855_STOLEN_MEMORY_32M			0x50
378#define i855_STOLEN_MEMORY_48M			0x60
379#define i855_STOLEN_MEMORY_64M			0x70
380#define i855_STOLEN_MEMORY_128M			0x80
381#define i855_STOLEN_MEMORY_256M			0x90
382
383#define G4X_STOLEN_MEMORY_96MB			0xa0	// GMS - Graphics Mode Select
384#define G4X_STOLEN_MEMORY_160MB			0xb0
385#define G4X_STOLEN_MEMORY_224MB			0xc0
386#define G4X_STOLEN_MEMORY_352MB			0xd0
387
388// SandyBridge (SNB)
389
390#define SNB_GRAPHICS_MEMORY_CONTROL		0x50
391
392#define SNB_STOLEN_MEMORY_MASK			0xf8
393#define SNB_STOLEN_MEMORY_32MB			(1 << 3)
394#define SNB_STOLEN_MEMORY_64MB			(2 << 3)
395#define SNB_STOLEN_MEMORY_96MB			(3 << 3)
396#define SNB_STOLEN_MEMORY_128MB			(4 << 3)
397#define SNB_STOLEN_MEMORY_160MB			(5 << 3)
398#define SNB_STOLEN_MEMORY_192MB			(6 << 3)
399#define SNB_STOLEN_MEMORY_224MB			(7 << 3)
400#define SNB_STOLEN_MEMORY_256MB			(8 << 3)
401#define SNB_STOLEN_MEMORY_288MB			(9 << 3)
402#define SNB_STOLEN_MEMORY_320MB			(10 << 3)
403#define SNB_STOLEN_MEMORY_352MB			(11 << 3)
404#define SNB_STOLEN_MEMORY_384MB			(12 << 3)
405#define SNB_STOLEN_MEMORY_416MB			(13 << 3)
406#define SNB_STOLEN_MEMORY_448MB			(14 << 3)
407#define SNB_STOLEN_MEMORY_480MB			(15 << 3)
408#define SNB_STOLEN_MEMORY_512MB			(16 << 3)
409
410#define SNB_GTT_SIZE_MASK				(3 << 8)
411#define SNB_GTT_SIZE_NONE				(0 << 8)
412#define SNB_GTT_SIZE_1MB				(1 << 8)
413#define SNB_GTT_SIZE_2MB				(2 << 8)
414
415// graphics page translation table
416#define INTEL_PAGE_TABLE_CONTROL		0x02020
417#define PAGE_TABLE_ENABLED				0x00000001
418#define INTEL_PAGE_TABLE_ERROR			0x02024
419#define INTEL_HARDWARE_STATUS_PAGE		0x02080
420#define i915_GTT_BASE					0x1c
421#define i830_GTT_BASE					0x10000	// (- 0x2ffff)
422#define i830_GTT_SIZE					0x20000
423#define i965_GTT_BASE					0x80000	// (- 0xfffff)
424#define i965_GTT_SIZE					0x80000
425#define i965_GTT_128K					(2 << 1)
426#define i965_GTT_256K					(1 << 1)
427#define i965_GTT_512K					(0 << 1)
428#define G33_GTT_1M						(1 << 8)
429#define G33_GTT_2M						(2 << 8)
430#define G4X_GTT_NONE					0x000	// GGMS - GSM Memory Size
431#define G4X_GTT_1M_NO_IVT				0x100	// no Intel Virtualization Tech.
432#define G4X_GTT_2M_NO_IVT				0x300
433#define G4X_GTT_2M_IVT					0x900	// with Intel Virt. Tech.
434#define G4X_GTT_3M_IVT					0xa00
435#define G4X_GTT_4M_IVT					0xb00
436
437
438#define GTT_ENTRY_VALID					0x01
439#define GTT_ENTRY_LOCAL_MEMORY			0x02
440#define GTT_PAGE_SHIFT					12
441
442
443// ring buffer
444#define INTEL_PRIMARY_RING_BUFFER		0x02030
445#define INTEL_SECONDARY_RING_BUFFER_0	0x02100
446#define INTEL_SECONDARY_RING_BUFFER_1	0x02110
447// offsets for the ring buffer base registers above
448#define RING_BUFFER_TAIL				0x0
449#define RING_BUFFER_HEAD				0x4
450#define RING_BUFFER_START				0x8
451#define RING_BUFFER_CONTROL				0xc
452#define INTEL_RING_BUFFER_SIZE_MASK		0x001ff000
453#define INTEL_RING_BUFFER_HEAD_MASK		0x001ffffc
454#define INTEL_RING_BUFFER_ENABLED		1
455
456// interrupts
457#define INTEL_INTERRUPT_ENABLED			0x020a0
458#define INTEL_INTERRUPT_IDENTITY		0x020a4
459#define INTEL_INTERRUPT_MASK			0x020a8
460#define INTEL_INTERRUPT_STATUS			0x020ac
461#define INTERRUPT_VBLANK_PIPEA			(1 << 7)
462#define INTERRUPT_VBLANK_PIPEB			(1 << 5)
463
464// PCH interrupts
465#define PCH_INTERRUPT_STATUS			0x44000
466#define PCH_INTERRUPT_MASK				0x44004
467#define PCH_INTERRUPT_IDENTITY			0x44008
468#define PCH_INTERRUPT_ENABLED			0x4400c
469
470#define PCH_INTERRUPT_VBLANK_PIPEA		(1 << 0)
471#define PCH_INTERRUPT_VBLANK_PIPEB		(1 << 5)
472#define PCH_INTERRUPT_VBLANK_PIPEC		(1 << 10)
473
474// SandyBridge had only two pipes, and things were shuffled aroud again with
475// the introduction of pipe C.
476#define PCH_INTERRUPT_VBLANK_PIPEA_SNB		(1 << 7)
477#define PCH_INTERRUPT_VBLANK_PIPEB_SNB		(1 << 15)
478#define PCH_INTERRUPT_GLOBAL_SNB			(1 << 31)
479
480// graphics port control
481#define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
482#define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
483#define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
484#define DISPLAY_MONITOR_MODE_MASK		(3UL << 10)
485#define DISPLAY_MONITOR_ON				0
486#define DISPLAY_MONITOR_SUSPEND			(1UL << 10)
487#define DISPLAY_MONITOR_STAND_BY		(2UL << 10)
488#define DISPLAY_MONITOR_OFF				(3UL << 10)
489#define DISPLAY_MONITOR_POLARITY_MASK	(3UL << 3)
490#define DISPLAY_MONITOR_POSITIVE_HSYNC	(1UL << 3)
491#define DISPLAY_MONITOR_POSITIVE_VSYNC	(2UL << 3)
492#define DISPLAY_MONITOR_PORT_DETECTED	(1UL << 2) // TMDS/DisplayPort only
493
494#define LVDS_POST2_RATE_SLOW			14 // PLL Divisors
495#define LVDS_POST2_RATE_FAST			7
496#define LVDS_B0B3_POWER_MASK			(3UL << 2)
497#define LVDS_B0B3_POWER_UP				(3UL << 2)
498#define LVDS_CLKB_POWER_MASK			(3UL << 4)
499#define LVDS_CLKB_POWER_UP				(3UL << 4)
500#define LVDS_A3_POWER_MASK				(3UL << 6)
501#define LVDS_A3_POWER_UP				(3UL << 6)
502#define LVDS_A0A2_CLKA_POWER_UP			(3UL << 8)
503#define LVDS_BORDER_ENABLE				(1UL << 15)
504#define LVDS_HSYNC_POLARITY				(1UL << 20)
505#define LVDS_VSYNC_POLARITY				(1UL << 21)
506#define LVDS_18BIT_DITHER				(1UL << 25)
507#define LVDS_PORT_EN					(1UL << 31)
508
509// PLL flags
510#define DISPLAY_PLL_ENABLED				(1UL << 31)
511#define DISPLAY_PLL_2X_CLOCK			(1UL << 30)
512#define DISPLAY_PLL_SYNC_LOCK_ENABLED	(1UL << 29)
513#define DISPLAY_PLL_NO_VGA_CONTROL		(1UL << 28)
514#define DISPLAY_PLL_MODE_NORMAL			(1UL << 26)
515#define DISPLAY_PLL_MODE_LVDS			(2UL << 26)
516#define DISPLAY_PLL_DIVIDE_HIGH			(1UL << 24)
517#define DISPLAY_PLL_DIVIDE_4X			(1UL << 23)
518#define DISPLAY_PLL_POST1_DIVIDE_2		(1UL << 21)
519#define DISPLAY_PLL_POST1_DIVISOR_MASK	0x001f0000
520#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK	0x00ff0000
521#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK  0x00ff8000
522#define DISPLAY_PLL_POST1_DIVISOR_SHIFT	16
523#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT	15
524#define DISPLAY_PLL_DIVISOR_1			(1UL << 8)
525#define DISPLAY_PLL_N_DIVISOR_MASK		0x001f0000
526#define DISPLAY_PLL_IGD_N_DIVISOR_MASK	0x00ff0000
527#define DISPLAY_PLL_M1_DIVISOR_MASK		0x00001f00
528#define DISPLAY_PLL_M2_DIVISOR_MASK		0x0000001f
529#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK	0x000000ff
530#define DISPLAY_PLL_N_DIVISOR_SHIFT		16
531#define DISPLAY_PLL_M1_DIVISOR_SHIFT	8
532#define DISPLAY_PLL_M2_DIVISOR_SHIFT	0
533#define DISPLAY_PLL_PULSE_PHASE_SHIFT	9
534
535// display
536
537#define INTEL_DISPLAY_OFFSET			0x1000
538
539#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_NORTH_PIPE_AND_PORT)
540#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_NORTH_PIPE_AND_PORT)
541#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_NORTH_PIPE_AND_PORT)
542#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_NORTH_PIPE_AND_PORT)
543#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_NORTH_PIPE_AND_PORT)
544#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_NORTH_PIPE_AND_PORT)
545#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_NORTH_PIPE_AND_PORT)
546#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_NORTH_PIPE_AND_PORT)
547#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_NORTH_PIPE_AND_PORT)
548#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_NORTH_PIPE_AND_PORT)
549#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_NORTH_PIPE_AND_PORT)
550#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_NORTH_PIPE_AND_PORT)
551
552#define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
553#define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)
554
555// Cougar Point transcoder pipe selection
556#define  PORT_TRANS_A_SEL_CPT			0
557#define  PORT_TRANS_B_SEL_CPT			(1<<29)
558#define  PORT_TRANS_C_SEL_CPT			(2<<29)
559#define  PORT_TRANS_SEL_MASK			(3<<29)
560
561// on PCH we also have to set the transcoder
562#define INTEL_TRANSCODER_A_HTOTAL		(0x0000 | REGS_SOUTH_TRANSCODER_PORT)
563#define INTEL_TRANSCODER_A_HBLANK		(0x0004 | REGS_SOUTH_TRANSCODER_PORT)
564#define INTEL_TRANSCODER_A_HSYNC		(0x0008 | REGS_SOUTH_TRANSCODER_PORT)
565#define INTEL_TRANSCODER_A_VTOTAL		(0x000c | REGS_SOUTH_TRANSCODER_PORT)
566#define INTEL_TRANSCODER_A_VBLANK		(0x0010 | REGS_SOUTH_TRANSCODER_PORT)
567#define INTEL_TRANSCODER_A_VSYNC		(0x0014 | REGS_SOUTH_TRANSCODER_PORT)
568#define INTEL_TRANSCODER_B_HTOTAL		(0x1000 | REGS_SOUTH_TRANSCODER_PORT)
569#define INTEL_TRANSCODER_B_HBLANK		(0x1004 | REGS_SOUTH_TRANSCODER_PORT)
570#define INTEL_TRANSCODER_B_HSYNC		(0x1008 | REGS_SOUTH_TRANSCODER_PORT)
571#define INTEL_TRANSCODER_B_VTOTAL		(0x100c | REGS_SOUTH_TRANSCODER_PORT)
572#define INTEL_TRANSCODER_B_VBLANK		(0x1010 | REGS_SOUTH_TRANSCODER_PORT)
573#define INTEL_TRANSCODER_B_VSYNC		(0x1014 | REGS_SOUTH_TRANSCODER_PORT)
574
575#define INTEL_TRANSCODER_A_IMAGE_SIZE	(0x001c | REGS_SOUTH_TRANSCODER_PORT)
576#define INTEL_TRANSCODER_B_IMAGE_SIZE	(0x101c | REGS_SOUTH_TRANSCODER_PORT)
577
578// TODO: Is there consolidation that could happen here with digital ports?
579
580#define INTEL_ANALOG_PORT				(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
581#define INTEL_DIGITAL_PORT_A			(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
582#define INTEL_DIGITAL_PORT_B			(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
583#define INTEL_DIGITAL_PORT_C			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
584#define INTEL_DIGITAL_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
585
586#define INTEL_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
587#define INTEL_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
588
589#define PCH_HDMI_PORT_B					(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
590#define PCH_HDMI_PORT_C					(0x1150 | REGS_SOUTH_TRANSCODER_PORT)
591#define PCH_HDMI_PORT_D					(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
592
593#define GEN4_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
594#define GEN4_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
595#define CHV_HDMI_PORT_D					(0x116C | REGS_SOUTH_TRANSCODER_PORT)
596
597// DDI Buffer Control (This replaces DP on Haswell+)
598#define DDI_BUF_CTL_A					(0x4000 | REGS_NORTH_PIPE_AND_PORT)
599#define DDI_BUF_CTL_B					(0x4100 | REGS_NORTH_PIPE_AND_PORT)
600#define DDI_BUF_CTL_C					(0x4200 | REGS_NORTH_PIPE_AND_PORT)
601#define DDI_BUF_CTL_D					(0x4300 | REGS_NORTH_PIPE_AND_PORT)
602#define DDI_BUF_CTL_E					(0x4400 | REGS_NORTH_PIPE_AND_PORT)
603#define 	DDI_BUF_CTL_ENABLE			(1 << 31)
604#define 	DDI_BUF_TRANS_SELECT(n)		((n) << 24)
605#define 	DDI_BUF_EMP_MASK			(0xf << 24)
606#define 	DDI_BUF_PORT_REVERSAL		(1 << 16)
607#define 	DDI_BUF_IS_IDLE				(1 << 7)
608#define 	DDI_A_4_LANES				(1 << 4)
609#define 	DDI_PORT_WIDTH(width)		(((width) - 1) << 1)
610#define 	DDI_INIT_DISPLAY_DETECTED	(1 << 0)
611
612// DP_A always @ 6xxxx, DP_B-DP_D move with PCH
613#define INTEL_DISPLAY_PORT_A			(0x4000 | REGS_NORTH_PIPE_AND_PORT)
614#define INTEL_DISPLAY_PORT_B			(0x4100 | REGS_SOUTH_TRANSCODER_PORT)
615#define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_SOUTH_TRANSCODER_PORT)
616#define INTEL_DISPLAY_PORT_D			(0x4300 | REGS_SOUTH_TRANSCODER_PORT)
617
618// Unless you're a damn Valley/CherryView unicorn :-(
619#define VLV_DISPLAY_PORT_B				(VLV_DISPLAY_BASE + 0x64100)
620#define VLV_DISPLAY_PORT_C				(VLV_DISPLAY_BASE + 0x64200)
621#define CHV_DISPLAY_PORT_D				(VLV_DISPLAY_BASE + 0x64300)
622
623// DP AUX channels
624#define INTEL_DP_AUX_CTL_A				(0x4010 | REGS_NORTH_PIPE_AND_PORT)
625#define INTEL_DP_AUX_CTL_B				(0x4110 | REGS_SOUTH_TRANSCODER_PORT)
626#define INTEL_DP_AUX_CTL_C				(0x4210 | REGS_SOUTH_TRANSCODER_PORT)
627#define INTEL_DP_AUX_CTL_D				(0x4310 | REGS_SOUTH_TRANSCODER_PORT)
628
629#define VLV_DP_AUX_CTL_B				(VLV_DISPLAY_BASE + 0x64110)
630#define VLV_DP_AUX_CTL_C				(VLV_DISPLAY_BASE + 0x64210)
631#define CHV_DP_AUX_CTL_D				(VLV_DISPLAY_BASE + 0x64310)
632
633#define INTEL_DP_AUX_CTL_BUSY			(1 << 31)
634#define INTEL_DP_AUX_CTL_DONE			(1 << 30)
635#define INTEL_DP_AUX_CTL_INTERRUPT		(1 << 29)
636#define INTEL_DP_AUX_CTL_TIMEOUT_ERROR	(1 << 28)
637#define INTEL_DP_AUX_CTL_TIMEOUT_400us	(0 << 26)
638#define INTEL_DP_AUX_CTL_TIMEOUT_600us	(1 << 26)
639#define INTEL_DP_AUX_CTL_TIMEOUT_800us	(2 << 26)
640#define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26)
641#define INTEL_DP_AUX_CTL_TIMEOUT_MASK	(3 << 26)
642#define INTEL_DP_AUX_CTL_RECEIVE_ERROR	(1 << 25)
643#define INTEL_DP_AUX_CTL_MSG_SIZE_MASK	(0x1f << 20)
644#define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20
645#define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
646#define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16
647#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
648#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0
649#define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
650
651// planes
652#define INTEL_PIPE_ENABLED				(1UL << 31)
653#define INTEL_PIPE_CONTROL				0x0008
654#define INTEL_PIPE_STATUS				0x0024
655
656#define INTEL_PLANE_OFFSET				0x1000
657
658#define INTEL_DISPLAY_A_PIPE_CONTROL	(0x0008	| REGS_NORTH_PLANE_CONTROL)
659#define INTEL_DISPLAY_B_PIPE_CONTROL	(0x1008 | REGS_NORTH_PLANE_CONTROL)
660#define INTEL_DISPLAY_A_PIPE_STATUS		(0x0024 | REGS_NORTH_PLANE_CONTROL)
661#define INTEL_DISPLAY_B_PIPE_STATUS		(0x1024 | REGS_NORTH_PLANE_CONTROL)
662
663#define DISPLAY_PIPE_VBLANK_ENABLED		(1UL << 17)
664#define DISPLAY_PIPE_VBLANK_STATUS		(1UL << 1)
665
666#define INTEL_DISPLAY_A_CONTROL			(0x0180 | REGS_NORTH_PLANE_CONTROL)
667#define INTEL_DISPLAY_A_BASE			(0x0184 | REGS_NORTH_PLANE_CONTROL)
668#define INTEL_DISPLAY_A_BYTES_PER_ROW	(0x0188 | REGS_NORTH_PLANE_CONTROL)
669#define INTEL_DISPLAY_A_POS				(0x018c | REGS_NORTH_PLANE_CONTROL)
670	// reserved on A
671#define INTEL_DISPLAY_A_PIPE_SIZE		(0x0190 | REGS_NORTH_PLANE_CONTROL)
672#define INTEL_DISPLAY_A_SURFACE			(0x019c | REGS_NORTH_PLANE_CONTROL)
673	// i965 and up only
674
675#define INTEL_DISPLAY_B_CONTROL			(0x1180 | REGS_NORTH_PLANE_CONTROL)
676#define INTEL_DISPLAY_B_BASE			(0x1184 | REGS_NORTH_PLANE_CONTROL)
677#define INTEL_DISPLAY_B_BYTES_PER_ROW	(0x1188 | REGS_NORTH_PLANE_CONTROL)
678#define INTEL_DISPLAY_B_POS				(0x118c | REGS_NORTH_PLANE_CONTROL)
679#define INTEL_DISPLAY_B_PIPE_SIZE		(0x1190 | REGS_NORTH_PLANE_CONTROL)
680#define INTEL_DISPLAY_B_SURFACE			(0x119c | REGS_NORTH_PLANE_CONTROL)
681	// i965 and up only
682
683// INTEL_DISPLAY_A_CONTROL source pixel format
684#define DISPLAY_CONTROL_ENABLED			(1UL << 31)
685#define DISPLAY_CONTROL_GAMMA			(1UL << 30)
686#define DISPLAY_CONTROL_COLOR_MASK		(0x0fUL << 26)
687#define DISPLAY_CONTROL_CMAP8			(2UL << 26)
688#define DISPLAY_CONTROL_RGB15			(4UL << 26)
689#define DISPLAY_CONTROL_RGB16			(5UL << 26)
690#define DISPLAY_CONTROL_RGB32			(6UL << 26)
691
692// INTEL_DISPLAY_A_PIPE_CONTROL ILK+
693#define INTEL_PIPE_DITHER_TYPE_MASK		(0x0000000c)
694#define INTEL_PIPE_DITHER_TYPE_SP		(0 << 2)
695#define INTEL_PIPE_DITHER_TYPE_ST1		(1 << 2)
696#define INTEL_PIPE_DITHER_TYPE_ST2		(2 << 2)
697#define INTEL_PIPE_DITHER_TYPE_TEMP		(3 << 2)
698#define INTEL_PIPE_DITHER_EN			(1 << 4)
699#define INTEL_PIPE_8BPC					(0 << 5)
700#define INTEL_PIPE_10BPC				(1 << 5)
701#define INTEL_PIPE_6BPC					(2 << 5)
702#define INTEL_PIPE_12BPC				(3 << 5)
703#define INTEL_PIPE_PROGRESSIVE			(0 << 21)
704
705// cursors
706#define INTEL_CURSOR_CONTROL			(0x0080 | REGS_NORTH_PLANE_CONTROL)
707#define INTEL_CURSOR_BASE				(0x0084 | REGS_NORTH_PLANE_CONTROL)
708#define INTEL_CURSOR_POSITION			(0x0088 | REGS_NORTH_PLANE_CONTROL)
709#define INTEL_CURSOR_PALETTE			(0x0090 | REGS_NORTH_PLANE_CONTROL)
710	// (- 0x009f)
711#define INTEL_CURSOR_SIZE				(0x00a0 | REGS_NORTH_PLANE_CONTROL)
712#define CURSOR_ENABLED					(1UL << 31)
713#define CURSOR_FORMAT_2_COLORS			(0UL << 24)
714#define CURSOR_FORMAT_3_COLORS			(1UL << 24)
715#define CURSOR_FORMAT_4_COLORS			(2UL << 24)
716#define CURSOR_FORMAT_ARGB				(4UL << 24)
717#define CURSOR_FORMAT_XRGB				(5UL << 24)
718#define CURSOR_POSITION_NEGATIVE		0x8000
719#define CURSOR_POSITION_MASK			0x3fff
720
721// palette registers
722#define INTEL_DISPLAY_A_PALETTE			(0xa000 | REGS_NORTH_SHARED)
723#define INTEL_DISPLAY_B_PALETTE			(0xa800 | REGS_NORTH_SHARED)
724
725// PLL registers
726#define INTEL_DISPLAY_A_PLL				(0x6014 | REGS_SOUTH_SHARED)
727#define INTEL_DISPLAY_B_PLL				(0x6018 | REGS_SOUTH_SHARED)
728#define CHV_DISPLAY_C_PLL				(0x6030 | REGS_SOUTH_SHARED)
729
730// Ironlake PCH reference clk control
731#define PCH_DREF_CONTROL					(0x6200 | REGS_SOUTH_SHARED)
732#define DREF_CONTROL_MASK					0x7fc3
733#define DREF_CPU_SOURCE_OUTPUT_DISABLE		(0 << 13)
734#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD	(2 << 13)
735#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD	(3 << 13)
736#define DREF_CPU_SOURCE_OUTPUT_MASK			(3 << 13)
737#define DREF_SSC_SOURCE_DISABLE				(0 << 11)
738#define DREF_SSC_SOURCE_ENABLE				(2 << 11)
739#define DREF_SSC_SOURCE_MASK				(3 << 11)
740#define DREF_NONSPREAD_SOURCE_DISABLE		(0 << 9)
741#define DREF_NONSPREAD_CK505_ENABLE			(1 << 9)
742#define DREF_NONSPREAD_SOURCE_ENABLE		(2 << 9)
743#define DREF_NONSPREAD_SOURCE_MASK			(3 << 9)
744#define DREF_SUPERSPREAD_SOURCE_DISABLE 	(0 << 7)
745#define DREF_SUPERSPREAD_SOURCE_ENABLE		(2 << 7)
746#define DREF_SUPERSPREAD_SOURCE_MASK		(3 << 7)
747#define DREF_SSC4_DOWNSPREAD				(0 << 6)
748#define DREF_SSC4_CENTERSPREAD				(1 << 6)
749#define DREF_SSC1_DISABLE					(0 << 1)
750#define DREF_SSC1_ENABLE					(1 << 1)
751#define DREF_SSC4_DISABLE					(0 << 0)
752#define DREF_SSC4_ENABLE					(1 << 0)
753
754//  Multiplier Divisor
755#define INTEL_DISPLAY_A_PLL_MD			(0x601C | REGS_SOUTH_SHARED)
756#define INTEL_DISPLAY_B_PLL_MD			(0x6020 | REGS_SOUTH_SHARED)
757#define CHV_DISPLAY_B_PLL_MD			(0x603C | REGS_SOUTH_SHARED)
758
759#define INTEL_DISPLAY_A_PLL_DIVISOR_0	(0x6040 | REGS_SOUTH_SHARED)
760#define INTEL_DISPLAY_A_PLL_DIVISOR_1	(0x6044 | REGS_SOUTH_SHARED)
761#define INTEL_DISPLAY_B_PLL_DIVISOR_0	(0x6048 | REGS_SOUTH_SHARED)
762#define INTEL_DISPLAY_B_PLL_DIVISOR_1	(0x604c | REGS_SOUTH_SHARED)
763
764// i2c
765#define INTEL_I2C_IO_A					(0x5010 | REGS_SOUTH_SHARED)
766#define INTEL_I2C_IO_B					(0x5014 | REGS_SOUTH_SHARED)
767#define INTEL_I2C_IO_C					(0x5018 | REGS_SOUTH_SHARED)
768#define INTEL_I2C_IO_D					(0x501c | REGS_SOUTH_SHARED)
769#define INTEL_I2C_IO_E					(0x5020 | REGS_SOUTH_SHARED)
770#define INTEL_I2C_IO_F					(0x5024 | REGS_SOUTH_SHARED)
771#define INTEL_I2C_IO_G					(0x5028 | REGS_SOUTH_SHARED)
772#define INTEL_I2C_IO_H					(0x502c | REGS_SOUTH_SHARED)
773
774#define I2C_CLOCK_DIRECTION_MASK		(1 << 0)
775#define I2C_CLOCK_DIRECTION_OUT			(1 << 1)
776#define I2C_CLOCK_VALUE_MASK			(1 << 2)
777#define I2C_CLOCK_VALUE_OUT				(1 << 3)
778#define I2C_CLOCK_VALUE_IN				(1 << 4)
779#define I2C_DATA_DIRECTION_MASK			(1 << 8)
780#define I2C_DATA_DIRECTION_OUT			(1 << 9)
781#define I2C_DATA_VALUE_MASK				(1 << 10)
782#define I2C_DATA_VALUE_OUT				(1 << 11)
783#define I2C_DATA_VALUE_IN				(1 << 12)
784#define I2C_RESERVED					((1 << 13) | (1 << 5))
785
786// TODO: on IronLake this is in the north shared block at 0x41000
787#define INTEL_VGA_DISPLAY_CONTROL		(0x1400 | REGS_NORTH_PLANE_CONTROL)
788#define VGA_DISPLAY_DISABLED			(1UL << 31)
789
790// LVDS panel
791#define INTEL_PANEL_STATUS				(0x1200 | REGS_NORTH_PIPE_AND_PORT)
792#define INTEL_PANEL_CONTROL				(0x1204 | REGS_NORTH_PIPE_AND_PORT)
793#define INTEL_PANEL_FIT_CONTROL			(0x1230 | REGS_NORTH_PIPE_AND_PORT)
794#define INTEL_PANEL_FIT_RATIOS			(0x1234 | REGS_NORTH_PIPE_AND_PORT)
795
796// LVDS on IronLake and up
797#define PCH_PANEL_STATUS				(0x7200 | REGS_SOUTH_SHARED)
798#define PCH_PANEL_CONTROL				(0x7204 | REGS_SOUTH_SHARED)
799#define PCH_PANEL_ON_DELAYS				(0x7208 | REGS_SOUTH_SHARED)
800#define PCH_PANEL_OFF_DELAYS			(0x720c | REGS_SOUTH_SHARED)
801#define PCH_PANEL_DIVISOR				(0x7210 | REGS_SOUTH_SHARED)
802#define PCH_LVDS_DETECTED				(1 << 1)
803
804#define PANEL_STATUS_POWER_ON			(1UL << 31)
805#define PANEL_CONTROL_POWER_TARGET_OFF	(0UL << 0)
806#define PANEL_CONTROL_POWER_TARGET_ON	(1UL << 0)
807#define PANEL_CONTROL_POWER_TARGET_RST	(1UL << 1)
808#define PANEL_REGISTER_UNLOCK			(0xabcd << 16)
809
810// PCH_PANEL_ON_DELAYS
811#define PANEL_DELAY_PORT_SELECT_MASK	(3 << 30)
812#define PANEL_DELAY_PORT_SELECT_LVDS	(0 << 30)
813#define PANEL_DELAY_PORT_SELECT_DPA		(1 << 30)
814#define PANEL_DELAY_PORT_SELECT_DPC		(2 << 30)
815#define PANEL_DELAY_PORT_SELECT_DPD		(3 << 30)
816
817// PCH_PANEL_DIVISOR
818#define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00
819#define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8
820#define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f
821#define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f
822
823// Backlight control registers
824#define PCH_BLC_PWM_CTL2                (0x8250 | REGS_NORTH_SHARED)
825#define PCH_BLC_PWM_CTL                 (0x8254 | REGS_NORTH_SHARED)
826#define PCH_SBLC_PWM_CTL2               (0x8254 | REGS_SOUTH_SHARED)
827
828#define MCH_BLC_PWM_CTL                 (0x1254 | REGS_NORTH_PIPE_AND_PORT)
829
830// ring buffer commands
831
832#define COMMAND_NOOP					0x00
833#define COMMAND_WAIT_FOR_EVENT			(0x03 << 23)
834#define COMMAND_WAIT_FOR_OVERLAY_FLIP	(1 << 16)
835
836#define COMMAND_FLUSH					(0x04 << 23)
837
838// overlay flip
839#define COMMAND_OVERLAY_FLIP			(0x11 << 23)
840#define COMMAND_OVERLAY_CONTINUE		(0 << 21)
841#define COMMAND_OVERLAY_ON				(1 << 21)
842#define COMMAND_OVERLAY_OFF				(2 << 21)
843#define OVERLAY_UPDATE_COEFFICIENTS		0x1
844
845// 2D acceleration
846#define XY_COMMAND_SOURCE_BLIT			0x54c00006
847#define XY_COMMAND_COLOR_BLIT			0x54000004
848#define XY_COMMAND_SETUP_MONO_PATTERN	0x44400007
849#define XY_COMMAND_SCANLINE_BLIT		0x49400001
850#define COMMAND_COLOR_BLIT				0x50000003
851#define COMMAND_BLIT_RGBA				0x00300000
852
853#define COMMAND_MODE_SOLID_PATTERN		0x80
854#define COMMAND_MODE_CMAP8				0x00
855#define COMMAND_MODE_RGB15				0x02
856#define COMMAND_MODE_RGB16				0x01
857#define COMMAND_MODE_RGB32				0x03
858
859// overlay
860#define INTEL_OVERLAY_UPDATE			0x30000
861#define INTEL_OVERLAY_TEST				0x30004
862#define INTEL_OVERLAY_STATUS			0x30008
863#define INTEL_OVERLAY_EXTENDED_STATUS	0x3000c
864#define INTEL_OVERLAY_GAMMA_5			0x30010
865#define INTEL_OVERLAY_GAMMA_4			0x30014
866#define INTEL_OVERLAY_GAMMA_3			0x30018
867#define INTEL_OVERLAY_GAMMA_2			0x3001c
868#define INTEL_OVERLAY_GAMMA_1			0x30020
869#define INTEL_OVERLAY_GAMMA_0			0x30024
870
871// FDI - Flexible Display Interface, the interface between the (CPU-internal)
872// GPU and the PCH display outputs. Proprietary interface, based on DisplayPort
873// though, so similar link training and all...
874// There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the
875// PCH for each display pipe.
876// FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to
877// transcoder B, so we have the same mapping as with the display pipes.
878#define PCH_FDI_RX_BASE_REGISTER		0xf0000
879#define PCH_FDI_RX_PIPE_OFFSET			0x01000
880#define PCH_FDI_RX_CONTROL				0x00c
881#define PCH_FDI_RX_MISC					0x010
882#define PCH_FDI_RX_IIR					0x014
883#define PCH_FDI_RX_IMR					0x018
884
885#define FDI_RX_ENABLE					(1 << 31)
886#define FDI_RX_PLL_ENABLED				(1 << 13)
887
888// FDI_tX interrupt register
889#define FDI_RX_INTER_LANE_ALIGN         (1 << 10)
890#define FDI_RX_SYMBOL_LOCK              (1 << 9)
891#define FDI_RX_BIT_LOCK                 (1 << 8)
892#define FDI_RX_TRAIN_PATTERN_2_FAIL     (1 << 7)
893#define FDI_RX_FS_CODE_ERR              (1 << 6)
894#define FDI_RX_FE_CODE_ERR              (1 << 5)
895#define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1 << 4)
896#define FDI_RX_HDCP_LINK_FAIL           (1 << 3)
897#define FDI_RX_PIXEL_FIFO_OVERFLOW      (1 << 2)
898#define FDI_RX_CROSS_CLOCK_OVERFLOW     (1 << 1)
899#define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
900
901#define FDI_FS_ERRC_ENABLE				(1 << 27)
902#define FDI_FE_ERRC_ENABLE				(1 << 26)
903
904#define PCH_FDI_RX_TRANS_UNIT_SIZE_1	0x30
905#define PCH_FDI_RX_TRANS_UNIT_SIZE_2	0x38
906#define FDI_RX_TRANS_UNIT_SIZE(x)		((x - 1) << 25)
907#define FDI_RX_TRANS_UNIT_MASK			0x7e000000
908
909#define FDI_RX_ENHANCE_FRAME_ENABLE		(1 << 6)
910#define FDI_RX_CLOCK_MASK				(1 << 4)
911#define FDI_RX_CLOCK_RAW				(0 << 4)
912#define FDI_RX_CLOCK_PCD				(1 << 4)
913
914// FDI RX MISC
915#define FDI_RX_PWRDN_LANE1_MASK		(3 << 26)
916#define FDI_RX_PWRDN_LANE1_VAL(x)	((x) << 26)
917#define FDI_RX_PWRDN_LANE0_MASK		(3 << 24)
918#define FDI_RX_PWRDN_LANE0_VAL(x)	((x) << 24)
919#define FDI_RX_TP1_TO_TP2_48		(2 << 20)
920#define FDI_RX_TP1_TO_TP2_64		(3 << 20)
921#define FDI_RX_FDI_DELAY_90			(0x90 << 0)
922
923#define PCH_FDI_TX_BASE_REGISTER			0x60000
924#define PCH_FDI_TX_PIPE_OFFSET				0x01000
925#define PCH_FDI_TX_CONTROL					0x100
926#define FDI_TX_ENABLE						(1 << 31)
927#define FDI_LINK_TRAIN_PATTERN_1			(0 << 28)
928#define FDI_LINK_TRAIN_PATTERN_2			(1 << 28)
929#define FDI_LINK_TRAIN_PATTERN_IDLE			(2 << 28)
930#define FDI_LINK_TRAIN_NONE					(3 << 28)
931#define FDI_LINK_TRAIN_VOLTAGE_0_4V			(0 << 25)
932#define FDI_LINK_TRAIN_VOLTAGE_0_6V			(1 << 25)
933#define FDI_LINK_TRAIN_VOLTAGE_0_8V			(2 << 25)
934#define FDI_LINK_TRAIN_VOLTAGE_1_2V			(3 << 25)
935#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE	(0 << 22)
936#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X	(1 << 22)
937#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X		(2 << 22)
938#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X		(3 << 22)
939
940// SNB A stepping
941#define FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
942#define FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
943#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
944#define FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x00 << 22)
945
946// SNB B stepping
947#define FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x00 << 22)
948#define FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
949#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
950#define FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
951#define FDI_LINK_TRAIN_VOL_EMP_MASK			(0x3f << 22)
952#define FDI_TX_ENHANCE_FRAME_ENABLE			(1 << 18)
953#define FDI_TX_PLL_ENABLED					(1 << 14)
954
955#define FDI_DP_PORT_WIDTH_SHIFT			19
956#define FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
957#define FDI_DP_PORT_WIDTH(width)		(((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
958
959#define FDI_PLL_BIOS_0					0x46000
960#define FDI_PLL_FB_CLOCK_MASK			0xff
961#define FDI_PLL_BIOS_1					0x46004
962#define FDI_PLL_BIOS_2					0x46008
963
964#define FDI_AUTO_TRAINING				(1 << 10)
965#define FDI_AUTO_TRAIN_DONE				(1 << 1)
966
967#define FDI_LINK_TRAIN_PATTERN_1_CPT	(0 << 8)
968#define FDI_LINK_TRAIN_PATTERN_2_CPT	(1 << 8)
969#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2 << 8)
970#define FDI_LINK_TRAIN_NORMAL_CPT		(3 << 8)
971#define FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3 << 8)
972
973// IvyBridge changes it up because... they hate developers?
974#define FDI_LINK_TRAIN_PATTERN_1_IVB	(0 << 8)
975#define FDI_LINK_TRAIN_PATTERN_2_IVB	(1 << 8)
976#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB	(2 << 8)
977#define FDI_LINK_TRAIN_NONE_IVB			(3 << 8)
978
979#define PCH_FDI_RXA_CHICKEN				(0x200c | REGS_SOUTH_SHARED)
980#define PCH_FDI_RXB_CHICKEN				(0x2010 | REGS_SOUTH_SHARED)
981#define FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
982#define FDI_RX_PHASE_SYNC_POINTER_OVR	(1 << 1)
983
984// CPU Panel Fitters - These are for IronLake and up and are the CPU internal
985// panel fitters.
986#define PCH_PANEL_FITTER_BASE_REGISTER	0x68000
987#define PCH_PANEL_FITTER_PIPE_OFFSET	0x00800
988
989#define PCH_PANEL_FITTER_WINDOW_POS		0x70
990#define PCH_PANEL_FITTER_WINDOW_SIZE	0x74
991#define PCH_PANEL_FITTER_CONTROL		0x80
992#define PCH_PANEL_FITTER_V_SCALE		0x84
993#define PCH_PANEL_FITTER_H_SCALE		0x90
994
995#define PANEL_FITTER_ENABLED			(1 << 31)
996#define PANEL_FITTER_FILTER_MASK		(3 << 23)
997
998struct overlay_scale {
999	uint32 _reserved0 : 3;
1000	uint32 horizontal_scale_fraction : 12;
1001	uint32 _reserved1 : 1;
1002	uint32 horizontal_downscale_factor : 3;
1003	uint32 _reserved2 : 1;
1004	uint32 vertical_scale_fraction : 12;
1005};
1006
1007#define OVERLAY_FORMAT_RGB15			0x2
1008#define OVERLAY_FORMAT_RGB16			0x3
1009#define OVERLAY_FORMAT_RGB32			0x1
1010#define OVERLAY_FORMAT_YCbCr422			0x8
1011#define OVERLAY_FORMAT_YCbCr411			0x9
1012#define OVERLAY_FORMAT_YCbCr420			0xc
1013
1014#define OVERLAY_MIRROR_NORMAL			0x0
1015#define OVERLAY_MIRROR_HORIZONTAL		0x1
1016#define OVERLAY_MIRROR_VERTICAL			0x2
1017
1018// The real overlay registers are written to using an update buffer
1019
1020struct overlay_registers {
1021	uint32 buffer_rgb0;
1022	uint32 buffer_rgb1;
1023	uint32 buffer_u0;
1024	uint32 buffer_v0;
1025	uint32 buffer_u1;
1026	uint32 buffer_v1;
1027	// (0x18) OSTRIDE - overlay stride
1028	uint16 stride_rgb;
1029	uint16 stride_uv;
1030	// (0x1c) YRGB_VPH - Y/RGB vertical phase
1031	uint16 vertical_phase0_rgb;
1032	uint16 vertical_phase1_rgb;
1033	// (0x20) UV_VPH - UV vertical phase
1034	uint16 vertical_phase0_uv;
1035	uint16 vertical_phase1_uv;
1036	// (0x24) HORZ_PH - horizontal phase
1037	uint16 horizontal_phase_rgb;
1038	uint16 horizontal_phase_uv;
1039	// (0x28) INIT_PHS - initial phase shift
1040	uint32 initial_vertical_phase0_shift_rgb0 : 4;
1041	uint32 initial_vertical_phase1_shift_rgb0 : 4;
1042	uint32 initial_horizontal_phase_shift_rgb0 : 4;
1043	uint32 initial_vertical_phase0_shift_uv : 4;
1044	uint32 initial_vertical_phase1_shift_uv : 4;
1045	uint32 initial_horizontal_phase_shift_uv : 4;
1046	uint32 _reserved0 : 8;
1047	// (0x2c) DWINPOS - destination window position
1048	uint16 window_left;
1049	uint16 window_top;
1050	// (0x30) DWINSZ - destination window size
1051	uint16 window_width;
1052	uint16 window_height;
1053	// (0x34) SWIDTH - source width
1054	uint16 source_width_rgb;
1055	uint16 source_width_uv;
1056	// (0x38) SWITDHSW - source width in 8 byte steps
1057	uint16 source_bytes_per_row_rgb;
1058	uint16 source_bytes_per_row_uv;
1059	uint16 source_height_rgb;
1060	uint16 source_height_uv;
1061	overlay_scale scale_rgb;
1062	overlay_scale scale_uv;
1063	// (0x48) OCLRC0 - overlay color correction 0
1064	uint32 brightness_correction : 8;		// signed, -128 to 127
1065	uint32 _reserved1 : 10;
1066	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
1067	uint32 _reserved2 : 5;
1068	// (0x4c) OCLRC1 - overlay color correction 1
1069	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
1070	uint32 _reserved3 : 6;
1071	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
1072	uint32 _reserved4 : 5;
1073	// (0x50) DCLRKV - destination color key value
1074	uint32 color_key_blue : 8;
1075	uint32 color_key_green : 8;
1076	uint32 color_key_red : 8;
1077	uint32 _reserved5 : 8;
1078	// (0x54) DCLRKM - destination color key mask
1079	uint32 color_key_mask_blue : 8;
1080	uint32 color_key_mask_green : 8;
1081	uint32 color_key_mask_red : 8;
1082	uint32 _reserved6 : 7;
1083	uint32 color_key_enabled : 1;
1084	// (0x58) SCHRKVH - source chroma key high value
1085	uint32 source_chroma_key_high_red : 8;
1086	uint32 source_chroma_key_high_blue : 8;
1087	uint32 source_chroma_key_high_green : 8;
1088	uint32 _reserved7 : 8;
1089	// (0x5c) SCHRKVL - source chroma key low value
1090	uint32 source_chroma_key_low_red : 8;
1091	uint32 source_chroma_key_low_blue : 8;
1092	uint32 source_chroma_key_low_green : 8;
1093	uint32 _reserved8 : 8;
1094	// (0x60) SCHRKEN - source chroma key enable
1095	uint32 _reserved9 : 24;
1096	uint32 source_chroma_key_red_enabled : 1;
1097	uint32 source_chroma_key_blue_enabled : 1;
1098	uint32 source_chroma_key_green_enabled : 1;
1099	uint32 _reserved10 : 5;
1100	// (0x64) OCONFIG - overlay configuration
1101	uint32 _reserved11 : 3;
1102	uint32 color_control_output_mode : 1;
1103	uint32 yuv_to_rgb_bypass : 1;
1104	uint32 _reserved12 : 11;
1105	uint32 gamma2_enabled : 1;
1106	uint32 _reserved13 : 1;
1107	uint32 select_pipe : 1;
1108	uint32 slot_time : 8;
1109	uint32 _reserved14 : 5;
1110	// (0x68) OCOMD - overlay command
1111	uint32 overlay_enabled : 1;
1112	uint32 active_field : 1;
1113	uint32 active_buffer : 2;
1114	uint32 test_mode : 1;
1115	uint32 buffer_field_mode : 1;
1116	uint32 _reserved15 : 1;
1117	uint32 tv_flip_field_enabled : 1;
1118	uint32 _reserved16 : 1;
1119	uint32 tv_flip_field_parity : 1;
1120	uint32 source_format : 4;
1121	uint32 ycbcr422_order : 2;
1122	uint32 _reserved18 : 1;
1123	uint32 mirroring_mode : 2;
1124	uint32 _reserved19 : 13;
1125
1126	uint32 _reserved20;
1127
1128	uint32 start_0y;
1129	uint32 start_1y;
1130	uint32 start_0u;
1131	uint32 start_0v;
1132	uint32 start_1u;
1133	uint32 start_1v;
1134	uint32 _reserved21[6];
1135#if 0
1136	// (0x70) AWINPOS - alpha blend window position
1137	uint32 awinpos;
1138	// (0x74) AWINSZ - alpha blend window size
1139	uint32 awinsz;
1140
1141	uint32 _reserved21[10];
1142#endif
1143
1144	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
1145	// the next two registers switch the usual Y/RGB vs. UV order)
1146	uint16 horizontal_scale_uv;
1147	uint16 horizontal_scale_rgb;
1148	// (0xa4) UVSCALEV - vertical downscale
1149	uint16 vertical_scale_uv;
1150	uint16 vertical_scale_rgb;
1151
1152	uint32 _reserved22[86];
1153
1154	// (0x200) polyphase filter coefficients
1155	uint16 vertical_coefficients_rgb[128];
1156	uint16 horizontal_coefficients_rgb[128];
1157
1158	uint32	_reserved23[64];
1159
1160	// (0x500)
1161	uint16 vertical_coefficients_uv[128];
1162	uint16 horizontal_coefficients_uv[128];
1163};
1164
1165// i965 overlay support is currently realized using its 3D hardware
1166#define INTEL_i965_OVERLAY_STATE_SIZE	36864
1167#define INTEL_i965_3D_CONTEXT_SIZE		32768
1168
1169inline bool
1170intel_uses_physical_overlay(intel_shared_info &info)
1171{
1172	return !info.device_type.InGroup(INTEL_GROUP_Gxx);
1173}
1174
1175
1176struct hardware_status {
1177	uint32	interrupt_status_register;
1178	uint32	_reserved0[3];
1179	void*	primary_ring_head_storage;
1180	uint32	_reserved1[3];
1181	void*	secondary_ring_0_head_storage;
1182	void*	secondary_ring_1_head_storage;
1183	uint32	_reserved2[2];
1184	void*	binning_head_storage;
1185	uint32	_reserved3[3];
1186	uint32	store[1008];
1187};
1188
1189#endif	/* INTEL_EXTREME_H */
1190