dp_raw.h revision 99756206
1/*
2 * Copyright 2012-2016 Haiku, Inc. All rights reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Alexander von Gluck, kallisti5@unixzen.com
7 */
8#ifndef _DP_RAW_H
9#define _DP_RAW_H
10
11
12/* ****************************************************** */
13/* *** AUX Channel Communications                     *** */
14// Native AUX Communications
15#define DP_AUX_NATIVE_WRITE                    0x8
16#define DP_AUX_NATIVE_READ                     0x9
17#define DP_AUX_NATIVE_REPLY_ACK                (0x0 << 0)
18#define DP_AUX_NATIVE_REPLY_NACK               (0x1 << 0)
19#define DP_AUX_NATIVE_REPLY_DEFER              (0x2 << 0)
20#define DP_AUX_NATIVE_REPLY_MASK               (0x3 << 0)
21// AUX i2c Communications
22#define DP_AUX_I2C_WRITE                       0x0
23#define DP_AUX_I2C_READ                        0x1
24#define DP_AUX_I2C_STATUS                      0x2
25#define DP_AUX_I2C_MOT                         0x4
26#define DP_AUX_I2C_REPLY_ACK                   (0x0 << 2)
27#define DP_AUX_I2C_REPLY_NACK                  (0x1 << 2)
28#define DP_AUX_I2C_REPLY_DEFER                 (0x2 << 2)
29#define DP_AUX_I2C_REPLY_MASK                  (0x3 << 2)
30
31
32/* ****************************************************** */
33/* *** DPCD (DisplayPort Configuration Data)          *** */
34/* *** Read / Written over DisplayPort AUX link       *** */
35
36/* *** DPCD Receiver Compatibility Field (0x0000)     *** */
37/* *** VESA DisplayPort Standard, rev 1.1, p112       *** */
38// DPCD Version (0x0)
39#define DP_DPCD_SIZE						0xf			// Size
40#define DP_DPCD_REV							0x0000		// Reg
41#define DP_DPCD_REV_MINOR_MASK				(15 << 0)	// Int
42#define DP_DPCD_REV_MAJOR_MASK				(15 << 4)	// Int
43#define DP_DPCD_REV_10						0x0010		// Value
44#define DP_DPCD_REV_11						0x0011		// Value
45// DP Maximum Link Rate (0x1)
46#define DP_MAX_LINK_RATE					0x0001		// Reg
47// Use DP_LINK_RATE_* for speed.
48// DP Maximum Lane Count (0x2)
49#define DP_MAX_LANE_COUNT					0x0002		// Reg
50#define DP_MAX_LANE_COUNT_MASK				(31 << 0)	// Count
51#define DP_MAX_LANE_COUNT_1					(1 << 0)	// Value
52#define DP_MAX_LANE_COUNT_2					(2 << 0)	// Value
53#define DP_MAX_LANE_COUNT_4					(4 << 0)	// Value
54#define DP_ENHANCED_FRAME_CAP_EN			(1 << 7)	// Bool, Rev 1.1
55// DP Maximum Downspread (0x3)
56#define DP_MAX_DOWNSPREAD					0x0003		// Reg
57#define DP_MAX_DOWNSPREAD_EN				(1 << 0)	// Bool
58#define DP_MAX_DOWNSPREAD_REQ_NO_HANDSHAKE	(1 << 6)	// Bool
59// DP Number of Receiver Ports (0x4)
60#define DP_NORP								0x0004		// Reg
61#define DP_NORP_MASK						(1 << 0)	// Count
62// DP Downstream Port Present (0x5)
63#define DP_DOWNSTREAMPORT					0x0005		// Reg
64#define DP_DOWNSTREAMPORT_EN				(1 << 0)	// Bool
65#define DP_DOWNSTREAMPORT_TYPE_MASK			(3 << 1)	// Mask
66#define DP_DOWNSTREAMPORT_TYPE_DP			(0 << 1)	// Value
67#define DP_DOWNSTREAMPORT_TYPE_ANALOG		(1 << 1)	// Value
68#define DP_DOWNSTREAMPORT_TYPE_DIGITAL		(2 << 1)	// Value
69#define DP_DOWNSTREAMPORT_TYPE_OTHER		(3 << 1)	// Value
70#define DP_DOWNSTREAMPORT_FORMAT_EN			(1 << 3)	// Bool
71// DP Main Link Channel Coding (0x6)
72#define DP_CURR_MAIN_CHAN_CODE				0x0006		// Reg
73#define DP_CURR_MAIN_CHAN_CODE_ANSIX3_EN	(1 << 0)	// Bool
74// DP Downstream Port Count (0x7) (Only 1.1+)
75#define DP_DOWNSTREAMPORT_COUNT				0x0007		// Reg
76#define DP_DOWNSTREAMPORT_COUNT_MASK		(15 << 0)	// Count
77#define DP_DOWNSTREAMPORT_COUNT_OUI_EN		(1 << 7)	// Bool
78// DP Port Capability 0
79#define DP_PORT0_CAPABILITY0				0x0008		// Reg
80#define DP_PORT1_CAPABILITY0				0x000A		// Reg
81#define DP_PORT_CAPABILITY0_EDID_EN			(1 << 1)	// Bool
82#define DP_PORT_CAPABILITY0_SECOND_EN		(1 << 2)	// Bool
83// DP Port Capability 1
84#define DP_PORT0_CAPABILITY1				0x0009		// Reg
85#define DP_PORT1_CAPABILITY1				0x000B		// Reg
86#define DP_PORT_CAPABILITY1_BUF_SIZE_MASK	(255 << 0)	// Size
87	// (value + 1) * 32 bytes per lane
88
89/* *** DPCD Link Configuration Field (0x0100)         *** */
90/* *** VESA DisplayPort Standard, rev 1.1, p117       *** */
91
92// DP Set Link Rate Per Lane (0x0100)
93#define DP_LINK_RATE						0x0100		// Reg
94#define DP_LINK_RATE_162					0x0006		// 1.62Ghz
95#define DP_LINK_RATE_270					0x000A		// 2.70Ghz
96#define DP_LINK_RATE_540					0x0014		// 5.40Ghz
97// DP Set Lane Count (0x0101)
98#define DP_LANE_COUNT						0x0101		// Reg
99#define DP_LANE_COUNT_MASK					(31 << 0)	// Count
100#define DP_ENHANCED_FRAME_EN				(1 << 7)	// Bool, Rev 1.1
101// DP Training Pattern (0x0102)
102#define DP_TRAIN							0x0102		// Reg
103#define DP_TRAIN_PATTERN_MASK				(3 << 0)	// Mask
104#define DP_TRAIN_PATTERN_DISABLED			(0 << 0)	// Value
105#define DP_TRAIN_PATTERN_1					(1 << 0)	// Value
106#define DP_TRAIN_PATTERN_2					(2 << 0)	// Value
107#define DP_TRAIN_PATTERN_3					(3 << 0)	// Value
108
109#define DP_TRAIN_QUAL_MASK					(3 << 2)	// Mask
110#define DP_TRAIN_QUAL_NONE					(0 << 2)	// Value
111#define DP_TRAIN_QUAL_D102					(1 << 2)	// Value
112#define DP_TRAIN_QUAL_SYMB_ERR				(2 << 2)	// Value
113#define DP_TRAIN_QUAL_PRBS7					(3 << 2)	// Value
114
115#define DP_TRAIN_CLOCK_RECOVER_EN			(1 << 4)	// Bool
116#define DP_TRAIN_SCRAMBLE_DI				(1 << 5)	// Bool (rev)
117#define DP_TRAIN_SYMBL_ERR_SEL_MASK			(3 << 6)	// Mask
118#define DP_TRAIN_SYMBL_ERR_SEL_BOTH			(0 << 6)	// Value
119#define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY	(1 << 6)	// Value
120#define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL		(2 << 6)	// Value
121// DP Training Lane n (0x0103 - 0x0106)
122#define DP_TRAIN_LANE0						0x0103		// Reg
123#define DP_TRAIN_LANE1						0x0104		// Reg
124#define DP_TRAIN_LANE2						0x0105		// Reg
125#define DP_TRAIN_LANE3						0x0106		// Reg
126
127#define DP_TRAIN_VCC_SWING_SHIFT			(0 << 0)	// Shift
128#define DP_TRAIN_VCC_SWING_MASK				(3 << 0)	// Mask
129#define DP_TRAIN_VCC_SWING_400				(0 << 0)	// Value
130#define DP_TRAIN_VCC_SWING_600				(1 << 0)	// Value
131#define DP_TRAIN_VCC_SWING_800				(2 << 0)	// Value
132#define DP_TRAIN_VCC_SWING_1200				(3 << 0)	// Value
133#define DP_TRAIN_MAX_SWING_EN				(1 << 2)	// Bool
134
135#define DP_TRAIN_PRE_EMPHASIS_SHIFT			(3 << 0)	// Shift
136#define DP_TRAIN_PRE_EMPHASIS_MASK			(3 << 3)	// Mask
137#define DP_TRAIN_PRE_EMPHASIS_0				(0 << 3)	// Value
138#define DP_TRAIN_PRE_EMPHASIS_3_5			(1 << 3)	// Value
139#define DP_TRAIN_PRE_EMPHASIS_6				(2 << 3)	// Value
140#define DP_TRAIN_PRE_EMPHASIS_9_5			(3 << 3)	// Value
141#define DP_TRAIN_MAX_EMPHASIS_EN			(1 << 5)	// Bool
142// DP Down-spread Control (0x0107)
143#define DP_DOWNSPREAD_CTRL					0x0107		// Reg
144#define DP_DOWNSPREAD_CTRL_FREQ_MASK		(1 << 0)	// Int
145#define DP_DOWNSPREAD_CTRL_AMP_EN			(1 << 4)	// Int
146// DP Main Link Channel Coding (0x0108)
147#define DP_MAIN_CHAN_CODE					0x0108		// Reg
148#define DP_MAIN_CHAN_CODE_ANSIX3_EN			(1 << 0)	// Bool
149
150/* *** DPCD Link / Sink Status Field (0x0200)         *** */
151/* *** VESA DisplayPort Standard, rev 1.1, p120       *** */
152
153// DP Sink Count (0x0200)
154#define DP_SINK_COUNT						0x0200		// Reg
155#define DP_SINK_COUNT_MASK					(63 << 0)	// Mask
156#define DP_SINK_COUNT_CP_READY				(1 << 6)	// Bool
157// DP Service IRQ Vector (0x0201)
158#define DP_SINK_IRQ_VECTOR					0x0201		// Reg
159#define DP_SINK_IRQ_TEST_REQ				(1 << 1)	// Bool
160#define DP_SINK_IRQ_CP_IRQ					(1 << 2)	// Bool
161#define DP_SINK_IRQ_VENDOR					(1 << 6)	// Bool
162// DP Lane Status      A B
163#define DP_LANE_STATUS_0_1					0x0202		// Reg
164#define DP_LANE_STATUS_2_3					0x0203		// Reg
165#define DP_LINK_STATUS_SIZE					6			// Size
166#define DP_LANE_STATUS_CR_DONE_A			(1 << 0)	// Bool
167#define DP_LANE_STATUS_CHEQ_DONE_A			(1 << 1)	// Bool
168#define DP_LANE_STATUS_SYMB_LOCK_A			(1 << 2)	// Bool
169#define DP_LANE_STATUS_CR_DONE_B			(1 << 4)	// Bool
170#define DP_LANE_STATUS_CHEQ_DONE_B			(1 << 5)	// Bool
171#define DP_LANE_STATUS_SYMB_LOCK_B			(1 << 6)	// Bool
172#define DP_LANE_STATUS_EQUALIZED_A			DP_LANE_STATUS_CR_DONE_A \
173											|| DP_LANE_STATUS_CHEQ_DONE_A \
174											|| DP_LANE_STATUS_SYMB_LOCK_A
175#define DP_LANE_STATUS_EQUALIZED_B			DP_LANE_STATUS_CR_DONE_B \
176											|| DP_LANE_STATUS_CHEQ_DONE_B \
177											|| DP_LANE_STATUS_SYMB_LOCK_B
178// DP Lane Align Status (0x0204)
179#define DP_LANE_ALIGN						0x0204		// Reg
180#define DP_LANE_ALIGN_DONE					(1 << 0)	// Bool
181#define DP_LANE_ALIGN_PORT_STATUS_CHANGE	(1 << 6)	// Bool
182#define DP_LANE_ALIGN_LINK_STATUS_UPDATE	(1 << 7)	// Bool
183// DP Sink Status (0x0205)
184#define DP_SINK_STATUS						0x0205		// Reg
185#define DP_SINK_STATUS_IN_SYNC_0			(1 << 0)	// Bool
186#define DP_SINK_STATUS_IN_SYNC_1			(1 << 1)	// Bool
187// DP Adjust Request   A B
188#define DP_ADJ_REQUEST_0_1					0x0206		// Reg
189#define DP_ADJ_REQUEST_2_3					0x0207		// Reg
190#define DP_ADJ_VCC_SWING_LANEA_SHIFT		0			// Shift
191#define DP_ADJ_VCC_SWING_LANEA_MASK			(3 << 0)	// Mask
192#define DP_ADJ_PRE_EMPHASIS_LANEA_SHIFT		2			// Shift
193#define DP_ADJ_PRE_EMPHASIS_LANEA_MASK		(3 << 2)	// Mask
194#define DP_ADJ_VCC_SWING_LANEB_SHIFT		4			// Shift
195#define DP_ADJ_VCC_SRING_LANEB_MASK			(3 << 4)	// Mask
196#define DP_ADJ_PRE_EMPHASIS_LANEB_SHIFT		6			// Shift
197#define DP_ADJ_PRE_EMPHASIS_LANEB_MASK		(3 << 6)	// Mask
198
199// TODO: 0x0210 - 0x0217
200
201/* *** DPCD Automated Self-testing Field (0x0218)     *** */
202/* *** VESA DisplayPort Standard, rev 1.1, p123       *** */
203
204// TODO: Optional Field
205
206/* *** DPCD Source Device Specific Field (0x0300)     *** */
207/* *** VESA DisplayPort Standard, rev 1.1, p127       *** */
208
209// TODO
210
211/* *** DPCD Sink Device Specific Field (0x0400)       *** */
212/* *** VESA DisplayPort Standard, rev 1.1, p127       *** */
213
214// TODO
215
216/* *** DPCD Branch Device Specific Field (0x0500)     *** */
217/* *** VESA DisplayPort Standard, rev 1.1, p127       *** */
218
219// TODO
220
221/* *** DPCD Sink Control Field (0x0600)               *** */
222/* *** VESA DisplayPort Standard, rev 1.1, p128       *** */
223
224#define DP_SET_POWER						0x0600		// Reg
225#define DP_SET_POWER_D0						(1 << 0)	// Value
226#define DP_SET_POWER_D3						(1 << 1)	// Value
227
228/* *** DPCD Reserved (0x0700+)                        *** */
229/* ****************************************************** */
230
231
232#endif /* _DP_RAW_H */
233