14185aa0cSAlexander von Gluck IV/*
299756206SAlexander von Gluck IV * Copyright 2012-2016 Haiku, Inc. All rights reserved.
34185aa0cSAlexander von Gluck IV * Distributed under the terms of the MIT License.
44185aa0cSAlexander von Gluck IV *
54185aa0cSAlexander von Gluck IV * Authors:
64185aa0cSAlexander von Gluck IV *		Alexander von Gluck, kallisti5@unixzen.com
74185aa0cSAlexander von Gluck IV */
84185aa0cSAlexander von Gluck IV#ifndef _DP_RAW_H
94185aa0cSAlexander von Gluck IV#define _DP_RAW_H
104185aa0cSAlexander von Gluck IV
114185aa0cSAlexander von Gluck IV
1237550d80SAlexander von Gluck IV/* ****************************************************** */
1337550d80SAlexander von Gluck IV/* *** AUX Channel Communications                     *** */
1437550d80SAlexander von Gluck IV// Native AUX Communications
157ea1ad10SAlexander von Gluck IV#define DP_AUX_NATIVE_WRITE                    0x8
167ea1ad10SAlexander von Gluck IV#define DP_AUX_NATIVE_READ                     0x9
177ea1ad10SAlexander von Gluck IV#define DP_AUX_NATIVE_REPLY_ACK                (0x0 << 0)
187ea1ad10SAlexander von Gluck IV#define DP_AUX_NATIVE_REPLY_NACK               (0x1 << 0)
197ea1ad10SAlexander von Gluck IV#define DP_AUX_NATIVE_REPLY_DEFER              (0x2 << 0)
207ea1ad10SAlexander von Gluck IV#define DP_AUX_NATIVE_REPLY_MASK               (0x3 << 0)
2137550d80SAlexander von Gluck IV// AUX i2c Communications
227ea1ad10SAlexander von Gluck IV#define DP_AUX_I2C_WRITE                       0x0
237ea1ad10SAlexander von Gluck IV#define DP_AUX_I2C_READ                        0x1
2466a16010SAlexander von Gluck IV#define DP_AUX_I2C_WRITE_STATUS_UPDATE         0x2
257ea1ad10SAlexander von Gluck IV#define DP_AUX_I2C_MOT                         0x4
267ea1ad10SAlexander von Gluck IV#define DP_AUX_I2C_REPLY_ACK                   (0x0 << 2)
277ea1ad10SAlexander von Gluck IV#define DP_AUX_I2C_REPLY_NACK                  (0x1 << 2)
287ea1ad10SAlexander von Gluck IV#define DP_AUX_I2C_REPLY_DEFER                 (0x2 << 2)
297ea1ad10SAlexander von Gluck IV#define DP_AUX_I2C_REPLY_MASK                  (0x3 << 2)
3037550d80SAlexander von Gluck IV
3137550d80SAlexander von Gluck IV
324185aa0cSAlexander von Gluck IV/* ****************************************************** */
334185aa0cSAlexander von Gluck IV/* *** DPCD (DisplayPort Configuration Data)          *** */
344185aa0cSAlexander von Gluck IV/* *** Read / Written over DisplayPort AUX link       *** */
354185aa0cSAlexander von Gluck IV
364185aa0cSAlexander von Gluck IV/* *** DPCD Receiver Compatibility Field (0x0000)     *** */
374185aa0cSAlexander von Gluck IV/* *** VESA DisplayPort Standard, rev 1.1, p112       *** */
384185aa0cSAlexander von Gluck IV// DPCD Version (0x0)
398ebdc440SAlexander von Gluck IV#define DP_DPCD_SIZE						0xf			// Size
40c6799d8aSAlexander von Gluck IV#define DP_DPCD_REV							0x0000		// Reg
41c6799d8aSAlexander von Gluck IV#define DP_DPCD_REV_MINOR_MASK				(15 << 0)	// Int
42c6799d8aSAlexander von Gluck IV#define DP_DPCD_REV_MAJOR_MASK				(15 << 4)	// Int
43c6799d8aSAlexander von Gluck IV#define DP_DPCD_REV_10						0x0010		// Value
44c6799d8aSAlexander von Gluck IV#define DP_DPCD_REV_11						0x0011		// Value
452da9ebb7SAlexander von Gluck IV#define DP_DPCD_REV_12						0x0012		// Value
464185aa0cSAlexander von Gluck IV// DP Maximum Link Rate (0x1)
47c6799d8aSAlexander von Gluck IV#define DP_MAX_LINK_RATE					0x0001		// Reg
48c6799d8aSAlexander von Gluck IV// Use DP_LINK_RATE_* for speed.
494185aa0cSAlexander von Gluck IV// DP Maximum Lane Count (0x2)
50c6799d8aSAlexander von Gluck IV#define DP_MAX_LANE_COUNT					0x0002		// Reg
51c6799d8aSAlexander von Gluck IV#define DP_MAX_LANE_COUNT_MASK				(31 << 0)	// Count
52c6799d8aSAlexander von Gluck IV#define DP_MAX_LANE_COUNT_1					(1 << 0)	// Value
53c6799d8aSAlexander von Gluck IV#define DP_MAX_LANE_COUNT_2					(2 << 0)	// Value
54c6799d8aSAlexander von Gluck IV#define DP_MAX_LANE_COUNT_4					(4 << 0)	// Value
55c6799d8aSAlexander von Gluck IV#define DP_ENHANCED_FRAME_CAP_EN			(1 << 7)	// Bool, Rev 1.1
564185aa0cSAlexander von Gluck IV// DP Maximum Downspread (0x3)
57c6799d8aSAlexander von Gluck IV#define DP_MAX_DOWNSPREAD					0x0003		// Reg
58c6799d8aSAlexander von Gluck IV#define DP_MAX_DOWNSPREAD_EN				(1 << 0)	// Bool
59c6799d8aSAlexander von Gluck IV#define DP_MAX_DOWNSPREAD_REQ_NO_HANDSHAKE	(1 << 6)	// Bool
604185aa0cSAlexander von Gluck IV// DP Number of Receiver Ports (0x4)
61c6799d8aSAlexander von Gluck IV#define DP_NORP								0x0004		// Reg
62c6799d8aSAlexander von Gluck IV#define DP_NORP_MASK						(1 << 0)	// Count
634185aa0cSAlexander von Gluck IV// DP Downstream Port Present (0x5)
64c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT					0x0005		// Reg
65c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT_EN				(1 << 0)	// Bool
66c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT_TYPE_MASK			(3 << 1)	// Mask
67c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT_TYPE_DP			(0 << 1)	// Value
68c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT_TYPE_ANALOG		(1 << 1)	// Value
69c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT_TYPE_DIGITAL		(2 << 1)	// Value
70c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT_TYPE_OTHER		(3 << 1)	// Value
71c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT_FORMAT_EN			(1 << 3)	// Bool
724185aa0cSAlexander von Gluck IV// DP Main Link Channel Coding (0x6)
73c6799d8aSAlexander von Gluck IV#define DP_CURR_MAIN_CHAN_CODE				0x0006		// Reg
74c6799d8aSAlexander von Gluck IV#define DP_CURR_MAIN_CHAN_CODE_ANSIX3_EN	(1 << 0)	// Bool
754185aa0cSAlexander von Gluck IV// DP Downstream Port Count (0x7) (Only 1.1+)
76c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT_COUNT				0x0007		// Reg
77c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT_COUNT_MASK		(15 << 0)	// Count
78c6799d8aSAlexander von Gluck IV#define DP_DOWNSTREAMPORT_COUNT_OUI_EN		(1 << 7)	// Bool
794185aa0cSAlexander von Gluck IV// DP Port Capability 0
80c6799d8aSAlexander von Gluck IV#define DP_PORT0_CAPABILITY0				0x0008		// Reg
81c6799d8aSAlexander von Gluck IV#define DP_PORT1_CAPABILITY0				0x000A		// Reg
82c6799d8aSAlexander von Gluck IV#define DP_PORT_CAPABILITY0_EDID_EN			(1 << 1)	// Bool
83c6799d8aSAlexander von Gluck IV#define DP_PORT_CAPABILITY0_SECOND_EN		(1 << 2)	// Bool
844185aa0cSAlexander von Gluck IV// DP Port Capability 1
85c6799d8aSAlexander von Gluck IV#define DP_PORT0_CAPABILITY1				0x0009		// Reg
86c6799d8aSAlexander von Gluck IV#define DP_PORT1_CAPABILITY1				0x000B		// Reg
87c6799d8aSAlexander von Gluck IV#define DP_PORT_CAPABILITY1_BUF_SIZE_MASK	(255 << 0)	// Size
884185aa0cSAlexander von Gluck IV	// (value + 1) * 32 bytes per lane
894185aa0cSAlexander von Gluck IV
904185aa0cSAlexander von Gluck IV/* *** DPCD Link Configuration Field (0x0100)         *** */
914185aa0cSAlexander von Gluck IV/* *** VESA DisplayPort Standard, rev 1.1, p117       *** */
924185aa0cSAlexander von Gluck IV
934185aa0cSAlexander von Gluck IV// DP Set Link Rate Per Lane (0x0100)
94c6799d8aSAlexander von Gluck IV#define DP_LINK_RATE						0x0100		// Reg
95c6799d8aSAlexander von Gluck IV#define DP_LINK_RATE_162					0x0006		// 1.62Ghz
96c6799d8aSAlexander von Gluck IV#define DP_LINK_RATE_270					0x000A		// 2.70Ghz
97c6799d8aSAlexander von Gluck IV#define DP_LINK_RATE_540					0x0014		// 5.40Ghz
984185aa0cSAlexander von Gluck IV// DP Set Lane Count (0x0101)
99c6799d8aSAlexander von Gluck IV#define DP_LANE_COUNT						0x0101		// Reg
100c6799d8aSAlexander von Gluck IV#define DP_LANE_COUNT_MASK					(31 << 0)	// Count
101c6799d8aSAlexander von Gluck IV#define DP_ENHANCED_FRAME_EN				(1 << 7)	// Bool, Rev 1.1
1024185aa0cSAlexander von Gluck IV// DP Training Pattern (0x0102)
103c6799d8aSAlexander von Gluck IV#define DP_TRAIN							0x0102		// Reg
104c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PATTERN_MASK				(3 << 0)	// Mask
105c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PATTERN_DISABLED			(0 << 0)	// Value
106c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PATTERN_1					(1 << 0)	// Value
107c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PATTERN_2					(2 << 0)	// Value
108c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PATTERN_3					(3 << 0)	// Value
109c6799d8aSAlexander von Gluck IV
110c6799d8aSAlexander von Gluck IV#define DP_TRAIN_QUAL_MASK					(3 << 2)	// Mask
111c6799d8aSAlexander von Gluck IV#define DP_TRAIN_QUAL_NONE					(0 << 2)	// Value
112c6799d8aSAlexander von Gluck IV#define DP_TRAIN_QUAL_D102					(1 << 2)	// Value
113c6799d8aSAlexander von Gluck IV#define DP_TRAIN_QUAL_SYMB_ERR				(2 << 2)	// Value
114c6799d8aSAlexander von Gluck IV#define DP_TRAIN_QUAL_PRBS7					(3 << 2)	// Value
115c6799d8aSAlexander von Gluck IV
116c6799d8aSAlexander von Gluck IV#define DP_TRAIN_CLOCK_RECOVER_EN			(1 << 4)	// Bool
117c6799d8aSAlexander von Gluck IV#define DP_TRAIN_SCRAMBLE_DI				(1 << 5)	// Bool (rev)
118c6799d8aSAlexander von Gluck IV#define DP_TRAIN_SYMBL_ERR_SEL_MASK			(3 << 6)	// Mask
119c6799d8aSAlexander von Gluck IV#define DP_TRAIN_SYMBL_ERR_SEL_BOTH			(0 << 6)	// Value
120c6799d8aSAlexander von Gluck IV#define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY	(1 << 6)	// Value
121c6799d8aSAlexander von Gluck IV#define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL		(2 << 6)	// Value
1224185aa0cSAlexander von Gluck IV// DP Training Lane n (0x0103 - 0x0106)
123c6799d8aSAlexander von Gluck IV#define DP_TRAIN_LANE0						0x0103		// Reg
124c6799d8aSAlexander von Gluck IV#define DP_TRAIN_LANE1						0x0104		// Reg
125c6799d8aSAlexander von Gluck IV#define DP_TRAIN_LANE2						0x0105		// Reg
126c6799d8aSAlexander von Gluck IV#define DP_TRAIN_LANE3						0x0106		// Reg
127c6799d8aSAlexander von Gluck IV
128c6799d8aSAlexander von Gluck IV#define DP_TRAIN_VCC_SWING_SHIFT			(0 << 0)	// Shift
129c6799d8aSAlexander von Gluck IV#define DP_TRAIN_VCC_SWING_MASK				(3 << 0)	// Mask
130c6799d8aSAlexander von Gluck IV#define DP_TRAIN_VCC_SWING_400				(0 << 0)	// Value
131c6799d8aSAlexander von Gluck IV#define DP_TRAIN_VCC_SWING_600				(1 << 0)	// Value
132c6799d8aSAlexander von Gluck IV#define DP_TRAIN_VCC_SWING_800				(2 << 0)	// Value
133c6799d8aSAlexander von Gluck IV#define DP_TRAIN_VCC_SWING_1200				(3 << 0)	// Value
134c6799d8aSAlexander von Gluck IV#define DP_TRAIN_MAX_SWING_EN				(1 << 2)	// Bool
135c6799d8aSAlexander von Gluck IV
136c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PRE_EMPHASIS_SHIFT			(3 << 0)	// Shift
137c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PRE_EMPHASIS_MASK			(3 << 3)	// Mask
138c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PRE_EMPHASIS_0				(0 << 3)	// Value
139c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PRE_EMPHASIS_3_5			(1 << 3)	// Value
140c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PRE_EMPHASIS_6				(2 << 3)	// Value
141c6799d8aSAlexander von Gluck IV#define DP_TRAIN_PRE_EMPHASIS_9_5			(3 << 3)	// Value
142c6799d8aSAlexander von Gluck IV#define DP_TRAIN_MAX_EMPHASIS_EN			(1 << 5)	// Bool
1434185aa0cSAlexander von Gluck IV// DP Down-spread Control (0x0107)
144c6799d8aSAlexander von Gluck IV#define DP_DOWNSPREAD_CTRL					0x0107		// Reg
145c6799d8aSAlexander von Gluck IV#define DP_DOWNSPREAD_CTRL_FREQ_MASK		(1 << 0)	// Int
146c6799d8aSAlexander von Gluck IV#define DP_DOWNSPREAD_CTRL_AMP_EN			(1 << 4)	// Int
1474185aa0cSAlexander von Gluck IV// DP Main Link Channel Coding (0x0108)
148c6799d8aSAlexander von Gluck IV#define DP_MAIN_CHAN_CODE					0x0108		// Reg
149c6799d8aSAlexander von Gluck IV#define DP_MAIN_CHAN_CODE_ANSIX3_EN			(1 << 0)	// Bool
1504185aa0cSAlexander von Gluck IV
1514185aa0cSAlexander von Gluck IV/* *** DPCD Link / Sink Status Field (0x0200)         *** */
1524185aa0cSAlexander von Gluck IV/* *** VESA DisplayPort Standard, rev 1.1, p120       *** */
1534185aa0cSAlexander von Gluck IV
1548dfc5dbbSAlexander von Gluck IV// DP Sink Count (0x0200)
1558dfc5dbbSAlexander von Gluck IV#define DP_SINK_COUNT						0x0200		// Reg
1568dfc5dbbSAlexander von Gluck IV#define DP_SINK_COUNT_MASK					(63 << 0)	// Mask
1578dfc5dbbSAlexander von Gluck IV#define DP_SINK_COUNT_CP_READY				(1 << 6)	// Bool
1588dfc5dbbSAlexander von Gluck IV// DP Service IRQ Vector (0x0201)
1598dfc5dbbSAlexander von Gluck IV#define DP_SINK_IRQ_VECTOR					0x0201		// Reg
1608dfc5dbbSAlexander von Gluck IV#define DP_SINK_IRQ_TEST_REQ				(1 << 1)	// Bool
1618dfc5dbbSAlexander von Gluck IV#define DP_SINK_IRQ_CP_IRQ					(1 << 2)	// Bool
1628dfc5dbbSAlexander von Gluck IV#define DP_SINK_IRQ_VENDOR					(1 << 6)	// Bool
1638dfc5dbbSAlexander von Gluck IV// DP Lane Status      A B
1648dfc5dbbSAlexander von Gluck IV#define DP_LANE_STATUS_0_1					0x0202		// Reg
1658dfc5dbbSAlexander von Gluck IV#define DP_LANE_STATUS_2_3					0x0203		// Reg
1668dfc5dbbSAlexander von Gluck IV#define DP_LINK_STATUS_SIZE					6			// Size
1678dfc5dbbSAlexander von Gluck IV#define DP_LANE_STATUS_CR_DONE_A			(1 << 0)	// Bool
1688dfc5dbbSAlexander von Gluck IV#define DP_LANE_STATUS_CHEQ_DONE_A			(1 << 1)	// Bool
1698dfc5dbbSAlexander von Gluck IV#define DP_LANE_STATUS_SYMB_LOCK_A			(1 << 2)	// Bool
1708dfc5dbbSAlexander von Gluck IV#define DP_LANE_STATUS_CR_DONE_B			(1 << 4)	// Bool
1718dfc5dbbSAlexander von Gluck IV#define DP_LANE_STATUS_CHEQ_DONE_B			(1 << 5)	// Bool
1728dfc5dbbSAlexander von Gluck IV#define DP_LANE_STATUS_SYMB_LOCK_B			(1 << 6)	// Bool
1737f167d4fSAlexander von Gluck IV#define DP_LANE_STATUS_EQUALIZED_A			(DP_LANE_STATUS_CR_DONE_A \
1747f167d4fSAlexander von Gluck IV											| DP_LANE_STATUS_CHEQ_DONE_A \
1757f167d4fSAlexander von Gluck IV											| DP_LANE_STATUS_SYMB_LOCK_A)
1767f167d4fSAlexander von Gluck IV#define DP_LANE_STATUS_EQUALIZED_B			(DP_LANE_STATUS_CR_DONE_B \
1777f167d4fSAlexander von Gluck IV											| DP_LANE_STATUS_CHEQ_DONE_B \
1787f167d4fSAlexander von Gluck IV											| DP_LANE_STATUS_SYMB_LOCK_B)
1798dfc5dbbSAlexander von Gluck IV// DP Lane Align Status (0x0204)
1808dfc5dbbSAlexander von Gluck IV#define DP_LANE_ALIGN						0x0204		// Reg
1818dfc5dbbSAlexander von Gluck IV#define DP_LANE_ALIGN_DONE					(1 << 0)	// Bool
1828dfc5dbbSAlexander von Gluck IV#define DP_LANE_ALIGN_PORT_STATUS_CHANGE	(1 << 6)	// Bool
1838dfc5dbbSAlexander von Gluck IV#define DP_LANE_ALIGN_LINK_STATUS_UPDATE	(1 << 7)	// Bool
1848dfc5dbbSAlexander von Gluck IV// DP Sink Status (0x0205)
1858dfc5dbbSAlexander von Gluck IV#define DP_SINK_STATUS						0x0205		// Reg
1868dfc5dbbSAlexander von Gluck IV#define DP_SINK_STATUS_IN_SYNC_0			(1 << 0)	// Bool
1878dfc5dbbSAlexander von Gluck IV#define DP_SINK_STATUS_IN_SYNC_1			(1 << 1)	// Bool
1888dfc5dbbSAlexander von Gluck IV// DP Adjust Request   A B
1898dfc5dbbSAlexander von Gluck IV#define DP_ADJ_REQUEST_0_1					0x0206		// Reg
1908dfc5dbbSAlexander von Gluck IV#define DP_ADJ_REQUEST_2_3					0x0207		// Reg
1918dfc5dbbSAlexander von Gluck IV#define DP_ADJ_VCC_SWING_LANEA_SHIFT		0			// Shift
1928dfc5dbbSAlexander von Gluck IV#define DP_ADJ_VCC_SWING_LANEA_MASK			(3 << 0)	// Mask
1938dfc5dbbSAlexander von Gluck IV#define DP_ADJ_PRE_EMPHASIS_LANEA_SHIFT		2			// Shift
1948dfc5dbbSAlexander von Gluck IV#define DP_ADJ_PRE_EMPHASIS_LANEA_MASK		(3 << 2)	// Mask
1958dfc5dbbSAlexander von Gluck IV#define DP_ADJ_VCC_SWING_LANEB_SHIFT		4			// Shift
1968dfc5dbbSAlexander von Gluck IV#define DP_ADJ_VCC_SRING_LANEB_MASK			(3 << 4)	// Mask
1978dfc5dbbSAlexander von Gluck IV#define DP_ADJ_PRE_EMPHASIS_LANEB_SHIFT		6			// Shift
1988dfc5dbbSAlexander von Gluck IV#define DP_ADJ_PRE_EMPHASIS_LANEB_MASK		(3 << 6)	// Mask
1998dfc5dbbSAlexander von Gluck IV
2008dfc5dbbSAlexander von Gluck IV// TODO: 0x0210 - 0x0217
2014185aa0cSAlexander von Gluck IV
2024185aa0cSAlexander von Gluck IV/* *** DPCD Automated Self-testing Field (0x0218)     *** */
2034185aa0cSAlexander von Gluck IV/* *** VESA DisplayPort Standard, rev 1.1, p123       *** */
2044185aa0cSAlexander von Gluck IV
2054185aa0cSAlexander von Gluck IV// TODO: Optional Field
2064185aa0cSAlexander von Gluck IV
2074185aa0cSAlexander von Gluck IV/* *** DPCD Source Device Specific Field (0x0300)     *** */
2084185aa0cSAlexander von Gluck IV/* *** VESA DisplayPort Standard, rev 1.1, p127       *** */
2094185aa0cSAlexander von Gluck IV
2104185aa0cSAlexander von Gluck IV// TODO
2114185aa0cSAlexander von Gluck IV
2124185aa0cSAlexander von Gluck IV/* *** DPCD Sink Device Specific Field (0x0400)       *** */
2134185aa0cSAlexander von Gluck IV/* *** VESA DisplayPort Standard, rev 1.1, p127       *** */
2144185aa0cSAlexander von Gluck IV
2154185aa0cSAlexander von Gluck IV// TODO
2164185aa0cSAlexander von Gluck IV
2174185aa0cSAlexander von Gluck IV/* *** DPCD Branch Device Specific Field (0x0500)     *** */
2184185aa0cSAlexander von Gluck IV/* *** VESA DisplayPort Standard, rev 1.1, p127       *** */
2194185aa0cSAlexander von Gluck IV
2204185aa0cSAlexander von Gluck IV// TODO
2214185aa0cSAlexander von Gluck IV
2224185aa0cSAlexander von Gluck IV/* *** DPCD Sink Control Field (0x0600)               *** */
2234185aa0cSAlexander von Gluck IV/* *** VESA DisplayPort Standard, rev 1.1, p128       *** */
2244185aa0cSAlexander von Gluck IV
2258dfc5dbbSAlexander von Gluck IV#define DP_SET_POWER						0x0600		// Reg
2268dfc5dbbSAlexander von Gluck IV#define DP_SET_POWER_D0						(1 << 0)	// Value
2278dfc5dbbSAlexander von Gluck IV#define DP_SET_POWER_D3						(1 << 1)	// Value
2284185aa0cSAlexander von Gluck IV
2294185aa0cSAlexander von Gluck IV/* *** DPCD Reserved (0x0700+)                        *** */
2304185aa0cSAlexander von Gluck IV/* ****************************************************** */
2314185aa0cSAlexander von Gluck IV
2324185aa0cSAlexander von Gluck IV
2334185aa0cSAlexander von Gluck IV#endif /* _DP_RAW_H */
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