ata_types.h revision a1ed294f
1/*
2 * Copyright 2002/03, Thomas Kurschel. All rights reserved.
3 * Distributed under the terms of the MIT License.
4 */
5#ifndef __ATA_TYPES_H__
6#define __ATA_TYPES_H__
7
8#include <iovec.h>
9#include <lendian_bitfield.h>
10
11// ATA task file.
12// contains the command block interpreted under different conditions with
13// first byte being first command register, second byte second command register
14// etc.; for lba48, registers must be written twice, therefore there
15// are twice as many bytes as registers - the first eight bytes are those
16// that must be written first, the second eight bytes are those that
17// must be written second.
18union ata_task_file {
19	struct {
20		uint8	features;
21		uint8	sector_count;
22		uint8	sector_number;
23		uint8	cylinder_0_7;
24		uint8	cylinder_8_15;
25		LBITFIELD8_3(
26			head				: 4,
27			device				: 1,
28			mode				: 3
29		);
30		uint8	command;
31	} chs;
32	struct {
33		uint8	features;
34		uint8	sector_count;
35		uint8	lba_0_7;
36		uint8	lba_8_15;
37		uint8	lba_16_23;
38		LBITFIELD8_3(
39			lba_24_27			: 4,
40			device				: 1,
41			mode				: 3
42		);
43		uint8	command;
44	} lba;
45	struct {
46		LBITFIELD8_3(
47			dma					: 1,
48			ovl					: 1,
49			_0_res2				: 6
50		);
51		LBITFIELD8_2(
52			_1_res0				: 3,
53			tag					: 5
54		);
55		uint8	_2_res;
56		uint8	byte_count_0_7;
57		uint8	byte_count_8_15;
58		LBITFIELD8_6(
59			lun					: 3,
60			_5_res3				: 1,
61			device				: 1,
62			_5_one5				: 1,
63			_5_res6				: 1,
64			_5_one7				: 1
65		);
66		uint8	command;
67	} packet;
68	struct {
69		LBITFIELD8_5(
70			ili					: 1,
71			eom					: 1,
72			abrt				: 1,
73			_0_res3				: 1,
74			sense_key			: 4
75		);
76		LBITFIELD8_4(
77			cmd_or_data			: 1,	// 1 - cmd, 0 - data
78			input_or_output	 	: 1,	// 0 - input (to device), 1 - output
79			release				: 1,
80			tag					: 5
81		);
82		uint8	_2_res;
83		uint8	byte_count_0_7;
84		uint8	byte_count_8_15;
85		LBITFIELD8_5(
86			_4_res0				: 4,
87			device				: 1,
88			_4_obs5				: 1,
89			_4_res6				: 1,
90			_4_obs7				: 1
91		);
92		LBITFIELD8_7(
93			chk					: 1,
94			_7_res1 			: 2,
95			drq					: 1,
96			serv				: 1,
97			dmrd				: 1,
98			drdy				: 1,
99			bsy					: 1
100		);
101	} packet_res;
102	struct {
103		uint8	sector_count;
104		LBITFIELD8_4(					// only <tag> is defined for write
105			cmd_or_data			: 1,	// 1 - cmd, 0 - data
106			input_or_output		: 1,	// 0 - input (to device), 1 - output
107			release				: 1,
108			tag					: 5
109		);
110		uint8	lba_0_7;
111		uint8	lba_8_15;
112		uint8	lba_16_23;
113		LBITFIELD8_3(
114			lba_24_27			: 4,
115			device				: 1,
116			mode				: 3
117		);
118		uint8	command;
119	} queued;
120	struct {
121		// low order bytes
122		uint8	features;
123		uint8	sector_count_0_7;
124		uint8	lba_0_7;
125		uint8	lba_8_15;
126		uint8	lba_16_23;
127		LBITFIELD8_3(
128			_5low_res0			: 4,
129			device				: 1,
130			mode				: 3
131		);
132		uint8	command;
133
134		// high order bytes
135		uint8	_0high_res;
136		uint8	sector_count_8_15;
137		uint8	lba_24_31;
138		uint8	lba_32_39;
139		uint8	lba_40_47;
140	} lba48;
141	struct {
142		// low order bytes
143		uint8	sector_count_0_7;
144		LBITFIELD8_4(
145			cmd_or_data			: 1,	// 1 - cmd, 0 - data
146			input_or_output	 	: 1,	// 0 - input (to device), 1 - output
147			release				: 1,
148			tag					: 5
149		);
150		uint8	lba_0_7;
151		uint8	lba_8_15;
152		uint8	lba_16_23;
153		LBITFIELD8_3(
154			_5low_res0			: 4,
155			device				: 1,
156			mode				: 3
157		);
158		uint8	command;
159
160		// high order bytes
161		uint8	sector_count_8_15;
162		uint8	_1high_res;
163		uint8	lba_24_31;
164		uint8	lba_32_39;
165		uint8	lba_40_47;
166	} queued48;
167	struct {
168		uint8	r[7+5];
169	} raw;
170	struct {
171		uint8	features;
172		uint8	sector_count;
173		uint8	sector_number;
174		uint8	cylinder_low;
175		uint8	cylinder_high;
176		uint8	device_head;
177		uint8	command;
178	} write;
179	struct {
180		uint8	error;
181		uint8	sector_count;
182		uint8	sector_number;
183		uint8	cylinder_low;
184		uint8	cylinder_high;
185		uint8	device_head;
186		uint8	status;
187	} read;
188};
189
190typedef union ata_task_file ata_task_file;
191
192// content of "mode" field
193enum {
194	ATA_MODE_CHS = 5,
195	ATA_MODE_LBA = 7
196};
197
198// mask for ata_task_file fields to be written
199enum {
200	ATA_MASK_FEATURES	 				= 0x01,
201	ATA_MASK_SECTOR_COUNT				= 0x02,
202
203	// CHS
204	ATA_MASK_SECTOR_NUMBER				= 0x04,
205	ATA_MASK_CYLINDER_LOW				= 0x08,
206	ATA_MASK_CYLINDER_HIGH				= 0x10,
207
208	// LBA
209	ATA_MASK_LBA_LOW					= 0x04,
210	ATA_MASK_LBA_MID					= 0x08,
211	ATA_MASK_LBA_HIGH					= 0x10,
212
213	// packet
214	ATA_MASK_BYTE_COUNT					= 0x18,
215
216	// packet and dma queued result
217	ATA_MASK_ERROR						= 0x01,
218	ATA_MASK_INTERRUPT_REASON			= 0x02,
219
220	ATA_MASK_DEVICE_HEAD				= 0x20,
221	ATA_MASK_COMMAND					= 0x40,
222
223	ATA_MASK_STATUS						= 0x40,
224
225	// for 48 bits, the following flags tell which registers to load twice
226	ATA_MASK_FEATURES_48				= 0x80 | ATA_MASK_FEATURES,
227	ATA_MASK_SECTOR_COUNT_48			= 0x100 | ATA_MASK_SECTOR_COUNT,
228	ATA_MASK_LBA_LOW_48					= 0x200 | ATA_MASK_LBA_LOW,
229	ATA_MASK_LBA_MID_48					= 0x400 | ATA_MASK_LBA_MID,
230	ATA_MASK_LBA_HIGH_48				= 0x800 | ATA_MASK_LBA_HIGH,
231
232	ATA_MASK_HOB						= 0xf80
233};
234
235// status register
236enum {
237	ATA_STATUS_ERROR					= 0x01,		// error
238	ATA_STATUS_INDEX					= 0x02,		// obsolete
239	ATA_STATUS_CORR						= 0x04,		// obsolete
240	ATA_STATUS_DATA_REQUEST				= 0x08,		// data request
241	ATA_STATUS_DSC						= 0x10,		// reserved
242	ATA_STATUS_SERVICE					= 0x10,		// ready to service device
243	ATA_STATUS_DWF						= 0x20,		// reserved
244	ATA_STATUS_DMA						= 0x20,		// reserved
245	ATA_STATUS_DMA_READY				= 0x20,		// packet: DMA ready
246	ATA_STATUS_DEVICE_FAULT				= 0x20,		// device fault
247	ATA_STATUS_DEVICE_READY				= 0x40,		// device ready
248	ATA_STATUS_BUSY						= 0x80		// busy
249};
250
251// device control register (ATA command block)
252enum {
253												// bit 0 must be zero
254	ATA_DEVICE_CONTROL_DISABLE_INTS		= 0x02,	// disable INTRQ
255	ATA_DEVICE_CONTROL_SOFT_RESET		= 0x04,	// software device reset
256	ATA_DEVICE_CONTROL_BIT3				= 0x08,	// obsolete. Must always be set
257												// bits inbetween are reserved
258	ATA_DEVICE_CONTROL_HIGH_ORDER_BYTE	= 0x80	// read high order byte
259												// (for 48-bit lba)
260};
261
262// error register - most bits are command specific
263enum {
264	// always used
265	ATA_ERROR_ABORTED					= 0x04,		// command aborted
266
267	// used for Ultra DMA modes
268	ATA_ERROR_INTERFACE_CRC				= 0x80,		// interface CRC error
269
270	// used by reading data transfers
271	ATA_ERROR_UNCORRECTABLE				= 0x40,		// uncorrectable data error
272	// used by writing data transfers
273	ATA_ERROR_WRITE_PROTECTED			= 0x40,		// media write protect
274
275	// used by all data transfer commands
276	ATA_ERROR_MEDIUM_CHANGED			= 0x20,		// medium changed
277	ATA_ERROR_INVALID_ADDRESS			= 0x10,		// invalid CHS address
278	ATA_ERROR_MEDIA_CHANGE_REQUESTED	= 0x08,		// media change requested
279	ATA_ERROR_NO_MEDIA					= 0x02,		// no media
280
281	ATA_ERROR_ALL						= 0xfe
282};
283
284typedef struct ata_channel_info *ata_channel_cookie;
285
286#endif	/* __ATA_TYPES_H__ */
287