1173362Sbenjsc/*	$FreeBSD$	*/
2173362Sbenjsc
3173362Sbenjsc/*-
4173362Sbenjsc * Copyright (c) 2006,2007
5173362Sbenjsc *	Damien Bergamini <damien.bergamini@free.fr>
6173362Sbenjsc *
7173362Sbenjsc * Permission to use, copy, modify, and distribute this software for any
8173362Sbenjsc * purpose with or without fee is hereby granted, provided that the above
9173362Sbenjsc * copyright notice and this permission notice appear in all copies.
10173362Sbenjsc *
11173362Sbenjsc * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12173362Sbenjsc * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13173362Sbenjsc * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14173362Sbenjsc * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15173362Sbenjsc * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16173362Sbenjsc * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17173362Sbenjsc * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18173362Sbenjsc */
19173362Sbenjsc
20173362Sbenjsc#define WPI_TX_RING_COUNT	256
21278366Sadrian#define WPI_TX_RING_LOMARK	192
22278366Sadrian#define WPI_TX_RING_HIMARK	224
23280119Sadrian
24280119Sadrian#ifdef DIAGNOSTIC
25280119Sadrian#define WPI_RX_RING_COUNT_LOG	8
26280119Sadrian#else
27278366Sadrian#define WPI_RX_RING_COUNT_LOG	6
28280119Sadrian#endif
29280119Sadrian
30278366Sadrian#define WPI_RX_RING_COUNT	(1 << WPI_RX_RING_COUNT_LOG)
31173362Sbenjsc
32278366Sadrian#define WPI_NTXQUEUES		8
33280058Sadrian#define WPI_DRV_NTXQUEUES	5
34280064Sadrian#define WPI_CMD_QUEUE_NUM	4
35280064Sadrian
36278366Sadrian#define WPI_NDMACHNLS		6
37278366Sadrian
38278366Sadrian/* Maximum scatter/gather. */
39280059Sadrian#define WPI_MAX_SCATTER		4
40278366Sadrian
41173362Sbenjsc/*
42173362Sbenjsc * Rings must be aligned on a 16K boundary.
43173362Sbenjsc */
44173362Sbenjsc#define WPI_RING_DMA_ALIGN	0x4000
45173362Sbenjsc
46278366Sadrian/* Maximum Rx buffer size. */
47173362Sbenjsc#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */
48173362Sbenjsc
49173362Sbenjsc/*
50173362Sbenjsc * Control and status registers.
51173362Sbenjsc */
52278366Sadrian#define WPI_HW_IF_CONFIG	0x000
53278366Sadrian#define WPI_INT			0x008
54278366Sadrian#define WPI_INT_MASK		0x00c
55278366Sadrian#define WPI_FH_INT		0x010
56278366Sadrian#define WPI_GPIO_IN		0x018
57173362Sbenjsc#define WPI_RESET		0x020
58278366Sadrian#define WPI_GP_CNTRL		0x024
59278366Sadrian#define WPI_EEPROM		0x02c
60278366Sadrian#define WPI_EEPROM_GP		0x030
61278366Sadrian#define WPI_GIO			0x03c
62278366Sadrian#define WPI_UCODE_GP1		0x054
63278366Sadrian#define WPI_UCODE_GP1_SET	0x058
64278366Sadrian#define WPI_UCODE_GP1_CLR	0x05c
65278366Sadrian#define WPI_UCODE_GP2		0x060
66278366Sadrian#define WPI_GIO_CHICKEN		0x100
67278366Sadrian#define WPI_ANA_PLL		0x20c
68278366Sadrian#define WPI_DBG_HPET_MEM	0x240
69278366Sadrian#define WPI_MEM_RADDR		0x40c
70278366Sadrian#define WPI_MEM_WADDR		0x410
71278366Sadrian#define WPI_MEM_WDATA		0x418
72278366Sadrian#define WPI_MEM_RDATA		0x41c
73278366Sadrian#define WPI_PRPH_WADDR		0x444
74278366Sadrian#define WPI_PRPH_RADDR		0x448
75278366Sadrian#define WPI_PRPH_WDATA		0x44c
76278366Sadrian#define WPI_PRPH_RDATA		0x450
77278366Sadrian#define WPI_HBUS_TARG_WRPTR	0x460
78173362Sbenjsc
79278366Sadrian/*
80278366Sadrian * Flow-Handler registers.
81278366Sadrian */
82278366Sadrian#define WPI_FH_CBBC_CTRL(qid)	(0x940 + (qid) * 8)
83278366Sadrian#define WPI_FH_CBBC_BASE(qid)	(0x944 + (qid) * 8)
84278366Sadrian#define WPI_FH_RX_CONFIG	0xc00
85278366Sadrian#define WPI_FH_RX_BASE		0xc04
86278366Sadrian#define WPI_FH_RX_WPTR		0xc20
87278366Sadrian#define WPI_FH_RX_RPTR_ADDR	0xc24
88278366Sadrian#define WPI_FH_RSSR_TBL		0xcc0
89278366Sadrian#define WPI_FH_RX_STATUS	0xcc4
90278366Sadrian#define WPI_FH_TX_CONFIG(qid)	(0xd00 + (qid) * 32)
91278366Sadrian#define WPI_FH_TX_BASE		0xe80
92278366Sadrian#define WPI_FH_MSG_CONFIG	0xe88
93278366Sadrian#define WPI_FH_TX_STATUS	0xe90
94173362Sbenjsc
95278366Sadrian
96173362Sbenjsc/*
97173362Sbenjsc * NIC internal memory offsets.
98173362Sbenjsc */
99278366Sadrian#define WPI_ALM_SCHED_MODE		0x2e00
100278366Sadrian#define WPI_ALM_SCHED_ARASTAT		0x2e04
101278366Sadrian#define WPI_ALM_SCHED_TXFACT		0x2e10
102278366Sadrian#define WPI_ALM_SCHED_TXF4MF		0x2e14
103278366Sadrian#define WPI_ALM_SCHED_TXF5MF		0x2e20
104278366Sadrian#define WPI_ALM_SCHED_SBYPASS_MODE1	0x2e2c
105278366Sadrian#define WPI_ALM_SCHED_SBYPASS_MODE2	0x2e30
106280093Sadrian#define WPI_APMG_CLK_CTRL		0x3000
107278366Sadrian#define WPI_APMG_CLK_EN			0x3004
108278366Sadrian#define WPI_APMG_CLK_DIS		0x3008
109278366Sadrian#define WPI_APMG_PS			0x300c
110278366Sadrian#define WPI_APMG_PCI_STT		0x3010
111278366Sadrian#define WPI_APMG_RFKILL			0x3014
112278366Sadrian#define WPI_BSM_WR_CTRL			0x3400
113278366Sadrian#define WPI_BSM_WR_MEM_SRC		0x3404
114278366Sadrian#define WPI_BSM_WR_MEM_DST		0x3408
115278366Sadrian#define WPI_BSM_WR_DWCOUNT		0x340c
116278366Sadrian#define WPI_BSM_DRAM_TEXT_ADDR		0x3490
117278366Sadrian#define WPI_BSM_DRAM_TEXT_SIZE		0x3494
118278366Sadrian#define WPI_BSM_DRAM_DATA_ADDR		0x3498
119278366Sadrian#define WPI_BSM_DRAM_DATA_SIZE		0x349c
120278366Sadrian#define WPI_BSM_SRAM_BASE		0x3800
121173362Sbenjsc
122173362Sbenjsc
123278366Sadrian/* Possible flags for register WPI_HW_IF_CONFIG. */
124278366Sadrian#define WPI_HW_IF_CONFIG_ALM_MB		(1 << 8)
125278366Sadrian#define WPI_HW_IF_CONFIG_ALM_MM		(1 << 9)
126278366Sadrian#define WPI_HW_IF_CONFIG_SKU_MRC	(1 << 10)
127278366Sadrian#define WPI_HW_IF_CONFIG_REV_D		(1 << 11)
128278366Sadrian#define WPI_HW_IF_CONFIG_TYPE_B		(1 << 12)
129173362Sbenjsc
130278366Sadrian/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */
131278366Sadrian#define WPI_PRPH_DWORD	((sizeof (uint32_t) - 1) << 24)
132173362Sbenjsc
133278366Sadrian/* Possible values for WPI_BSM_WR_MEM_DST. */
134278366Sadrian#define WPI_FW_TEXT_BASE	0x00000000
135278366Sadrian#define WPI_FW_DATA_BASE	0x00800000
136173362Sbenjsc
137278366Sadrian/* Possible flags for WPI_GPIO_IN. */
138278366Sadrian#define WPI_GPIO_IN_VMAIN	(1 << 9)
139173362Sbenjsc
140278366Sadrian/* Possible flags for register WPI_RESET. */
141278366Sadrian#define WPI_RESET_NEVO			(1 << 0)
142278366Sadrian#define WPI_RESET_SW			(1 << 7)
143278366Sadrian#define WPI_RESET_MASTER_DISABLED	(1 << 8)
144278366Sadrian#define WPI_RESET_STOP_MASTER		(1 << 9)
145173362Sbenjsc
146278366Sadrian/* Possible flags for register WPI_GP_CNTRL. */
147278366Sadrian#define WPI_GP_CNTRL_MAC_ACCESS_ENA	(1 <<  0)
148278366Sadrian#define WPI_GP_CNTRL_MAC_CLOCK_READY	(1 <<  0)
149278366Sadrian#define WPI_GP_CNTRL_INIT_DONE		(1 <<  2)
150278366Sadrian#define WPI_GP_CNTRL_MAC_ACCESS_REQ	(1 <<  3)
151278366Sadrian#define WPI_GP_CNTRL_SLEEP		(1 <<  4)
152278366Sadrian#define WPI_GP_CNTRL_PS_MASK		(7 << 24)
153278366Sadrian#define WPI_GP_CNTRL_MAC_PS		(4 << 24)
154278366Sadrian#define WPI_GP_CNTRL_RFKILL		(1 << 27)
155173362Sbenjsc
156278366Sadrian/* Possible flags for register WPI_GIO_CHICKEN. */
157278366Sadrian#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX	(1 << 23)
158278366Sadrian#define WPI_GIO_CHICKEN_DIS_L0S_TIMER	(1 << 29)
159173362Sbenjsc
160278366Sadrian/* Possible flags for register WPI_GIO. */
161278366Sadrian#define WPI_GIO_L0S_ENA			(1 << 1)
162173362Sbenjsc
163278366Sadrian/* Possible flags for register WPI_FH_RX_CONFIG. */
164278366Sadrian#define WPI_FH_RX_CONFIG_DMA_ENA	(1U  << 31)
165278366Sadrian#define WPI_FH_RX_CONFIG_RDRBD_ENA	(1   << 29)
166278366Sadrian#define WPI_FH_RX_CONFIG_WRSTATUS_ENA	(1   << 27)
167278366Sadrian#define WPI_FH_RX_CONFIG_MAXFRAG	(1   << 24)
168278366Sadrian#define WPI_FH_RX_CONFIG_NRBD(x)	((x) << 20)
169278366Sadrian#define WPI_FH_RX_CONFIG_IRQ_DST_HOST	(1   << 12)
170278366Sadrian#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x)	((x) <<  4)
171173362Sbenjsc
172278366Sadrian/* Possible flags for register WPI_ANA_PLL. */
173278366Sadrian#define WPI_ANA_PLL_INIT	(1 << 24)
174173362Sbenjsc
175278366Sadrian/* Possible flags for register WPI_UCODE_GP1*. */
176278366Sadrian#define WPI_UCODE_GP1_MAC_SLEEP		(1 << 0)
177278366Sadrian#define WPI_UCODE_GP1_RFKILL		(1 << 1)
178278366Sadrian#define WPI_UCODE_GP1_CMD_BLOCKED	(1 << 2)
179173362Sbenjsc
180278366Sadrian/* Possible flags for register WPI_FH_RX_STATUS. */
181278366Sadrian#define	WPI_FH_RX_STATUS_IDLE	(1 << 24)
182173362Sbenjsc
183278366Sadrian/* Possible flags for register WPI_BSM_WR_CTRL. */
184278366Sadrian#define WPI_BSM_WR_CTRL_START_EN	(1  << 30)
185278366Sadrian#define WPI_BSM_WR_CTRL_START		(1U << 31)
186173362Sbenjsc
187278366Sadrian/* Possible flags for register WPI_INT. */
188278366Sadrian#define WPI_INT_ALIVE		(1  <<  0)
189278366Sadrian#define WPI_INT_WAKEUP		(1  <<  1)
190278366Sadrian#define WPI_INT_SW_RX		(1  <<  3)
191278366Sadrian#define WPI_INT_SW_ERR		(1  << 25)
192278366Sadrian#define WPI_INT_FH_TX		(1  << 27)
193278366Sadrian#define WPI_INT_HW_ERR		(1  << 29)
194278366Sadrian#define WPI_INT_FH_RX		(1U << 31)
195173362Sbenjsc
196278366Sadrian/* Shortcut. */
197278366Sadrian#define WPI_INT_MASK_DEF					\
198278366Sadrian	(WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX  |	\
199278366Sadrian	 WPI_INT_FH_RX  | WPI_INT_ALIVE  | WPI_INT_WAKEUP |	\
200278366Sadrian	 WPI_INT_SW_RX)
201173362Sbenjsc
202278366Sadrian/* Possible flags for register WPI_FH_INT. */
203278366Sadrian#define WPI_FH_INT_RX_CHNL(x)	(1 << ((x) + 16))
204278366Sadrian#define WPI_FH_INT_HI_PRIOR	(1 << 30)
205278366Sadrian/* Shortcuts for the above. */
206278366Sadrian#define WPI_FH_INT_RX			\
207278366Sadrian	(WPI_FH_INT_RX_CHNL(0) |	\
208278366Sadrian	 WPI_FH_INT_RX_CHNL(1) |	\
209278366Sadrian	 WPI_FH_INT_RX_CHNL(2) |	\
210278366Sadrian	 WPI_FH_INT_HI_PRIOR)
211173362Sbenjsc
212278366Sadrian/* Possible flags for register WPI_FH_TX_STATUS. */
213278366Sadrian#define WPI_FH_TX_STATUS_IDLE(qid)	\
214278366Sadrian	(1 << ((qid) + 24) | 1 << ((qid) + 16))
215278366Sadrian
216278366Sadrian/* Possible flags for register WPI_EEPROM. */
217278366Sadrian#define WPI_EEPROM_READ_VALID	(1 << 0)
218278366Sadrian
219278366Sadrian/* Possible flags for register WPI_EEPROM_GP. */
220173362Sbenjsc#define WPI_EEPROM_VERSION	0x00000007
221278366Sadrian#define WPI_EEPROM_GP_IF_OWNER	0x00000180
222173362Sbenjsc
223278366Sadrian/* Possible flags for register WPI_APMG_PS. */
224278366Sadrian#define WPI_APMG_PS_PWR_SRC_MASK	(3 << 24)
225173362Sbenjsc
226278366Sadrian/* Possible flags for registers WPI_APMG_CLK_*. */
227278366Sadrian#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT	(1 <<  9)
228278366Sadrian#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT	(1 << 11)
229278366Sadrian
230278366Sadrian/* Possible flags for register WPI_APMG_PCI_STT. */
231278366Sadrian#define WPI_APMG_PCI_STT_L1A_DIS	(1 << 11)
232278366Sadrian
233173362Sbenjscstruct wpi_shared {
234280064Sadrian	uint32_t	txbase[WPI_NTXQUEUES];
235173362Sbenjsc	uint32_t	next;
236173362Sbenjsc	uint32_t	reserved[2];
237173362Sbenjsc} __packed;
238173362Sbenjsc
239173362Sbenjsc#define WPI_MAX_SEG_LEN	65520
240173362Sbenjscstruct wpi_tx_desc {
241278366Sadrian	uint8_t		reserved1[3];
242278366Sadrian	uint8_t		nsegs;
243173362Sbenjsc#define WPI_PAD32(x)	(roundup2(x, 4) - (x))
244173362Sbenjsc
245173362Sbenjsc	struct {
246173362Sbenjsc		uint32_t	addr;
247173362Sbenjsc		uint32_t	len;
248278366Sadrian	} __packed	segs[WPI_MAX_SCATTER];
249278366Sadrian	uint8_t		reserved2[28];
250173362Sbenjsc} __packed;
251173362Sbenjsc
252173362Sbenjscstruct wpi_tx_stat {
253278366Sadrian	uint8_t		rtsfailcnt;
254278366Sadrian	uint8_t		ackfailcnt;
255278366Sadrian	uint8_t		btkillcnt;
256173362Sbenjsc	uint8_t		rate;
257173362Sbenjsc	uint32_t	duration;
258173362Sbenjsc	uint32_t	status;
259282378Sadrian#define WPI_TX_STATUS_SUCCESS			0x01
260282378Sadrian#define WPI_TX_STATUS_DIRECT_DONE		0x02
261282378Sadrian#define WPI_TX_STATUS_FAIL			0x80
262282378Sadrian#define WPI_TX_STATUS_FAIL_SHORT_LIMIT		0x82
263282378Sadrian#define WPI_TX_STATUS_FAIL_LONG_LIMIT		0x83
264282378Sadrian#define WPI_TX_STATUS_FAIL_FIFO_UNDERRUN	0x84
265282378Sadrian#define WPI_TX_STATUS_FAIL_MGMNT_ABORT		0x85
266282378Sadrian#define WPI_TX_STATUS_FAIL_NEXT_FRAG		0x86
267282378Sadrian#define WPI_TX_STATUS_FAIL_LIFE_EXPIRE		0x87
268282378Sadrian#define WPI_TX_STATUS_FAIL_NODE_PS		0x88
269282378Sadrian#define WPI_TX_STATUS_FAIL_ABORTED		0x89
270282378Sadrian#define WPI_TX_STATUS_FAIL_BT_RETRY		0x8a
271282378Sadrian#define WPI_TX_STATUS_FAIL_NODE_INVALID		0x8b
272282378Sadrian#define WPI_TX_STATUS_FAIL_FRAG_DROPPED		0x8c
273282378Sadrian#define WPI_TX_STATUS_FAIL_TID_DISABLE		0x8d
274282378Sadrian#define WPI_TX_STATUS_FAIL_FRAME_FLUSHED	0x8e
275282378Sadrian#define WPI_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL	0x8f
276282378Sadrian#define WPI_TX_STATUS_FAIL_TX_LOCKED		0x90
277282378Sadrian#define WPI_TX_STATUS_FAIL_NO_BEACON_ON_RADAR	0x91
278282378Sadrian
279173362Sbenjsc} __packed;
280173362Sbenjsc
281173362Sbenjscstruct wpi_rx_desc {
282173362Sbenjsc	uint32_t	len;
283173362Sbenjsc	uint8_t		type;
284173362Sbenjsc#define WPI_UC_READY		  1
285173362Sbenjsc#define WPI_RX_DONE		 27
286173362Sbenjsc#define WPI_TX_DONE		 28
287173362Sbenjsc#define WPI_START_SCAN		130
288177043Sthompsa#define WPI_SCAN_RESULTS	131
289173362Sbenjsc#define WPI_STOP_SCAN		132
290278366Sadrian#define WPI_BEACON_SENT		144
291278366Sadrian#define WPI_RX_STATISTICS	156
292278366Sadrian#define WPI_BEACON_STATISTICS	157
293173362Sbenjsc#define WPI_STATE_CHANGED	161
294278366Sadrian#define WPI_BEACON_MISSED	162
295173362Sbenjsc
296173362Sbenjsc	uint8_t		flags;
297173362Sbenjsc	uint8_t		idx;
298173362Sbenjsc	uint8_t		qid;
299173362Sbenjsc} __packed;
300173362Sbenjsc
301280064Sadrian#define WPI_RX_DESC_QID_MSK		0x07
302280064Sadrian#define WPI_UNSOLICITED_RX_NOTIF	0x80
303280064Sadrian
304173362Sbenjscstruct wpi_rx_stat {
305173362Sbenjsc	uint8_t		len;
306173362Sbenjsc#define WPI_STAT_MAXLEN	20
307173362Sbenjsc
308173362Sbenjsc	uint8_t		id;
309173362Sbenjsc	uint8_t		rssi;	/* received signal strength */
310280064Sadrian#define WPI_RSSI_OFFSET	-95
311173362Sbenjsc
312173362Sbenjsc	uint8_t		agc;	/* access gain control */
313173362Sbenjsc	uint16_t	signal;
314173362Sbenjsc	uint16_t	noise;
315173362Sbenjsc} __packed;
316173362Sbenjsc
317173362Sbenjscstruct wpi_rx_head {
318173362Sbenjsc	uint16_t	chan;
319173362Sbenjsc	uint16_t	flags;
320278366Sadrian#define WPI_STAT_FLAG_SHPREAMBLE	(1 << 2)
321278366Sadrian
322173362Sbenjsc	uint8_t		reserved;
323278366Sadrian	uint8_t		plcp;
324173362Sbenjsc	uint16_t	len;
325173362Sbenjsc} __packed;
326173362Sbenjsc
327173362Sbenjscstruct wpi_rx_tail {
328173362Sbenjsc	uint32_t	flags;
329173362Sbenjsc#define WPI_RX_NO_CRC_ERR	(1 << 0)
330173362Sbenjsc#define WPI_RX_NO_OVFL_ERR	(1 << 1)
331173362Sbenjsc/* shortcut for the above */
332173362Sbenjsc#define WPI_RX_NOERROR		(WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR)
333278366Sadrian#define WPI_RX_CIPHER_MASK	(7 <<  8)
334278366Sadrian#define WPI_RX_CIPHER_CCMP	(2 <<  8)
335278366Sadrian#define WPI_RX_DECRYPT_MASK	(3 << 11)
336278366Sadrian#define WPI_RX_DECRYPT_OK	(3 << 11)
337278366Sadrian
338173362Sbenjsc	uint64_t	tstamp;
339173362Sbenjsc	uint32_t	tbeacon;
340173362Sbenjsc} __packed;
341173362Sbenjsc
342173362Sbenjscstruct wpi_tx_cmd {
343173362Sbenjsc	uint8_t	code;
344278366Sadrian#define WPI_CMD_RXON		 16
345278366Sadrian#define WPI_CMD_RXON_ASSOC	 17
346278366Sadrian#define WPI_CMD_EDCA_PARAMS	 19
347278366Sadrian#define WPI_CMD_TIMING		 20
348173362Sbenjsc#define WPI_CMD_ADD_NODE	 24
349278366Sadrian#define WPI_CMD_DEL_NODE	 25
350173362Sbenjsc#define WPI_CMD_TX_DATA		 28
351173362Sbenjsc#define WPI_CMD_MRR_SETUP	 71
352173362Sbenjsc#define WPI_CMD_SET_LED		 72
353173362Sbenjsc#define WPI_CMD_SET_POWER_MODE	119
354173362Sbenjsc#define WPI_CMD_SCAN		128
355282392Sadrian#define WPI_CMD_SCAN_ABORT	129
356173362Sbenjsc#define WPI_CMD_SET_BEACON	145
357173362Sbenjsc#define WPI_CMD_TXPOWER		151
358278366Sadrian#define WPI_CMD_BT_COEX		155
359278366Sadrian#define WPI_CMD_GET_STATISTICS	156
360173362Sbenjsc
361173362Sbenjsc	uint8_t	flags;
362173362Sbenjsc	uint8_t	idx;
363173362Sbenjsc	uint8_t	qid;
364278366Sadrian	uint8_t	data[124];
365173362Sbenjsc} __packed;
366173362Sbenjsc
367278366Sadrian/* Structure for command WPI_CMD_RXON. */
368278366Sadrianstruct wpi_rxon {
369173362Sbenjsc	uint8_t		myaddr[IEEE80211_ADDR_LEN];
370173362Sbenjsc	uint16_t	reserved1;
371173362Sbenjsc	uint8_t		bssid[IEEE80211_ADDR_LEN];
372173362Sbenjsc	uint16_t	reserved2;
373278366Sadrian	uint8_t		wlap[IEEE80211_ADDR_LEN];
374173362Sbenjsc	uint16_t	reserved3;
375173362Sbenjsc	uint8_t		mode;
376173362Sbenjsc#define WPI_MODE_HOSTAP		1
377173362Sbenjsc#define WPI_MODE_STA		3
378173362Sbenjsc#define WPI_MODE_IBSS		4
379173362Sbenjsc#define WPI_MODE_MONITOR	6
380173362Sbenjsc
381278366Sadrian	uint8_t		air;
382173362Sbenjsc	uint16_t	reserved4;
383173362Sbenjsc	uint8_t		ofdm_mask;
384173362Sbenjsc	uint8_t		cck_mask;
385173362Sbenjsc	uint16_t	associd;
386173362Sbenjsc	uint32_t	flags;
387278366Sadrian#define WPI_RXON_24GHZ		(1 <<  0)
388278366Sadrian#define WPI_RXON_CCK		(1 <<  1)
389278366Sadrian#define WPI_RXON_AUTO		(1 <<  2)
390278366Sadrian#define WPI_RXON_SHSLOT		(1 <<  4)
391278366Sadrian#define WPI_RXON_SHPREAMBLE	(1 <<  5)
392278366Sadrian#define WPI_RXON_NODIVERSITY	(1 <<  7)
393278366Sadrian#define WPI_RXON_ANTENNA_A	(1 <<  8)
394278366Sadrian#define WPI_RXON_ANTENNA_B	(1 <<  9)
395278366Sadrian#define WPI_RXON_TSF		(1 << 15)
396278366Sadrian#define WPI_RXON_CTS_TO_SELF	(1 << 30)
397173362Sbenjsc
398173362Sbenjsc	uint32_t	filter;
399173362Sbenjsc#define WPI_FILTER_PROMISC	(1 << 0)
400173362Sbenjsc#define WPI_FILTER_CTL		(1 << 1)
401173362Sbenjsc#define WPI_FILTER_MULTICAST	(1 << 2)
402173362Sbenjsc#define WPI_FILTER_NODECRYPT	(1 << 3)
403173362Sbenjsc#define WPI_FILTER_BSS		(1 << 5)
404173362Sbenjsc#define WPI_FILTER_BEACON	(1 << 6)
405280105Sadrian#define WPI_FILTER_ASSOC	(1 << 7)    /* Accept associaton requests. */
406173362Sbenjsc
407173362Sbenjsc	uint8_t		chan;
408278366Sadrian	uint16_t	reserved5;
409173362Sbenjsc} __packed;
410173362Sbenjsc
411278366Sadrian/* Structure for command WPI_CMD_RXON_ASSOC. */
412173362Sbenjscstruct wpi_assoc {
413173362Sbenjsc	uint32_t	flags;
414173362Sbenjsc	uint32_t	filter;
415173362Sbenjsc	uint8_t		ofdm_mask;
416173362Sbenjsc	uint8_t		cck_mask;
417173362Sbenjsc	uint16_t	reserved;
418173362Sbenjsc} __packed;
419173362Sbenjsc
420278366Sadrian/* Structure for command WPI_CMD_EDCA_PARAMS. */
421278366Sadrianstruct wpi_edca_params {
422173362Sbenjsc	uint32_t	flags;
423278366Sadrian#define WPI_EDCA_UPDATE	(1 << 0)
424278366Sadrian
425173362Sbenjsc	struct {
426173362Sbenjsc		uint16_t	cwmin;
427173362Sbenjsc		uint16_t	cwmax;
428173362Sbenjsc		uint8_t		aifsn;
429173362Sbenjsc		uint8_t		reserved;
430278366Sadrian		uint16_t	txoplimit;
431173362Sbenjsc	} __packed	ac[WME_NUM_AC];
432173362Sbenjsc} __packed;
433173362Sbenjsc
434278366Sadrian/* Structure for command WPI_CMD_TIMING. */
435278366Sadrianstruct wpi_cmd_timing {
436173362Sbenjsc	uint64_t	tstamp;
437173362Sbenjsc	uint16_t	bintval;
438173362Sbenjsc	uint16_t	atim;
439173362Sbenjsc	uint32_t	binitval;
440173362Sbenjsc	uint16_t	lintval;
441173362Sbenjsc	uint16_t	reserved;
442173362Sbenjsc} __packed;
443173362Sbenjsc
444278366Sadrian/* Structure for command WPI_CMD_ADD_NODE. */
445173362Sbenjscstruct wpi_node_info {
446173362Sbenjsc	uint8_t		control;
447278366Sadrian#define WPI_NODE_UPDATE		(1 << 0)
448173362Sbenjsc
449173362Sbenjsc	uint8_t		reserved1[3];
450278366Sadrian	uint8_t		macaddr[IEEE80211_ADDR_LEN];
451173362Sbenjsc	uint16_t	reserved2;
452173362Sbenjsc	uint8_t		id;
453173362Sbenjsc#define WPI_ID_BSS		0
454278366Sadrian#define WPI_ID_IBSS_MIN		2
455278366Sadrian#define WPI_ID_IBSS_MAX		23
456173362Sbenjsc#define WPI_ID_BROADCAST	24
457278366Sadrian#define WPI_ID_UNDEFINED	(uint8_t)-1
458173362Sbenjsc
459173362Sbenjsc	uint8_t		flags;
460278366Sadrian#define WPI_FLAG_KEY_SET	(1 << 0)
461278366Sadrian
462173362Sbenjsc	uint16_t	reserved3;
463278366Sadrian	uint16_t	kflags;
464278366Sadrian#define WPI_KFLAG_CCMP		(1 <<  1)
465278366Sadrian#define WPI_KFLAG_KID(kid)	((kid) << 8)
466278366Sadrian#define WPI_KFLAG_MULTICAST	(1 << 14)
467278366Sadrian
468278366Sadrian	uint8_t		tsc2;
469173362Sbenjsc	uint8_t		reserved4;
470173362Sbenjsc	uint16_t	ttak[5];
471173362Sbenjsc	uint16_t	reserved5;
472173362Sbenjsc	uint8_t		key[IEEE80211_KEYBUF_SIZE];
473173362Sbenjsc	uint32_t	action;
474278366Sadrian#define WPI_ACTION_SET_RATE	(1 << 2)
475278366Sadrian
476173362Sbenjsc	uint32_t	mask;
477173362Sbenjsc	uint16_t	tid;
478278366Sadrian	uint8_t		plcp;
479173362Sbenjsc	uint8_t		antenna;
480278366Sadrian#define WPI_ANTENNA_A		(1 << 6)
481278366Sadrian#define WPI_ANTENNA_B		(1 << 7)
482278366Sadrian#define WPI_ANTENNA_BOTH	(WPI_ANTENNA_A | WPI_ANTENNA_B)
483278366Sadrian
484173362Sbenjsc	uint8_t		add_imm;
485173362Sbenjsc	uint8_t		del_imm;
486173362Sbenjsc	uint16_t	add_imm_start;
487173362Sbenjsc} __packed;
488173362Sbenjsc
489278366Sadrian/* Structure for command WPI_CMD_DEL_NODE. */
490278366Sadrianstruct wpi_cmd_del_node {
491278366Sadrian	uint8_t		count;
492278366Sadrian	uint8_t		reserved1[3];
493278366Sadrian	uint8_t		macaddr[IEEE80211_ADDR_LEN];
494278366Sadrian	uint16_t	reserved2;
495278366Sadrian} __packed;
496278366Sadrian
497278366Sadrian/* Structure for command WPI_CMD_TX_DATA. */
498173362Sbenjscstruct wpi_cmd_data {
499173362Sbenjsc	uint16_t	len;
500173362Sbenjsc	uint16_t	lnext;
501173362Sbenjsc	uint32_t	flags;
502173362Sbenjsc#define WPI_TX_NEED_RTS		(1 <<  1)
503280059Sadrian#define WPI_TX_NEED_CTS		(1 <<  2)
504173362Sbenjsc#define WPI_TX_NEED_ACK		(1 <<  3)
505173362Sbenjsc#define WPI_TX_FULL_TXOP	(1 <<  7)
506278366Sadrian#define WPI_TX_BT_DISABLE	(1 << 12) 	/* bluetooth coexistence */
507173362Sbenjsc#define WPI_TX_AUTO_SEQ		(1 << 13)
508278764Sadrian#define WPI_TX_MORE_FRAG	(1 << 14)
509173362Sbenjsc#define WPI_TX_INSERT_TSTAMP	(1 << 16)
510173362Sbenjsc
511278366Sadrian	uint8_t		plcp;
512173362Sbenjsc	uint8_t		id;
513173362Sbenjsc	uint8_t		tid;
514173362Sbenjsc	uint8_t		security;
515278366Sadrian#define WPI_CIPHER_WEP		1
516278366Sadrian#define WPI_CIPHER_CCMP		2
517278366Sadrian#define WPI_CIPHER_TKIP		3
518278366Sadrian#define WPI_CIPHER_WEP104	9
519278366Sadrian
520173362Sbenjsc	uint8_t		key[IEEE80211_KEYBUF_SIZE];
521173362Sbenjsc	uint8_t		tkip[IEEE80211_WEP_MICLEN];
522173362Sbenjsc	uint32_t	fnext;
523289163Sadrian#define WPI_NEXT_STA_ID(id)	((id) << 8)
524289163Sadrian
525173362Sbenjsc	uint32_t	lifetime;
526173362Sbenjsc#define WPI_LIFETIME_INFINITE	0xffffffff
527278366Sadrian
528173362Sbenjsc	uint8_t		ofdm_mask;
529173362Sbenjsc	uint8_t		cck_mask;
530173362Sbenjsc	uint8_t		rts_ntries;
531173362Sbenjsc	uint8_t		data_ntries;
532173362Sbenjsc	uint16_t	timeout;
533173362Sbenjsc	uint16_t	txop;
534173362Sbenjsc} __packed;
535173362Sbenjsc
536278366Sadrian/* Structure for command WPI_CMD_SET_BEACON. */
537173362Sbenjscstruct wpi_cmd_beacon {
538173362Sbenjsc	uint16_t	len;
539173362Sbenjsc	uint16_t	reserved1;
540173362Sbenjsc	uint32_t	flags;	/* same as wpi_cmd_data */
541278366Sadrian	uint8_t		plcp;
542173362Sbenjsc	uint8_t		id;
543173362Sbenjsc	uint8_t		reserved2[30];
544173362Sbenjsc	uint32_t	lifetime;
545173362Sbenjsc	uint8_t		ofdm_mask;
546173362Sbenjsc	uint8_t		cck_mask;
547173362Sbenjsc	uint16_t	reserved3[3];
548173362Sbenjsc	uint16_t	tim;
549173362Sbenjsc	uint8_t		timsz;
550173362Sbenjsc	uint8_t		reserved4;
551173362Sbenjsc} __packed;
552173362Sbenjsc
553278366Sadrian/* Structure for notification WPI_BEACON_MISSED. */
554278366Sadrianstruct wpi_beacon_missed {
555280059Sadrian	uint32_t consecutive;
556280059Sadrian	uint32_t total;
557280059Sadrian	uint32_t expected;
558280059Sadrian	uint32_t received;
559173976Sbenjsc} __packed;
560173976Sbenjsc
561173976Sbenjsc
562278366Sadrian/* Structure for command WPI_CMD_MRR_SETUP. */
563278366Sadrian#define WPI_RIDX_MAX	11
564173362Sbenjscstruct wpi_mrr_setup {
565278366Sadrian	uint32_t	which;
566173362Sbenjsc#define