1178676Ssam/*	$FreeBSD$	*/
2210111Sbschmidt/*	$OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $	*/
3178676Ssam
4178676Ssam/*-
5198429Srpaulo * Copyright (c) 2007, 2008
6178676Ssam *	Damien Bergamini <damien.bergamini@free.fr>
7178676Ssam *
8178676Ssam * Permission to use, copy, modify, and distribute this software for any
9178676Ssam * purpose with or without fee is hereby granted, provided that the above
10178676Ssam * copyright notice and this permission notice appear in all copies.
11178676Ssam *
12178676Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13178676Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14178676Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15178676Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16178676Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17178676Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18178676Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19178676Ssam */
20257034Sadrian#ifndef	__IF_IWNREG_H__
21257034Sadrian#define	__IF_IWNREG_H__
22178676Ssam
23253898Sadrian#define	IWN_CT_KILL_THRESHOLD		114	/* in Celsius */
24253898Sadrian#define	IWN_CT_KILL_EXIT_THRESHOLD	95	/* in Celsius */
25253898Sadrian
26178676Ssam#define IWN_TX_RING_COUNT	256
27198429Srpaulo#define IWN_TX_RING_LOMARK	192
28198429Srpaulo#define IWN_TX_RING_HIMARK	224
29198429Srpaulo#define IWN_RX_RING_COUNT_LOG	6
30198429Srpaulo#define IWN_RX_RING_COUNT	(1 << IWN_RX_RING_COUNT_LOG)
31178676Ssam
32198429Srpaulo#define IWN4965_NTXQUEUES	16
33198429Srpaulo#define IWN5000_NTXQUEUES	20
34178676Ssam
35221651Sbschmidt#define IWN4965_FIRSTAGGQUEUE	7
36221651Sbschmidt#define IWN5000_FIRSTAGGQUEUE	10
37221651Sbschmidt
38198429Srpaulo#define IWN4965_NDMACHNLS	7
39198429Srpaulo#define IWN5000_NDMACHNLS	8
40178676Ssam
41198429Srpaulo#define IWN_SRVC_DMACHNL	9
42198429Srpaulo
43201209Srpaulo#define IWN_ICT_SIZE		4096
44201209Srpaulo#define IWN_ICT_COUNT		(IWN_ICT_SIZE / sizeof (uint32_t))
45201209Srpaulo
46253898Sadrian/* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */
47253898Sadrian#define	IWN_CMD_QUEUE_NUM		4
48253898Sadrian#define	IWN_PAN_CMD_QUEUE		9
49253898Sadrian
50198429Srpaulo/* Maximum number of DMA segments for TX. */
51178676Ssam#define IWN_MAX_SCATTER	20
52178676Ssam
53198429Srpaulo/* RX buffers must be large enough to hold a full 4K A-MPDU. */
54178676Ssam#define IWN_RBUF_SIZE	(4 * 1024)
55178676Ssam
56198429Srpaulo#if defined(__LP64__)
57198429Srpaulo/* HW supports 36-bit DMA addresses. */
58198429Srpaulo#define IWN_LOADDR(paddr)	((uint32_t)(paddr))
59198429Srpaulo#define IWN_HIADDR(paddr)	(((paddr) >> 32) & 0xf)
60198429Srpaulo#else
61198429Srpaulo#define IWN_LOADDR(paddr)	(paddr)
62198429Srpaulo#define IWN_HIADDR(paddr)	(0)
63198429Srpaulo#endif
64198429Srpaulo
65178676Ssam/*
66178676Ssam * Control and status registers.
67178676Ssam */
68198429Srpaulo#define IWN_HW_IF_CONFIG	0x000
69198429Srpaulo#define IWN_INT_COALESCING	0x004
70201209Srpaulo#define IWN_INT_PERIODIC	0x005	/* use IWN_WRITE_1 */
71198429Srpaulo#define IWN_INT			0x008
72201209Srpaulo#define IWN_INT_MASK		0x00c
73198429Srpaulo#define IWN_FH_INT		0x010
74253866Sadrian#define IWN_GPIO_IN		0x018	/* read external chip pins */
75178676Ssam#define IWN_RESET		0x020
76198429Srpaulo#define IWN_GP_CNTRL		0x024
77198429Srpaulo#define IWN_HW_REV		0x028
78198429Srpaulo#define IWN_EEPROM		0x02c
79198429Srpaulo#define IWN_EEPROM_GP		0x030
80198429Srpaulo#define IWN_OTP_GP		0x034
81198429Srpaulo#define IWN_GIO			0x03c
82253866Sadrian#define IWN_GP_UCODE		0x048
83201209Srpaulo#define IWN_GP_DRIVER		0x050
84253866Sadrian#define IWN_UCODE_GP1		0x054
85253866Sadrian#define IWN_UCODE_GP1_SET	0x058
86198429Srpaulo#define IWN_UCODE_GP1_CLR	0x05c
87253866Sadrian#define IWN_UCODE_GP2		0x060
88198429Srpaulo#define IWN_LED			0x094
89201209Srpaulo#define IWN_DRAM_INT_TBL	0x0a0
90220729Sbschmidt#define IWN_SHADOW_REG_CTRL	0x0a8
91198429Srpaulo#define IWN_GIO_CHICKEN		0x100
92198429Srpaulo#define IWN_ANA_PLL		0x20c
93201209Srpaulo#define IWN_HW_REV_WA		0x22c
94198429Srpaulo#define IWN_DBG_HPET_MEM	0x240
95201209Srpaulo#define IWN_DBG_LINK_PWR_MGMT	0x250
96253866Sadrian/* Need nic_lock for use above */
97198429Srpaulo#define IWN_MEM_RADDR		0x40c
98178676Ssam#define IWN_MEM_WADDR		0x410
99178676Ssam#define IWN_MEM_WDATA		0x418
100198429Srpaulo#define IWN_MEM_RDATA		0x41c
101253898Sadrian#define	IWN_TARG_MBX_C		0x430
102220726Sbschmidt#define IWN_PRPH_WADDR  	0x444
103220726Sbschmidt#define IWN_PRPH_RADDR   	0x448
104220726Sbschmidt#define IWN_PRPH_WDATA  	0x44c
105220726Sbschmidt#define IWN_PRPH_RDATA   	0x450
106198429Srpaulo#define IWN_HBUS_TARG_WRPTR	0x460
107178676Ssam
108198429Srpaulo/*
109198429Srpaulo * Flow-Handler registers.
110198429Srpaulo */
111198429Srpaulo#define IWN_FH_TFBD_CTRL0(qid)		(0x1900 + (qid) * 8)
112198429Srpaulo#define IWN_FH_TFBD_CTRL1(qid)		(0x1904 + (qid) * 8)
113198429Srpaulo#define IWN_FH_KW_ADDR			0x197c
114198429Srpaulo#define IWN_FH_SRAM_ADDR(qid)		(0x19a4 + (qid) * 4)
115198429Srpaulo#define IWN_FH_CBBC_QUEUE(qid)		(0x19d0 + (qid) * 4)
116198429Srpaulo#define IWN_FH_STATUS_WPTR		0x1bc0
117198429Srpaulo#define IWN_FH_RX_BASE			0x1bc4
118198429Srpaulo#define IWN_FH_RX_WPTR			0x1bc8
119198429Srpaulo#define IWN_FH_RX_CONFIG		0x1c00
120198429Srpaulo#define IWN_FH_RX_STATUS		0x1c44
121198429Srpaulo#define IWN_FH_TX_CONFIG(qid)		(0x1d00 + (qid) * 32)
122198429Srpaulo#define IWN_FH_TXBUF_STATUS(qid)	(0x1d08 + (qid) * 32)
123198429Srpaulo#define IWN_FH_TX_CHICKEN		0x1e98
124198429Srpaulo#define IWN_FH_TX_STATUS		0x1eb0
125178676Ssam
126198429Srpaulo/*
127198429Srpaulo * TX scheduler registers.
128198429Srpaulo */
129198429Srpaulo#define IWN_SCHED_BASE			0xa02c00
130198429Srpaulo#define IWN_SCHED_SRAM_ADDR		(IWN_SCHED_BASE + 0x000)
131198429Srpaulo#define IWN5000_SCHED_DRAM_ADDR		(IWN_SCHED_BASE + 0x008)
132198429Srpaulo#define IWN4965_SCHED_DRAM_ADDR		(IWN_SCHED_BASE + 0x010)
133198429Srpaulo#define IWN5000_SCHED_TXFACT		(IWN_SCHED_BASE + 0x010)
134198429Srpaulo#define IWN4965_SCHED_TXFACT		(IWN_SCHED_BASE + 0x01c)
135198429Srpaulo#define IWN4965_SCHED_QUEUE_RDPTR(qid)	(IWN_SCHED_BASE + 0x064 + (qid) * 4)
136198429Srpaulo#define IWN5000_SCHED_QUEUE_RDPTR(qid)	(IWN_SCHED_BASE + 0x068 + (qid) * 4)
137198429Srpaulo#define IWN4965_SCHED_QCHAIN_SEL	(IWN_SCHED_BASE + 0x0d0)
138198429Srpaulo#define IWN4965_SCHED_INTR_MASK		(IWN_SCHED_BASE + 0x0e4)
139198429Srpaulo#define IWN5000_SCHED_QCHAIN_SEL	(IWN_SCHED_BASE + 0x0e8)
140198429Srpaulo#define IWN4965_SCHED_QUEUE_STATUS(qid)	(IWN_SCHED_BASE + 0x104 + (qid) * 4)
141198429Srpaulo#define IWN5000_SCHED_INTR_MASK		(IWN_SCHED_BASE + 0x108)
142198429Srpaulo#define IWN5000_SCHED_QUEUE_STATUS(qid)	(IWN_SCHED_BASE + 0x10c + (qid) * 4)
143198429Srpaulo#define IWN5000_SCHED_AGGR_SEL		(IWN_SCHED_BASE + 0x248)
144178676Ssam
145178676Ssam/*
146198429Srpaulo * Offsets in TX scheduler's SRAM.
147198429Srpaulo */
148198429Srpaulo#define IWN4965_SCHED_CTX_OFF		0x380
149198429Srpaulo#define IWN4965_SCHED_CTX_LEN		416
150198429Srpaulo#define IWN4965_SCHED_QUEUE_OFFSET(qid)	(0x380 + (qid) * 8)
151198429Srpaulo#define IWN4965_SCHED_TRANS_TBL(qid)	(0x500 + (qid) * 2)
152198429Srpaulo#define IWN5000_SCHED_CTX_OFF		0x600
153198429Srpaulo#define IWN5000_SCHED_CTX_LEN		520
154198429Srpaulo#define IWN5000_SCHED_QUEUE_OFFSET(qid)	(0x600 + (qid) * 8)
155198429Srpaulo#define IWN5000_SCHED_TRANS_TBL(qid)	(0x7e0 + (qid) * 2)
156198429Srpaulo
157198429Srpaulo/*
158178676Ssam * NIC internal memory offsets.
159178676Ssam */
160201209Srpaulo#define IWN_APMG_CLK_CTRL	0x3000
161201209Srpaulo#define IWN_APMG_CLK_EN		0x3004
162198429Srpaulo#define IWN_APMG_CLK_DIS	0x3008
163198429Srpaulo#define IWN_APMG_PS		0x300c
164201209Srpaulo#define IWN_APMG_DIGITAL_SVR	0x3058
165201209Srpaulo#define IWN_APMG_ANALOG_SVR	0x306c
166198429Srpaulo#define IWN_APMG_PCI_STT	0x3010
167198429Srpaulo#define IWN_BSM_WR_CTRL		0x3400
168198429Srpaulo#define IWN_BSM_WR_MEM_SRC	0x3404
169198429Srpaulo#define IWN_BSM_WR_MEM_DST	0x3408
170198429Srpaulo#define IWN_BSM_WR_DWCOUNT	0x340c
171198429Srpaulo#define IWN_BSM_DRAM_TEXT_ADDR	0x3490
172198429Srpaulo#define IWN_BSM_DRAM_TEXT_SIZE	0x3494
173198429Srpaulo#define IWN_BSM_DRAM_DATA_ADDR	0x3498
174198429Srpaulo#define IWN_BSM_DRAM_DATA_SIZE	0x349c
175198429Srpaulo#define IWN_BSM_SRAM_BASE	0x3800
176178676Ssam
177198429Srpaulo/* Possible flags for register IWN_HW_IF_CONFIG. */
178198429Srpaulo#define IWN_HW_IF_CONFIG_4965_R		(1 <<  4)
179198429Srpaulo#define IWN_HW_IF_CONFIG_MAC_SI		(1 <<  8)
180198429Srpaulo#define IWN_HW_IF_CONFIG_RADIO_SI	(1 <<  9)
181198429Srpaulo#define IWN_HW_IF_CONFIG_EEPROM_LOCKED	(1 << 21)
182198429Srpaulo#define IWN_HW_IF_CONFIG_NIC_READY	(1 << 22)
183198429Srpaulo#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A	(1 << 23)
184198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE_DONE	(1 << 25)
185198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE	(1 << 27)
186178676Ssam
187201209Srpaulo/* Possible values for register IWN_INT_PERIODIC. */
188201209Srpaulo#define IWN_INT_PERIODIC_DIS	0x00
189201209Srpaulo#define IWN_INT_PERIODIC_ENA	0xff
190201209Srpaulo
191198429Srpaulo/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
192198429Srpaulo#define IWN_PRPH_DWORD	((sizeof (uint32_t) - 1) << 24)
193178676Ssam
194198429Srpaulo/* Possible values for IWN_BSM_WR_MEM_DST. */
195198429Srpaulo#define IWN_FW_TEXT_BASE	0x00000000
196198429Srpaulo#define IWN_FW_DATA_BASE	0x00800000
197178676Ssam
198198429Srpaulo/* Possible flags for register IWN_RESET. */
199198429Srpaulo#define IWN_RESET_NEVO			(1 << 0)
200198429Srpaulo#define IWN_RESET_SW			(1 << 7)
201198429Srpaulo#define IWN_RESET_MASTER_DISABLED	(1 << 8)
202198429Srpaulo#define IWN_RESET_STOP_MASTER		(1 << 9)
203258780Seadler#define IWN_RESET_LINK_PWR_MGMT_DIS	(1U << 31)
204178676Ssam
205198429Srpaulo/* Possible flags for register IWN_GP_CNTRL. */
206198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_ENA	(1 << 0)
207198429Srpaulo#define IWN_GP_CNTRL_MAC_CLOCK_READY	(1 << 0)
208198429Srpaulo#define IWN_GP_CNTRL_INIT_DONE		(1 << 2)
209198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_REQ	(1 << 3)
210198429Srpaulo#define IWN_GP_CNTRL_SLEEP		(1 << 4)
211198429Srpaulo#define IWN_GP_CNTRL_RFKILL		(1 << 27)
212178676Ssam
213198429Srpaulo/* Possible flags for register IWN_GIO_CHICKEN. */
214198429Srpaulo#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX	(1 << 23)
215198429Srpaulo#define IWN_GIO_CHICKEN_DIS_L0S_TIMER	(1 << 29)
216178676Ssam
217198429Srpaulo/* Possible flags for register IWN_GIO. */
218198429Srpaulo#define IWN_GIO_L0S_ENA		(1 << 1)
219178676Ssam
220201209Srpaulo/* Possible flags for register IWN_GP_DRIVER. */
221201209Srpaulo#define IWN_GP_DRIVER_RADIO_3X3_HYB	(0 << 0)
222201209Srpaulo#define IWN_GP_DRIVER_RADIO_2X2_HYB	(1 << 0)
223201209Srpaulo#define IWN_GP_DRIVER_RADIO_2X2_IPA	(2 << 0)
224206444Sbschmidt#define IWN_GP_DRIVER_CALIB_VER6	(1 << 2)
225220729Sbschmidt#define IWN_GP_DRIVER_6050_1X2		(1 << 3)
226253898Sadrian#define	IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT	(1 << 7)
227257880Sadrian#define	IWN_GP_DRIVER_NONE		0
228201209Srpaulo
229198429Srpaulo/* Possible flags for register IWN_UCODE_GP1_CLR. */
230198429Srpaulo#define IWN_UCODE_GP1_RFKILL		(1 << 1)
231198429Srpaulo#define IWN_UCODE_GP1_CMD_BLOCKED	(1 << 2)
232198429Srpaulo#define IWN_UCODE_GP1_CTEMP_STOP_RF	(1 << 3)
233253898Sadrian#define	IWN_UCODE_GP1_CFG_COMPLETE	(1 << 5)
234178676Ssam
235198429Srpaulo/* Possible flags/values for register IWN_LED. */
236198429Srpaulo#define IWN_LED_BSM_CTRL	(1 << 5)
237198429Srpaulo#define IWN_LED_OFF		0x00000038
238198429Srpaulo#define IWN_LED_ON		0x00000078
239178676Ssam
240253898Sadrian#define	IWN_MAX_BLINK_TBL	10
241253898Sadrian#define	IWN_LED_STATIC_ON	0
242253898Sadrian#define	IWN_LED_STATIC_OFF	1
243253898Sadrian#define	IWN_LED_SLOW_BLINK	2
244253898Sadrian#define	IWN_LED_INT_BLINK	3
245253898Sadrian#define	IWN_LED_UNIT		0x1388	/* 5 ms */
246253898Sadrian
247253898Sadrianstatic const struct {
248253898Sadrian	uint16_t	tpt;	/* Mb/s */
249253898Sadrian	uint8_t		on_time;
250253898Sadrian	uint8_t		off_time;
251253898Sadrian} blink_tbl[] =
252253898Sadrian{
253253898Sadrian	{300, 5, 5},
254253898Sadrian	{200, 8, 8},
255253898Sadrian	{100, 11, 11},
256253898Sadrian	{70, 13, 13},
257253898Sadrian	{50, 15, 15},
258253898Sadrian	{20, 17, 17},
259253898Sadrian	{10, 19, 19},
260253898Sadrian	{5, 22, 22},
261253898Sadrian	{1, 26, 26},
262253898Sadrian	{0, 33, 33},
263253898Sadrian	/* SOLID_ON */
264253898Sadrian};
265253898Sadrian
266201209Srpaulo/* Possible flags for register IWN_DRAM_INT_TBL. */
267201209Srpaulo#define IWN_DRAM_INT_TBL_WRAP_CHECK	(1 << 27)
268258780Seadler#define IWN_DRAM_INT_TBL_ENABLE		(1U << 31)
269201209Srpaulo
270198429Srpaulo/* Possible values for register IWN_ANA_PLL. */
271198429Srpaulo#define IWN_ANA_PLL_INIT	0x00880300
272178676Ssam
273198429Srpaulo/* Possible flags for register IWN_FH_RX_STATUS. */
274198429Srpaulo#define	IWN_FH_RX_STATUS_IDLE	(1 << 24)
275178676Ssam
276198429Srpaulo/* Possible flags for register IWN_BSM_WR_CTRL. */
277198429Srpaulo#define IWN_BSM_WR_CTRL_START_EN	(1 << 30)
278258780Seadler#define IWN_BSM_WR_CTRL_START		(1U << 31)
279178676Ssam
280198429Srpaulo/* Possible flags for register IWN_INT. */
281198429Srpaulo#define IWN_INT_ALIVE		(1 <<  0)
282198429Srpaulo#define IWN_INT_WAKEUP		(1 <<  1)
283198429Srpaulo#define IWN_INT_SW_RX		(1 <<  3)
284198429Srpaulo#define IWN_INT_CT_REACHED	(1 <<  6)
285198429Srpaulo#define IWN_INT_RF_TOGGLED	(1 <<  7)
286198429Srpaulo#define IWN_INT_SW_ERR		(1 << 25)
287201209Srpaulo#define IWN_INT_SCHED		(1 << 26)
288198429Srpaulo#define IWN_INT_FH_TX		(1 << 27)
289201209Srpaulo#define IWN_INT_RX_PERIODIC	(1 << 28)
290198429Srpaulo#define IWN_INT_HW_ERR		(1 << 29)
291258780Seadler#define IWN_INT_FH_RX		(1U << 31)
292178676Ssam
293198429Srpaulo/* Shortcut. */
294201209Srpaulo#define IWN_INT_MASK_DEF						\
295198429Srpaulo	(IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX |		\
296198429Srpaulo	 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP |		\
297198429Srpaulo	 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
298178676Ssam
299198429Srpaulo/* Possible flags for register IWN_FH_INT. */
300198429Srpaulo#define IWN_FH_INT_TX_CHNL(x)	(1 << (x))
301198429Srpaulo#define IWN_FH_INT_RX_CHNL(x)	(1 << ((x) + 16))
302198429Srpaulo#define IWN_FH_INT_HI_PRIOR	(1 << 30)
303198429Srpaulo/* Shortcuts for the above. */
304198429Srpaulo#define IWN_FH_INT_TX							\
305198429Srpaulo	(IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
306198429Srpaulo#define IWN_FH_INT_RX							\
307198429Srpaulo	(IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
308178676Ssam
309198429Srpaulo/* Possible flags/values for register IWN_FH_TX_CONFIG. */
310198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_PAUSE		0
311258780Seadler#define IWN_FH_TX_CONFIG_DMA_ENA		(1U << 31)
312198429Srpaulo#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD	(1 << 20)
313178676Ssam
314198429Srpaulo/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
315198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBNUM(x)	((x) << 20)
316198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBIDX(x)	((x) << 12)
317198429Srpaulo#define IWN_FH_TXBUF_STATUS_TFBD_VALID	3
318198429Srpaulo
319198429Srpaulo/* Possible flags for register IWN_FH_TX_CHICKEN. */
320198429Srpaulo#define IWN_FH_TX_CHICKEN_SCHED_RETRY	(1 << 1)
321198429Srpaulo
322198429Srpaulo/* Possible flags for register IWN_FH_TX_STATUS. */
323220659Sbschmidt#define IWN_FH_TX_STATUS_IDLE(chnl)	(1 << ((chnl) + 16))
324198429Srpaulo
325198429Srpaulo/* Possible flags for register IWN_FH_RX_CONFIG. */
326258780Seadler#define IWN_FH_RX_CONFIG_ENA		(1U << 31)
327198429Srpaulo#define IWN_FH_RX_CONFIG_NRBD(x)	((x) << 20)
328198429Srpaulo#define IWN_FH_RX_CONFIG_RB_SIZE_8K	(1 << 16)
329198429Srpaulo#define IWN_FH_RX_CONFIG_SINGLE_FRAME	(1 << 15)
330198429Srpaulo#define IWN_FH_RX_CONFIG_IRQ_DST_HOST	(1 << 12)
331198429Srpaulo#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x)	((x) << 4)
332198429Srpaulo#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY	(1 <<  2)
333198429Srpaulo
334198429Srpaulo/* Possible flags for register IWN_FH_TX_CONFIG. */
335258780Seadler#define IWN_FH_TX_CONFIG_DMA_ENA	(1U << 31)
336198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA	(1 <<  3)
337198429Srpaulo
338198429Srpaulo/* Possible flags for register IWN_EEPROM. */
339198429Srpaulo#define IWN_EEPROM_READ_VALID	(1 << 0)
340198429Srpaulo#define IWN_EEPROM_CMD		(1 << 1)
341198429Srpaulo
342198429Srpaulo/* Possible flags for register IWN_EEPROM_GP. */
343198429Srpaulo#define IWN_EEPROM_GP_IF_OWNER	0x00000180
344198429Srpaulo
345198429Srpaulo/* Possible flags for register IWN_OTP_GP. */
346198429Srpaulo#define IWN_OTP_GP_DEV_SEL_OTP		(1 << 16)
347198429Srpaulo#define IWN_OTP_GP_RELATIVE_ACCESS	(1 << 17)
348198429Srpaulo#define IWN_OTP_GP_ECC_CORR_STTS	(1 << 20)
349198429Srpaulo#define IWN_OTP_GP_ECC_UNCORR_STTS	(1 << 21)
350198429Srpaulo
351198429Srpaulo/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */
352198429Srpaulo#define IWN4965_TXQ_STATUS_ACTIVE	0x0007fc01
353198429Srpaulo#define IWN4965_TXQ_STATUS_INACTIVE	0x0007fc00
354198429Srpaulo#define IWN4965_TXQ_STATUS_AGGR_ENA	(1 << 5 | 1 << 8)
355198429Srpaulo#define IWN4965_TXQ_STATUS_CHGACT	(1 << 10)
356198429Srpaulo#define IWN5000_TXQ_STATUS_ACTIVE	0x00ff0018
357198429Srpaulo#define IWN5000_TXQ_STATUS_INACTIVE	0x00ff0010
358198429Srpaulo#define IWN5000_TXQ_STATUS_CHGACT	(1 << 19)
359198429Srpaulo
360201209Srpaulo/* Possible flags for registers IWN_APMG_CLK_*. */
361198429Srpaulo#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT	(1 <<  9)
362198429Srpaulo#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT	(1 << 11)
363198429Srpaulo
364198429Srpaulo/* Possible flags for register IWN_APMG_PS. */
365198429Srpaulo#define IWN_APMG_PS_EARLY_PWROFF_DIS	(1 << 22)
366198429Srpaulo#define IWN_APMG_PS_PWR_SRC(x)		((x) << 24)
367198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VMAIN	0
368198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VAUX	2
369198429Srpaulo#define IWN_APMG_PS_PWR_SRC_MASK	IWN_APMG_PS_PWR_SRC(3)
370198429Srpaulo#define IWN_APMG_PS_RESET_REQ		(1 << 26)
371198429Srpaulo
372201209Srpaulo/* Possible flags for register IWN_APMG_DIGITAL_SVR. */
373201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x)		(((x) & 0xf) << 5)
374201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK	\
375201209Srpaulo	IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf)
376201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32	\
377201209Srpaulo	IWN_APMG_DIGITAL_SVR_VOLTAGE(3)
378201209Srpaulo
379198429Srpaulo/* Possible flags for IWN_APMG_PCI_STT. */
380198429Srpaulo#define IWN_APMG_PCI_STT_L1A_DIS	(1 << 11)
381198429Srpaulo
382198429Srpaulo/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
383258780Seadler#define IWN_FW_UPDATED	(1U << 31)
384178676Ssam
385198429Srpaulo#define IWN_SCHED_WINSZ		64
386198429Srpaulo#define IWN_SCHED_LIMIT		64
387198429Srpaulo#define IWN4965_SCHED_COUNT	512
388198429Srpaulo#define IWN5000_SCHED_COUNT	(IWN_TX_RING_COUNT + IWN_SCHED_WINSZ)
389198429Srpaulo#define IWN4965_SCHEDSZ		(IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2)
390198429Srpaulo#define IWN5000_SCHEDSZ		(IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2)
391178676Ssam
392198429Srpaulostruct iwn_tx_desc {
393198429Srpaulo	uint8_t		reserved1[3];
394198429Srpaulo	uint8_t		nsegs;
395198429Srpaulo	struct {
396198429Srpaulo		uint32_t	addr;
397198429Srpaulo		uint16_t	len;
398198429Srpaulo	} __packed	segs[IWN_MAX_SCATTER];
399198429Srpaulo	/* Pad to 128 bytes. */
400198429Srpaulo	uint32_t	reserved2;
401198429Srpaulo} __packed;
402178676Ssam
403198429Srpaulostruct iwn_rx_status {
404178676Ssam	uint16_t	closed_count;
405178676Ssam	uint16_t	closed_rx_count;
406178676Ssam	uint16_t	finished_count;
407178676Ssam	uint16_t	finished_rx_count;
408178676Ssam	uint32_t	reserved[2];
409178676Ssam} __packed;
410178676Ssam
411178676Ssamstruct iwn_rx_desc {
412253898Sadrian	/*
413253898Sadrian	 * The first 4 bytes of the RX frame header contain both the RX frame
414253898Sadrian	 * size and some flags.
415253898Sadrian	 * Bit fields:
416253898Sadrian	 * 31:    flag flush RB request
417253898Sadrian	 * 30:    flag ignore TC (terminal counter) request
418253898Sadrian	 * 29:    flag fast IRQ request
419253898Sadrian	 * 28-14: Reserved
420253898Sadrian	 * 13-00: RX frame size
421253898Sadrian	 */
422178676Ssam	uint32_t	len;
423178676Ssam	uint8_t		type;
424198429Srpaulo#define IWN_UC_READY			  1
425198429Srpaulo#define IWN_ADD_NODE_DONE		 24
426198429Srpaulo#define IWN_TX_DONE			 28
427253898Sadrian#define	IWN_REPLY_LED_CMD		72
428198429Srpaulo#define IWN5000_CALIBRATION_RESULT	102
429198429Srpaulo#define IWN5000_CALIBRATION_DONE	103
430198429Srpaulo#define IWN_START_SCAN			130
431253898Sadrian#define	IWN_NOTIF_SCAN_RESULT		131
432198429Srpaulo#define IWN_STOP_SCAN			132
433198429Srpaulo#define IWN_RX_STATISTICS		156
434198429Srpaulo#define IWN_BEACON_STATISTICS		157
435198429Srpaulo#define IWN_STATE_CHANGED		161
436198429Srpaulo#define IWN_BEACON_MISSED		162
437198429Srpaulo#define IWN_RX_PHY			192
438198429Srpaulo#define IWN_MPDU_RX_DONE		193
439198429Srpaulo#define IWN_RX_DONE			195
440201209Srpaulo#define IWN_RX_COMPRESSED_BA		197
441178676Ssam
442253898Sadrian	uint8_t		flags;	/* 0:5 reserved, 6 abort, 7 internal */
443253898Sadrian	uint8_t		idx;	/* position within TX queue */
444178676Ssam	uint8_t		qid;
445253898Sadrian	/* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX
446253898Sadrian	 * or uCode-originated notification
447253898Sadrian	 */
448178676Ssam} __packed;
449178676Ssam
450253898Sadrian#define	IWN_RX_DESC_QID_MSK		0x1F
451253898Sadrian#define	IWN_UNSOLICITED_RX_NOTIF	0x80
452253898Sadrian
453253898Sadrian/* CARD_STATE_NOTIFICATION */
454253898Sadrian#define	IWN_STATE_CHANGE_HW_CARD_DISABLED		0x01
455253898Sadrian#define	IWN_STATE_CHANGE_SW_CARD_DISABLED		0x02
456253898Sadrian#define	IWN_STATE_CHANGE_CT_CARD_DISABLED		0x04
457253898Sadrian#define	IWN_STATE_CHANGE_RXON_CARD_DISABLED		0x10
458253898Sadrian
459198429Srpaulo/* Possible RX status flags. */
460198429Srpaulo#define IWN_RX_NO_CRC_ERR	(1 <<  0)
461198429Srpaulo#define IWN_RX_NO_OVFL_ERR	(1 <<  1)
462198429Srpaulo/* Shortcut for the above. */
463178676Ssam#define IWN_RX_NOERROR	(IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR)
464198429Srpaulo#define IWN_RX_MPDU_MIC_OK	(1 <<  6)
465198429Srpaulo#define IWN_RX_CIPHER_MASK	(7 <<  8)
466198429Srpaulo#define IWN_RX_CIPHER_CCMP	(2 <<  8)
467198429Srpaulo#define IWN_RX_MPDU_DEC		(1 << 11)
468198429Srpaulo#define IWN_RX_DECRYPT_MASK	(3 << 11)
469198429Srpaulo#define IWN_RX_DECRYPT_OK	(3 << 11)
470178676Ssam
471178676Ssamstruct iwn_tx_cmd {
472178676Ssam	uint8_t	code;
473201209Srpaulo#define IWN_CMD_RXON			 16
474201209Srpaulo#define IWN_CMD_RXON_ASSOC		 17
475198429Srpaulo#define IWN_CMD_EDCA_PARAMS		 19
476198429Srpaulo#define IWN_CMD_TIMING			 20
477198429Srpaulo#define IWN_CMD_ADD_NODE		 24
478198429Srpaulo#define IWN_CMD_TX_DATA			 28
479198429Srpaulo#define IWN_CMD_LINK_QUALITY		 78
480198429Srpaulo#define IWN_CMD_SET_LED			 72
481198429Srpaulo#define IWN5000_CMD_WIMAX_COEX		 90
482253898Sadrian#define	IWN_TEMP_NOTIFICATION		98
483198429Srpaulo#define IWN5000_CMD_CALIB_CONFIG	101
484202986Srpaulo#define IWN5000_CMD_CALIB_RESULT	102
485202986Srpaulo#define IWN5000_CMD_CALIB_COMPLETE	103
486198429Srpaulo#define IWN_CMD_SET_POWER_MODE		119
487198429Srpaulo#define IWN_CMD_SCAN			128
488202986Srpaulo#define IWN_CMD_SCAN_RESULTS		131
489201209Srpaulo#define IWN_CMD_TXPOWER_DBM		149
490198429Srpaulo#define IWN_CMD_TXPOWER			151
491201209Srpaulo#define IWN5000_CMD_TX_ANT_CONFIG	152
492270738Sadrian#define IWN_CMD_TXPOWER_DBM_V1		152
493198429Srpaulo#define IWN_CMD_BT_COEX			155
494198429Srpaulo#define IWN_CMD_GET_STATISTICS		156
495198429Srpaulo#define IWN_CMD_SET_CRITICAL_TEMP	164
496198429Srpaulo#define IWN_CMD_SET_SENSITIVITY		168
497198429Srpaulo#define IWN_CMD_PHY_CALIB		176
498220891Sbschmidt#define IWN_CMD_BT_COEX_PRIOTABLE	204
499220891Sbschmidt#define IWN_CMD_BT_COEX_PROT		205
500253898Sadrian#define	IWN_CMD_BT_COEX_NOTIF		206
501253898Sadrian/* PAN commands */
502253898Sadrian#define	IWN_CMD_WIPAN_PARAMS			0xb2
503253898Sadrian#define	IWN_CMD_WIPAN_RXON			0xb3
504253898Sadrian#define	IWN_CMD_WIPAN_RXON_TIMING		0xb4
505253898Sadrian#define	IWN_CMD_WIPAN_RXON_ASSOC		0xb6
506253898Sadrian#define	IWN_CMD_WIPAN_QOS_PARAM			0xb7
507253898Sadrian#define	IWN_CMD_WIPAN_WEPKEY			0xb8
508253898Sadrian#define	IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH	0xb9
509253898Sadrian#define	IWN_CMD_WIPAN_NOA_NOTIFICATION		0xbc
510253898Sadrian#define	IWN_CMD_WIPAN_DEACTIVATION_COMPLETE	0xbd
511198429Srpaulo
512178676Ssam	uint8_t	flags;
513178676Ssam	uint8_t	idx;
514178676Ssam	uint8_t	qid;
515178676Ssam	uint8_t	data[136];
516178676Ssam} __packed;
517178676Ssam
518253898Sadrian/*
519253898Sadrian * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156
520253898Sadrian * all devices identical.
521253898Sadrian *
522253898Sadrian * This command triggers an immediate response containing uCode statistics.
523253898Sadrian * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157.
524253898Sadrian *
525253898Sadrian * If the CLEAR_STATS configuration flag is set, uCode will clear its
526253898Sadrian * internal copy of the statistics (counters) after issuing the response.
527253898Sadrian * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below).
528253898Sadrian *
529253898Sadrian * If the DISABLE_NOTIF configuration flag is set, uCode will not issue
530253898Sadrian * IWN_BEACON_STATISTICS after received beacons.  This flag
531253898Sadrian * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself.
532253898Sadrian */
533253898Sadrianstruct iwn_statistics_cmd {
534253898Sadrian	uint32_t	configuration_flags;
535253898Sadrian#define	IWN_STATS_CONF_CLEAR_STATS		htole32(0x1)
536253898Sadrian#define	IWN_STATS_CONF_DISABLE_NOTIF	htole32(0x2)
537253898Sadrian} __packed;
538253898Sadrian
539198429Srpaulo/* Antenna flags, used in various commands. */
540198429Srpaulo#define IWN_ANT_A	(1 << 0)
541198429Srpaulo#define IWN_ANT_B	(1 << 1)
542198429Srpaulo#define IWN_ANT_C	(1 << 2)
543201209Srpaulo/* Shortcuts. */
544201209Srpaulo#define IWN_ANT_AB	(IWN_ANT_A | IWN_ANT_B)
545201209Srpaulo#define IWN_ANT_BC	(IWN_ANT_B | IWN_ANT_C)
546253898Sadrian#define	IWN_ANT_AC	(IWN_ANT_A | IWN_ANT_C)
547198429Srpaulo#define IWN_ANT_ABC	(IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
548198429Srpaulo
549201209Srpaulo/* Structure for command IWN_CMD_RXON. */
550198429Srpaulostruct iwn_rxon {
551178676Ssam	uint8_t		myaddr[IEEE80211_ADDR_LEN];
552178676Ssam	uint16_t	reserved1;
553178676Ssam	uint8_t		bssid[IEEE80211_ADDR_LEN];
554178676Ssam	uint16_t	reserved2;
555178676Ssam	uint8_t		wlap[IEEE80211_ADDR_LEN];
556178676Ssam	uint16_t	reserved3;
557178676Ssam	uint8_t		mode;
558178676Ssam#define IWN_MODE_HOSTAP		1
559178676Ssam#define IWN_MODE_STA		3
560178676Ssam#define IWN_MODE_IBSS		4
561178676Ssam#define IWN_MODE_MONITOR	6
562253898Sadrian#define	IWN_MODE_2STA		8
563253898Sadrian#define	IWN_MODE_P2P		9
564198429Srpaulo
565198429Srpaulo	uint8_t		air;
566178676Ssam	uint16_t	rxchain;
567201209Srpaulo#define IWN_RXCHAIN_DRIVER_FORCE	(1 << 0)
568201209Srpaulo#define IWN_RXCHAIN_VALID(x)		(((x) & IWN_ANT_ABC) << 1)
569201209Srpaulo#define IWN_RXCHAIN_FORCE_SEL(x)	(((x) & IWN_ANT_ABC) << 4)
570201209Srpaulo#define IWN_RXCHAIN_FORCE_MIMO_SEL(x)	(((x) & IWN_ANT_ABC) << 7)
571198429Srpaulo#define IWN_RXCHAIN_IDLE_COUNT(x)	((x) << 10)
572198429Srpaulo#define IWN_RXCHAIN_MIMO_COUNT(x)	((x) << 12)
573198429Srpaulo#define IWN_RXCHAIN_MIMO_FORCE		(1 << 14)
574198429Srpaulo
575198429Srpaulo	uint8_t		ofdm_mask;
576198429Srpaulo	uint8_t		cck_mask;
577178676Ssam	uint16_t	associd;
578178676Ssam	uint32_t	flags;
579201209Srpaulo#define IWN_RXON_24GHZ		(1 <<  0)
580201209Srpaulo#define IWN_RXON_CCK		(1 <<  1)
581201209Srpaulo#define IWN_RXON_AUTO		(1 <<  2)
582201209Srpaulo#define IWN_RXON_SHSLOT		(1 <<  4)
583201209Srpaulo#define IWN_RXON_SHPREAMBLE	(1 <<  5)
584201209Srpaulo#define IWN_RXON_NODIVERSITY	(1 <<  7)
585201209Srpaulo#define IWN_RXON_ANTENNA_A	(1 <<  8)
586201209Srpaulo#define IWN_RXON_ANTENNA_B	(1 <<  9)
587201209Srpaulo#define IWN_RXON_TSF		(1 << 15)
588221653Sbschmidt#define IWN_RXON_HT_HT40MINUS	(1 << 22)
589285234Sadrian
590221653Sbschmidt#define IWN_RXON_HT_PROTMODE(x)	(x << 23)
591285234Sadrian
592285234Sadrian/* 0=legacy, 1=pure40, 2=mixed */
593221653Sbschmidt#define IWN_RXON_HT_MODEPURE40	(1 << 25)
594221653Sbschmidt#define IWN_RXON_HT_MODEMIXED	(2 << 25)
595285234Sadrian
596201209Srpaulo#define IWN_RXON_CTS_TO_SELF	(1 << 30)
597198429Srpaulo
598178676Ssam	uint32_t	filter;
599198429Srpaulo#define IWN_FILTER_PROMISC	(1 << 0)
600198429Srpaulo#define IWN_FILTER_CTL		(1 << 1)
601198429Srpaulo#define IWN_FILTER_MULTICAST	(1 << 2)
602198429Srpaulo#define IWN_FILTER_NODECRYPT	(1 << 3)
603198429Srpaulo#define IWN_FILTER_BSS		(1 << 5)
604198429Srpaulo#define IWN_FILTER_BEACON	(1 << 6)
605198429Srpaulo
606198429Srpaulo	uint8_t		chan;
607198429Srpaulo	uint8_t		reserved4;
608198429Srpaulo	uint8_t		ht_single_mask;
609198429Srpaulo	uint8_t		ht_dual_mask;
610201209Srpaulo	/* The following fields are for >=5000 Series only. */
611198429Srpaulo	uint8_t		ht_triple_mask;
612198429Srpaulo	uint8_t		reserved5;
613198429Srpaulo	uint16_t	acquisition;
614198429Srpaulo	uint16_t	reserved6;
615178676Ssam} __packed;
616178676Ssam
617198429Srpaulo#define IWN4965_RXONSZ	(sizeof (struct iwn_rxon) - 6)
618198429Srpaulo#define IWN5000_RXONSZ	(sizeof (struct iwn_rxon))
619198429Srpaulo
620198429Srpaulo/* Structure for command IWN_CMD_ASSOCIATE. */
621178676Ssamstruct iwn_assoc {
622178676Ssam	uint32_t	flags;
623178676Ssam	uint32_t	filter;
624178676Ssam	uint8_t		ofdm_mask;
625178676Ssam	uint8_t		cck_mask;
626178676Ssam	uint16_t	reserved;
627178676Ssam} __packed;
628178676Ssam
629198429Srpaulo/* Structure for command IWN_CMD_EDCA_PARAMS. */
630178676Ssamstruct iwn_edca_params {
631178676Ssam	uint32_t	flags;
632178676Ssam#define IWN_EDCA_UPDATE	(1 << 0)
633178676Ssam#define IWN_EDCA_TXOP	(1 << 4)
634178676Ssam
635178676Ssam	struct {
636178676Ssam		uint16_t	cwmin;
637178676Ssam		uint16_t	cwmax;
638178676Ssam		uint8_t		aifsn;
639178676Ssam		uint8_t		reserved;
640178676Ssam		uint16_t	txoplimit;
641201209Srpaulo	} __packed	ac[WME_NUM_AC];
642178676Ssam} __packed;
643178676Ssam
644198429Srpaulo/* Structure for command IWN_CMD_TIMING. */
645198429Srpaulostruct iwn_cmd_timing {
646178676Ssam	uint64_t	tstamp;
647178676Ssam	uint16_t	bintval;
648178676Ssam	uint16_t	atim;
649178676Ssam	uint32_t	binitval;
650178676Ssam	uint16_t	lintval;
651253898Sadrian	uint8_t		dtim_period;
652253898Sadrian	uint8_t		delta_cp_bss_tbtts;
653178676Ssam} __packed;
654178676Ssam
655198429Srpaulo/* Structure for command IWN_CMD_ADD_NODE. */
656178676Ssamstruct iwn_node_info {
657178676Ssam	uint8_t		control;
658178676Ssam#define IWN_NODE_UPDATE		(1 << 0)
659198429Srpaulo
660178676Ssam	uint8_t		reserved1[3];
661198429Srpaulo
662178676Ssam	uint8_t		macaddr[IEEE80211_ADDR_LEN];
663178676Ssam	uint16_t	reserved2;
664178676Ssam	uint8_t		id;
665178676Ssam#define IWN_ID_BSS		 0
666253898Sadrian#define	IWN_STA_ID		1
667253898Sadrian
668253898Sadrian#define	IWN_PAN_ID_BCAST		14
669198429Srpaulo#define IWN5000_ID_BROADCAST	15
670198429Srpaulo#define IWN4965_ID_BROADCAST	31
671198429Srpaulo
672178676Ssam	uint8_t		flags;
673198429Srpaulo#define IWN_FLAG_SET_KEY		(1 << 0)
674198429Srpaulo#define IWN_FLAG_SET_DISABLE_TID	(1 << 1)
675198429Srpaulo#define IWN_FLAG_SET_TXRATE		(1 << 2)
676198429Srpaulo#define IWN_FLAG_SET_ADDBA		(1 << 3)
677198429Srpaulo#define IWN_FLAG_SET_DELBA		(1 << 4)
678198429Srpaulo
679178676Ssam	uint16_t	reserved3;
680198429Srpaulo	uint16_t	kflags;
681198429Srpaulo#define IWN_KFLAG_CCMP		(1 <<  1)
682198429Srpaulo#define IWN_KFLAG_MAP		(1 <<  3)
683198429Srpaulo#define IWN_KFLAG_KID(kid)	((kid) << 8)
684198429Srpaulo#define IWN_KFLAG_INVALID	(1 << 11)
685198429Srpaulo#define IWN_KFLAG_GROUP		(1 << 14)
686198429Srpaulo
687178676Ssam	uint8_t		tsc2;	/* TKIP TSC2 */
688178676Ssam	uint8_t		reserved4;
689178676Ssam	uint16_t	ttak[5];
690198429Srpaulo	uint8_t		kid;
691198429Srpaulo	uint8_t		reserved5;
692198429Srpaulo	uint8_t		key[16];
693198429Srpaulo	/* The following 3 fields are for 5000 Series only. */
694198429Srpaulo	uint64_t	tsc;
695198429Srpaulo	uint8_t		rxmic[8];
696198429Srpaulo	uint8_t		txmic[8];
697198429Srpaulo
698178676Ssam	uint32_t	htflags;
699221653Sbschmidt#define IWN_SMPS_MIMO_PROT		(1 << 17)
700198429Srpaulo#define IWN_AMDPU_SIZE_FACTOR(x)	((x) << 19)
701221653Sbschmidt#define IWN_NODE_HT40			(1 << 21)
702221653Sbschmidt#define IWN_SMPS_MIMO_DIS		(1 << 22)
703198429Srpaulo#define IWN_AMDPU_DENSITY(x)		((x) << 23)
704198429Srpaulo
705178676Ssam	uint32_t	mask;
706198429Srpaulo	uint16_t	disable_tid;
707198429Srpaulo	uint16_t	reserved6;
708198429Srpaulo	uint8_t		addba_tid;
709198429Srpaulo	uint8_t		delba_tid;
710198429Srpaulo	uint16_t	addba_ssn;
711198429Srpaulo	uint32_t	reserved7;
712198429Srpaulo} __packed;
713198429Srpaulo
714198429Srpaulostruct iwn4965_node_info {
715198429Srpaulo	uint8_t		control;
716198429Srpaulo	uint8_t		reserved1[3];
717198429Srpaulo	uint8_t		macaddr[IEEE80211_ADDR_LEN];
718198429Srpaulo	uint16_t	reserved2;
719198429Srpaulo	uint8_t		id;
720198429Srpaulo	uint8_t		flags;
721198429Srpaulo	uint16_t	reserved3;
722198429Srpaulo	uint16_t	kflags;
723198429Srpaulo	uint8_t		tsc2;	/* TKIP TSC2 */
724198429Srpaulo	uint8_t		reserved4;
725198429Srpaulo	uint16_t	ttak[5];
726198429Srpaulo	uint8_t		kid;
727198429Srpaulo	uint8_t		reserved5;
728198429Srpaulo	uint8_t		key[16];
729198429Srpaulo	uint32_t	htflags;
730198429Srpaulo	uint32_t	mask;
731198429Srpaulo	uint16_t	disable_tid;
732198429Srpaulo	uint16_t	reserved6;
733198429Srpaulo	uint8_t		addba_tid;
734198429Srpaulo	uint8_t		delba_tid;
735198429Srpaulo	uint16_t	addba_ssn;
736198429Srpaulo	uint32_t	reserved7;
737198429Srpaulo} __packed;
738198429Srpaulo
739221649Sbschmidt#define IWN_RFLAG_MCS		(1 << 8)
740221648Sbschmidt#define IWN_RFLAG_CCK		(1 << 9)
741221649Sbschmidt#define IWN_RFLAG_GREENFIELD	(1 << 10)
742221649Sbschmidt#define IWN_RFLAG_HT40		(1 << 11)
743221649Sbschmidt#define IWN_RFLAG_DUPLICATE	(1 << 12)
744221649Sbschmidt#define IWN_RFLAG_SGI		(1 << 13)
745221648Sbschmidt#define IWN_RFLAG_ANT(x)	((x) << 14)
746178676Ssam
747198429Srpaulo/* Structure for command IWN_CMD_TX_DATA. */
748178676Ssamstruct iwn_cmd_data {
749178676Ssam	uint16_t	len;
750178676Ssam	uint16_t	lnext;
751178676Ssam	uint32_t	flags;
752198429Srpaulo#define IWN_TX_NEED_PROTECTION	(1 <<  0)	/* 5000 only */
753178676Ssam#define IWN_TX_NEED_RTS		(1 <<  1)
754178676Ssam#define IWN_TX_NEED_CTS		(1 <<  2)
755178676Ssam#define IWN_TX_NEED_ACK		(1 <<  3)
756198429Srpaulo#define IWN_TX_LINKQ		(1 <<  4)
757198429Srpaulo#define IWN_TX_IMM_BA		(1 <<  6)
758178676Ssam#define IWN_TX_FULL_TXOP	(1 <<  7)
759178676Ssam#define IWN_TX_BT_DISABLE	(1 << 12)	/* bluetooth coexistence */
760178676Ssam#define IWN_TX_AUTO_SEQ		(1 << 13)
761198429Srpaulo#define IWN_TX_MORE_FRAG	(1 << 14)
762178676Ssam#define IWN_TX_INSERT_TSTAMP	(1 << 16)
763178676Ssam#define IWN_TX_NEED_PADDING	(1 << 20)
764178676Ssam
765198429Srpaulo	uint32_t	scratch;
766221648Sbschmidt	uint32_t	rate;
767198429Srpaulo
768178676Ssam	uint8_t		id;
769178676Ssam	uint8_t		security;
770178676Ssam#define IWN_CIPHER_WEP40	1
771178676Ssam#define IWN_CIPHER_CCMP		2
772178676Ssam#define IWN_CIPHER_TKIP		3
773178676Ssam#define IWN_CIPHER_WEP104	9
774178676Ssam
775198429Srpaulo	uint8_t		linkq;
776178676Ssam	uint8_t		reserved2;
777198429Srpaulo	uint8_t		key[16];
778178676Ssam	uint16_t	fnext;
779178676Ssam	uint16_t	reserved3;
780178676Ssam	uint32_t	lifetime;
781178676Ssam#define IWN_LIFETIME_INFINITE	0xffffffff
782178676Ssam
783178676Ssam	uint32_t	loaddr;
784178676Ssam	uint8_t		hiaddr;
785178676Ssam	uint8_t		rts_ntries;
786178676Ssam	uint8_t		data_ntries;
787178676Ssam	uint8_t		tid;
788178676Ssam	uint16_t	timeout;
789178676Ssam	uint16_t	txop;
790178676Ssam} __packed;
791178676Ssam
792198429Srpaulo/* Structure for command IWN_CMD_LINK_QUALITY. */
793178676Ssam#define IWN_MAX_TX_RETRIES	16
794178676Ssamstruct iwn_cmd_link_quality {
795178676Ssam	uint8_t		id;
796178676Ssam	uint8_t		reserved1;
797178676Ssam	uint16_t	ctl;
798178676Ssam	uint8_t		flags;
799198429Srpaulo	uint8_t		mimo;
800198429Srpaulo	uint8_t		antmsk_1stream;
801198429Srpaulo	uint8_t		antmsk_2stream;
802201209Srpaulo	uint8_t		ridx[WME_NUM_AC];
803198429Srpaulo	uint16_t	ampdu_limit;
804198429Srpaulo	uint8_t		ampdu_threshold;
805198429Srpaulo	uint8_t		ampdu_max;
806178676Ssam	uint32_t	reserved2;
807221648Sbschmidt	uint32_t	retry[IWN_MAX_TX_RETRIES];
808178676Ssam	uint32_t	reserved3;
809178676Ssam} __packed;
810178676Ssam
811198429Srpaulo/* Structure for command IWN_CMD_SET_LED. */
812178676Ssamstruct iwn_cmd_led {
813178676Ssam	uint32_t	unit;	/* multiplier (in usecs) */
814178676Ssam	uint8_t		which;
815178676Ssam#define IWN_LED_ACTIVITY	1
816178676Ssam#define IWN_LED_LINK		2
817178676Ssam
818178676Ssam	uint8_t		off;
819178676Ssam	uint8_t		on;
820178676Ssam	uint8_t		reserved;
821178676Ssam} __packed;
822178676Ssam
823198429Srpaulo/* Structure for command IWN5000_CMD_WIMAX_COEX. */
824198429Srpaulostruct iwn5000_wimax_coex {
825198429Srpaulo	uint32_t	flags;
826201209Srpaulo#define IWN_WIMAX_COEX_STA_TABLE_VALID		(1 << 0)
827201209Srpaulo#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK	(1 << 2)
828201209Srpaulo#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK		(1 << 3)
829201209Srpaulo#define IWN_WIMAX_COEX_ENABLE			(1 << 7)
830201209Srpaulo
831201209Srpaulo	struct iwn5000_wimax_event {
832198429Srpaulo		uint8_t	request;
833198429Srpaulo		uint8_t	window;
834198429Srpaulo		uint8_t	reserved;
835198429Srpaulo		uint8_t	flags;
836198429Srpaulo	} __packed	events[16];
837198429Srpaulo} __packed;
838198429Srpaulo
839198429Srpaulo/* Structures for command IWN5000_CMD_CALIB_CONFIG. */
840198429Srpaulostruct iwn5000_calib_elem {
841198429Srpaulo	uint32_t	enable;
842198429Srpaulo	uint32_t	start;
843227805Sbschmidt#define	IWN5000_CALIB_DC	(1 << 1)
844227805Sbschmidt
845198429Srpaulo	uint32_t	send;
846198429Srpaulo	uint32_t	apply;
847198429Srpaulo	uint32_t	reserved;
848198429Srpaulo} __packed;
849198429Srpaulo
850198429Srpaulostruct iwn5000_calib_status {
851198429Srpaulo	struct iwn5000_calib_elem	once;
852198429Srpaulo	struct iwn5000_calib_elem	perd;
853198429Srpaulo	uint32_t			flags;
854198429Srpaulo} __packed;
855198429Srpaulo
856198429Srpaulostruct iwn5000_calib_config {
857198429Srpaulo	struct iwn5000_calib_status	ucode;
858198429Srpaulo	struct iwn5000_calib_status	driver;
859198429Srpaulo	uint32_t			reserved;
860198429Srpaulo} __packed;
861198429Srpaulo
862198429Srpaulo/* Structure for command IWN_CMD_SET_POWER_MODE. */
863198429Srpaulostruct iwn_pmgt_cmd {
864178676Ssam	uint16_t	flags;
865198429Srpaulo#define IWN_PS_ALLOW_SLEEP	(1 << 0)
866198429Srpaulo#define IWN_PS_NOTIFY		(1 << 1)
867198429Srpaulo#define IWN_PS_SLEEP_OVER_DTIM	(1 << 2)
868198429Srpaulo#define IWN_PS_PCI_PMGT		(1 << 3)
869198429Srpaulo#define IWN_PS_FAST_PD		(1 << 4)
870253898Sadrian#define	IWN_PS_BEACON_FILTERING	(1 << 5)
871253898Sadrian#define	IWN_PS_SHADOW_REG	(1 << 6)
872253898Sadrian#define	IWN_PS_CT_KILL		(1 << 7)
873253898Sadrian#define	IWN_PS_BT_SCD		(1 << 8)
874253898Sadrian#define	IWN_PS_ADVANCED_PM	(1 << 9)
875178676Ssam
876198429Srpaulo	uint8_t		keepalive;
877178676Ssam	uint8_t		debug;
878198429Srpaulo	uint32_t	rxtimeout;
879198429Srpaulo	uint32_t	txtimeout;
880198429Srpaulo	uint32_t	intval[5];
881178676Ssam	uint32_t	beacons;
882178676Ssam} __packed;
883178676Ssam
884198429Srpaulo/* Structures for command IWN_CMD_SCAN. */
885178676Ssamstruct iwn_scan_essid {
886178676Ssam	uint8_t	id;
887178676Ssam	uint8_t	len;
888178676Ssam	uint8_t	data[IEEE80211_NWID_LEN];
889178676Ssam} __packed;
890178676Ssam
891178676Ssamstruct iwn_scan_hdr {
892178676Ssam	uint16_t	len;
893258117Sadrian	uint8_t		scan_flags;
894178676Ssam	uint8_t		nchan;
895198429Srpaulo	uint16_t	quiet_time;
896198429Srpaulo	uint16_t	quiet_threshold;
897178676Ssam	uint16_t	crc_threshold;
898178676Ssam	uint16_t	rxchain;
899178676Ssam	uint32_t	max_svc;	/* background scans */
900178676Ssam	uint32_t	pause_svc;	/* background scans */
901178676Ssam	uint32_t	flags;
902178676Ssam	uint32_t	filter;
903178676Ssam
904198429Srpaulo	/* Followed by a struct iwn_cmd_data. */
905198429Srpaulo	/* Followed by an array of 20 structs iwn_scan_essid. */
906198429Srpaulo	/* Followed by probe request body. */
907198429Srpaulo	/* Followed by an array of ``nchan'' structs iwn_scan_chan. */
908178676Ssam} __packed;
909178676Ssam
910178676Ssamstruct iwn_scan_chan {
911198429Srpaulo	uint32_t	flags;
912253898Sadrian#define	IWN_CHAN_PASSIVE	(0 << 0)
913198429Srpaulo#define IWN_CHAN_ACTIVE		(1 << 0)
914198429Srpaulo#define IWN_CHAN_NPBREQS(x)	(((1 << (x)) - 1) << 1)
915178676Ssam
916198429Srpaulo	uint16_t	chan;
917178676Ssam	uint8_t		rf_gain;
918178676Ssam	uint8_t		dsp_gain;
919178676Ssam	uint16_t	active;		/* msecs */
920178676Ssam	uint16_t	passive;	/* msecs */
921178676Ssam} __packed;
922178676Ssam
923253898Sadrian#define	IWN_SCAN_CRC_TH_DISABLED	0
924253898Sadrian#define	IWN_SCAN_CRC_TH_DEFAULT		htole16(1)
925253898Sadrian#define	IWN_SCAN_CRC_TH_NEVER		htole16(0xffff)
926253898Sadrian
927198429Srpaulo/* Maximum size of a scan command. */
928198429Srpaulo#define IWN_SCAN_MAXSZ	(MCLBYTES - 4)
929198429Srpaulo
930258829Sadrian/*
931258829Sadrian * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
932258829Sadrian * sending probe req.  This should be set long enough to hear probe responses
933258829Sadrian * from more than one AP.
934258829Sadrian */
935258829Sadrian#define	IWN_ACTIVE_DWELL_TIME_2GHZ	(30)	/* all times in msec */
936258829Sadrian#define	IWN_ACTIVE_DWELL_TIME_5GHZ	(20)
937258829Sadrian#define	IWN_ACTIVE_DWELL_FACTOR_2GHZ	(3)
938258829Sadrian#define	IWN_ACTIVE_DWELL_FACTOR_5GHZ	(2)
939253898Sadrian
940258829Sadrian/*
941258829Sadrian * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
942258829Sadrian * Must be set longer than active dwell time.
943258829Sadrian * For the most reliable scan, set > AP beacon interval (typically 100msec).
944258829Sadrian */
945258829Sadrian#define	IWN_PASSIVE_DWELL_TIME_2GHZ	(20)	/* all times in msec */