if_alc.c revision 211052
1/*-
2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice unmodified, this list of conditions, and the following
10 *    disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/alc/if_alc.c 211052 2010-08-08 00:23:36Z yongari $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/endian.h>
37#include <sys/kernel.h>
38#include <sys/lock.h>
39#include <sys/malloc.h>
40#include <sys/mbuf.h>
41#include <sys/module.h>
42#include <sys/mutex.h>
43#include <sys/rman.h>
44#include <sys/queue.h>
45#include <sys/socket.h>
46#include <sys/sockio.h>
47#include <sys/sysctl.h>
48#include <sys/taskqueue.h>
49
50#include <net/bpf.h>
51#include <net/if.h>
52#include <net/if_arp.h>
53#include <net/ethernet.h>
54#include <net/if_dl.h>
55#include <net/if_llc.h>
56#include <net/if_media.h>
57#include <net/if_types.h>
58#include <net/if_vlan_var.h>
59
60#include <netinet/in.h>
61#include <netinet/in_systm.h>
62#include <netinet/ip.h>
63#include <netinet/tcp.h>
64
65#include <dev/mii/mii.h>
66#include <dev/mii/miivar.h>
67
68#include <dev/pci/pcireg.h>
69#include <dev/pci/pcivar.h>
70
71#include <machine/atomic.h>
72#include <machine/bus.h>
73#include <machine/in_cksum.h>
74
75#include <dev/alc/if_alcreg.h>
76#include <dev/alc/if_alcvar.h>
77
78/* "device miibus" required.  See GENERIC if you get errors here. */
79#include "miibus_if.h"
80#undef ALC_USE_CUSTOM_CSUM
81
82#ifdef ALC_USE_CUSTOM_CSUM
83#define	ALC_CSUM_FEATURES	(CSUM_TCP | CSUM_UDP)
84#else
85#define	ALC_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
86#endif
87
88MODULE_DEPEND(alc, pci, 1, 1, 1);
89MODULE_DEPEND(alc, ether, 1, 1, 1);
90MODULE_DEPEND(alc, miibus, 1, 1, 1);
91
92/* Tunables. */
93static int msi_disable = 0;
94static int msix_disable = 0;
95TUNABLE_INT("hw.alc.msi_disable", &msi_disable);
96TUNABLE_INT("hw.alc.msix_disable", &msix_disable);
97
98/*
99 * Devices supported by this driver.
100 */
101static struct alc_dev {
102	uint16_t	alc_vendorid;
103	uint16_t	alc_deviceid;
104	const char	*alc_name;
105} alc_devs[] = {
106	{ VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131,
107		"Atheros AR8131 PCIe Gigabit Ethernet" },
108	{ VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132,
109		"Atheros AR8132 PCIe Fast Ethernet" }
110};
111
112static void	alc_aspm(struct alc_softc *);
113static int	alc_attach(device_t);
114static int	alc_check_boundary(struct alc_softc *);
115static int	alc_detach(device_t);
116static void	alc_disable_l0s_l1(struct alc_softc *);
117static int	alc_dma_alloc(struct alc_softc *);
118static void	alc_dma_free(struct alc_softc *);
119static void	alc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
120static int	alc_encap(struct alc_softc *, struct mbuf **);
121#ifndef __NO_STRICT_ALIGNMENT
122static struct mbuf *
123		alc_fixup_rx(struct ifnet *, struct mbuf *);
124#endif
125static void	alc_get_macaddr(struct alc_softc *);
126static void	alc_init(void *);
127static void	alc_init_cmb(struct alc_softc *);
128static void	alc_init_locked(struct alc_softc *);
129static void	alc_init_rr_ring(struct alc_softc *);
130static int	alc_init_rx_ring(struct alc_softc *);
131static void	alc_init_smb(struct alc_softc *);
132static void	alc_init_tx_ring(struct alc_softc *);
133static void	alc_int_task(void *, int);
134static int	alc_intr(void *);
135static int	alc_ioctl(struct ifnet *, u_long, caddr_t);
136static void	alc_mac_config(struct alc_softc *);
137static int	alc_miibus_readreg(device_t, int, int);
138static void	alc_miibus_statchg(device_t);
139static int	alc_miibus_writereg(device_t, int, int, int);
140static int	alc_mediachange(struct ifnet *);
141static void	alc_mediastatus(struct ifnet *, struct ifmediareq *);
142static int	alc_newbuf(struct alc_softc *, struct alc_rxdesc *);
143static void	alc_phy_down(struct alc_softc *);
144static void	alc_phy_reset(struct alc_softc *);
145static int	alc_probe(device_t);
146static void	alc_reset(struct alc_softc *);
147static int	alc_resume(device_t);
148static void	alc_rxeof(struct alc_softc *, struct rx_rdesc *);
149static int	alc_rxintr(struct alc_softc *, int);
150static void	alc_rxfilter(struct alc_softc *);
151static void	alc_rxvlan(struct alc_softc *);
152static void	alc_setlinkspeed(struct alc_softc *);
153static void	alc_setwol(struct alc_softc *);
154static int	alc_shutdown(device_t);
155static void	alc_start(struct ifnet *);
156static void	alc_start_queue(struct alc_softc *);
157static void	alc_stats_clear(struct alc_softc *);
158static void	alc_stats_update(struct alc_softc *);
159static void	alc_stop(struct alc_softc *);
160static void	alc_stop_mac(struct alc_softc *);
161static void	alc_stop_queue(struct alc_softc *);
162static int	alc_suspend(device_t);
163static void	alc_sysctl_node(struct alc_softc *);
164static void	alc_tick(void *);
165static void	alc_tx_task(void *, int);
166static void	alc_txeof(struct alc_softc *);
167static void	alc_watchdog(struct alc_softc *);
168static int	sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
169static int	sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS);
170static int	sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS);
171
172static device_method_t alc_methods[] = {
173	/* Device interface. */
174	DEVMETHOD(device_probe,		alc_probe),
175	DEVMETHOD(device_attach,	alc_attach),
176	DEVMETHOD(device_detach,	alc_detach),
177	DEVMETHOD(device_shutdown,	alc_shutdown),
178	DEVMETHOD(device_suspend,	alc_suspend),
179	DEVMETHOD(device_resume,	alc_resume),
180
181	/* MII interface. */
182	DEVMETHOD(miibus_readreg,	alc_miibus_readreg),
183	DEVMETHOD(miibus_writereg,	alc_miibus_writereg),
184	DEVMETHOD(miibus_statchg,	alc_miibus_statchg),
185
186	{ NULL, NULL }
187};
188
189static driver_t alc_driver = {
190	"alc",
191	alc_methods,
192	sizeof(struct alc_softc)
193};
194
195static devclass_t alc_devclass;
196
197DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0);
198DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0);
199
200static struct resource_spec alc_res_spec_mem[] = {
201	{ SYS_RES_MEMORY,	PCIR_BAR(0),	RF_ACTIVE },
202	{ -1,			0,		0 }
203};
204
205static struct resource_spec alc_irq_spec_legacy[] = {
206	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
207	{ -1,			0,		0 }
208};
209
210static struct resource_spec alc_irq_spec_msi[] = {
211	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
212	{ -1,			0,		0 }
213};
214
215static struct resource_spec alc_irq_spec_msix[] = {
216	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
217	{ -1,			0,		0 }
218};
219
220static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 };
221
222static int
223alc_miibus_readreg(device_t dev, int phy, int reg)
224{
225	struct alc_softc *sc;
226	uint32_t v;
227	int i;
228
229	sc = device_get_softc(dev);
230
231	if (phy != sc->alc_phyaddr)
232		return (0);
233
234	/*
235	 * For AR8132 fast ethernet controller, do not report 1000baseT
236	 * capability to mii(4). Even though AR8132 uses the same
237	 * model/revision number of F1 gigabit PHY, the PHY has no
238	 * ability to establish 1000baseT link.
239	 */
240	if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 &&
241	    reg == MII_EXTSR)
242		return (0);
243
244	CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
245	    MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
246	for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
247		DELAY(5);
248		v = CSR_READ_4(sc, ALC_MDIO);
249		if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
250			break;
251	}
252
253	if (i == 0) {
254		device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
255		return (0);
256	}
257
258	return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
259}
260
261static int
262alc_miibus_writereg(device_t dev, int phy, int reg, int val)
263{
264	struct alc_softc *sc;
265	uint32_t v;
266	int i;
267
268	sc = device_get_softc(dev);
269
270	if (phy != sc->alc_phyaddr)
271		return (0);
272
273	CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
274	    (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
275	    MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
276	for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
277		DELAY(5);
278		v = CSR_READ_4(sc, ALC_MDIO);
279		if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
280			break;
281	}
282
283	if (i == 0)
284		device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
285
286	return (0);
287}
288
289static void
290alc_miibus_statchg(device_t dev)
291{
292	struct alc_softc *sc;
293	struct mii_data *mii;
294	struct ifnet *ifp;
295	uint32_t reg;
296
297	sc = device_get_softc(dev);
298
299	mii = device_get_softc(sc->alc_miibus);
300	ifp = sc->alc_ifp;
301	if (mii == NULL || ifp == NULL ||
302	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
303		return;
304
305	sc->alc_flags &= ~ALC_FLAG_LINK;
306	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
307	    (IFM_ACTIVE | IFM_AVALID)) {
308		switch (IFM_SUBTYPE(mii->mii_media_active)) {
309		case IFM_10_T:
310		case IFM_100_TX:
311			sc->alc_flags |= ALC_FLAG_LINK;
312			break;
313		case IFM_1000_T:
314			if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
315				sc->alc_flags |= ALC_FLAG_LINK;
316			break;
317		default:
318			break;
319		}
320	}
321	alc_stop_queue(sc);
322	/* Stop Rx/Tx MACs. */
323	alc_stop_mac(sc);
324
325	/* Program MACs with resolved speed/duplex/flow-control. */
326	if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
327		alc_start_queue(sc);
328		alc_mac_config(sc);
329		/* Re-enable Tx/Rx MACs. */
330		reg = CSR_READ_4(sc, ALC_MAC_CFG);
331		reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
332		CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
333	}
334	alc_aspm(sc);
335}
336
337static void
338alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
339{
340	struct alc_softc *sc;
341	struct mii_data *mii;
342
343	sc = ifp->if_softc;
344	ALC_LOCK(sc);
345	if ((ifp->if_flags & IFF_UP) == 0) {
346		ALC_UNLOCK(sc);
347		return;
348	}
349	mii = device_get_softc(sc->alc_miibus);
350
351	mii_pollstat(mii);
352	ALC_UNLOCK(sc);
353	ifmr->ifm_status = mii->mii_media_status;
354	ifmr->ifm_active = mii->mii_media_active;
355}
356
357static int
358alc_mediachange(struct ifnet *ifp)
359{
360	struct alc_softc *sc;
361	struct mii_data *mii;
362	struct mii_softc *miisc;
363	int error;
364
365	sc = ifp->if_softc;
366	ALC_LOCK(sc);
367	mii = device_get_softc(sc->alc_miibus);
368	if (mii->mii_instance != 0) {
369		LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
370			mii_phy_reset(miisc);
371	}
372	error = mii_mediachg(mii);
373	ALC_UNLOCK(sc);
374
375	return (error);
376}
377
378static int
379alc_probe(device_t dev)
380{
381	struct alc_dev *sp;
382	int i;
383	uint16_t vendor, devid;
384
385	vendor = pci_get_vendor(dev);
386	devid = pci_get_device(dev);
387	sp = alc_devs;
388	for (i = 0; i < sizeof(alc_devs) / sizeof(alc_devs[0]); i++) {
389		if (vendor == sp->alc_vendorid &&
390		    devid == sp->alc_deviceid) {
391			device_set_desc(dev, sp->alc_name);
392			return (BUS_PROBE_DEFAULT);
393		}
394		sp++;
395	}
396
397	return (ENXIO);
398}
399
400static void
401alc_get_macaddr(struct alc_softc *sc)
402{
403	uint32_t ea[2], opt;
404	int i;
405
406	opt = CSR_READ_4(sc, ALC_OPT_CFG);
407	if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
408		/*
409		 * EEPROM found, let TWSI reload EEPROM configuration.
410		 * This will set ethernet address of controller.
411		 */
412		if ((opt & OPT_CFG_CLK_ENB) == 0) {
413			opt |= OPT_CFG_CLK_ENB;
414			CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
415			CSR_READ_4(sc, ALC_OPT_CFG);
416			DELAY(1000);
417		}
418		CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
419		    TWSI_CFG_SW_LD_START);
420		for (i = 100; i > 0; i--) {
421			DELAY(1000);
422			if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
423			    TWSI_CFG_SW_LD_START) == 0)
424				break;
425		}
426		if (i == 0)
427			device_printf(sc->alc_dev,
428			    "reloading EEPROM timeout!\n");
429	} else {
430		if (bootverbose)
431			device_printf(sc->alc_dev, "EEPROM not found!\n");
432	}
433	if ((opt & OPT_CFG_CLK_ENB) != 0) {
434		opt &= ~OPT_CFG_CLK_ENB;
435		CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
436		CSR_READ_4(sc, ALC_OPT_CFG);
437		DELAY(1000);
438	}
439
440	ea[0] = CSR_READ_4(sc, ALC_PAR0);
441	ea[1] = CSR_READ_4(sc, ALC_PAR1);
442	sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
443	sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
444	sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
445	sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
446	sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
447	sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
448}
449
450static void
451alc_disable_l0s_l1(struct alc_softc *sc)
452{
453	uint32_t pmcfg;
454
455	/* Another magic from vendor. */
456	pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
457	pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
458	    PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK |
459	    PM_CFG_SERDES_PD_EX_L1);
460	pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
461	    PM_CFG_SERDES_L1_ENB;
462	CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
463}
464
465static void
466alc_phy_reset(struct alc_softc *sc)
467{
468	uint16_t data;
469
470	/* Reset magic from Linux. */
471	CSR_WRITE_2(sc, ALC_GPHY_CFG,
472	    GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET);
473	CSR_READ_2(sc, ALC_GPHY_CFG);
474	DELAY(10 * 1000);
475
476	CSR_WRITE_2(sc, ALC_GPHY_CFG,
477	    GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
478	    GPHY_CFG_SEL_ANA_RESET);
479	CSR_READ_2(sc, ALC_GPHY_CFG);
480	DELAY(10 * 1000);
481
482	/* Load DSP codes, vendor magic. */
483	data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
484	    ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
485	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
486	    ALC_MII_DBG_ADDR, MII_ANA_CFG18);
487	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
488	    ALC_MII_DBG_DATA, data);
489
490	data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) |
491	    ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
492	    ANA_SERDES_EN_LCKDT;
493	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
494	    ALC_MII_DBG_ADDR, MII_ANA_CFG5);
495	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
496	    ALC_MII_DBG_DATA, data);
497
498	data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) &
499	    ANA_LONG_CABLE_TH_100_MASK) |
500	    ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) &
501	    ANA_SHORT_CABLE_TH_100_SHIFT) |
502	    ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW;
503	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
504	    ALC_MII_DBG_ADDR, MII_ANA_CFG54);
505	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
506	    ALC_MII_DBG_DATA, data);
507
508	data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) |
509	    ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) |
510	    ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) |
511	    ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK);
512	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
513	    ALC_MII_DBG_ADDR, MII_ANA_CFG4);
514	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
515	    ALC_MII_DBG_DATA, data);
516
517	data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) |
518	    ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB |
519	    ANA_OEN_125M;
520	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
521	    ALC_MII_DBG_ADDR, MII_ANA_CFG0);
522	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
523	    ALC_MII_DBG_DATA, data);
524	DELAY(1000);
525}
526
527static void
528alc_phy_down(struct alc_softc *sc)
529{
530
531	/* Force PHY down. */
532	CSR_WRITE_2(sc, ALC_GPHY_CFG,
533	    GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
534	    GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW);
535	DELAY(1000);
536}
537
538static void
539alc_aspm(struct alc_softc *sc)
540{
541	uint32_t pmcfg;
542
543	ALC_LOCK_ASSERT(sc);
544
545	pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
546	pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
547	pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB;
548	pmcfg |= PM_CFG_SERDES_L1_ENB;
549	pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
550	pmcfg |= PM_CFG_MAC_ASPM_CHK;
551	if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
552		pmcfg |= PM_CFG_SERDES_PLL_L1_ENB;
553		pmcfg &= ~PM_CFG_CLK_SWH_L1;
554		pmcfg &= ~PM_CFG_ASPM_L1_ENB;
555		pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
556	} else {
557		pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB;
558		pmcfg |= PM_CFG_CLK_SWH_L1;
559		pmcfg &= ~PM_CFG_ASPM_L1_ENB;
560		pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
561	}
562	CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
563}
564
565static int
566alc_attach(device_t dev)
567{
568	struct alc_softc *sc;
569	struct ifnet *ifp;
570	char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" };
571	uint16_t burst;
572	int base, error, i, msic, msixc, pmc, state;
573	uint32_t cap, ctl, val;
574
575	error = 0;
576	sc = device_get_softc(dev);
577	sc->alc_dev = dev;
578
579	mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
580	    MTX_DEF);
581	callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0);
582	TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc);
583
584	/* Map the device. */
585	pci_enable_busmaster(dev);
586	sc->alc_res_spec = alc_res_spec_mem;
587	sc->alc_irq_spec = alc_irq_spec_legacy;
588	error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res);
589	if (error != 0) {
590		device_printf(dev, "cannot allocate memory resources.\n");
591		goto fail;
592	}
593
594	/* Set PHY address. */
595	sc->alc_phyaddr = ALC_PHY_ADDR;
596
597	/* Initialize DMA parameters. */
598	sc->alc_dma_rd_burst = 0;
599	sc->alc_dma_wr_burst = 0;
600	sc->alc_rcb = DMA_CFG_RCB_64;
601	if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) {
602		sc->alc_flags |= ALC_FLAG_PCIE;
603		burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL);
604		sc->alc_dma_rd_burst =
605		    (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12;
606		sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5;
607		if (bootverbose) {
608			device_printf(dev, "Read request size : %u bytes.\n",
609			    alc_dma_burst[sc->alc_dma_rd_burst]);
610			device_printf(dev, "TLP payload size : %u bytes.\n",
611			    alc_dma_burst[sc->alc_dma_wr_burst]);
612		}
613		if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
614			sc->alc_dma_rd_burst = 3;
615		if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
616			sc->alc_dma_wr_burst = 3;
617		/* Clear data link and flow-control protocol error. */
618		val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
619		val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
620		CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
621		/* Disable ASPM L0S and L1. */
622		cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP);
623		if ((cap & PCIM_LINK_CAP_ASPM) != 0) {
624			ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL);
625			if ((ctl & 0x08) != 0)
626				sc->alc_rcb = DMA_CFG_RCB_128;
627			if (bootverbose)
628				device_printf(dev, "RCB %u bytes\n",
629				    sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
630			state = ctl & 0x03;
631			if (bootverbose)
632				device_printf(sc->alc_dev, "ASPM %s %s\n",
633				    aspm_state[state],
634				    state == 0 ? "disabled" : "enabled");
635			if (state != 0)
636				alc_disable_l0s_l1(sc);
637		}
638	}
639
640	/* Reset PHY. */
641	alc_phy_reset(sc);
642
643	/* Reset the ethernet controller. */
644	alc_reset(sc);
645
646	/*
647	 * One odd thing is AR8132 uses the same PHY hardware(F1
648	 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
649	 * the PHY supports 1000Mbps but that's not true. The PHY
650	 * used in AR8132 can't establish gigabit link even if it
651	 * shows the same PHY model/revision number of AR8131.
652	 */
653	if (pci_get_device(dev) == DEVICEID_ATHEROS_AR8132)
654		sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO;
655	else
656		sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON;
657	/*
658	 * It seems that AR8131/AR8132 has silicon bug for SMB. In
659	 * addition, Atheros said that enabling SMB wouldn't improve
660	 * performance. However I think it's bad to access lots of
661	 * registers to extract MAC statistics.
662	 */
663	sc->alc_flags |= ALC_FLAG_SMB_BUG;
664	/*
665	 * Don't use Tx CMB. It is known to have silicon bug.
666	 */
667	sc->alc_flags |= ALC_FLAG_CMB_BUG;
668	sc->alc_rev = pci_get_revid(dev);
669	sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
670	    MASTER_CHIP_REV_SHIFT;
671	if (bootverbose) {
672		device_printf(dev, "PCI device revision : 0x%04x\n",
673		    sc->alc_rev);
674		device_printf(dev, "Chip id/revision : 0x%04x\n",
675		    sc->alc_chip_rev);
676	}
677	device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n",
678	    CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
679	    CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
680
681	/* Allocate IRQ resources. */
682	msixc = pci_msix_count(dev);
683	msic = pci_msi_count(dev);
684	if (bootverbose) {
685		device_printf(dev, "MSIX count : %d\n", msixc);
686		device_printf(dev, "MSI count : %d\n", msic);
687	}
688	/* Prefer MSIX over MSI. */
689	if (msix_disable == 0 || msi_disable == 0) {
690		if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES &&
691		    pci_alloc_msix(dev, &msixc) == 0) {
692			if (msic == ALC_MSIX_MESSAGES) {
693				device_printf(dev,
694				    "Using %d MSIX message(s).\n", msixc);
695				sc->alc_flags |= ALC_FLAG_MSIX;
696				sc->alc_irq_spec = alc_irq_spec_msix;
697			} else
698				pci_release_msi(dev);
699		}
700		if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 &&
701		    msic == ALC_MSI_MESSAGES &&
702		    pci_alloc_msi(dev, &msic) == 0) {
703			if (msic == ALC_MSI_MESSAGES) {
704				device_printf(dev,
705				    "Using %d MSI message(s).\n", msic);
706				sc->alc_flags |= ALC_FLAG_MSI;
707				sc->alc_irq_spec = alc_irq_spec_msi;
708			} else
709				pci_release_msi(dev);
710		}
711	}
712
713	error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq);
714	if (error != 0) {
715		device_printf(dev, "cannot allocate IRQ resources.\n");
716		goto fail;
717	}
718
719	/* Create device sysctl node. */
720	alc_sysctl_node(sc);
721
722	if ((error = alc_dma_alloc(sc) != 0))
723		goto fail;
724
725	/* Load station address. */
726	alc_get_macaddr(sc);
727
728	ifp = sc->alc_ifp = if_alloc(IFT_ETHER);
729	if (ifp == NULL) {
730		device_printf(dev, "cannot allocate ifnet structure.\n");
731		error = ENXIO;
732		goto fail;
733	}
734
735	ifp->if_softc = sc;
736	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
737	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
738	ifp->if_ioctl = alc_ioctl;
739	ifp->if_start = alc_start;
740	ifp->if_init = alc_init;
741	ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1;
742	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
743	IFQ_SET_READY(&ifp->if_snd);
744	ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
745	ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO;
746	if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
747		ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
748	ifp->if_capenable = ifp->if_capabilities;
749
750	/* Set up MII bus. */
751	if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange,
752	    alc_mediastatus)) != 0) {
753		device_printf(dev, "no PHY found!\n");
754		goto fail;
755	}
756
757	ether_ifattach(ifp, sc->alc_eaddr);
758
759	/* VLAN capability setup. */
760	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
761	    IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
762	ifp->if_capenable = ifp->if_capabilities;
763	/*
764	 * XXX
765	 * It seems enabling Tx checksum offloading makes more trouble.
766	 * Sometimes the controller does not receive any frames when
767	 * Tx checksum offloading is enabled. I'm not sure whether this
768	 * is a bug in Tx checksum offloading logic or I got broken
769	 * sample boards. To safety, don't enable Tx checksum offloading
770	 * by default but give chance to users to toggle it if they know
771	 * their controllers work without problems.
772	 */
773	ifp->if_capenable &= ~IFCAP_TXCSUM;
774	ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
775
776	/* Tell the upper layer(s) we support long frames. */
777	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
778
779	/* Create local taskq. */
780	TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp);
781	sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK,
782	    taskqueue_thread_enqueue, &sc->alc_tq);
783	if (sc->alc_tq == NULL) {
784		device_printf(dev, "could not create taskqueue.\n");
785		ether_ifdetach(ifp);
786		error = ENXIO;
787		goto fail;
788	}
789	taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq",
790	    device_get_nameunit(sc->alc_dev));
791
792	if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
793		msic = ALC_MSIX_MESSAGES;
794	else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
795		msic = ALC_MSI_MESSAGES;
796	else
797		msic = 1;
798	for (i = 0; i < msic; i++) {
799		error = bus_setup_intr(dev, sc->alc_irq[i],
800		    INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc,
801		    &sc->alc_intrhand[i]);
802		if (error != 0)
803			break;
804	}
805	if (error != 0) {
806		device_printf(dev, "could not set up interrupt handler.\n");
807		taskqueue_free(sc->alc_tq);
808		sc->alc_tq = NULL;
809		ether_ifdetach(ifp);
810		goto fail;
811	}
812
813fail:
814	if (error != 0)
815		alc_detach(dev);
816
817	return (error);
818}
819
820static int
821alc_detach(device_t dev)
822{
823	struct alc_softc *sc;
824	struct ifnet *ifp;
825	int i, msic;
826
827	sc = device_get_softc(dev);
828
829	ifp = sc->alc_ifp;
830	if (device_is_attached(dev)) {
831		ALC_LOCK(sc);
832		sc->alc_flags |= ALC_FLAG_DETACH;
833		alc_stop(sc);
834		ALC_UNLOCK(sc);
835		callout_drain(&sc->alc_tick_ch);
836		taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
837		taskqueue_drain(sc->alc_tq, &sc->alc_tx_task);
838		ether_ifdetach(ifp);
839	}
840
841	if (sc->alc_tq != NULL) {
842		taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
843		taskqueue_free(sc->alc_tq);
844		sc->alc_tq = NULL;
845	}
846
847	if (sc->alc_miibus != NULL) {
848		device_delete_child(dev, sc->alc_miibus);
849		sc->alc_miibus = NULL;
850	}
851	bus_generic_detach(dev);
852	alc_dma_free(sc);
853
854	if (ifp != NULL) {
855		if_free(ifp);
856		sc->alc_ifp = NULL;
857	}
858
859	if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
860		msic = ALC_MSIX_MESSAGES;
861	else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
862		msic = ALC_MSI_MESSAGES;
863	else
864		msic = 1;
865	for (i = 0; i < msic; i++) {
866		if (sc->alc_intrhand[i] != NULL) {
867			bus_teardown_intr(dev, sc->alc_irq[i],
868			    sc->alc_intrhand[i]);
869			sc->alc_intrhand[i] = NULL;
870		}
871	}
872	if (sc->alc_res[0] != NULL)
873		alc_phy_down(sc);
874	bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq);
875	if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0)
876		pci_release_msi(dev);
877	bus_release_resources(dev, sc->alc_res_spec, sc->alc_res);
878	mtx_destroy(&sc->alc_mtx);
879
880	return (0);
881}
882
883#define	ALC_SYSCTL_STAT_ADD32(c, h, n, p, d)	\
884	    SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
885#define	ALC_SYSCTL_STAT_ADD64(c, h, n, p, d)	\
886	    SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
887
888static void
889alc_sysctl_node(struct alc_softc *sc)
890{
891	struct sysctl_ctx_list *ctx;
892	struct sysctl_oid_list *child, *parent;
893	struct sysctl_oid *tree;
894	struct alc_hw_stats *stats;
895	int error;
896
897	stats = &sc->alc_stats;
898	ctx = device_get_sysctl_ctx(sc->alc_dev);
899	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev));
900
901	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
902	    CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0,
903	    sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation");
904	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
905	    CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0,
906	    sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation");
907	/* Pull in device tunables. */
908	sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
909	error = resource_int_value(device_get_name(sc->alc_dev),
910	    device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod);
911	if (error == 0) {
912		if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN ||
913		    sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) {
914			device_printf(sc->alc_dev, "int_rx_mod value out of "
915			    "range; using default: %d\n",
916			    ALC_IM_RX_TIMER_DEFAULT);
917			sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
918		}
919	}
920	sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
921	error = resource_int_value(device_get_name(sc->alc_dev),
922	    device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod);
923	if (error == 0) {
924		if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN ||
925		    sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) {
926			device_printf(sc->alc_dev, "int_tx_mod value out of "
927			    "range; using default: %d\n",
928			    ALC_IM_TX_TIMER_DEFAULT);
929			sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
930		}
931	}
932	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
933	    CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0,
934	    sysctl_hw_alc_proc_limit, "I",
935	    "max number of Rx events to process");
936	/* Pull in device tunables. */
937	sc->alc_process_limit = ALC_PROC_DEFAULT;
938	error = resource_int_value(device_get_name(sc->alc_dev),
939	    device_get_unit(sc->alc_dev), "process_limit",
940	    &sc->alc_process_limit);
941	if (error == 0) {
942		if (sc->alc_process_limit < ALC_PROC_MIN ||
943		    sc->alc_process_limit > ALC_PROC_MAX) {
944			device_printf(sc->alc_dev,
945			    "process_limit value out of range; "
946			    "using default: %d\n", ALC_PROC_DEFAULT);
947			sc->alc_process_limit = ALC_PROC_DEFAULT;
948		}
949	}
950
951	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
952	    NULL, "ALC statistics");
953	parent = SYSCTL_CHILDREN(tree);
954
955	/* Rx statistics. */
956	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
957	    NULL, "Rx MAC statistics");
958	child = SYSCTL_CHILDREN(tree);
959	ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
960	    &stats->rx_frames, "Good frames");
961	ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
962	    &stats->rx_bcast_frames, "Good broadcast frames");
963	ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
964	    &stats->rx_mcast_frames, "Good multicast frames");
965	ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
966	    &stats->rx_pause_frames, "Pause control frames");
967	ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
968	    &stats->rx_control_frames, "Control frames");
969	ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
970	    &stats->rx_crcerrs, "CRC errors");
971	ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
972	    &stats->rx_lenerrs, "Frames with length mismatched");
973	ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
974	    &stats->rx_bytes, "Good octets");
975	ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
976	    &stats->rx_bcast_bytes, "Good broadcast octets");
977	ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
978	    &stats->rx_mcast_bytes, "Good multicast octets");
979	ALC_SYSCTL_STAT_ADD32(ctx, child, "runts",
980	    &stats->rx_runts, "Too short frames");
981	ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments",
982	    &stats->rx_fragments, "Fragmented frames");
983	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
984	    &stats->rx_pkts_64, "64 bytes frames");
985	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
986	    &stats->rx_pkts_65_127, "65 to 127 bytes frames");
987	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
988	    &stats->rx_pkts_128_255, "128 to 255 bytes frames");
989	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
990	    &stats->rx_pkts_256_511, "256 to 511 bytes frames");
991	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
992	    &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
993	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
994	    &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
995	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
996	    &stats->rx_pkts_1519_max, "1519 to max frames");
997	ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
998	    &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
999	ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1000	    &stats->rx_fifo_oflows, "FIFO overflows");
1001	ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
1002	    &stats->rx_rrs_errs, "Return status write-back errors");
1003	ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
1004	    &stats->rx_alignerrs, "Alignment errors");
1005	ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered",
1006	    &stats->rx_pkts_filtered,
1007	    "Frames dropped due to address filtering");
1008
1009	/* Tx statistics. */
1010	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1011	    NULL, "Tx MAC statistics");
1012	child = SYSCTL_CHILDREN(tree);
1013	ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1014	    &stats->tx_frames, "Good frames");
1015	ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1016	    &stats->tx_bcast_frames, "Good broadcast frames");
1017	ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1018	    &stats->tx_mcast_frames, "Good multicast frames");
1019	ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1020	    &stats->tx_pause_frames, "Pause control frames");
1021	ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1022	    &stats->tx_control_frames, "Control frames");
1023	ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
1024	    &stats->tx_excess_defer, "Frames with excessive derferrals");
1025	ALC_SYSCTL_STAT_ADD32(ctx, child, "defers",
1026	    &stats->tx_excess_defer, "Frames with derferrals");
1027	ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1028	    &stats->tx_bytes, "Good octets");
1029	ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1030	    &stats->tx_bcast_bytes, "Good broadcast octets");
1031	ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1032	    &stats->tx_mcast_bytes, "Good multicast octets");
1033	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1034	    &stats->tx_pkts_64, "64 bytes frames");
1035	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1036	    &stats->tx_pkts_65_127, "65 to 127 bytes frames");
1037	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1038	    &stats->tx_pkts_128_255, "128 to 255 bytes frames");
1039	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1040	    &stats->tx_pkts_256_511, "256 to 511 bytes frames");
1041	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1042	    &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
1043	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1044	    &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
1045	ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1046	    &stats->tx_pkts_1519_max, "1519 to max frames");
1047	ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
1048	    &stats->tx_single_colls, "Single collisions");
1049	ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
1050	    &stats->tx_multi_colls, "Multiple collisions");
1051	ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
1052	    &stats->tx_late_colls, "Late collisions");
1053	ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
1054	    &stats->tx_excess_colls, "Excessive collisions");
1055	ALC_SYSCTL_STAT_ADD32(ctx, child, "abort",
1056	    &stats->tx_abort, "Aborted frames due to Excessive collisions");
1057	ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns",
1058	    &stats->tx_underrun, "FIFO underruns");
1059	ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
1060	    &stats->tx_desc_underrun, "Descriptor write-back errors");
1061	ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1062	    &stats->tx_lenerrs, "Frames with length mismatched");
1063	ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1064	    &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
1065}
1066
1067#undef ALC_SYSCTL_STAT_ADD32
1068#undef ALC_SYSCTL_STAT_ADD64
1069
1070struct alc_dmamap_arg {
1071	bus_addr_t	alc_busaddr;
1072};
1073
1074static void
1075alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1076{
1077	struct alc_dmamap_arg *ctx;
1078
1079	if (error != 0)
1080		return;
1081
1082	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1083
1084	ctx = (struct alc_dmamap_arg *)arg;
1085	ctx->alc_busaddr = segs[0].ds_addr;
1086}
1087
1088/*
1089 * Normal and high Tx descriptors shares single Tx high address.
1090 * Four Rx descriptor/return rings and CMB shares the same Rx
1091 * high address.
1092 */
1093static int
1094alc_check_boundary(struct alc_softc *sc)
1095{
1096	bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end;
1097
1098	rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ;
1099	rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ;
1100	cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ;
1101	tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ;
1102
1103	/* 4GB boundary crossing is not allowed. */
1104	if ((ALC_ADDR_HI(rx_ring_end) !=
1105	    ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) ||
1106	    (ALC_ADDR_HI(rr_ring_end) !=
1107	    ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) ||
1108	    (ALC_ADDR_HI(cmb_end) !=
1109	    ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) ||
1110	    (ALC_ADDR_HI(tx_ring_end) !=
1111	    ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr)))
1112		return (EFBIG);
1113	/*
1114	 * Make sure Rx return descriptor/Rx descriptor/CMB use
1115	 * the same high address.
1116	 */
1117	if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) ||
1118	    (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end)))
1119		return (EFBIG);
1120
1121	return (0);
1122}
1123
1124static int
1125alc_dma_alloc(struct alc_softc *sc)
1126{
1127	struct alc_txdesc *txd;
1128	struct alc_rxdesc *rxd;
1129	bus_addr_t lowaddr;
1130	struct alc_dmamap_arg ctx;
1131	int error, i;
1132
1133	lowaddr = BUS_SPACE_MAXADDR;
1134again:
1135	/* Create parent DMA tag. */
1136	error = bus_dma_tag_create(
1137	    bus_get_dma_tag(sc->alc_dev), /* parent */
1138	    1, 0,			/* alignment, boundary */
1139	    lowaddr,			/* lowaddr */
1140	    BUS_SPACE_MAXADDR,		/* highaddr */
1141	    NULL, NULL,			/* filter, filterarg */
1142	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1143	    0,				/* nsegments */
1144	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1145	    0,				/* flags */
1146	    NULL, NULL,			/* lockfunc, lockarg */
1147	    &sc->alc_cdata.alc_parent_tag);
1148	if (error != 0) {
1149		device_printf(sc->alc_dev,
1150		    "could not create parent DMA tag.\n");
1151		goto fail;
1152	}
1153
1154	/* Create DMA tag for Tx descriptor ring. */
1155	error = bus_dma_tag_create(
1156	    sc->alc_cdata.alc_parent_tag, /* parent */
1157	    ALC_TX_RING_ALIGN, 0,	/* alignment, boundary */
1158	    BUS_SPACE_MAXADDR,		/* lowaddr */
1159	    BUS_SPACE_MAXADDR,		/* highaddr */
1160	    NULL, NULL,			/* filter, filterarg */
1161	    ALC_TX_RING_SZ,		/* maxsize */
1162	    1,				/* nsegments */
1163	    ALC_TX_RING_SZ,		/* maxsegsize */
1164	    0,				/* flags */
1165	    NULL, NULL,			/* lockfunc, lockarg */
1166	    &sc->alc_cdata.alc_tx_ring_tag);
1167	if (error != 0) {
1168		device_printf(sc->alc_dev,
1169		    "could not create Tx ring DMA tag.\n");
1170		goto fail;
1171	}
1172
1173	/* Create DMA tag for Rx free descriptor ring. */
1174	error = bus_dma_tag_create(
1175	    sc->alc_cdata.alc_parent_tag, /* parent */
1176	    ALC_RX_RING_ALIGN, 0,	/* alignment, boundary */
1177	    BUS_SPACE_MAXADDR,		/* lowaddr */
1178	    BUS_SPACE_MAXADDR,		/* highaddr */
1179	    NULL, NULL,			/* filter, filterarg */
1180	    ALC_RX_RING_SZ,		/* maxsize */
1181	    1,				/* nsegments */
1182	    ALC_RX_RING_SZ,		/* maxsegsize */
1183	    0,				/* flags */
1184	    NULL, NULL,			/* lockfunc, lockarg */
1185	    &sc->alc_cdata.alc_rx_ring_tag);
1186	if (error != 0) {
1187		device_printf(sc->alc_dev,
1188		    "could not create Rx ring DMA tag.\n");
1189		goto fail;
1190	}
1191	/* Create DMA tag for Rx return descriptor ring. */
1192	error = bus_dma_tag_create(
1193	    sc->alc_cdata.alc_parent_tag, /* parent */
1194	    ALC_RR_RING_ALIGN, 0,	/* alignment, boundary */
1195	    BUS_SPACE_MAXADDR,		/* lowaddr */
1196	    BUS_SPACE_MAXADDR,		/* highaddr */
1197	    NULL, NULL,			/* filter, filterarg */
1198	    ALC_RR_RING_SZ,		/* maxsize */
1199	    1,				/* nsegments */
1200	    ALC_RR_RING_SZ,		/* maxsegsize */
1201	    0,				/* flags */
1202	    NULL, NULL,			/* lockfunc, lockarg */
1203	    &sc->alc_cdata.alc_rr_ring_tag);
1204	if (error != 0) {
1205		device_printf(sc->alc_dev,
1206		    "could not create Rx return ring DMA tag.\n");
1207		goto fail;
1208	}
1209
1210	/* Create DMA tag for coalescing message block. */
1211	error = bus_dma_tag_create(
1212	    sc->alc_cdata.alc_parent_tag, /* parent */
1213	    ALC_CMB_ALIGN, 0,		/* alignment, boundary */
1214	    BUS_SPACE_MAXADDR,		/* lowaddr */
1215	    BUS_SPACE_MAXADDR,		/* highaddr */
1216	    NULL, NULL,			/* filter, filterarg */
1217	    ALC_CMB_SZ,			/* maxsize */
1218	    1,				/* nsegments */
1219	    ALC_CMB_SZ,			/* maxsegsize */
1220	    0,				/* flags */
1221	    NULL, NULL,			/* lockfunc, lockarg */
1222	    &sc->alc_cdata.alc_cmb_tag);
1223	if (error != 0) {
1224		device_printf(sc->alc_dev,
1225		    "could not create CMB DMA tag.\n");
1226		goto fail;
1227	}
1228	/* Create DMA tag for status message block. */
1229	error = bus_dma_tag_create(
1230	    sc->alc_cdata.alc_parent_tag, /* parent */
1231	    ALC_SMB_ALIGN, 0,		/* alignment, boundary */
1232	    BUS_SPACE_MAXADDR,		/* lowaddr */
1233	    BUS_SPACE_MAXADDR,		/* highaddr */
1234	    NULL, NULL,			/* filter, filterarg */
1235	    ALC_SMB_SZ,			/* maxsize */
1236	    1,				/* nsegments */
1237	    ALC_SMB_SZ,			/* maxsegsize */
1238	    0,				/* flags */
1239	    NULL, NULL,			/* lockfunc, lockarg */
1240	    &sc->alc_cdata.alc_smb_tag);
1241	if (error != 0) {
1242		device_printf(sc->alc_dev,
1243		    "could not create SMB DMA tag.\n");
1244		goto fail;
1245	}
1246
1247	/* Allocate DMA'able memory and load the DMA map for Tx ring. */
1248	error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag,
1249	    (void **)&sc->alc_rdata.alc_tx_ring,
1250	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1251	    &sc->alc_cdata.alc_tx_ring_map);
1252	if (error != 0) {
1253		device_printf(sc->alc_dev,
1254		    "could not allocate DMA'able memory for Tx ring.\n");
1255		goto fail;
1256	}
1257	ctx.alc_busaddr = 0;
1258	error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag,
1259	    sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring,
1260	    ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0);
1261	if (error != 0 || ctx.alc_busaddr == 0) {
1262		device_printf(sc->alc_dev,
1263		    "could not load DMA'able memory for Tx ring.\n");
1264		goto fail;
1265	}
1266	sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr;
1267
1268	/* Allocate DMA'able memory and load the DMA map for Rx ring. */
1269	error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag,
1270	    (void **)&sc->alc_rdata.alc_rx_ring,
1271	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1272	    &sc->alc_cdata.alc_rx_ring_map);
1273	if (error != 0) {
1274		device_printf(sc->alc_dev,
1275		    "could not allocate DMA'able memory for Rx ring.\n");
1276		goto fail;
1277	}
1278	ctx.alc_busaddr = 0;
1279	error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag,
1280	    sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring,
1281	    ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0);
1282	if (error != 0 || ctx.alc_busaddr == 0) {
1283		device_printf(sc->alc_dev,
1284		    "could not load DMA'able memory for Rx ring.\n");
1285		goto fail;
1286	}
1287	sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr;
1288
1289	/* Allocate DMA'able memory and load the DMA map for Rx return ring. */
1290	error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag,
1291	    (void **)&sc->alc_rdata.alc_rr_ring,
1292	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1293	    &sc->alc_cdata.alc_rr_ring_map);
1294	if (error != 0) {
1295		device_printf(sc->alc_dev,
1296		    "could not allocate DMA'able memory for Rx return ring.\n");
1297		goto fail;
1298	}
1299	ctx.alc_busaddr = 0;
1300	error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag,
1301	    sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring,
1302	    ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0);
1303	if (error != 0 || ctx.alc_busaddr == 0) {
1304		device_printf(sc->alc_dev,
1305		    "could not load DMA'able memory for Tx ring.\n");
1306		goto fail;
1307	}
1308	sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr;
1309
1310	/* Allocate DMA'able memory and load the DMA map for CMB. */
1311	error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag,
1312	    (void **)&sc->alc_rdata.alc_cmb,
1313	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1314	    &sc->alc_cdata.alc_cmb_map);
1315	if (error != 0) {
1316		device_printf(sc->alc_dev,
1317		    "could not allocate DMA'able memory for CMB.\n");
1318		goto fail;
1319	}
1320	ctx.alc_busaddr = 0;
1321	error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag,
1322	    sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb,
1323	    ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0);
1324	if (error != 0 || ctx.alc_busaddr == 0) {
1325		device_printf(sc->alc_dev,
1326		    "could not load DMA'able memory for CMB.\n");
1327		goto fail;
1328	}
1329	sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr;
1330
1331	/* Allocate DMA'able memory and load the DMA map for SMB. */
1332	error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag,
1333	    (void **)&sc->alc_rdata.alc_smb,
1334	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1335	    &sc->alc_cdata.alc_smb_map);
1336	if (error != 0) {
1337		device_printf(sc->alc_dev,
1338		    "could not allocate DMA'able memory for SMB.\n");
1339		goto fail;
1340	}
1341	ctx.alc_busaddr = 0;
1342	error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag,
1343	    sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb,
1344	    ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0);
1345	if (error != 0 || ctx.alc_busaddr == 0) {
1346		device_printf(sc->alc_dev,
1347		    "could not load DMA'able memory for CMB.\n");
1348		goto fail;
1349	}
1350	sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr;
1351
1352	/* Make sure we've not crossed 4GB boundary. */
1353	if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1354	    (error = alc_check_boundary(sc)) != 0) {
1355		device_printf(sc->alc_dev, "4GB boundary crossed, "
1356		    "switching to 32bit DMA addressing mode.\n");
1357		alc_dma_free(sc);
1358		/*
1359		 * Limit max allowable DMA address space to 32bit
1360		 * and try again.
1361		 */
1362		lowaddr = BUS_SPACE_MAXADDR_32BIT;
1363		goto again;
1364	}
1365
1366	/*
1367	 * Create Tx buffer parent tag.
1368	 * AR8131/AR8132 allows 64bit DMA addressing of Tx/Rx buffers
1369	 * so it needs separate parent DMA tag as parent DMA address
1370	 * space could be restricted to be within 32bit address space
1371	 * by 4GB boundary crossing.
1372	 */
1373	error = bus_dma_tag_create(
1374	    bus_get_dma_tag(sc->alc_dev), /* parent */
1375	    1, 0,			/* alignment, boundary */
1376	    BUS_SPACE_MAXADDR,		/* lowaddr */
1377	    BUS_SPACE_MAXADDR,		/* highaddr */
1378	    NULL, NULL,			/* filter, filterarg */
1379	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1380	    0,				/* nsegments */
1381	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1382	    0,				/* flags */
1383	    NULL, NULL,			/* lockfunc, lockarg */
1384	    &sc->alc_cdata.alc_buffer_tag);
1385	if (error != 0) {
1386		device_printf(sc->alc_dev,
1387		    "could not create parent buffer DMA tag.\n");
1388		goto fail;
1389	}
1390
1391	/* Create DMA tag for Tx buffers. */
1392	error = bus_dma_tag_create(
1393	    sc->alc_cdata.alc_buffer_tag, /* parent */
1394	    1, 0,			/* alignment, boundary */
1395	    BUS_SPACE_MAXADDR,		/* lowaddr */
1396	    BUS_SPACE_MAXADDR,		/* highaddr */
1397	    NULL, NULL,			/* filter, filterarg */
1398	    ALC_TSO_MAXSIZE,		/* maxsize */
1399	    ALC_MAXTXSEGS,		/* nsegments */
1400	    ALC_TSO_MAXSEGSIZE,		/* maxsegsize */
1401	    0,				/* flags */
1402	    NULL, NULL,			/* lockfunc, lockarg */
1403	    &sc->alc_cdata.alc_tx_tag);
1404	if (error != 0) {
1405		device_printf(sc->alc_dev, "could not create Tx DMA tag.\n");
1406		goto fail;
1407	}
1408
1409	/* Create DMA tag for Rx buffers. */
1410	error = bus_dma_tag_create(
1411	    sc->alc_cdata.alc_buffer_tag, /* parent */
1412	    ALC_RX_BUF_ALIGN, 0,	/* alignment, boundary */
1413	    BUS_SPACE_MAXADDR,		/* lowaddr */
1414	    BUS_SPACE_MAXADDR,		/* highaddr */
1415	    NULL, NULL,			/* filter, filterarg */
1416	    MCLBYTES,			/* maxsize */
1417	    1,				/* nsegments */
1418	    MCLBYTES,			/* maxsegsize */
1419	    0,				/* flags */
1420	    NULL, NULL,			/* lockfunc, lockarg */
1421	    &sc->alc_cdata.alc_rx_tag);
1422	if (error != 0) {
1423		device_printf(sc->alc_dev, "could not create Rx DMA tag.\n");
1424		goto fail;
1425	}
1426	/* Create DMA maps for Tx buffers. */
1427	for (i = 0; i < ALC_TX_RING_CNT; i++) {
1428		txd = &sc->alc_cdata.alc_txdesc[i];
1429		txd->tx_m = NULL;
1430		txd->tx_dmamap = NULL;
1431		error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0,
1432		    &txd->tx_dmamap);
1433		if (error != 0) {
1434			device_printf(sc->alc_dev,
1435			    "could not create Tx dmamap.\n");
1436			goto fail;
1437		}
1438	}
1439	/* Create DMA maps for Rx buffers. */
1440	if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
1441	    &sc->alc_cdata.alc_rx_sparemap)) != 0) {
1442		device_printf(sc->alc_dev,
1443		    "could not create spare Rx dmamap.\n");
1444		goto fail;
1445	}
1446	for (i = 0; i < ALC_RX_RING_CNT; i++) {
1447		rxd = &sc->alc_cdata.alc_rxdesc[i];
1448		rxd->rx_m = NULL;
1449		rxd->rx_dmamap = NULL;
1450		error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
1451		    &rxd->rx_dmamap);
1452		if (error != 0) {
1453			device_printf(sc->alc_dev,
1454			    "could not create Rx dmamap.\n");
1455			goto fail;
1456		}
1457	}
1458
1459fail:
1460	return (error);
1461}
1462
1463static void
1464alc_dma_free(struct alc_softc *sc)
1465{
1466	struct alc_txdesc *txd;
1467	struct alc_rxdesc *rxd;
1468	int i;
1469
1470	/* Tx buffers. */
1471	if (sc->alc_cdata.alc_tx_tag != NULL) {
1472		for (i = 0; i < ALC_TX_RING_CNT; i++) {
1473			txd = &sc->alc_cdata.alc_txdesc[i];
1474			if (txd->tx_dmamap != NULL) {
1475				bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag,
1476				    txd->tx_dmamap);
1477				txd->tx_dmamap = NULL;
1478			}
1479		}
1480		bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag);
1481		sc->alc_cdata.alc_tx_tag = NULL;
1482	}
1483	/* Rx buffers */
1484	if (sc->alc_cdata.alc_rx_tag != NULL) {
1485		for (i = 0; i < ALC_RX_RING_CNT; i++) {
1486			rxd = &sc->alc_cdata.alc_rxdesc[i];
1487			if (rxd->rx_dmamap != NULL) {
1488				bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
1489				    rxd->rx_dmamap);
1490				rxd->rx_dmamap = NULL;
1491			}
1492		}
1493		if (sc->alc_cdata.alc_rx_sparemap != NULL) {
1494			bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
1495			    sc->alc_cdata.alc_rx_sparemap);
1496			sc->alc_cdata.alc_rx_sparemap = NULL;
1497		}
1498		bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag);
1499		sc->alc_cdata.alc_rx_tag = NULL;
1500	}
1501	/* Tx descriptor ring. */
1502	if (sc->alc_cdata.alc_tx_ring_tag != NULL) {
1503		if (sc->alc_cdata.alc_tx_ring_map != NULL)
1504			bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag,
1505			    sc->alc_cdata.alc_tx_ring_map);
1506		if (sc->alc_cdata.alc_tx_ring_map != NULL &&
1507		    sc->alc_rdata.alc_tx_ring != NULL)
1508			bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag,
1509			    sc->alc_rdata.alc_tx_ring,
1510			    sc->alc_cdata.alc_tx_ring_map);
1511		sc->alc_rdata.alc_tx_ring = NULL;
1512		sc->alc_cdata.alc_tx_ring_map = NULL;
1513		bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag);
1514		sc->alc_cdata.alc_tx_ring_tag = NULL;
1515	}
1516	/* Rx ring. */
1517	if (sc->alc_cdata.alc_rx_ring_tag != NULL) {
1518		if (sc->alc_cdata.alc_rx_ring_map != NULL)
1519			bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag,
1520			    sc->alc_cdata.alc_rx_ring_map);
1521		if (sc->alc_cdata.alc_rx_ring_map != NULL &&
1522		    sc->alc_rdata.alc_rx_ring != NULL)
1523			bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag,
1524			    sc->alc_rdata.alc_rx_ring,
1525			    sc->alc_cdata.alc_rx_ring_map);
1526		sc->alc_rdata.alc_rx_ring = NULL;
1527		sc->alc_cdata.alc_rx_ring_map = NULL;
1528		bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag);
1529		sc->alc_cdata.alc_rx_ring_tag = NULL;
1530	}
1531	/* Rx return ring. */
1532	if (sc->alc_cdata.alc_rr_ring_tag != NULL) {
1533		if (sc->alc_cdata.alc_rr_ring_map != NULL)
1534			bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag,
1535			    sc->alc_cdata.alc_rr_ring_map);
1536		if (sc->alc_cdata.alc_rr_ring_map != NULL &&
1537		    sc->alc_rdata.alc_rr_ring != NULL)
1538			bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag,
1539			    sc->alc_rdata.alc_rr_ring,
1540			    sc->alc_cdata.alc_rr_ring_map);
1541		sc->alc_rdata.alc_rr_ring = NULL;
1542		sc->alc_cdata.alc_rr_ring_map = NULL;
1543		bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag);
1544		sc->alc_cdata.alc_rr_ring_tag = NULL;
1545	}
1546	/* CMB block */
1547	if (sc->alc_cdata.alc_cmb_tag != NULL) {
1548		if (sc->alc_cdata.alc_cmb_map != NULL)
1549			bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag,
1550			    sc->alc_cdata.alc_cmb_map);
1551		if (sc->alc_cdata.alc_cmb_map != NULL &&
1552		    sc->alc_rdata.alc_cmb != NULL)
1553			bus_dmamem_free(sc->alc_cdata.alc_cmb_tag,
1554			    sc->alc_rdata.alc_cmb,
1555			    sc->alc_cdata.alc_cmb_map);
1556		sc->alc_rdata.alc_cmb = NULL;
1557		sc->alc_cdata.alc_cmb_map = NULL;
1558		bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag);
1559		sc->alc_cdata.alc_cmb_tag = NULL;
1560	}
1561	/* SMB block */
1562	if (sc->alc_cdata.alc_smb_tag != NULL) {
1563		if (sc->alc_cdata.alc_smb_map != NULL)
1564			bus_dmamap_unload(sc->alc_cdata.alc_smb_tag,
1565			    sc->alc_cdata.alc_smb_map);
1566		if (sc->alc_cdata.alc_smb_map != NULL &&
1567		    sc->alc_rdata.alc_smb != NULL)
1568			bus_dmamem_free(sc->alc_cdata.alc_smb_tag,
1569			    sc->alc_rdata.alc_smb,
1570			    sc->alc_cdata.alc_smb_map);
1571		sc->alc_rdata.alc_smb = NULL;
1572		sc->alc_cdata.alc_smb_map = NULL;
1573		bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag);
1574		sc->alc_cdata.alc_smb_tag = NULL;
1575	}
1576	if (sc->alc_cdata.alc_buffer_tag != NULL) {
1577		bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag);
1578		sc->alc_cdata.alc_buffer_tag = NULL;
1579	}
1580	if (sc->alc_cdata.alc_parent_tag != NULL) {
1581		bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag);
1582		sc->alc_cdata.alc_parent_tag = NULL;
1583	}
1584}
1585
1586static int
1587alc_shutdown(device_t dev)
1588{
1589
1590	return (alc_suspend(dev));
1591}
1592
1593/*
1594 * Note, this driver resets the link speed to 10/100Mbps by
1595 * restarting auto-negotiation in suspend/shutdown phase but we
1596 * don't know whether that auto-negotiation would succeed or not
1597 * as driver has no control after powering off/suspend operation.
1598 * If the renegotiation fail WOL may not work. Running at 1Gbps
1599 * will draw more power than 375mA at 3.3V which is specified in
1600 * PCI specification and that would result in complete
1601 * shutdowning power to ethernet controller.
1602 *
1603 * TODO
1604 * Save current negotiated media speed/duplex/flow-control to
1605 * softc and restore the same link again after resuming. PHY
1606 * handling such as power down/resetting to 100Mbps may be better
1607 * handled in suspend method in phy driver.
1608 */
1609static void
1610alc_setlinkspeed(struct alc_softc *sc)
1611{
1612	struct mii_data *mii;
1613	int aneg, i;
1614
1615	mii = device_get_softc(sc->alc_miibus);
1616	mii_pollstat(mii);
1617	aneg = 0;
1618	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1619	    (IFM_ACTIVE | IFM_AVALID)) {
1620		switch IFM_SUBTYPE(mii->mii_media_active) {
1621		case IFM_10_T:
1622		case IFM_100_TX:
1623			return;
1624		case IFM_1000_T:
1625			aneg++;
1626			break;
1627		default:
1628			break;
1629		}
1630	}
1631	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0);
1632	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1633	    MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1634	alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1635	    MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1636	DELAY(1000);
1637	if (aneg != 0) {
1638		/*
1639		 * Poll link state until alc(4) get a 10/100Mbps link.
1640		 */
1641		for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1642			mii_pollstat(mii);
1643			if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1644			    == (IFM_ACTIVE | IFM_AVALID)) {
1645				switch (IFM_SUBTYPE(
1646				    mii->mii_media_active)) {
1647				case IFM_10_T:
1648				case IFM_100_TX:
1649					alc_mac_config(sc);
1650					return;
1651				default:
1652					break;
1653				}
1654			}
1655			ALC_UNLOCK(sc);
1656			pause("alclnk", hz);
1657			ALC_LOCK(sc);
1658		}
1659		if (i == MII_ANEGTICKS_GIGE)
1660			device_printf(sc->alc_dev,
1661			    "establishing a link failed, WOL may not work!");
1662	}
1663	/*
1664	 * No link, force MAC to have 100Mbps, full-duplex link.
1665	 * This is the last resort and may/may not work.
1666	 */
1667	mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1668	mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1669	alc_mac_config(sc);
1670}
1671
1672static void
1673alc_setwol(struct alc_softc *sc)
1674{
1675	struct ifnet *ifp;
1676	uint32_t reg, pmcs;
1677	uint16_t pmstat;
1678	int pmc;
1679
1680	ALC_LOCK_ASSERT(sc);
1681
1682	alc_disable_l0s_l1(sc);
1683	ifp = sc->alc_ifp;
1684	if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) != 0) {
1685		/* Disable WOL. */
1686		CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
1687		reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
1688		reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1689		CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1690		/* Force PHY power down. */
1691		alc_phy_down(sc);
1692		CSR_WRITE_4(sc, ALC_MASTER_CFG,
1693		    CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
1694		return;
1695	}
1696
1697	if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1698		if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
1699			alc_setlinkspeed(sc);
1700		CSR_WRITE_4(sc, ALC_MASTER_CFG,
1701		    CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS);
1702	}
1703
1704	pmcs = 0;
1705	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1706		pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1707	CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
1708	reg = CSR_READ_4(sc, ALC_MAC_CFG);
1709	reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1710	    MAC_CFG_BCAST);
1711	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1712		reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1713	if ((ifp->if_capenable & IFCAP_WOL) != 0)
1714		reg |= MAC_CFG_RX_ENB;
1715	CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
1716
1717	reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
1718	reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1719	CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1720	if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1721		/* WOL disabled, PHY power down. */
1722		alc_phy_down(sc);
1723		CSR_WRITE_4(sc, ALC_MASTER_CFG,
1724		    CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
1725	}
1726	/* Request PME. */
1727	pmstat = pci_read_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, 2);
1728	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1729	if ((ifp->if_capenable & IFCAP_WOL) != 0)
1730		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1731	pci_write_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1732}
1733
1734static int
1735alc_suspend(device_t dev)
1736{
1737	struct alc_softc *sc;
1738
1739	sc = device_get_softc(dev);
1740
1741	ALC_LOCK(sc);
1742	alc_stop(sc);
1743	alc_setwol(sc);
1744	ALC_UNLOCK(sc);
1745
1746	return (0);
1747}
1748
1749static int
1750alc_resume(device_t dev)
1751{
1752	struct alc_softc *sc;
1753	struct ifnet *ifp;
1754	int pmc;
1755	uint16_t pmstat;
1756
1757	sc = device_get_softc(dev);
1758
1759	ALC_LOCK(sc);
1760	if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) == 0) {
1761		/* Disable PME and clear PME status. */
1762		pmstat = pci_read_config(sc->alc_dev,
1763		    pmc + PCIR_POWER_STATUS, 2);
1764		if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1765			pmstat &= ~PCIM_PSTAT_PMEENABLE;
1766			pci_write_config(sc->alc_dev,
1767			    pmc + PCIR_POWER_STATUS, pmstat, 2);
1768		}
1769	}
1770	/* Reset PHY. */
1771	alc_phy_reset(sc);
1772	ifp = sc->alc_ifp;
1773	if ((ifp->if_flags & IFF_UP) != 0) {
1774		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1775		alc_init_locked(sc);
1776	}
1777	ALC_UNLOCK(sc);
1778
1779	return (0);
1780}
1781
1782static int
1783alc_encap(struct alc_softc *sc, struct mbuf **m_head)
1784{
1785	struct alc_txdesc *txd, *txd_last;
1786	struct tx_desc *desc;
1787	struct mbuf *m;
1788	struct ip *ip;
1789	struct tcphdr *tcp;
1790	bus_dma_segment_t txsegs[ALC_MAXTXSEGS];
1791	bus_dmamap_t map;
1792	uint32_t cflags, hdrlen, poff, vtag;
1793	int error, idx, nsegs, prod;
1794
1795	ALC_LOCK_ASSERT(sc);
1796
1797	M_ASSERTPKTHDR((*m_head));
1798
1799	m = *m_head;
1800	ip = NULL;
1801	tcp = NULL;
1802	poff = 0;
1803	if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) {
1804		/*
1805		 * AR8131/AR8132 requires offset of TCP/UDP header in its
1806		 * Tx descriptor to perform Tx checksum offloading. TSO
1807		 * also requires TCP header offset and modification of
1808		 * IP/TCP header. This kind of operation takes many CPU
1809		 * cycles on FreeBSD so fast host CPU is required to get
1810		 * smooth TSO performance.
1811		 */
1812
1813		if (M_WRITABLE(m) == 0) {
1814			/* Get a writable copy. */
1815			m = m_dup(*m_head, M_DONTWAIT);
1816			/* Release original mbufs. */
1817			m_freem(*m_head);
1818			if (m == NULL) {
1819				*m_head = NULL;
1820				return (ENOBUFS);
1821			}
1822			*m_head = m;
1823		}
1824
1825		m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
1826		if (m == NULL) {
1827			*m_head = NULL;
1828			return (ENOBUFS);
1829		}
1830		ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
1831		poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
1832		if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1833			m = m_pullup(m, poff + sizeof(struct tcphdr));
1834			if (m == NULL) {
1835				*m_head = NULL;
1836				return (ENOBUFS);
1837			}
1838			tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1839			m = m_pullup(m, poff + (tcp->th_off << 2));
1840			if (m == NULL) {
1841				*m_head = NULL;
1842				return (ENOBUFS);
1843			}
1844			/*
1845			 * Due to strict adherence of Microsoft NDIS
1846			 * Large Send specification, hardware expects
1847			 * a pseudo TCP checksum inserted by upper
1848			 * stack. Unfortunately the pseudo TCP
1849			 * checksum that NDIS refers to does not include
1850			 * TCP payload length so driver should recompute
1851			 * the pseudo checksum here. Hopefully this
1852			 * wouldn't be much burden on modern CPUs.
1853			 *
1854			 * Reset IP checksum and recompute TCP pseudo
1855			 * checksum as NDIS specification said.
1856			 */
1857			ip->ip_sum = 0;
1858			tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1859			    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1860		}
1861		*m_head = m;
1862	}
1863
1864	prod = sc->alc_cdata.alc_tx_prod;
1865	txd = &sc->alc_cdata.alc_txdesc[prod];
1866	txd_last = txd;
1867	map = txd->tx_dmamap;
1868
1869	error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map,
1870	    *m_head, txsegs, &nsegs, 0);
1871	if (error == EFBIG) {
1872		m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS);
1873		if (m == NULL) {
1874			m_freem(*m_head);
1875			*m_head = NULL;
1876			return (ENOMEM);
1877		}
1878		*m_head = m;
1879		error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map,
1880		    *m_head, txsegs, &nsegs, 0);
1881		if (error != 0) {
1882			m_freem(*m_head);
1883			*m_head = NULL;
1884			return (error);
1885		}
1886	} else if (error != 0)
1887		return (error);
1888	if (nsegs == 0) {
1889		m_freem(*m_head);
1890		*m_head = NULL;
1891		return (EIO);
1892	}
1893
1894	/* Check descriptor overrun. */
1895	if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) {
1896		bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map);
1897		return (ENOBUFS);
1898	}
1899	bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE);
1900
1901	m = *m_head;
1902	cflags = TD_ETHERNET;
1903	vtag = 0;
1904	desc = NULL;
1905	idx = 0;
1906	/* Configure VLAN hardware tag insertion. */
1907	if ((m->m_flags & M_VLANTAG) != 0) {
1908		vtag = htons(m->m_pkthdr.ether_vtag);
1909		vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK;
1910		cflags |= TD_INS_VLAN_TAG;
1911	}
1912	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1913		/* Request TSO and set MSS. */
1914		cflags |= TD_TSO | TD_TSO_DESCV1;
1915		cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) &
1916		    TD_MSS_MASK;
1917		/* Set TCP header offset. */
1918		cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) &
1919		    TD_TCPHDR_OFFSET_MASK;
1920		/*
1921		 * AR8131/AR8132 requires the first buffer should
1922		 * only hold IP/TCP header data. Payload should
1923		 * be handled in other descriptors.
1924		 */
1925		hdrlen = poff + (tcp->th_off << 2);
1926		desc = &sc->alc_rdata.alc_tx_ring[prod];
1927		desc->len = htole32(TX_BYTES(hdrlen | vtag));
1928		desc->flags = htole32(cflags);
1929		desc->addr = htole64(txsegs[0].ds_addr);
1930		sc->alc_cdata.alc_tx_cnt++;
1931		ALC_DESC_INC(prod, ALC_TX_RING_CNT);
1932		if (m->m_len - hdrlen > 0) {
1933			/* Handle remaining payload of the first fragment. */
1934			desc = &sc->alc_rdata.alc_tx_ring[prod];
1935			desc->len = htole32(TX_BYTES((m->m_len - hdrlen) |
1936			    vtag));
1937			desc->flags = htole32(cflags);
1938			desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
1939			sc->alc_cdata.alc_tx_cnt++;
1940			ALC_DESC_INC(prod, ALC_TX_RING_CNT);
1941		}
1942		/* Handle remaining fragments. */
1943		idx = 1;
1944	} else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) {
1945		/* Configure Tx checksum offload. */
1946#ifdef ALC_USE_CUSTOM_CSUM
1947		cflags |= TD_CUSTOM_CSUM;
1948		/* Set checksum start offset. */
1949		cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) &
1950		    TD_PLOAD_OFFSET_MASK;
1951		/* Set checksum insertion position of TCP/UDP. */
1952		cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) <<
1953		    TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK;
1954#else
1955		if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1956			cflags |= TD_IPCSUM;
1957		if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1958			cflags |= TD_TCPCSUM;
1959		if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1960			cflags |= TD_UDPCSUM;
1961		/* Set TCP/UDP header offset. */
1962		cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) &
1963		    TD_L4HDR_OFFSET_MASK;
1964#endif
1965	}
1966	for (; idx < nsegs; idx++) {
1967		desc = &sc->alc_rdata.alc_tx_ring[prod];
1968		desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag);
1969		desc->flags = htole32(cflags);
1970		desc->addr = htole64(txsegs[idx].ds_addr);
1971		sc->alc_cdata.alc_tx_cnt++;
1972		ALC_DESC_INC(prod, ALC_TX_RING_CNT);
1973	}
1974	/* Update producer index. */
1975	sc->alc_cdata.alc_tx_prod = prod;
1976
1977	/* Finally set EOP on the last descriptor. */
1978	prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT;
1979	desc = &sc->alc_rdata.alc_tx_ring[prod];
1980	desc->flags |= htole32(TD_EOP);
1981
1982	/* Swap dmamap of the first and the last. */
1983	txd = &sc->alc_cdata.alc_txdesc[prod];
1984	map = txd_last->tx_dmamap;
1985	txd_last->tx_dmamap = txd->tx_dmamap;
1986	txd->tx_dmamap = map;
1987	txd->tx_m = m;
1988
1989	return (0);
1990}
1991
1992static void
1993alc_tx_task(void *arg, int pending)
1994{
1995	struct ifnet *ifp;
1996
1997	ifp = (struct ifnet *)arg;
1998	alc_start(ifp);
1999}
2000
2001static void
2002alc_start(struct ifnet *ifp)
2003{
2004	struct alc_softc *sc;
2005	struct mbuf *m_head;
2006	int enq;
2007
2008	sc = ifp->if_softc;
2009
2010	ALC_LOCK(sc);
2011
2012	/* Reclaim transmitted frames. */
2013	if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
2014		alc_txeof(sc);
2015
2016	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2017	    IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) {
2018		ALC_UNLOCK(sc);
2019		return;
2020	}
2021
2022	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
2023		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2024		if (m_head == NULL)
2025			break;
2026		/*
2027		 * Pack the data into the transmit ring. If we
2028		 * don't have room, set the OACTIVE flag and wait
2029		 * for the NIC to drain the ring.
2030		 */
2031		if (alc_encap(sc, &m_head)) {
2032			if (m_head == NULL)
2033				break;
2034			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2035			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2036			break;
2037		}
2038
2039		enq++;
2040		/*
2041		 * If there's a BPF listener, bounce a copy of this frame
2042		 * to him.
2043		 */
2044		ETHER_BPF_MTAP(ifp, m_head);
2045	}
2046
2047	if (enq > 0) {
2048		/* Sync descriptors. */
2049		bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
2050		    sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
2051		/* Kick. Assume we're using normal Tx priority queue. */
2052		CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
2053		    (sc->alc_cdata.alc_tx_prod <<
2054		    MBOX_TD_PROD_LO_IDX_SHIFT) &
2055		    MBOX_TD_PROD_LO_IDX_MASK);
2056		/* Set a timeout in case the chip goes out to lunch. */
2057		sc->alc_watchdog_timer = ALC_TX_TIMEOUT;
2058	}
2059
2060	ALC_UNLOCK(sc);
2061}
2062
2063static void
2064alc_watchdog(struct alc_softc *sc)
2065{
2066	struct ifnet *ifp;
2067
2068	ALC_LOCK_ASSERT(sc);
2069
2070	if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer)
2071		return;
2072
2073	ifp = sc->alc_ifp;
2074	if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
2075		if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n");
2076		ifp->if_oerrors++;
2077		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2078		alc_init_locked(sc);
2079		return;
2080	}
2081	if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n");
2082	ifp->if_oerrors++;
2083	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2084	alc_init_locked(sc);
2085	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2086		taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task);
2087}
2088
2089static int
2090alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2091{
2092	struct alc_softc *sc;
2093	struct ifreq *ifr;
2094	struct mii_data *mii;
2095	int error, mask;
2096
2097	sc = ifp->if_softc;
2098	ifr = (struct ifreq *)data;
2099	error = 0;
2100	switch (cmd) {
2101	case SIOCSIFMTU:
2102		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALC_JUMBO_MTU ||
2103		    ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 &&
2104		    ifr->ifr_mtu > ETHERMTU))
2105			error = EINVAL;
2106		else if (ifp->if_mtu != ifr->ifr_mtu) {
2107			ALC_LOCK(sc);
2108			ifp->if_mtu = ifr->ifr_mtu;
2109			/* AR8131/AR8132 has 13 bits MSS field. */
2110			if (ifp->if_mtu > ALC_TSO_MTU &&
2111			    (ifp->if_capenable & IFCAP_TSO4) != 0) {
2112				ifp->if_capenable &= ~IFCAP_TSO4;
2113				ifp->if_hwassist &= ~CSUM_TSO;
2114				VLAN_CAPABILITIES(ifp);
2115			}
2116			ALC_UNLOCK(sc);
2117		}
2118		break;
2119	case SIOCSIFFLAGS:
2120		ALC_LOCK(sc);
2121		if ((ifp->if_flags & IFF_UP) != 0) {
2122			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2123			    ((ifp->if_flags ^ sc->alc_if_flags) &
2124			    (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2125				alc_rxfilter(sc);
2126			else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0)
2127				alc_init_locked(sc);
2128		} else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2129			alc_stop(sc);
2130		sc->alc_if_flags = ifp->if_flags;
2131		ALC_UNLOCK(sc);
2132		break;
2133	case SIOCADDMULTI:
2134	case SIOCDELMULTI:
2135		ALC_LOCK(sc);
2136		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2137			alc_rxfilter(sc);
2138		ALC_UNLOCK(sc);
2139		break;
2140	case SIOCSIFMEDIA:
2141	case SIOCGIFMEDIA:
2142		mii = device_get_softc(sc->alc_miibus);
2143		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2144		break;
2145	case SIOCSIFCAP:
2146		ALC_LOCK(sc);
2147		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2148		if ((mask & IFCAP_TXCSUM) != 0 &&
2149		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2150			ifp->if_capenable ^= IFCAP_TXCSUM;
2151			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2152				ifp->if_hwassist |= ALC_CSUM_FEATURES;
2153			else
2154				ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
2155		}
2156		if ((mask & IFCAP_TSO4) != 0 &&
2157		    (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2158			ifp->if_capenable ^= IFCAP_TSO4;
2159			if ((ifp->if_capenable & IFCAP_TSO4) != 0) {
2160				/* AR8131/AR8132 has 13 bits MSS field. */
2161				if (ifp->if_mtu > ALC_TSO_MTU) {
2162					ifp->if_capenable &= ~IFCAP_TSO4;
2163					ifp->if_hwassist &= ~CSUM_TSO;
2164				} else
2165					ifp->if_hwassist |= CSUM_TSO;
2166			} else
2167				ifp->if_hwassist &= ~CSUM_TSO;
2168		}
2169		if ((mask & IFCAP_WOL_MCAST) != 0 &&
2170		    (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2171			ifp->if_capenable ^= IFCAP_WOL_MCAST;
2172		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2173		    (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2174			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2175		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2176		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2177			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2178			alc_rxvlan(sc);
2179		}
2180		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2181		    (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2182			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2183		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2184		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2185			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2186		if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2187			ifp->if_capenable &=
2188			    ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
2189		ALC_UNLOCK(sc);
2190		VLAN_CAPABILITIES(ifp);
2191		break;
2192	default:
2193		error = ether_ioctl(ifp, cmd, data);
2194		break;
2195	}
2196
2197	return (error);
2198}
2199
2200static void
2201alc_mac_config(struct alc_softc *sc)
2202{
2203	struct mii_data *mii;
2204	uint32_t reg;
2205
2206	ALC_LOCK_ASSERT(sc);
2207
2208	mii = device_get_softc(sc->alc_miibus);
2209	reg = CSR_READ_4(sc, ALC_MAC_CFG);
2210	reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2211	    MAC_CFG_SPEED_MASK);
2212	/* Reprogram MAC with resolved speed/duplex. */
2213	switch (IFM_SUBTYPE(mii->mii_media_active)) {
2214	case IFM_10_T:
2215	case IFM_100_TX:
2216		reg |= MAC_CFG_SPEED_10_100;
2217		break;
2218	case IFM_1000_T:
2219		reg |= MAC_CFG_SPEED_1000;
2220		break;
2221	}
2222	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2223		reg |= MAC_CFG_FULL_DUPLEX;
2224#ifdef notyet
2225		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2226			reg |= MAC_CFG_TX_FC;
2227		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2228			reg |= MAC_CFG_RX_FC;
2229#endif
2230	}
2231	CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2232}
2233
2234static void
2235alc_stats_clear(struct alc_softc *sc)
2236{
2237	struct smb sb, *smb;
2238	uint32_t *reg;
2239	int i;
2240
2241	if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2242		bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2243		    sc->alc_cdata.alc_smb_map,
2244		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2245		smb = sc->alc_rdata.alc_smb;
2246		/* Update done, clear. */
2247		smb->updated = 0;
2248		bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2249		    sc->alc_cdata.alc_smb_map,
2250		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2251	} else {
2252		for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
2253		    reg++) {
2254			CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2255			i += sizeof(uint32_t);
2256		}
2257		/* Read Tx statistics. */
2258		for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
2259		    reg++) {
2260			CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2261			i += sizeof(uint32_t);
2262		}
2263	}
2264}
2265
2266static void
2267alc_stats_update(struct alc_softc *sc)
2268{
2269	struct alc_hw_stats *stat;
2270	struct smb sb, *smb;
2271	struct ifnet *ifp;
2272	uint32_t *reg;
2273	int i;
2274
2275	ALC_LOCK_ASSERT(sc);
2276
2277	ifp = sc->alc_ifp;
2278	stat = &sc->alc_stats;
2279	if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2280		bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2281		    sc->alc_cdata.alc_smb_map,
2282		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2283		smb = sc->alc_rdata.alc_smb;
2284		if (smb->updated == 0)
2285			return;
2286	} else {
2287		smb = &sb;
2288		/* Read Rx statistics. */
2289		for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
2290		    reg++) {
2291			*reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2292			i += sizeof(uint32_t);
2293		}
2294		/* Read Tx statistics. */
2295		for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
2296		    reg++) {
2297			*reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2298			i += sizeof(uint32_t);
2299		}
2300	}
2301
2302	/* Rx stats. */
2303	stat->rx_frames += smb->rx_frames;
2304	stat->rx_bcast_frames += smb->rx_bcast_frames;
2305	stat->rx_mcast_frames += smb->rx_mcast_frames;
2306	stat->rx_pause_frames += smb->rx_pause_frames;
2307	stat->rx_control_frames += smb->rx_control_frames;
2308	stat->rx_crcerrs += smb->rx_crcerrs;
2309	stat->rx_lenerrs += smb->rx_lenerrs;
2310	stat->rx_bytes += smb->rx_bytes;
2311	stat->rx_runts += smb->rx_runts;
2312	stat->rx_fragments += smb->rx_fragments;
2313	stat->rx_pkts_64 += smb->rx_pkts_64;
2314	stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2315	stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2316	stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2317	stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2318	stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2319	stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2320	stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2321	stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2322	stat->rx_rrs_errs += smb->rx_rrs_errs;
2323	stat->rx_alignerrs += smb->rx_alignerrs;
2324	stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2325	stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2326	stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2327
2328	/* Tx stats. */
2329	stat->tx_frames += smb->tx_frames;
2330	stat->tx_bcast_frames += smb->tx_bcast_frames;
2331	stat->tx_mcast_frames += smb->tx_mcast_frames;
2332	stat->tx_pause_frames += smb->tx_pause_frames;
2333	stat->tx_excess_defer += smb->tx_excess_defer;
2334	stat->tx_control_frames += smb->tx_control_frames;
2335	stat->tx_deferred += smb->tx_deferred;
2336	stat->tx_bytes += smb->tx_bytes;
2337	stat->tx_pkts_64 += smb->tx_pkts_64;
2338	stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2339	stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2340	stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2341	stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2342	stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2343	stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2344	stat->tx_single_colls += smb->tx_single_colls;
2345	stat->tx_multi_colls += smb->tx_multi_colls;
2346	stat->tx_late_colls += smb->tx_late_colls;
2347	stat->tx_excess_colls += smb->tx_excess_colls;
2348	stat->tx_abort += smb->tx_abort;
2349	stat->tx_underrun += smb->tx_underrun;
2350	stat->tx_desc_underrun += smb->tx_desc_underrun;
2351	stat->tx_lenerrs += smb->tx_lenerrs;
2352	stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2353	stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2354	stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2355
2356	/* Update counters in ifnet. */
2357	ifp->if_opackets += smb->tx_frames;
2358
2359	ifp->if_collisions += smb->tx_single_colls +
2360	    smb->tx_multi_colls * 2 + smb->tx_late_colls +
2361	    smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2362
2363	/*
2364	 * XXX
2365	 * tx_pkts_truncated counter looks suspicious. It constantly
2366	 * increments with no sign of Tx errors. This may indicate
2367	 * the counter name is not correct one so I've removed the
2368	 * counter in output errors.
2369	 */
2370	ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2371	    smb->tx_underrun;
2372
2373	ifp->if_ipackets += smb->rx_frames;
2374
2375	ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2376	    smb->rx_runts + smb->rx_pkts_truncated +
2377	    smb->rx_fifo_oflows + smb->rx_rrs_errs +
2378	    smb->rx_alignerrs;
2379
2380	if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2381		/* Update done, clear. */
2382		smb->updated = 0;
2383		bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2384		    sc->alc_cdata.alc_smb_map,
2385		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2386	}
2387}
2388
2389static int
2390alc_intr(void *arg)
2391{
2392	struct alc_softc *sc;
2393	uint32_t status;
2394
2395	sc = (struct alc_softc *)arg;
2396
2397	status = CSR_READ_4(sc, ALC_INTR_STATUS);
2398	if ((status & ALC_INTRS) == 0)
2399		return (FILTER_STRAY);
2400	/* Disable interrupts. */
2401	CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
2402	taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
2403
2404	return (FILTER_HANDLED);
2405}
2406
2407static void
2408alc_int_task(void *arg, int pending)
2409{
2410	struct alc_softc *sc;
2411	struct ifnet *ifp;
2412	uint32_t status;
2413	int more;
2414
2415	sc = (struct alc_softc *)arg;
2416	ifp = sc->alc_ifp;
2417
2418	status = CSR_READ_4(sc, ALC_INTR_STATUS);
2419	more = atomic_readandclear_int(&sc->alc_morework);
2420	if (more != 0)
2421		status |= INTR_RX_PKT;
2422	if ((status & ALC_INTRS) == 0)
2423		goto done;
2424
2425	/* Acknowledge interrupts but still disable interrupts. */
2426	CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
2427
2428	more = 0;
2429	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2430		if ((status & INTR_RX_PKT) != 0) {
2431			more = alc_rxintr(sc, sc->alc_process_limit);
2432			if (more == EAGAIN)
2433				atomic_set_int(&sc->alc_morework, 1);
2434			else if (more == EIO) {
2435				ALC_LOCK(sc);
2436				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2437				alc_init_locked(sc);
2438				ALC_UNLOCK(sc);
2439				return;
2440			}
2441		}
2442		if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
2443		    INTR_TXQ_TO_RST)) != 0) {
2444			if ((status & INTR_DMA_RD_TO_RST) != 0)
2445				device_printf(sc->alc_dev,
2446				    "DMA read error! -- resetting\n");
2447			if ((status & INTR_DMA_WR_TO_RST) != 0)
2448				device_printf(sc->alc_dev,
2449				    "DMA write error! -- resetting\n");
2450			if ((status & INTR_TXQ_TO_RST) != 0)
2451				device_printf(sc->alc_dev,
2452				    "TxQ reset! -- resetting\n");
2453			ALC_LOCK(sc);
2454			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2455			alc_init_locked(sc);
2456			ALC_UNLOCK(sc);
2457			return;
2458		}
2459		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2460		    !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2461			taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task);
2462	}
2463
2464	if (more == EAGAIN ||
2465	    (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) {
2466		taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
2467		return;
2468	}
2469
2470done:
2471	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2472		/* Re-enable interrupts if we're running. */
2473		CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
2474	}
2475}
2476
2477static void
2478alc_txeof(struct alc_softc *sc)
2479{
2480	struct ifnet *ifp;
2481	struct alc_txdesc *txd;
2482	uint32_t cons, prod;
2483	int prog;
2484
2485	ALC_LOCK_ASSERT(sc);
2486
2487	ifp = sc->alc_ifp;
2488
2489	if (sc->alc_cdata.alc_tx_cnt == 0)
2490		return;
2491	bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
2492	    sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE);
2493	if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
2494		bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
2495		    sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD);
2496		prod = sc->alc_rdata.alc_cmb->cons;
2497	} else
2498		prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
2499	/* Assume we're using normal Tx priority queue. */
2500	prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
2501	    MBOX_TD_CONS_LO_IDX_SHIFT;
2502	cons = sc->alc_cdata.alc_tx_cons;
2503	/*
2504	 * Go through our Tx list and free mbufs for those
2505	 * frames which have been transmitted.
2506	 */
2507	for (prog = 0; cons != prod; prog++,
2508	    ALC_DESC_INC(cons, ALC_TX_RING_CNT)) {
2509		if (sc->alc_cdata.alc_tx_cnt <= 0)
2510			break;
2511		prog++;
2512		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2513		sc->alc_cdata.alc_tx_cnt--;
2514		txd = &sc->alc_cdata.alc_txdesc[cons];
2515		if (txd->tx_m != NULL) {
2516			/* Reclaim transmitted mbufs. */
2517			bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
2518			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2519			bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
2520			    txd->tx_dmamap);
2521			m_freem(txd->tx_m);
2522			txd->tx_m = NULL;
2523		}
2524	}
2525
2526	if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
2527		bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
2528		    sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD);
2529	sc->alc_cdata.alc_tx_cons = cons;
2530	/*
2531	 * Unarm watchdog timer only when there is no pending
2532	 * frames in Tx queue.
2533	 */
2534	if (sc->alc_cdata.alc_tx_cnt == 0)
2535		sc->alc_watchdog_timer = 0;
2536}
2537
2538static int
2539alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd)
2540{
2541	struct mbuf *m;
2542	bus_dma_segment_t segs[1];
2543	bus_dmamap_t map;
2544	int nsegs;
2545
2546	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2547	if (m == NULL)
2548		return (ENOBUFS);
2549	m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX;
2550#ifndef __NO_STRICT_ALIGNMENT
2551	m_adj(m, sizeof(uint64_t));
2552#endif
2553
2554	if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag,
2555	    sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2556		m_freem(m);
2557		return (ENOBUFS);
2558	}
2559	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2560
2561	if (rxd->rx_m != NULL) {
2562		bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
2563		    BUS_DMASYNC_POSTREAD);
2564		bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap);
2565	}
2566	map = rxd->rx_dmamap;
2567	rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap;
2568	sc->alc_cdata.alc_rx_sparemap = map;
2569	bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
2570	    BUS_DMASYNC_PREREAD);
2571	rxd->rx_m = m;
2572	rxd->rx_desc->addr = htole64(segs[0].ds_addr);
2573	return (0);
2574}
2575
2576static int
2577alc_rxintr(struct alc_softc *sc, int count)
2578{
2579	struct ifnet *ifp;
2580	struct rx_rdesc *rrd;
2581	uint32_t nsegs, status;
2582	int rr_cons, prog;
2583
2584	bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
2585	    sc->alc_cdata.alc_rr_ring_map,
2586	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2587	bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
2588	    sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2589	rr_cons = sc->alc_cdata.alc_rr_cons;
2590	ifp = sc->alc_ifp;
2591	for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) {
2592		if (count-- <= 0)
2593			break;
2594		rrd = &sc->alc_rdata.alc_rr_ring[rr_cons];
2595		status = le32toh(rrd->status);
2596		if ((status & RRD_VALID) == 0)
2597			break;
2598		nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo));
2599		if (nsegs == 0) {
2600			/* This should not happen! */
2601			device_printf(sc->alc_dev,
2602			    "unexpected segment count -- resetting\n");
2603			return (EIO);
2604		}
2605		alc_rxeof(sc, rrd);
2606		/* Clear Rx return status. */
2607		rrd->status = 0;
2608		ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT);
2609		sc->alc_cdata.alc_rx_cons += nsegs;
2610		sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT;
2611		prog += nsegs;
2612	}
2613
2614	if (prog > 0) {
2615		/* Update the consumer index. */
2616		sc->alc_cdata.alc_rr_cons = rr_cons;
2617		/* Sync Rx return descriptors. */
2618		bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
2619		    sc->alc_cdata.alc_rr_ring_map,
2620		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2621		/*
2622		 * Sync updated Rx descriptors such that controller see
2623		 * modified buffer addresses.
2624		 */
2625		bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
2626		    sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
2627		/*
2628		 * Let controller know availability of new Rx buffers.
2629		 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors
2630		 * it may be possible to update ALC_MBOX_RD0_PROD_IDX
2631		 * only when Rx buffer pre-fetching is required. In
2632		 * addition we already set ALC_RX_RD_FREE_THRESH to
2633		 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However
2634		 * it still seems that pre-fetching needs more
2635		 * experimentation.
2636		 */
2637		CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
2638		    sc->alc_cdata.alc_rx_cons);
2639	}
2640
2641	return (count > 0 ? 0 : EAGAIN);
2642}
2643
2644#ifndef __NO_STRICT_ALIGNMENT
2645static struct mbuf *
2646alc_fixup_rx(struct ifnet *ifp, struct mbuf *m)
2647{
2648	struct mbuf *n;
2649        int i;
2650        uint16_t *src, *dst;
2651
2652	src = mtod(m, uint16_t *);
2653	dst = src - 3;
2654
2655	if (m->m_next == NULL) {
2656		for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2657			*dst++ = *src++;
2658		m->m_data -= 6;
2659		return (m);
2660	}
2661	/*
2662	 * Append a new mbuf to received mbuf chain and copy ethernet
2663	 * header from the mbuf chain. This can save lots of CPU
2664	 * cycles for jumbo frame.
2665	 */
2666	MGETHDR(n, M_DONTWAIT, MT_DATA);
2667	if (n == NULL) {
2668		ifp->if_iqdrops++;
2669		m_freem(m);
2670		return (NULL);
2671	}
2672	bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
2673	m->m_data += ETHER_HDR_LEN;
2674	m->m_len -= ETHER_HDR_LEN;
2675	n->m_len = ETHER_HDR_LEN;
2676	M_MOVE_PKTHDR(n, m);
2677	n->m_next = m;
2678	return (n);
2679}
2680#endif
2681
2682/* Receive a frame. */
2683static void
2684alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd)
2685{
2686	struct alc_rxdesc *rxd;
2687	struct ifnet *ifp;
2688	struct mbuf *mp, *m;
2689	uint32_t rdinfo, status, vtag;
2690	int count, nsegs, rx_cons;
2691
2692	ifp = sc->alc_ifp;
2693	status = le32toh(rrd->status);
2694	rdinfo = le32toh(rrd->rdinfo);
2695	rx_cons = RRD_RD_IDX(rdinfo);
2696	nsegs = RRD_RD_CNT(rdinfo);
2697
2698	sc->alc_cdata.alc_rxlen = RRD_BYTES(status);
2699	if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) {
2700		/*
2701		 * We want to pass the following frames to upper
2702		 * layer regardless of error status of Rx return
2703		 * ring.
2704		 *
2705		 *  o IP/TCP/UDP checksum is bad.
2706		 *  o frame length and protocol specific length
2707		 *     does not match.
2708		 *
2709		 *  Force network stack compute checksum for
2710		 *  errored frames.
2711		 */
2712		status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
2713		if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC |
2714		    RRD_ERR_RUNT) != 0)
2715			return;
2716	}
2717
2718	for (count = 0; count < nsegs; count++,
2719	    ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) {
2720		rxd = &sc->alc_cdata.alc_rxdesc[rx_cons];
2721		mp = rxd->rx_m;
2722		/* Add a new receive buffer to the ring. */
2723		if (alc_newbuf(sc, rxd) != 0) {
2724			ifp->if_iqdrops++;
2725			/* Reuse Rx buffers. */
2726			if (sc->alc_cdata.alc_rxhead != NULL)
2727				m_freem(sc->alc_cdata.alc_rxhead);
2728			break;
2729		}
2730
2731		/*
2732		 * Assume we've received a full sized frame.
2733		 * Actual size is fixed when we encounter the end of
2734		 * multi-segmented frame.
2735		 */
2736		mp->m_len = sc->alc_buf_size;
2737
2738		/* Chain received mbufs. */
2739		if (sc->alc_cdata.alc_rxhead == NULL) {
2740			sc->alc_cdata.alc_rxhead = mp;
2741			sc->alc_cdata.alc_rxtail = mp;
2742		} else {
2743			mp->m_flags &= ~M_PKTHDR;
2744			sc->alc_cdata.alc_rxprev_tail =
2745			    sc->alc_cdata.alc_rxtail;
2746			sc->alc_cdata.alc_rxtail->m_next = mp;
2747			sc->alc_cdata.alc_rxtail = mp;
2748		}
2749
2750		if (count == nsegs - 1) {
2751			/* Last desc. for this frame. */
2752			m = sc->alc_cdata.alc_rxhead;
2753			m->m_flags |= M_PKTHDR;
2754			/*
2755			 * It seems that L1C/L2C controller has no way
2756			 * to tell hardware to strip CRC bytes.
2757			 */
2758			m->m_pkthdr.len =
2759			    sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN;
2760			if (nsegs > 1) {
2761				/* Set last mbuf size. */
2762				mp->m_len = sc->alc_cdata.alc_rxlen -
2763				    (nsegs - 1) * sc->alc_buf_size;
2764				/* Remove the CRC bytes in chained mbufs. */
2765				if (mp->m_len <= ETHER_CRC_LEN) {
2766					sc->alc_cdata.alc_rxtail =
2767					    sc->alc_cdata.alc_rxprev_tail;
2768					sc->alc_cdata.alc_rxtail->m_len -=
2769					    (ETHER_CRC_LEN - mp->m_len);
2770					sc->alc_cdata.alc_rxtail->m_next = NULL;
2771					m_freem(mp);
2772				} else {
2773					mp->m_len -= ETHER_CRC_LEN;
2774				}
2775			} else
2776				m->m_len = m->m_pkthdr.len;
2777			m->m_pkthdr.rcvif = ifp;
2778			/*
2779			 * Due to hardware bugs, Rx checksum offloading
2780			 * was intentionally disabled.
2781			 */
2782			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2783			    (status & RRD_VLAN_TAG) != 0) {
2784				vtag = RRD_VLAN(le32toh(rrd->vtag));
2785				m->m_pkthdr.ether_vtag = ntohs(vtag);
2786				m->m_flags |= M_VLANTAG;
2787			}
2788#ifndef __NO_STRICT_ALIGNMENT
2789			m = alc_fixup_rx(ifp, m);
2790			if (m != NULL)
2791#endif
2792			{
2793			/* Pass it on. */
2794			(*ifp->if_input)(ifp, m);
2795			}
2796		}
2797	}
2798	/* Reset mbuf chains. */
2799	ALC_RXCHAIN_RESET(sc);
2800}
2801
2802static void
2803alc_tick(void *arg)
2804{
2805	struct alc_softc *sc;
2806	struct mii_data *mii;
2807
2808	sc = (struct alc_softc *)arg;
2809
2810	ALC_LOCK_ASSERT(sc);
2811
2812	mii = device_get_softc(sc->alc_miibus);
2813	mii_tick(mii);
2814	alc_stats_update(sc);
2815	/*
2816	 * alc(4) does not rely on Tx completion interrupts to reclaim
2817	 * transferred buffers. Instead Tx completion interrupts are
2818	 * used to hint for scheduling Tx task. So it's necessary to
2819	 * release transmitted buffers by kicking Tx completion
2820	 * handler. This limits the maximum reclamation delay to a hz.
2821	 */
2822	alc_txeof(sc);
2823	alc_watchdog(sc);
2824	callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
2825}
2826
2827static void
2828alc_reset(struct alc_softc *sc)
2829{
2830	uint32_t reg;
2831	int i;
2832
2833	CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET);
2834	for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
2835		DELAY(10);
2836		if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
2837			break;
2838	}
2839	if (i == 0)
2840		device_printf(sc->alc_dev, "master reset timeout!\n");
2841
2842	for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
2843		if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0)
2844			break;
2845		DELAY(10);
2846	}
2847
2848	if (i == 0)
2849		device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);
2850}
2851
2852static void
2853alc_init(void *xsc)
2854{
2855	struct alc_softc *sc;
2856
2857	sc = (struct alc_softc *)xsc;
2858	ALC_LOCK(sc);
2859	alc_init_locked(sc);
2860	ALC_UNLOCK(sc);
2861}
2862
2863static void
2864alc_init_locked(struct alc_softc *sc)
2865{
2866	struct ifnet *ifp;
2867	struct mii_data *mii;
2868	uint8_t eaddr[ETHER_ADDR_LEN];
2869	bus_addr_t paddr;
2870	uint32_t reg, rxf_hi, rxf_lo;
2871
2872	ALC_LOCK_ASSERT(sc);
2873
2874	ifp = sc->alc_ifp;
2875	mii = device_get_softc(sc->alc_miibus);
2876
2877	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2878		return;
2879	/*
2880	 * Cancel any pending I/O.
2881	 */
2882	alc_stop(sc);
2883	/*
2884	 * Reset the chip to a known state.
2885	 */
2886	alc_reset(sc);
2887
2888	/* Initialize Rx descriptors. */
2889	if (alc_init_rx_ring(sc) != 0) {
2890		device_printf(sc->alc_dev, "no memory for Rx buffers.\n");
2891		alc_stop(sc);
2892		return;
2893	}
2894	alc_init_rr_ring(sc);
2895	alc_init_tx_ring(sc);
2896	alc_init_cmb(sc);
2897	alc_init_smb(sc);
2898
2899	/* Reprogram the station address. */
2900	bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2901	CSR_WRITE_4(sc, ALC_PAR0,
2902	    eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2903	CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
2904	/*
2905	 * Clear WOL status and disable all WOL feature as WOL
2906	 * would interfere Rx operation under normal environments.
2907	 */
2908	CSR_READ_4(sc, ALC_WOL_CFG);
2909	CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2910	/* Set Tx descriptor base addresses. */
2911	paddr = sc->alc_rdata.alc_tx_ring_paddr;
2912	CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2913	CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2914	/* We don't use high priority ring. */
2915	CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
2916	/* Set Tx descriptor counter. */
2917	CSR_WRITE_4(sc, ALC_TD_RING_CNT,
2918	    (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
2919	/* Set Rx descriptor base addresses. */
2920	paddr = sc->alc_rdata.alc_rx_ring_paddr;
2921	CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2922	CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2923	/* We use one Rx ring. */
2924	CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
2925	CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
2926	CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
2927	/* Set Rx descriptor counter. */
2928	CSR_WRITE_4(sc, ALC_RD_RING_CNT,
2929	    (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
2930
2931	/*
2932	 * Let hardware split jumbo frames into alc_max_buf_sized chunks.
2933	 * if it do not fit the buffer size. Rx return descriptor holds
2934	 * a counter that indicates how many fragments were made by the
2935	 * hardware. The buffer size should be multiple of 8 bytes.
2936	 * Since hardware has limit on the size of buffer size, always
2937	 * use the maximum value.
2938	 * For strict-alignment architectures make sure to reduce buffer
2939	 * size by 8 bytes to make room for alignment fixup.
2940	 */
2941#ifndef __NO_STRICT_ALIGNMENT
2942	sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t);
2943#else
2944	sc->alc_buf_size = RX_BUF_SIZE_MAX;
2945#endif
2946	CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
2947
2948	paddr = sc->alc_rdata.alc_rr_ring_paddr;
2949	/* Set Rx return descriptor base addresses. */
2950	CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2951	/* We use one Rx return ring. */
2952	CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
2953	CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
2954	CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
2955	/* Set Rx return descriptor counter. */
2956	CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
2957	    (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
2958	paddr = sc->alc_rdata.alc_cmb_paddr;
2959	CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
2960	paddr = sc->alc_rdata.alc_smb_paddr;
2961	CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2962	CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
2963
2964	/* Tell hardware that we're ready to load DMA blocks. */
2965	CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
2966
2967	/* Configure interrupt moderation timer. */
2968	reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
2969	reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
2970	CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
2971	reg = CSR_READ_4(sc, ALC_MASTER_CFG);
2972	reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2973	/*
2974	 * We don't want to automatic interrupt clear as task queue
2975	 * for the interrupt should know interrupt status.
2976	 */
2977	reg &= ~MASTER_INTR_RD_CLR;
2978	reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2979	if (ALC_USECS(sc->alc_int_rx_mod) != 0)
2980		reg |= MASTER_IM_RX_TIMER_ENB;
2981	if (ALC_USECS(sc->alc_int_tx_mod) != 0)
2982		reg |= MASTER_IM_TX_TIMER_ENB;
2983	CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2984	/*
2985	 * Disable interrupt re-trigger timer. We don't want automatic
2986	 * re-triggering of un-ACKed interrupts.
2987	 */
2988	CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
2989	/* Configure CMB. */
2990	if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
2991		CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
2992		CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
2993	} else
2994		CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
2995	/*
2996	 * Hardware can be configured to issue SMB interrupt based
2997	 * on programmed interval. Since there is a callout that is
2998	 * invoked for every hz in driver we use that instead of
2999	 * relying on periodic SMB interrupt.
3000	 */
3001	CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
3002	/* Clear MAC statistics. */
3003	alc_stats_clear(sc);
3004
3005	/*
3006	 * Always use maximum frame size that controller can support.
3007	 * Otherwise received frames that has larger frame length
3008	 * than alc(4) MTU would be silently dropped in hardware. This
3009	 * would make path-MTU discovery hard as sender wouldn't get
3010	 * any responses from receiver. alc(4) supports
3011	 * multi-fragmented frames on Rx path so it has no issue on
3012	 * assembling fragmented frames. Using maximum frame size also
3013	 * removes the need to reinitialize hardware when interface
3014	 * MTU configuration was changed.
3015	 *
3016	 * Be conservative in what you do, be liberal in what you
3017	 * accept from others - RFC 793.
3018	 */
3019	CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN);
3020
3021	/* Disable header split(?) */
3022	CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
3023
3024	/* Configure IPG/IFG parameters. */
3025	CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
3026	    ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
3027	    ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
3028	    ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
3029	    ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
3030	/* Set parameters for half-duplex media. */
3031	CSR_WRITE_4(sc, ALC_HDPX_CFG,
3032	    ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
3033	    HDPX_CFG_LCOL_MASK) |
3034	    ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
3035	    HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
3036	    ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
3037	    HDPX_CFG_ABEBT_MASK) |
3038	    ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
3039	    HDPX_CFG_JAMIPG_MASK));
3040	/*
3041	 * Set TSO/checksum offload threshold. For frames that is
3042	 * larger than this threshold, hardware wouldn't do
3043	 * TSO/checksum offloading.
3044	 */
3045	CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
3046	    (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
3047	    TSO_OFFLOAD_THRESH_MASK);
3048	/* Configure TxQ. */
3049	reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
3050	    TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
3051	reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
3052	    TXQ_CFG_TD_BURST_MASK;
3053	CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
3054
3055	/* Configure Rx free descriptor pre-fetching. */
3056	CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
3057	    ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) &
3058	    RX_RD_FREE_THRESH_HI_MASK) |
3059	    ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) &
3060	    RX_RD_FREE_THRESH_LO_MASK));
3061
3062	/*
3063	 * Configure flow control parameters.
3064	 * XON  : 80% of Rx FIFO
3065	 * XOFF : 30% of Rx FIFO
3066	 */
3067	reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
3068	rxf_hi = (reg * 8) / 10;
3069	rxf_lo = (reg * 3)/ 10;
3070	CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
3071	    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
3072	    RX_FIFO_PAUSE_THRESH_LO_MASK) |
3073	    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
3074	     RX_FIFO_PAUSE_THRESH_HI_MASK));
3075
3076	/* Disable RSS until I understand L1C/L2C's RSS logic. */
3077	CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
3078	CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
3079
3080	/* Configure RxQ. */
3081	reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
3082	    RXQ_CFG_RD_BURST_MASK;
3083	reg |= RXQ_CFG_RSS_MODE_DIS;
3084	if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0)
3085		reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
3086	CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3087
3088	/* Configure Rx DMAW request thresold. */
3089	CSR_WRITE_4(sc, ALC_RD_DMA_CFG,
3090	    ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) &
3091	    RD_DMA_CFG_THRESH_MASK) |
3092	    ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) &
3093	    RD_DMA_CFG_TIMER_MASK));
3094	/* Configure DMA parameters. */
3095	reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
3096	reg |= sc->alc_rcb;
3097	if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
3098		reg |= DMA_CFG_CMB_ENB;
3099	if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
3100		reg |= DMA_CFG_SMB_ENB;
3101	else
3102		reg |= DMA_CFG_SMB_DIS;
3103	reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
3104	    DMA_CFG_RD_BURST_SHIFT;
3105	reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
3106	    DMA_CFG_WR_BURST_SHIFT;
3107	reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
3108	    DMA_CFG_RD_DELAY_CNT_MASK;
3109	reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
3110	    DMA_CFG_WR_DELAY_CNT_MASK;
3111	CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3112
3113	/*
3114	 * Configure Tx/Rx MACs.
3115	 *  - Auto-padding for short frames.
3116	 *  - Enable CRC generation.
3117	 *  Actual reconfiguration of MAC for resolved speed/duplex
3118	 *  is followed after detection of link establishment.
3119	 *  AR8131/AR8132 always does checksum computation regardless
3120	 *  of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
3121	 *  have bug in protocol field in Rx return structure so
3122	 *  these controllers can't handle fragmented frames. Disable
3123	 *  Rx checksum offloading until there is a newer controller
3124	 *  that has sane implementation.
3125	 */
3126	reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
3127	    ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
3128	    MAC_CFG_PREAMBLE_MASK);
3129	if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
3130		reg |= MAC_CFG_SPEED_10_100;
3131	else
3132		reg |= MAC_CFG_SPEED_1000;
3133	CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3134
3135	/* Set up the receive filter. */
3136	alc_rxfilter(sc);
3137	alc_rxvlan(sc);
3138
3139	/* Acknowledge all pending interrupts and clear it. */
3140	CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
3141	CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3142	CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
3143
3144	sc->alc_flags &= ~ALC_FLAG_LINK;
3145	/* Switch to the current media. */
3146	mii_mediachg(mii);
3147
3148	callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
3149
3150	ifp->if_drv_flags |= IFF_DRV_RUNNING;
3151	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3152}
3153
3154static void
3155alc_stop(struct alc_softc *sc)
3156{
3157	struct ifnet *ifp;
3158	struct alc_txdesc *txd;
3159	struct alc_rxdesc *rxd;
3160	uint32_t reg;
3161	int i;
3162
3163	ALC_LOCK_ASSERT(sc);
3164	/*
3165	 * Mark the interface down and cancel the watchdog timer.
3166	 */
3167	ifp = sc->alc_ifp;
3168	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3169	sc->alc_flags &= ~ALC_FLAG_LINK;
3170	callout_stop(&sc->alc_tick_ch);
3171	sc->alc_watchdog_timer = 0;
3172	alc_stats_update(sc);
3173	/* Disable interrupts. */
3174	CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
3175	CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3176	alc_stop_queue(sc);
3177	/* Disable DMA. */
3178	reg = CSR_READ_4(sc, ALC_DMA_CFG);
3179	reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
3180	reg |= DMA_CFG_SMB_DIS;
3181	CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3182	DELAY(1000);
3183	/* Stop Rx/Tx MACs. */
3184	alc_stop_mac(sc);
3185	/* Disable interrupts which might be touched in taskq handler. */
3186	CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3187
3188	/* Reclaim Rx buffers that have been processed. */
3189	if (sc->alc_cdata.alc_rxhead != NULL)
3190		m_freem(sc->alc_cdata.alc_rxhead);
3191	ALC_RXCHAIN_RESET(sc);
3192	/*
3193	 * Free Tx/Rx mbufs still in the queues.
3194	 */
3195	for (i = 0; i < ALC_RX_RING_CNT; i++) {
3196		rxd = &sc->alc_cdata.alc_rxdesc[i];
3197		if (rxd->rx_m != NULL) {
3198			bus_dmamap_sync(sc->alc_cdata.alc_rx_tag,
3199			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3200			bus_dmamap_unload(sc->alc_cdata.alc_rx_tag,
3201			    rxd->rx_dmamap);
3202			m_freem(rxd->rx_m);
3203			rxd->rx_m = NULL;
3204		}
3205	}
3206	for (i = 0; i < ALC_TX_RING_CNT; i++) {
3207		txd = &sc->alc_cdata.alc_txdesc[i];
3208		if (txd->tx_m != NULL) {
3209			bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
3210			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3211			bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
3212			    txd->tx_dmamap);
3213			m_freem(txd->tx_m);
3214			txd->tx_m = NULL;
3215		}
3216	}
3217}
3218
3219static void
3220alc_stop_mac(struct alc_softc *sc)
3221{
3222	uint32_t reg;
3223	int i;
3224
3225	ALC_LOCK_ASSERT(sc);
3226
3227	/* Disable Rx/Tx MAC. */
3228	reg = CSR_READ_4(sc, ALC_MAC_CFG);
3229	if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
3230		reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
3231		CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3232	}
3233	for (i = ALC_TIMEOUT; i > 0; i--) {
3234		reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3235		if (reg == 0)
3236			break;
3237		DELAY(10);
3238	}
3239	if (i == 0)
3240		device_printf(sc->alc_dev,
3241		    "could not disable Rx/Tx MAC(0x%08x)!\n", reg);
3242}
3243
3244static void
3245alc_start_queue(struct alc_softc *sc)
3246{
3247	uint32_t qcfg[] = {
3248		0,
3249		RXQ_CFG_QUEUE0_ENB,
3250		RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB,
3251		RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB,
3252		RXQ_CFG_ENB
3253	};
3254	uint32_t cfg;
3255
3256	ALC_LOCK_ASSERT(sc);
3257
3258	/* Enable RxQ. */
3259	cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
3260	cfg &= ~RXQ_CFG_ENB;
3261	cfg |= qcfg[1];
3262	CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
3263	/* Enable TxQ. */
3264	cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
3265	cfg |= TXQ_CFG_ENB;
3266	CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
3267}
3268
3269static void
3270alc_stop_queue(struct alc_softc *sc)
3271{
3272	uint32_t reg;
3273	int i;
3274
3275	ALC_LOCK_ASSERT(sc);
3276
3277	/* Disable RxQ. */
3278	reg = CSR_READ_4(sc, ALC_RXQ_CFG);
3279	if ((reg & RXQ_CFG_ENB) != 0) {
3280		reg &= ~RXQ_CFG_ENB;
3281		CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3282	}
3283	/* Disable TxQ. */
3284	reg = CSR_READ_4(sc, ALC_TXQ_CFG);
3285	if ((reg & TXQ_CFG_ENB) == 0) {
3286		reg &= ~TXQ_CFG_ENB;
3287		CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
3288	}
3289	for (i = ALC_TIMEOUT; i > 0; i--) {
3290		reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3291		if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
3292			break;
3293		DELAY(10);
3294	}
3295	if (i == 0)
3296		device_printf(sc->alc_dev,
3297		    "could not disable RxQ/TxQ (0x%08x)!\n", reg);
3298}
3299
3300static void
3301alc_init_tx_ring(struct alc_softc *sc)
3302{
3303	struct alc_ring_data *rd;
3304	struct alc_txdesc *txd;
3305	int i;
3306
3307	ALC_LOCK_ASSERT(sc);
3308
3309	sc->alc_cdata.alc_tx_prod = 0;
3310	sc->alc_cdata.alc_tx_cons = 0;
3311	sc->alc_cdata.alc_tx_cnt = 0;
3312
3313	rd = &sc->alc_rdata;
3314	bzero(rd->alc_tx_ring, ALC_TX_RING_SZ);
3315	for (i = 0; i < ALC_TX_RING_CNT; i++) {
3316		txd = &sc->alc_cdata.alc_txdesc[i];
3317		txd->tx_m = NULL;
3318	}
3319
3320	bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
3321	    sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
3322}
3323
3324static int
3325alc_init_rx_ring(struct alc_softc *sc)
3326{
3327	struct alc_ring_data *rd;
3328	struct alc_rxdesc *rxd;
3329	int i;
3330
3331	ALC_LOCK_ASSERT(sc);
3332
3333	sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1;
3334	sc->alc_morework = 0;
3335	rd = &sc->alc_rdata;
3336	bzero(rd->alc_rx_ring, ALC_RX_RING_SZ);
3337	for (i = 0; i < ALC_RX_RING_CNT; i++) {
3338		rxd = &sc->alc_cdata.alc_rxdesc[i];
3339		rxd->rx_m = NULL;
3340		rxd->rx_desc = &rd->alc_rx_ring[i];
3341		if (alc_newbuf(sc, rxd) != 0)
3342			return (ENOBUFS);
3343	}
3344
3345	/*
3346	 * Since controller does not update Rx descriptors, driver
3347	 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE
3348	 * is enough to ensure coherence.
3349	 */
3350	bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
3351	    sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
3352	/* Let controller know availability of new Rx buffers. */
3353	CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
3354
3355	return (0);
3356}
3357
3358static void
3359alc_init_rr_ring(struct alc_softc *sc)
3360{
3361	struct alc_ring_data *rd;
3362
3363	ALC_LOCK_ASSERT(sc);
3364
3365	sc->alc_cdata.alc_rr_cons = 0;
3366	ALC_RXCHAIN_RESET(sc);
3367
3368	rd = &sc->alc_rdata;
3369	bzero(rd->alc_rr_ring, ALC_RR_RING_SZ);
3370	bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
3371	    sc->alc_cdata.alc_rr_ring_map,
3372	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3373}
3374
3375static void
3376alc_init_cmb(struct alc_softc *sc)
3377{
3378	struct alc_ring_data *rd;
3379
3380	ALC_LOCK_ASSERT(sc);
3381
3382	rd = &sc->alc_rdata;
3383	bzero(rd->alc_cmb, ALC_CMB_SZ);
3384	bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map,
3385	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3386}
3387
3388static void
3389alc_init_smb(struct alc_softc *sc)
3390{
3391	struct alc_ring_data *rd;
3392
3393	ALC_LOCK_ASSERT(sc);
3394
3395	rd = &sc->alc_rdata;
3396	bzero(rd->alc_smb, ALC_SMB_SZ);
3397	bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map,
3398	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3399}
3400
3401static void
3402alc_rxvlan(struct alc_softc *sc)
3403{
3404	struct ifnet *ifp;
3405	uint32_t reg;
3406
3407	ALC_LOCK_ASSERT(sc);
3408
3409	ifp = sc->alc_ifp;
3410	reg = CSR_READ_4(sc, ALC_MAC_CFG);
3411	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3412		reg |= MAC_CFG_VLAN_TAG_STRIP;
3413	else
3414		reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3415	CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3416}
3417
3418static void
3419alc_rxfilter(struct alc_softc *sc)
3420{
3421	struct ifnet *ifp;
3422	struct ifmultiaddr *ifma;
3423	uint32_t crc;
3424	uint32_t mchash[2];
3425	uint32_t rxcfg;
3426
3427	ALC_LOCK_ASSERT(sc);
3428
3429	ifp = sc->alc_ifp;
3430
3431	bzero(mchash, sizeof(mchash));
3432	rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
3433	rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3434	if ((ifp->if_flags & IFF_BROADCAST) != 0)
3435		rxcfg |= MAC_CFG_BCAST;
3436	if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3437		if ((ifp->if_flags & IFF_PROMISC) != 0)
3438			rxcfg |= MAC_CFG_PROMISC;
3439		if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3440			rxcfg |= MAC_CFG_ALLMULTI;
3441		mchash[0] = 0xFFFFFFFF;
3442		mchash[1] = 0xFFFFFFFF;
3443		goto chipit;
3444	}
3445
3446	if_maddr_rlock(ifp);
3447	TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) {
3448		if (ifma->ifma_addr->sa_family != AF_LINK)
3449			continue;
3450		crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3451		    ifma->ifma_addr), ETHER_ADDR_LEN);
3452		mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3453	}
3454	if_maddr_runlock(ifp);
3455
3456chipit:
3457	CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
3458	CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
3459	CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
3460}
3461
3462static int
3463sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3464{
3465	int error, value;
3466
3467	if (arg1 == NULL)
3468		return (EINVAL);
3469	value = *(int *)arg1;
3470	error = sysctl_handle_int(oidp, &value, 0, req);
3471	if (error || req->newptr == NULL)
3472		return (error);
3473	if (value < low || value > high)
3474		return (EINVAL);
3475	*(int *)arg1 = value;
3476
3477	return (0);
3478}
3479
3480static int
3481sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS)
3482{
3483	return (sysctl_int_range(oidp, arg1, arg2, req,
3484	    ALC_PROC_MIN, ALC_PROC_MAX));
3485}
3486
3487static int
3488sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS)
3489{
3490
3491	return (sysctl_int_range(oidp, arg1, arg2, req,
3492	    ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX));
3493}
3494