Searched refs:regs (Results 1 - 25 of 146) sorted by relevance

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/haiku/src/libs/libunwind/aarch64/
H A Dgen-offsets.c30 SC ("R0", regs[0]);
31 SC ("R1", regs[1]);
32 SC ("R2", regs[2]);
33 SC ("R3", regs[3]);
34 SC ("R4", regs[4]);
35 SC ("R5", regs[5]);
36 SC ("R6", regs[6]);
37 SC ("R7", regs[7]);
38 SC ("R8", regs[8]);
39 SC ("R9", regs[
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H A DGresume.c43 unsigned long regs[24]; local
44 regs[0] = uc->uc_mcontext.regs[0];
45 regs[1] = uc->uc_mcontext.regs[1];
46 regs[2] = uc->uc_mcontext.regs[2];
47 regs[3] = uc->uc_mcontext.regs[3];
48 regs[
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/haiku/headers/private/graphics/radeon/
H A Dmmio.h14 #define INREG8( regs, addr ) (*(regs + (addr)))
16 #define OUTREG8( regs, addr, val ) do { *(regs + (addr)) = (val); } while( 0 )
18 #define INREG( regs, addr ) (*((vuint32 *)(regs + (addr))))
20 #define OUTREG( regs, addr, val ) do { *(vuint32 *)(regs + (addr)) = (val); } while( 0 )
22 #define OUTREGP( regs, addr, val, mask ) \
24 uint32 tmp = INREG( (regs), (add
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H A Dpll_access.h19 void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic );
24 void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic );
36 uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr );
39 void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val );
42 void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask );
/haiku/src/libs/libunwind/arm/
H A DGresume.c43 unsigned long regs[10]; local
44 regs[0] = uc->regs[4];
45 regs[1] = uc->regs[5];
46 regs[2] = uc->regs[6];
47 regs[3] = uc->regs[7];
48 regs[
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/haiku/src/system/boot/platform/bios_ia32/
H A Dkeyboard.cpp19 bios_regs regs; local
20 regs.eax = 0x0100;
21 call_bios(0x16, &regs);
24 if (regs.flags & ZERO_FLAG)
28 regs.eax = 0;
29 call_bios(0x16, &regs);
31 return regs.eax & 0xffff;
58 bios_regs regs; local
61 regs.eax = 0x0200;
62 call_bios(0x16, &regs);
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H A Dbios.cpp23 extern "C" void call_bios_internal(uint8 num, struct bios_regs* regs);
27 call_bios(uint8 num, struct bios_regs* regs) argument
34 num, regs->eax, regs->ebx, regs->ecx, regs->edx, regs->esi, regs->edi,
35 regs->es, regs
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H A Dapm.cpp28 struct bios_regs regs; local
29 regs.eax = BIOS_APM_CHECK;
30 regs.ebx = 0;
31 call_bios(0x15, &regs);
33 if ((regs.flags & CARRY_FLAG) != 0
34 || (regs.ebx & 0xffff) != 'PM') {
40 gKernelArgs.platform_args.apm.version = regs.eax & 0xffff;
41 gKernelArgs.platform_args.apm.flags = regs.ecx & 0xffff;
54 regs.eax = BIOS_APM_DISCONNECT;
55 regs
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/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dpll_access.c16 void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic ) argument
24 INREG( regs, RADEON_CLOCK_CNTL_DATA);
25 INREG( regs, RADEON_CRTC_GEN_CNTL);
28 void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic ) argument
50 save = INREG( regs, RADEON_CLOCK_CNTL_INDEX );
52 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, tmp );
53 tmp = INREG( regs, RADEON_CLOCK_CNTL_DATA );
54 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, save );
59 uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr ) argument
63 OUTREG8( regs, RADEON_CLOCK_CNTL_INDE
71 Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val ) argument
84 Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask ) argument
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H A Dvip.c32 vuint8 *regs = di->regs; local
36 OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x2000 );
43 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, 0,
48 INREG( regs, RADEON_VIPH_REG_DATA );
57 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,
62 *data = INREG( regs, RADEON_VIPH_REG_DATA );
72 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,
99 vuint8 *regs = di->regs; local
192 vuint8 *regs = di->regs; local
230 vuint8 *regs = di->regs; local
296 vuint8 *regs = di->regs; local
348 vuint8 *regs = di->regs; local
366 vuint8 *regs = di->regs; local
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H A DCP_setup.c130 if( (INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_ACTIVE) == 0 ) {
147 INREG( di->regs, RADEON_RBBM_STATUS ),
148 INREG( di->regs, RADEON_CP_STAT ),
149 INREG( di->regs, RADEON_AIC_TLB_ADDR ),
150 INREG( di->regs, RADEON_AIC_TLB_DATA ));
167 int slots = INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;
186 OUTREGP( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL,
192 if( (INREG( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT )
208 vuint8 *regs = di->regs; local
326 vuint8 *regs = di->regs; local
377 vuint8 *regs = di->regs; local
393 vuint8 *regs = di->regs; local
434 vuint8 *regs = di->regs; local
582 vuint8 *regs = di->regs; local
642 vuint8 *regs = di->regs; local
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/haiku/src/system/libroot/os/arch/x86_64/
H A Dsystem_info.cpp16 __cpuid_count(eax, 0, info->regs.eax, info->regs.ebx, info->regs.ecx,
17 info->regs.edx);
/haiku/headers/private/kernel/arch/x86/
H A Darch_hpet.h22 #define HPET_GET_REVID(regs) ((regs)->capabilities & HPET_CAP_MASK_REVID)
23 #define HPET_GET_NUM_TIMERS(regs) (((regs)->capabilities & HPET_CAP_MASK_NUMTIMERS) >> 8)
24 #define HPET_IS_64BIT(regs) (((regs)->capabilities & HPET_CAP_MASK_WIDTH) >> 13)
25 #define HPET_IS_LEGACY_CAPABLE(regs) (((regs)->capabilities & HPET_CAP_MASK_LEGACY) >> 15)
26 #define HPET_GET_VENDOR_ID(regs) (((regs)
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/haiku/src/add-ons/accelerants/radeon/
H A Ddpms.c59 vuint8 *regs = ai->regs; local
68 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON );
70 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON );
78 old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);
82 Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb );
84 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, 0, ~(RADEON_LVDS_BLON | RADEON_LVDS_ON) );
87 Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl );
97 vuint8 *regs = ai->regs; local
119 vuint8 *regs = ai->regs; local
150 vuint8 *regs = ai->regs; local
172 vuint8 *regs = ai->regs; local
198 vuint8 *regs = ai->regs; local
240 vuint8 *regs = ai->regs; local
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H A Dflat_panel.c23 vuint8 *regs = ai->regs; local
25 values->fp_horz_stretch = INREG( regs, RADEON_FP_HORZ_STRETCH );
26 values->fp_vert_stretch = INREG( regs, RADEON_FP_VERT_STRETCH );
110 vuint8 *regs = ai->regs; local
112 OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch );
113 OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch );
120 vuint8 *regs = ai->regs; local
254 vuint8 *regs = ai->regs; local
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H A Dmonitor_detection.c40 vuint8 *regs = info->ai->regs; local
43 value = INREG(regs, info->port);
56 vuint8 *regs = info->ai->regs; local
59 value = INREG(regs, info->port);
65 OUTREG(regs, info->port, value);
104 vuint8 *regs = ai->regs; local
109 old_crtc_ext_cntl = INREG(regs, RADEON_CRTC_EXT_CNT
180 vuint8 *regs = ai->regs; local
231 vuint8 *regs = ai->regs; local
334 vuint8 *regs = ai->regs; local
419 vuint8 *regs = ai->regs; local
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/haiku/src/add-ons/kernel/drivers/timer/
H A Dhpet.h23 #define HPET_GET_REVID(regs) ((regs)->capabilities & HPET_CAP_MASK_REVID)
24 #define HPET_GET_NUM_TIMERS(regs) (((regs)->capabilities & HPET_CAP_MASK_NUMTIMERS) >> 8)
25 #define HPET_IS_64BIT(regs) (((regs)->capabilities & HPET_CAP_MASK_WIDTH) >> 13)
26 #define HPET_IS_LEGACY_CAPABLE(regs) (((regs)->capabilities & HPET_CAP_MASK_LEGACY) >> 15)
27 #define HPET_GET_VENDOR_ID(regs) (((regs)
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/haiku/src/system/kernel/arch/x86/64/
H A Dcpuid.cpp16 __cpuid_count(eax, ecx, info->regs.eax, info->regs.ebx, info->regs.ecx,
17 info->regs.edx);
/haiku/src/system/kernel/arch/x86/32/
H A Dapm.cpp92 call_apm_bios(bios_regs *regs) argument
106 : "=a" (regs->eax), "=b" (regs->ebx), "=c" (regs->ecx), "=d" (regs->edx),
107 "=S" (regs->esi), "=m" (regs->flags)
108 : "a" (regs->eax), "b" (regs->ebx), "c" (regs
124 bios_regs regs; local
139 bios_regs regs; local
156 bios_regs regs; local
168 bios_regs regs; local
181 bios_regs regs; local
209 bios_regs regs; local
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/haiku/src/add-ons/accelerants/matrox/engine/
H A Dmga_globals.h5 extern vuint32 *regs;
H A Dmga_globals.c14 vuint32 *regs; variable
/haiku/src/add-ons/accelerants/matrox/
H A Dglobal.h5 extern vuint32 *regs;
/haiku/src/add-ons/accelerants/radeon_hd/
H A Ddisplay.cpp40 /*! Populate regs with device dependant register locations */
42 init_registers(register_info* regs, uint8 crtcID) argument
44 memset(regs, 0, sizeof(register_info));
55 regs->vgaControl = AVIVO_D1VGA_CONTROL;
59 regs->vgaControl = AVIVO_D2VGA_CONTROL;
63 regs->vgaControl = EVERGREEN_D3VGA_CONTROL;
67 regs->vgaControl = EVERGREEN_D4VGA_CONTROL;
71 regs->vgaControl = EVERGREEN_D5VGA_CONTROL;
75 regs->vgaControl = EVERGREEN_D6VGA_CONTROL;
83 regs
602 register_info* regs = gDisplay[crtcID]->regs; local
667 register_info* regs = gDisplay[crtcID]->regs; local
703 register_info* regs = gDisplay[crtcID]->regs; local
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/haiku/src/add-ons/kernel/drivers/dvb/cx23882/
H A Dcx23882.h36 void * regs; member in struct:__anon4
55 #define reg_read8(offset) (*(volatile uint8 *) ((char *)(device->regs) + (offset)))
56 #define reg_read16(offset) (*(volatile uint16 *)((char *)(device->regs) + (offset)))
57 #define reg_read32(offset) (*(volatile uint32 *)((char *)(device->regs) + (offset)))
58 #define reg_write8(offset, value) (*(volatile uint8 *) ((char *)(device->regs) + (offset)) = value)
59 #define reg_write16(offset, value) (*(volatile uint16 *)((char *)(device->regs) + (offset)) = value)
60 #define reg_write32(offset, value) (*(volatile uint32 *)((char *)(device->regs) + (offset)) = value)
/haiku/src/add-ons/accelerants/skeleton/engine/
H A Dglobals.c15 vuint32 *regs; variable

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