Lines Matching defs:REGS_SOUTH_SHARED

124 #define REGS_SOUTH_SHARED					(4 << REGISTER_BLOCK_SHIFT)
726 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED)
727 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED)
728 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED)
731 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED)
755 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED)
756 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED)
757 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED)
759 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED)
760 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED)
761 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED)
762 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED)
765 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED)
766 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED)
767 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED)
768 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED)
769 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED)
770 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED)
771 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED)
772 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED)
797 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED)
798 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED)
799 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED)
800 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED)
801 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED)
826 #define PCH_SBLC_PWM_CTL2 (0x8254 | REGS_SOUTH_SHARED)
979 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED)
980 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED)