intel_extreme.h revision 13af65c4
1/*
2 * Copyright 2006-2014, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Axel D��rfler, axeld@pinc-software.de
7 */
8#ifndef INTEL_EXTREME_H
9#define INTEL_EXTREME_H
10
11
12#include "lock.h"
13
14#include <Accelerant.h>
15#include <Drivers.h>
16#include <PCI.h>
17
18#include <edid.h>
19
20
21#define VENDOR_ID_INTEL			0x8086
22
23#define INTEL_TYPE_FAMILY_MASK	0x000f0000
24#define INTEL_TYPE_GROUP_MASK	0x000ffff0
25#define INTEL_TYPE_MODEL_MASK	0x000fffff
26// families
27#define INTEL_TYPE_7xx			0x00010000
28#define INTEL_TYPE_8xx			0x00020000
29#define INTEL_TYPE_9xx			0x00040000
30// groups
31#define INTEL_TYPE_83x			(INTEL_TYPE_8xx | 0x0010)
32#define INTEL_TYPE_85x			(INTEL_TYPE_8xx | 0x0020)
33#define INTEL_TYPE_91x			(INTEL_TYPE_9xx | 0x0040)
34#define INTEL_TYPE_94x			(INTEL_TYPE_9xx | 0x0080)
35#define INTEL_TYPE_96x			(INTEL_TYPE_9xx | 0x0100)
36#define INTEL_TYPE_Gxx			(INTEL_TYPE_9xx | 0x0200)
37#define INTEL_TYPE_G4x			(INTEL_TYPE_9xx | 0x0400)
38#define INTEL_TYPE_IGD			(INTEL_TYPE_9xx | 0x0800)
39#define INTEL_TYPE_ILK			(INTEL_TYPE_9xx | 0x1000)
40#define INTEL_TYPE_SNB			(INTEL_TYPE_9xx | 0x2000)
41#define INTEL_TYPE_IVB			(INTEL_TYPE_9xx | 0x4000)
42// models
43#define INTEL_TYPE_SERVER		0x0004
44#define INTEL_TYPE_MOBILE		0x0008
45#define INTEL_TYPE_915			(INTEL_TYPE_91x)
46#define INTEL_TYPE_915M			(INTEL_TYPE_91x | INTEL_TYPE_MOBILE)
47#define INTEL_TYPE_945			(INTEL_TYPE_94x)
48#define INTEL_TYPE_945M			(INTEL_TYPE_94x | INTEL_TYPE_MOBILE)
49#define INTEL_TYPE_965			(INTEL_TYPE_96x)
50#define INTEL_TYPE_965M			(INTEL_TYPE_96x | INTEL_TYPE_MOBILE)
51#define INTEL_TYPE_G33			(INTEL_TYPE_Gxx)
52#define INTEL_TYPE_G45			(INTEL_TYPE_G4x)
53#define INTEL_TYPE_GM45			(INTEL_TYPE_G4x | INTEL_TYPE_MOBILE)
54#define INTEL_TYPE_IGDG			(INTEL_TYPE_IGD)
55#define INTEL_TYPE_IGDGM		(INTEL_TYPE_IGD | INTEL_TYPE_MOBILE)
56#define INTEL_TYPE_ILKG			(INTEL_TYPE_ILK)
57#define INTEL_TYPE_ILKGM		(INTEL_TYPE_ILK | INTEL_TYPE_MOBILE)
58#define INTEL_TYPE_SNBG			(INTEL_TYPE_SNB)
59#define INTEL_TYPE_SNBGM		(INTEL_TYPE_SNB | INTEL_TYPE_MOBILE)
60#define INTEL_TYPE_SNBGS		(INTEL_TYPE_SNB | INTEL_TYPE_SERVER)
61#define INTEL_TYPE_IVBG			(INTEL_TYPE_IVB)
62#define INTEL_TYPE_IVBGM		(INTEL_TYPE_IVB | INTEL_TYPE_MOBILE)
63#define INTEL_TYPE_IVBGS		(INTEL_TYPE_IVB | INTEL_TYPE_SERVER)
64
65#define DEVICE_NAME				"intel_extreme"
66#define INTEL_ACCELERANT_NAME	"intel_extreme.accelerant"
67
68// We encode the register block into the value and extract/translate it when
69// actually accessing.
70#define REGISTER_BLOCK_COUNT				6
71#define REGISTER_BLOCK_SHIFT				24
72#define REGISTER_BLOCK_MASK					0xff000000
73#define REGISTER_REGISTER_MASK				0x00ffffff
74#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
75#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
76
77#define REGS_FLAT							(0 << REGISTER_BLOCK_SHIFT)
78#define REGS_NORTH_SHARED					(1 << REGISTER_BLOCK_SHIFT)
79#define REGS_NORTH_PIPE_AND_PORT			(2 << REGISTER_BLOCK_SHIFT)
80#define REGS_NORTH_PLANE_CONTROL			(3 << REGISTER_BLOCK_SHIFT)
81#define REGS_SOUTH_SHARED					(4 << REGISTER_BLOCK_SHIFT)
82#define REGS_SOUTH_TRANSCODER_PORT			(5 << REGISTER_BLOCK_SHIFT)
83
84// register blocks for (G)MCH/ICH based platforms
85#define MCH_SHARED_REGISTER_BASE						0x00000
86#define MCH_PIPE_AND_PORT_REGISTER_BASE					0x60000
87#define MCH_PLANE_CONTROL_REGISTER_BASE					0x70000
88#define ICH_SHARED_REGISTER_BASE						0x00000
89#define ICH_PORT_REGISTER_BASE							0x60000
90
91// PCH - Platform Control Hub - Newer hardware moves from a MCH/ICH based setup
92// to a PCH based one, that means anything that used to communicate via (G)MCH
93// registers needs to use different ones on PCH based platforms (Ironlake and
94// up, SandyBridge, etc.).
95#define PCH_NORTH_SHARED_REGISTER_BASE					0x40000
96#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE			0x60000
97#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE			0x70000
98#define PCH_SOUTH_SHARED_REGISTER_BASE					0xc0000
99#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE		0xe0000
100
101
102struct DeviceType {
103	uint32			type;
104
105	DeviceType(int t)
106	{
107		type = t;
108	}
109
110	DeviceType& operator=(int t)
111	{
112		type = t;
113		return *this;
114	}
115
116	bool InFamily(uint32 family) const
117	{
118		return (type & INTEL_TYPE_FAMILY_MASK) == family;
119	}
120
121	bool InGroup(uint32 group) const
122	{
123		return (type & INTEL_TYPE_GROUP_MASK) == group;
124	}
125
126	bool IsModel(uint32 model) const
127	{
128		return (type & INTEL_TYPE_MODEL_MASK) == model;
129	}
130
131	bool HasPlatformControlHub() const
132	{
133		return InGroup(INTEL_TYPE_ILK) || InGroup(INTEL_TYPE_SNB)
134			|| InGroup(INTEL_TYPE_IVB);
135	}
136};
137
138// info about PLL on graphics card
139struct pll_info {
140	uint32			reference_frequency;
141	uint32			max_frequency;
142	uint32			min_frequency;
143	uint32			divisor_register;
144};
145
146struct ring_buffer {
147	struct lock		lock;
148	uint32			register_base;
149	uint32			offset;
150	uint32			size;
151	uint32			position;
152	uint32			space_left;
153	uint8*			base;
154};
155
156struct overlay_registers;
157
158struct intel_shared_info {
159	area_id			mode_list_area;		// area containing display mode list
160	uint32			mode_count;
161
162	display_mode	current_mode;
163	uint32			bytes_per_row;
164	uint32			bits_per_pixel;
165	uint32			dpms_mode;
166
167	area_id			registers_area;			// area of memory mapped registers
168	uint32			register_blocks[REGISTER_BLOCK_COUNT];
169	uint8*			status_page;
170	phys_addr_t		physical_status_page;
171	uint8*			graphics_memory;
172	phys_addr_t		physical_graphics_memory;
173	uint32			graphics_memory_size;
174
175	addr_t			frame_buffer;
176	uint32			frame_buffer_offset;
177
178	bool			got_vbt;
179	bool			single_head_locked;
180
181	struct lock		accelerant_lock;
182	struct lock		engine_lock;
183
184	ring_buffer		primary_ring_buffer;
185
186	int32			overlay_channel_used;
187	bool			overlay_active;
188	uintptr_t		overlay_token;
189	phys_addr_t		physical_overlay_registers;
190	uint32			overlay_offset;
191
192	bool			hardware_cursor_enabled;
193	sem_id			vblank_sem;
194
195	uint8*			cursor_memory;
196	phys_addr_t		physical_cursor_memory;
197	uint32			cursor_buffer_offset;
198	uint32			cursor_format;
199	bool			cursor_visible;
200	uint16			cursor_hot_x;
201	uint16			cursor_hot_y;
202
203	DeviceType		device_type;
204	char			device_identifier[32];
205	struct pll_info	pll_info;
206
207	edid1_info		vesa_edid_info;
208	bool			has_vesa_edid_info;
209};
210
211//----------------- ioctl() interface ----------------
212
213// magic code for ioctls
214#define INTEL_PRIVATE_DATA_MAGIC		'itic'
215
216// list ioctls
217enum {
218	INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
219
220	INTEL_GET_DEVICE_NAME,
221	INTEL_ALLOCATE_GRAPHICS_MEMORY,
222	INTEL_FREE_GRAPHICS_MEMORY
223};
224
225// retrieve the area_id of the kernel/accelerant shared info
226struct intel_get_private_data {
227	uint32	magic;				// magic number
228	area_id	shared_info_area;
229};
230
231// allocate graphics memory
232struct intel_allocate_graphics_memory {
233	uint32	magic;
234	uint32	size;
235	uint32	alignment;
236	uint32	flags;
237	addr_t	buffer_base;
238};
239
240// free graphics memory
241struct intel_free_graphics_memory {
242	uint32 	magic;
243	addr_t	buffer_base;
244};
245
246//----------------------------------------------------------
247// Register definitions, taken from X driver
248
249// PCI bridge memory management
250#define INTEL_GRAPHICS_MEMORY_CONTROL	0x52
251	// GGC - (G)MCH Graphics Control Register
252#define MEMORY_CONTROL_ENABLED			0x0004
253#define MEMORY_MASK						0x0001
254#define STOLEN_MEMORY_MASK				0x00f0
255#define i965_GTT_MASK					0x000e
256#define G33_GTT_MASK					0x0300
257#define G4X_GTT_MASK					0x0f00	// GGMS (GSM Memory Size) mask
258
259// models i830 and up
260#define i830_LOCAL_MEMORY_ONLY			0x10
261#define i830_STOLEN_512K				0x20
262#define i830_STOLEN_1M					0x30
263#define i830_STOLEN_8M					0x40
264#define i830_FRAME_BUFFER_64M			0x01
265#define i830_FRAME_BUFFER_128M			0x00
266
267// models i855 and up
268#define i855_STOLEN_MEMORY_1M			0x10
269#define i855_STOLEN_MEMORY_4M			0x20
270#define i855_STOLEN_MEMORY_8M			0x30
271#define i855_STOLEN_MEMORY_16M			0x40
272#define i855_STOLEN_MEMORY_32M			0x50
273#define i855_STOLEN_MEMORY_48M			0x60
274#define i855_STOLEN_MEMORY_64M			0x70
275#define i855_STOLEN_MEMORY_128M			0x80
276#define i855_STOLEN_MEMORY_256M			0x90
277
278#define G4X_STOLEN_MEMORY_96MB			0xa0	// GMS - Graphics Mode Select
279#define G4X_STOLEN_MEMORY_160MB			0xb0
280#define G4X_STOLEN_MEMORY_224MB			0xc0
281#define G4X_STOLEN_MEMORY_352MB			0xd0
282
283// SandyBridge (SNB)
284#define SNB_GRAPHICS_MEMORY_CONTROL		0x50
285
286#define SNB_STOLEN_MEMORY_MASK			0xf8
287#define SNB_STOLEN_MEMORY_32MB			(1 << 3)
288#define SNB_STOLEN_MEMORY_64MB			(2 << 3)
289#define SNB_STOLEN_MEMORY_96MB			(3 << 3)
290#define SNB_STOLEN_MEMORY_128MB			(4 << 3)
291#define SNB_STOLEN_MEMORY_160MB			(5 << 3)
292#define SNB_STOLEN_MEMORY_192MB			(6 << 3)
293#define SNB_STOLEN_MEMORY_224MB			(7 << 3)
294#define SNB_STOLEN_MEMORY_256MB			(8 << 3)
295#define SNB_STOLEN_MEMORY_288MB			(9 << 3)
296#define SNB_STOLEN_MEMORY_320MB			(10 << 3)
297#define SNB_STOLEN_MEMORY_352MB			(11 << 3)
298#define SNB_STOLEN_MEMORY_384MB			(12 << 3)
299#define SNB_STOLEN_MEMORY_416MB			(13 << 3)
300#define SNB_STOLEN_MEMORY_448MB			(14 << 3)
301#define SNB_STOLEN_MEMORY_480MB			(15 << 3)
302#define SNB_STOLEN_MEMORY_512MB			(16 << 3)
303
304#define SNB_GTT_SIZE_MASK				(3 << 8)
305#define SNB_GTT_SIZE_NONE				(0 << 8)
306#define SNB_GTT_SIZE_1MB				(1 << 8)
307#define SNB_GTT_SIZE_2MB				(2 << 8)
308
309// graphics page translation table
310#define INTEL_PAGE_TABLE_CONTROL		0x02020
311#define PAGE_TABLE_ENABLED				0x00000001
312#define INTEL_PAGE_TABLE_ERROR			0x02024
313#define INTEL_HARDWARE_STATUS_PAGE		0x02080
314#define i915_GTT_BASE					0x1c
315#define i830_GTT_BASE					0x10000	// (- 0x2ffff)
316#define i830_GTT_SIZE					0x20000
317#define i965_GTT_BASE					0x80000	// (- 0xfffff)
318#define i965_GTT_SIZE					0x80000
319#define i965_GTT_128K					(2 << 1)
320#define i965_GTT_256K					(1 << 1)
321#define i965_GTT_512K					(0 << 1)
322#define G33_GTT_1M						(1 << 8)
323#define G33_GTT_2M						(2 << 8)
324#define G4X_GTT_NONE					0x000	// GGMS - GSM Memory Size
325#define G4X_GTT_1M_NO_IVT				0x100	// no Intel Virtualization Tech.
326#define G4X_GTT_2M_NO_IVT				0x300
327#define G4X_GTT_2M_IVT					0x900	// with Intel Virt. Tech.
328#define G4X_GTT_3M_IVT					0xa00
329#define G4X_GTT_4M_IVT					0xb00
330
331
332#define GTT_ENTRY_VALID					0x01
333#define GTT_ENTRY_LOCAL_MEMORY			0x02
334#define GTT_PAGE_SHIFT					12
335
336
337// ring buffer
338#define INTEL_PRIMARY_RING_BUFFER		0x02030
339#define INTEL_SECONDARY_RING_BUFFER_0	0x02100
340#define INTEL_SECONDARY_RING_BUFFER_1	0x02110
341// offsets for the ring buffer base registers above
342#define RING_BUFFER_TAIL				0x0
343#define RING_BUFFER_HEAD				0x4
344#define RING_BUFFER_START				0x8
345#define RING_BUFFER_CONTROL				0xc
346#define INTEL_RING_BUFFER_SIZE_MASK		0x001ff000
347#define INTEL_RING_BUFFER_HEAD_MASK		0x001ffffc
348#define INTEL_RING_BUFFER_ENABLED		1
349
350// interrupts
351#define INTEL_INTERRUPT_ENABLED			0x020a0
352#define INTEL_INTERRUPT_IDENTITY		0x020a4
353#define INTEL_INTERRUPT_MASK			0x020a8
354#define INTEL_INTERRUPT_STATUS			0x020ac
355#define INTERRUPT_VBLANK_PIPEA			(1 << 7)
356#define INTERRUPT_VBLANK_PIPEB			(1 << 5)
357
358// PCH interrupts
359#define PCH_INTERRUPT_STATUS			0x44000
360#define PCH_INTERRUPT_MASK				0x44004
361#define PCH_INTERRUPT_IDENTITY			0x44008
362#define PCH_INTERRUPT_ENABLED			0x4400c
363#define PCH_INTERRUPT_VBLANK_PIPEA		(1 << 7)
364#define PCH_INTERRUPT_VBLANK_PIPEB		(1 << 15)
365
366// display ports
367#define INTEL_DISPLAY_A_ANALOG_PORT		(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
368#define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
369#define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
370#define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
371#define DISPLAY_MONITOR_MODE_MASK		(3UL << 10)
372#define DISPLAY_MONITOR_ON				0
373#define DISPLAY_MONITOR_SUSPEND			(1UL << 10)
374#define DISPLAY_MONITOR_STAND_BY		(2UL << 10)
375#define DISPLAY_MONITOR_OFF				(3UL << 10)
376#define DISPLAY_MONITOR_POLARITY_MASK	(3UL << 3)
377#define DISPLAY_MONITOR_POSITIVE_HSYNC	(1UL << 3)
378#define DISPLAY_MONITOR_POSITIVE_VSYNC	(2UL << 3)
379#define INTEL_DISPLAY_A_DIGITAL_PORT	(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
380#define INTEL_DISPLAY_C_DIGITAL			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
381#define INTEL_DISPLAY_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
382#define LVDS_POST2_RATE_SLOW			14 // PLL Divisors
383#define LVDS_POST2_RATE_FAST			7
384#define LVDS_CLKB_POWER_MASK			(3 << 4)
385#define LVDS_CLKB_POWER_UP				(3 << 4)
386#define LVDS_PORT_EN					(1 << 31)
387#define LVDS_A0A2_CLKA_POWER_UP			(3 << 8)
388#define LVDS_PIPEB_SELECT				(1 << 30)
389#define LVDS_B0B3PAIRS_POWER_UP			(3 << 2)
390#define LVDS_PLL_MODE_LVDS				(2 << 26)
391#define LVDS_18BIT_DITHER				(1 << 25)
392
393// PLL flags
394#define DISPLAY_PLL_ENABLED				(1UL << 31)
395#define DISPLAY_PLL_2X_CLOCK			(1UL << 30)
396#define DISPLAY_PLL_SYNC_LOCK_ENABLED	(1UL << 29)
397#define DISPLAY_PLL_NO_VGA_CONTROL		(1UL << 28)
398#define DISPLAY_PLL_MODE_ANALOG			(1UL << 26)
399#define DISPLAY_PLL_DIVIDE_HIGH			(1UL << 24)
400#define DISPLAY_PLL_DIVIDE_4X			(1UL << 23)
401#define DISPLAY_PLL_POST1_DIVIDE_2		(1UL << 21)
402#define DISPLAY_PLL_POST1_DIVISOR_MASK	0x001f0000
403#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK	0x00ff0000
404#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK  0x00ff8000
405#define DISPLAY_PLL_POST1_DIVISOR_SHIFT	16
406#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT	15
407#define DISPLAY_PLL_DIVISOR_1			(1UL << 8)
408#define DISPLAY_PLL_N_DIVISOR_MASK		0x001f0000
409#define DISPLAY_PLL_IGD_N_DIVISOR_MASK	0x00ff0000
410#define DISPLAY_PLL_M1_DIVISOR_MASK		0x00001f00
411#define DISPLAY_PLL_M2_DIVISOR_MASK		0x0000001f
412#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK	0x000000ff
413#define DISPLAY_PLL_N_DIVISOR_SHIFT		16
414#define DISPLAY_PLL_M1_DIVISOR_SHIFT	8
415#define DISPLAY_PLL_M2_DIVISOR_SHIFT	0
416#define DISPLAY_PLL_PULSE_PHASE_SHIFT	9
417
418// display
419#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_SOUTH_TRANSCODER_PORT)
420#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_SOUTH_TRANSCODER_PORT)
421#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_SOUTH_TRANSCODER_PORT)
422#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_SOUTH_TRANSCODER_PORT)
423#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_SOUTH_TRANSCODER_PORT)
424#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_SOUTH_TRANSCODER_PORT)
425#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_SOUTH_TRANSCODER_PORT)
426#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_SOUTH_TRANSCODER_PORT)
427#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_SOUTH_TRANSCODER_PORT)
428#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_SOUTH_TRANSCODER_PORT)
429#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_SOUTH_TRANSCODER_PORT)
430#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_SOUTH_TRANSCODER_PORT)
431
432#define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
433#define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)
434
435#define INTEL_DISPLAY_B_DIGITAL_PORT	(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
436
437// planes
438#define INTEL_DISPLAY_A_PIPE_CONTROL	(0x0008 | REGS_NORTH_PLANE_CONTROL)
439#define INTEL_DISPLAY_B_PIPE_CONTROL	(0x1008 | REGS_NORTH_PLANE_CONTROL)
440#define DISPLAY_PIPE_ENABLED			(1UL << 31)
441
442#define INTEL_DISPLAY_A_PIPE_STATUS		(0x0024 | REGS_NORTH_PLANE_CONTROL)
443#define INTEL_DISPLAY_B_PIPE_STATUS		(0x1024 | REGS_NORTH_PLANE_CONTROL)
444#define DISPLAY_PIPE_VBLANK_ENABLED		(1UL << 17)
445#define DISPLAY_PIPE_VBLANK_STATUS		(1UL << 1)
446
447#define INTEL_DISPLAY_A_CONTROL			(0x0180 | REGS_NORTH_PLANE_CONTROL)
448#define INTEL_DISPLAY_A_BASE			(0x0184 | REGS_NORTH_PLANE_CONTROL)
449#define INTEL_DISPLAY_A_BYTES_PER_ROW	(0x0188 | REGS_NORTH_PLANE_CONTROL)
450#define INTEL_DISPLAY_A_POS				(0x018c | REGS_NORTH_PLANE_CONTROL)
451	// reserved on A
452#define INTEL_DISPLAY_A_PIPE_SIZE		(0x0190 | REGS_NORTH_PLANE_CONTROL)
453#define INTEL_DISPLAY_A_SURFACE			(0x019c | REGS_NORTH_PLANE_CONTROL)
454	// i965 and up only
455
456#define INTEL_DISPLAY_B_CONTROL			(0x1180 | REGS_NORTH_PLANE_CONTROL)
457#define INTEL_DISPLAY_B_BASE			(0x1184 | REGS_NORTH_PLANE_CONTROL)
458#define INTEL_DISPLAY_B_BYTES_PER_ROW	(0x1188 | REGS_NORTH_PLANE_CONTROL)
459#define INTEL_DISPLAY_B_POS				(0x118c | REGS_NORTH_PLANE_CONTROL)
460#define INTEL_DISPLAY_B_PIPE_SIZE		(0x1190 | REGS_NORTH_PLANE_CONTROL)
461#define INTEL_DISPLAY_B_SURFACE			(0x119c | REGS_NORTH_PLANE_CONTROL)
462	// i965 and up only
463
464#define DISPLAY_CONTROL_ENABLED			(1UL << 31)
465#define DISPLAY_CONTROL_GAMMA			(1UL << 30)
466#define DISPLAY_CONTROL_COLOR_MASK		(0x0fUL << 26)
467#define DISPLAY_CONTROL_CMAP8			(2UL << 26)
468#define DISPLAY_CONTROL_RGB15			(4UL << 26)
469#define DISPLAY_CONTROL_RGB16			(5UL << 26)
470#define DISPLAY_CONTROL_RGB32			(6UL << 26)
471
472// cursors
473#define INTEL_CURSOR_CONTROL			(0x0080 | REGS_NORTH_PLANE_CONTROL)
474#define INTEL_CURSOR_BASE				(0x0084 | REGS_NORTH_PLANE_CONTROL)
475#define INTEL_CURSOR_POSITION			(0x0088 | REGS_NORTH_PLANE_CONTROL)
476#define INTEL_CURSOR_PALETTE			(0x0090 | REGS_NORTH_PLANE_CONTROL)
477	// (- 0x009f)
478#define INTEL_CURSOR_SIZE				(0x00a0 | REGS_NORTH_PLANE_CONTROL)
479#define CURSOR_ENABLED					(1UL << 31)
480#define CURSOR_FORMAT_2_COLORS			(0UL << 24)
481#define CURSOR_FORMAT_3_COLORS			(1UL << 24)
482#define CURSOR_FORMAT_4_COLORS			(2UL << 24)
483#define CURSOR_FORMAT_ARGB				(4UL << 24)
484#define CURSOR_FORMAT_XRGB				(5UL << 24)
485#define CURSOR_POSITION_NEGATIVE		0x8000
486#define CURSOR_POSITION_MASK			0x3fff
487
488// palette registers
489#define INTEL_DISPLAY_A_PALETTE			(0xa000 | REGS_NORTH_SHARED)
490#define INTEL_DISPLAY_B_PALETTE			(0xa800 | REGS_NORTH_SHARED)
491
492// PLL registers
493#define INTEL_DISPLAY_A_PLL				(0x6014 | REGS_SOUTH_SHARED)
494#define INTEL_DISPLAY_B_PLL				(0x6018 | REGS_SOUTH_SHARED)
495#define INTEL_DISPLAY_A_PLL_MULTIPLIER_DIVISOR \
496										(0x601c | REGS_SOUTH_SHARED)
497#define INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR \
498										(0x6020 | REGS_SOUTH_SHARED)
499#define INTEL_DISPLAY_A_PLL_DIVISOR_0	(0x6040 | REGS_SOUTH_SHARED)
500#define INTEL_DISPLAY_A_PLL_DIVISOR_1	(0x6044 | REGS_SOUTH_SHARED)
501#define INTEL_DISPLAY_B_PLL_DIVISOR_0	(0x6048 | REGS_SOUTH_SHARED)
502#define INTEL_DISPLAY_B_PLL_DIVISOR_1	(0x604c | REGS_SOUTH_SHARED)
503
504// i2c
505#define INTEL_I2C_IO_A					(0x5010 | REGS_SOUTH_SHARED)
506#define INTEL_I2C_IO_B					(0x5014 | REGS_SOUTH_SHARED)
507#define INTEL_I2C_IO_C					(0x5018 | REGS_SOUTH_SHARED)
508#define INTEL_I2C_IO_D					(0x501c | REGS_SOUTH_SHARED)
509#define INTEL_I2C_IO_E					(0x5020 | REGS_SOUTH_SHARED)
510#define INTEL_I2C_IO_F					(0x5024 | REGS_SOUTH_SHARED)
511#define INTEL_I2C_IO_G					(0x5028 | REGS_SOUTH_SHARED)
512#define INTEL_I2C_IO_H					(0x502c | REGS_SOUTH_SHARED)
513
514#define I2C_CLOCK_DIRECTION_MASK		(1 << 0)
515#define I2C_CLOCK_DIRECTION_OUT			(1 << 1)
516#define I2C_CLOCK_VALUE_MASK			(1 << 2)
517#define I2C_CLOCK_VALUE_OUT				(1 << 3)
518#define I2C_CLOCK_VALUE_IN				(1 << 4)
519#define I2C_DATA_DIRECTION_MASK			(1 << 8)
520#define I2C_DATA_DIRECTION_OUT			(1 << 9)
521#define I2C_DATA_VALUE_MASK				(1 << 10)
522#define I2C_DATA_VALUE_OUT				(1 << 11)
523#define I2C_DATA_VALUE_IN				(1 << 12)
524#define I2C_RESERVED					((1 << 13) | (1 << 5))
525
526// TODO: on IronLake this is in the north shared block at 0x41000
527#define INTEL_VGA_DISPLAY_CONTROL		0x71400
528#define VGA_DISPLAY_DISABLED			(1UL << 31)
529
530// LVDS panel
531#define INTEL_PANEL_STATUS				0x61200
532#define PANEL_STATUS_POWER_ON			(1UL << 31)
533#define INTEL_PANEL_CONTROL				0x61204
534#define PANEL_CONTROL_POWER_TARGET_ON	(1UL << 0)
535#define INTEL_PANEL_FIT_CONTROL			0x61230
536#define INTEL_PANEL_FIT_RATIOS			0x61234
537
538// LVDS on IronLake and up
539#define PCH_PANEL_CONTROL				0xc7200
540#define PCH_PANEL_STATUS				0xc7204
541#define PANEL_REGISTER_UNLOCK			(0xabcd << 16)
542#define PCH_LVDS_DETECTED				(1 << 1)
543
544
545// ring buffer commands
546
547#define COMMAND_NOOP					0x00
548#define COMMAND_WAIT_FOR_EVENT			(0x03 << 23)
549#define COMMAND_WAIT_FOR_OVERLAY_FLIP	(1 << 16)
550
551#define COMMAND_FLUSH					(0x04 << 23)
552
553// overlay flip
554#define COMMAND_OVERLAY_FLIP			(0x11 << 23)
555#define COMMAND_OVERLAY_CONTINUE		(0 << 21)
556#define COMMAND_OVERLAY_ON				(1 << 21)
557#define COMMAND_OVERLAY_OFF				(2 << 21)
558#define OVERLAY_UPDATE_COEFFICIENTS		0x1
559
560// 2D acceleration
561#define XY_COMMAND_SOURCE_BLIT			0x54c00006
562#define XY_COMMAND_COLOR_BLIT			0x54000004
563#define XY_COMMAND_SETUP_MONO_PATTERN	0x44400007
564#define XY_COMMAND_SCANLINE_BLIT		0x49400001
565#define COMMAND_COLOR_BLIT				0x50000003
566#define COMMAND_BLIT_RGBA				0x00300000
567
568#define COMMAND_MODE_SOLID_PATTERN		0x80
569#define COMMAND_MODE_CMAP8				0x00
570#define COMMAND_MODE_RGB15				0x02
571#define COMMAND_MODE_RGB16				0x01
572#define COMMAND_MODE_RGB32				0x03
573
574// overlay
575#define INTEL_OVERLAY_UPDATE			0x30000
576#define INTEL_OVERLAY_TEST				0x30004
577#define INTEL_OVERLAY_STATUS			0x30008
578#define INTEL_OVERLAY_EXTENDED_STATUS	0x3000c
579#define INTEL_OVERLAY_GAMMA_5			0x30010
580#define INTEL_OVERLAY_GAMMA_4			0x30014
581#define INTEL_OVERLAY_GAMMA_3			0x30018
582#define INTEL_OVERLAY_GAMMA_2			0x3001c
583#define INTEL_OVERLAY_GAMMA_1			0x30020
584#define INTEL_OVERLAY_GAMMA_0			0x30024
585
586struct overlay_scale {
587	uint32 _reserved0 : 3;
588	uint32 horizontal_scale_fraction : 12;
589	uint32 _reserved1 : 1;
590	uint32 horizontal_downscale_factor : 3;
591	uint32 _reserved2 : 1;
592	uint32 vertical_scale_fraction : 12;
593};
594
595#define OVERLAY_FORMAT_RGB15			0x2
596#define OVERLAY_FORMAT_RGB16			0x3
597#define OVERLAY_FORMAT_RGB32			0x1
598#define OVERLAY_FORMAT_YCbCr422			0x8
599#define OVERLAY_FORMAT_YCbCr411			0x9
600#define OVERLAY_FORMAT_YCbCr420			0xc
601
602#define OVERLAY_MIRROR_NORMAL			0x0
603#define OVERLAY_MIRROR_HORIZONTAL		0x1
604#define OVERLAY_MIRROR_VERTICAL			0x2
605
606// The real overlay registers are written to using an update buffer
607
608struct overlay_registers {
609	uint32 buffer_rgb0;
610	uint32 buffer_rgb1;
611	uint32 buffer_u0;
612	uint32 buffer_v0;
613	uint32 buffer_u1;
614	uint32 buffer_v1;
615	// (0x18) OSTRIDE - overlay stride
616	uint16 stride_rgb;
617	uint16 stride_uv;
618	// (0x1c) YRGB_VPH - Y/RGB vertical phase
619	uint16 vertical_phase0_rgb;
620	uint16 vertical_phase1_rgb;
621	// (0x20) UV_VPH - UV vertical phase
622	uint16 vertical_phase0_uv;
623	uint16 vertical_phase1_uv;
624	// (0x24) HORZ_PH - horizontal phase
625	uint16 horizontal_phase_rgb;
626	uint16 horizontal_phase_uv;
627	// (0x28) INIT_PHS - initial phase shift
628	uint32 initial_vertical_phase0_shift_rgb0 : 4;
629	uint32 initial_vertical_phase1_shift_rgb0 : 4;
630	uint32 initial_horizontal_phase_shift_rgb0 : 4;
631	uint32 initial_vertical_phase0_shift_uv : 4;
632	uint32 initial_vertical_phase1_shift_uv : 4;
633	uint32 initial_horizontal_phase_shift_uv : 4;
634	uint32 _reserved0 : 8;
635	// (0x2c) DWINPOS - destination window position
636	uint16 window_left;
637	uint16 window_top;
638	// (0x30) DWINSZ - destination window size
639	uint16 window_width;
640	uint16 window_height;
641	// (0x34) SWIDTH - source width
642	uint16 source_width_rgb;
643	uint16 source_width_uv;
644	// (0x38) SWITDHSW - source width in 8 byte steps
645	uint16 source_bytes_per_row_rgb;
646	uint16 source_bytes_per_row_uv;
647	uint16 source_height_rgb;
648	uint16 source_height_uv;
649	overlay_scale scale_rgb;
650	overlay_scale scale_uv;
651	// (0x48) OCLRC0 - overlay color correction 0
652	uint32 brightness_correction : 8;		// signed, -128 to 127
653	uint32 _reserved1 : 10;
654	uint32 contrast_correction : 9;			// fixed point: 3.6 bits
655	uint32 _reserved2 : 5;
656	// (0x4c) OCLRC1 - overlay color correction 1
657	uint32 saturation_cos_correction : 10;	// fixed point: 3.7 bits
658	uint32 _reserved3 : 6;
659	uint32 saturation_sin_correction : 11;	// signed fixed point: 3.7 bits
660	uint32 _reserved4 : 5;
661	// (0x50) DCLRKV - destination color key value
662	uint32 color_key_blue : 8;
663	uint32 color_key_green : 8;
664	uint32 color_key_red : 8;
665	uint32 _reserved5 : 8;
666	// (0x54) DCLRKM - destination color key mask
667	uint32 color_key_mask_blue : 8;
668	uint32 color_key_mask_green : 8;
669	uint32 color_key_mask_red : 8;
670	uint32 _reserved6 : 7;
671	uint32 color_key_enabled : 1;
672	// (0x58) SCHRKVH - source chroma key high value
673	uint32 source_chroma_key_high_red : 8;
674	uint32 source_chroma_key_high_blue : 8;
675	uint32 source_chroma_key_high_green : 8;
676	uint32 _reserved7 : 8;
677	// (0x5c) SCHRKVL - source chroma key low value
678	uint32 source_chroma_key_low_red : 8;
679	uint32 source_chroma_key_low_blue : 8;
680	uint32 source_chroma_key_low_green : 8;
681	uint32 _reserved8 : 8;
682	// (0x60) SCHRKEN - source chroma key enable
683	uint32 _reserved9 : 24;
684	uint32 source_chroma_key_red_enabled : 1;
685	uint32 source_chroma_key_blue_enabled : 1;
686	uint32 source_chroma_key_green_enabled : 1;
687	uint32 _reserved10 : 5;
688	// (0x64) OCONFIG - overlay configuration
689	uint32 _reserved11 : 3;
690	uint32 color_control_output_mode : 1;
691	uint32 yuv_to_rgb_bypass : 1;
692	uint32 _reserved12 : 11;
693	uint32 gamma2_enabled : 1;
694	uint32 _reserved13 : 1;
695	uint32 select_pipe : 1;
696	uint32 slot_time : 8;
697	uint32 _reserved14 : 5;
698	// (0x68) OCOMD - overlay command
699	uint32 overlay_enabled : 1;
700	uint32 active_field : 1;
701	uint32 active_buffer : 2;
702	uint32 test_mode : 1;
703	uint32 buffer_field_mode : 1;
704	uint32 _reserved15 : 1;
705	uint32 tv_flip_field_enabled : 1;
706	uint32 _reserved16 : 1;
707	uint32 tv_flip_field_parity : 1;
708	uint32 source_format : 4;
709	uint32 ycbcr422_order : 2;
710	uint32 _reserved18 : 1;
711	uint32 mirroring_mode : 2;
712	uint32 _reserved19 : 13;
713
714	uint32 _reserved20;
715
716	uint32 start_0y;
717	uint32 start_1y;
718	uint32 start_0u;
719	uint32 start_0v;
720	uint32 start_1u;
721	uint32 start_1v;
722	uint32 _reserved21[6];
723#if 0
724	// (0x70) AWINPOS - alpha blend window position
725	uint32 awinpos;
726	// (0x74) AWINSZ - alpha blend window size
727	uint32 awinsz;
728
729	uint32 _reserved21[10];
730#endif
731
732	// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
733	// the next two registers switch the usual Y/RGB vs. UV order)
734	uint16 horizontal_scale_uv;
735	uint16 horizontal_scale_rgb;
736	// (0xa4) UVSCALEV - vertical downscale
737	uint16 vertical_scale_uv;
738	uint16 vertical_scale_rgb;
739
740	uint32 _reserved22[86];
741
742	// (0x200) polyphase filter coefficients
743	uint16 vertical_coefficients_rgb[128];
744	uint16 horizontal_coefficients_rgb[128];
745
746	uint32	_reserved23[64];
747
748	// (0x500)
749	uint16 vertical_coefficients_uv[128];
750	uint16 horizontal_coefficients_uv[128];
751};
752
753// i965 overlay support is currently realized using its 3D hardware
754#define INTEL_i965_OVERLAY_STATE_SIZE	36864
755#define INTEL_i965_3D_CONTEXT_SIZE		32768
756
757inline bool
758intel_uses_physical_overlay(intel_shared_info &info)
759{
760	return !info.device_type.InGroup(INTEL_TYPE_Gxx);
761}
762
763
764struct hardware_status {
765	uint32	interrupt_status_register;
766	uint32	_reserved0[3];
767	void*	primary_ring_head_storage;
768	uint32	_reserved1[3];
769	void*	secondary_ring_0_head_storage;
770	void*	secondary_ring_1_head_storage;
771	uint32	_reserved2[2];
772	void*	binning_head_storage;
773	uint32	_reserved3[3];
774	uint32	store[1008];
775};
776
777#endif	/* INTEL_EXTREME_H */
778